M37272M6

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 1. DESCRIPTION The M37272M6/M8-XXXSP/FP and M37272MA-XXXSP are singlechip microcomputers designed with CMOS silicon gate technology. They have a OSD, data slicer, and I 2C-BUS interface, so it is useful for a channel selection system for TV with a closed caption decoder. The features of the M37272E8SP/FP and M37272EFSP are similar to those of the M37272M6-XXXSP except that the chip has a built-in PROM which can be written electrically. The difference between M37272M6-XXXSP/FP, M37272M8-XXXSP/FP and M37272MAXXXSP are the ROM size and RAM size. Accordingly, the following descriptions will be for the M37272M6-XXXSP/FP. 2. FEATURES q Number of basic instructions .................................................... 71 q Memory size ROM .............. 24K bytes (M37272M6-XXXSP/FP) 32K bytes (M37272M8-XXXSP/FP, M37272E8SP/FP) 40K bytes (M37272MA-XXXSP) 60K bytes (M37272EFSP) RAM ............... 1024 bytes (M37272M6-XXXSP/FP) 1152 bytes (M37272M8-XXXSP/FP, M37272E8SP/FP) 1472 bytes (M37272MA-XXXSP, M37272EFSP) (*ROM correction memory included) q Minimum instruction execution time ......................................... 0.5 µ s (at 8 MHz oscillation frequency) q Power source voltage ................................................. 5 V ± 10 % q Subroutine nesting ............................................. 128 levels (Max.) q Interrupts ....................................................... 17 types, 16 vectors q 8-bit timers .................................................................................. 6 q Programmable I/O ports (Ports P0, P1, P2, P30, P31) ............. 26 q Input ports (Ports P50, P5 1) ........................................................ 2 q Output ports (Ports P52–P55) ..................................................... 4 q 12 V withstand ports ................................................................... 6 q LED drive ports ........................................................................... 4 qSerial I/O ............................................................ 8-bit ! 1 channel q Multi-master I2C-BUS interface .............................. 1 (2 systems) q A-D comparator (6-bit resolution) ................................ 6 channels q PWM output circuit ......................................................... 8-bit ! 6 q Power dissipation In high-speed mode ......................................................... 165 mW (at VCC = 5.5V, 8 MHz oscillation frequency, OSD on, and Data slicer on) In low-speed mode ......................................................... 0.33 mW (at VCC = 5.5V, 32 kHz oscillation frequency) q ROM correction function ................................................ 2 vectors q Closed caption data slicer q OSD function Display characters ................................... 32 characters ! 2 lines (It is possible to display 3 lines or more by software) Kinds of characters ........................................................ 254 kinds Character display area ............................ CC mode: 16 ! 26 dots OSD mode: 16 ! 20 dots Kinds of character sizes ..................................... CC mode: 1 kind OSD mode: 8 kinds Kinds of character colors .................................. 8 colors (R, G, B) Coloring unit ................... character, character background, raster Display position Horizontal: 128 levels Vertical: 512 levels Attribute ........................................................................................ CC mode: smooth italic, underline, flash, automatic solid space OSD mode: border Smoth roll-up Window function 3. APPLICATION TV with a closed caption decoder Rev. 1.5 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER TABLE OF CONTENTS 1. DESCRIPTION .......................................................................... 1 2. FEAUTURES ............................................................................. 1 3. APPLICATION ............................................................................ 1 4. PIN CONFIGURATION .............................................................. 3 5. FUNCTIONAL BLOCK DIAGRAM ............................................. 4 6. PERFORMANCE OVERVIEW ................................................... 5 7. PIN DESCRIPTION ................................................................... 7 8. FUNCTIONAL DESCRIPTION ................................................. 11 8.1 CENTRAL PROCESSING UNIT (CPU) .................... 11 8.2 MEMORY .................................................................. 12 8.3 INTERRUPTS ........................................................... 18 8.4 TIMERS ..................................................................... 23 8.5 SERIAL I/O ................................................................ 26 8.6 MULTI-MASTER I2C-BUS INTERFACE .................... 29 8.7 PWM OUTPUT CIRCUIT .......................................... 42 8.8 A-D COMPARATOR .................................................. 46 8.9 ROM CORRECTION FUNCTION ............................. 48 8.10 DATA SLICER ......................................................... 49 8.11 OSD FUNCTIONS ................................................... 60 8.11.1 Display Position ....................................... 65 8.11.2 Dot size .................................................... 69 8.11.3 Clock for OSD .......................................... 70 8.11.4 Field Determination Display ..................... 71 8.11.5 Memory For OSD ..................................... 73 8.11.6 Character Color ....................................... 77 8.11.7 Character Background Color ................... 77 8.11.8 OUT1, OUT2 Signals ............................... 78 8.11.9 Attribute .................................................... 79 8.11.10 Multiple Display ...................................... 84 8.11.11 Automatic Solid Space Function ............ 85 8.11.12 Window Function ................................... 86 8.11.13 OSD Output Pin Control ........................ 88 8.11.14 Raster Coloring Function ....................... 89 8.12. SOFTWARE RUNAWAY DETECT FUNCTION ..... 91 8.13. RESET CIRCUIT .................................................... 92 8.14. CLOCK GENERATING CIRCUIT ........................... 93 8.15. DISPLAY OSCILLATION CIRCUIT ........................ 96 8.16. AUTO-CLEAR CIRCUIT ......................................... 96 8.17. ADDRESSING MODE ............................................ 96 8.18. MACHINE INSTRUCTIONS ................................... 96 9. PROGRAMMING NOTES ........................................................ 96 10. ABSOLUTE MAXIMUM RATINGS ......................................... 97 11. RECOMMENDED OPERATING CONDITIONS ..................... 97 12. ELECTRIC CHARACTERISTICS .......................................... 98 13. A-D COMPARISON CHARACTERISTICS ........................... 100 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ......... 100 15. PROM PROGRAMMING METHOD ..................................... 101 16. DATA REQUIRED FOR MASK ORDERS ............................ 102 17. MASK CONFIRMATION FORM ........................................... 103 18. MARK SPECIFICATION FORM ........................................... 112 19. ONE TIME PROM VERSIONS M37272E8SP/FP, M37272EFSP MARKING ..................................................... 114 20. APPENDIX ........................................................................... 115 21. PACKAGE OUTLINE ........................................................... 140 Rev. 1.3 2 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 4. PIN CONFIGURATION P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2 P25 AVCC HLF VHOLD CVIN CNVSS XIN XOUT VSS 1 2 3 4 5 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC M37272M6/M8/MA-XXXSP M37272E8/EFSP 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Outline 42P4B Fig. 4.1 Pin Configuration (1) (Top View) P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2 P25 AVCC HLF VHOLD CVIN CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC Outline 42P2R-A/E Fig. 4.2 Pin Configuration (2) (Top View) M37272M6/M8-XXXFP M37272E8FP Rev. 1.4 3 INT1 INT2 INT3 SDA2 SDA1 SCL2 SCL1 SIN SCLK SOUT PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 AD1–6 10 9 8 7 6 5 4 3 13 12 11 36 37 38 26 27 28 29 30 31 32 33 34 35 I/O port P0 I/O port P2 I/O port P1 I/O ports P30, P31 Output ports P52–P55 Output for display Input ports P50, P51 Synchronous signal input OUT1 B G R VSYNC HSYNC 4 VSS CNVSS 21 18 17 24 23 16 15 Clock input Clock output Pins for data slicer CVIN VHOLD HLF 25 14 22 XIN XOUT Reset input RESET AVCC VCC I/O ports P26, P27 Clock input for Clock output for OSD/ OSD/sub-clock input sub-clock output OSC1/XCIN OSC2/XCOUT 19 20 Clock generating circuit Data slicer Data bus Timer count source selection circuit TIM2 TIM3 Fig. 5.1 Functional Block Diagram of M37272 Program counter 5. FUNCTIONAL BLOCK DIAGRAM ROM correction circuit ROM PCL (8) Timer 2 T2 (8) Timer 3 T3 (8) RAM Progam counter Timer 1 T1 (8) PCH (8) Address bus Timer 4 T4 (8) Control signal Index register 8-bit arithmetic and logical unit X (8) Y (8) Instruction register (8) Stack pointer S (8) Timer 5 T5 (8) Timer 6 T6 (8) Instruction decoder Accumulator A (8) Processor status register PS (8) Index register OS D circuit A-D comparator SI/O P 2 ( 8) P 3 ( 2) Multi-master I2C-BUS interface PWM P 5 ( 6) P10 OUT2 P 0 ( 8) P 1 ( 8) 39 40 41 42 2 1 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Rev. 1.3 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 6. PERFORMANCE OVERVIEW Table 6.1 Performance Overview Parameter Number of basic instructions Instruction execution time Clock frequency Memory size ROM M37272M6-XXXSP/FP M37272M8-XXXSP/FP,M37272E8SP/FP M37272MA-XXXSP RAM M37272EFSP M37272M6-XXXSP/FP M37272M8-XXXSP/FP,M37272E8SP/FP M37272MA-XXXSP, M37272EFSP OSD ROM OSD RAM Input/Output ports P0 P10–P17 I/O I/O Functions 71 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 24K bytes 32K bytes 40K bytes 60K bytes 1024 bytes (ROM correction memory included) 1152 bytes (ROM correction memory included) 1472 bytes (ROM correction memory included) 10K bytes 128 bytes 8-bit ! 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 8-bit ! 1 (CMOS input/output structure, however, N-channel open-drain output structure, when P11–P14 are used as multi-master I2C-BUS interface, can be used as OSD output pin, A-D input pins, INT input pin, multimaster I2C-BUS interface) 8-bit ! 1 (P2 is CMOS input/output structure, however, N-channel opendrain output structure when P20 and 21 are used as serial output, can be used as serial input/output pins, timer external clock input pins, OSD clock input/output pin, sub-clock input/output pins) 2-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins) 2-bit ! 1 (can be used as OSD input pins) 4-bit ! 1 (CMOS output structure, can be used as OSD output pins) 8-bit ! 1 I2C-BUS interface 1 (2 systems) 6 channels (6-bit resolution) 8-bit ! 6 8-bit timer ! 6 2 vectors 128 levels (maximum) INT external interrupt ! 3, Internal timer interrupt ! 6, Serial I/O interrupt ! 1, OSD interrupt ! 1, Multi-master I2C-BUS interface interrupt ! 1, Data slicer interrupt ! 1, f(XIN)/4096 interrupt ! 1, VSYNC interrupt ! 1, BRK instruction interrupt ! 1, reset ! 1 2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator) Built-in P20–P27 I/O P30, P31 P50, P51 P52–P55 Serial I/O Multi-master A-D comparator PWM output circuit Timers ROM correction function Subroutine nesting Interrupt I/O Input Output Clock generating circuit Data slicer Rev. 1.3 5 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Table 6.2 Performance Overview (Continued) Parameter OSD function Number of display characters Dot structure Kinds of characters Kinds of character sizes 1 screen : 8 Character font coloring Display position Power source voltage Power In high-speed dissipation mode In low-speed mode In stop mode Operating temperature range Device structure Package OSD ON OSD OFF OSD OFF Data slicer ON Data slicer OFF Data slicer OFF 32 characters ! 2 lines CC mode: 16 ! 26 dots (character display area : 16 ! 20 dots) OSD mode: 16 ! 20 dots 254 kinds CC mode: 1 kinds OSD mode: 8 kinds 1 screen: 8 kinds (per character unit) Horizontal: 128 levels, Vertical: 512 levels 5V ± 10% 165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz) 82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz) 0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stopped) 0.055 mW ( maximum ) –10 °C to 70 °C CMOS silicon gate process 42-pin plastic molded DIP 42-pin plastic molded SSOP Functions Rev. 1.3 6 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7. PIN DESCRIPTION Table 7.1 Pin Description Pin Name Input/ Output Functions Apply voltage of 5 V ± 10 % to (typical) VCC and AVCC, and 0 V to VSS. This is connected to VSS. Input To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. (See note 1) Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output structure is N-channel open-drain output. Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively. P06 pin is also used as analog input pin AD4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. (See note 1) Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P10, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively. P15 pin is also used as INT external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. (See note 1) P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output structure is N-channel open-drain output. P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain output. P22 pin is also used as serial I/O data input pin SIN. Pins P2 3 and P24 are also used as timer external clock input pins TIM3 and TIM2 respectively. P26 pin is also used as OSD clock input pin OSC1. (See note 2) P27 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output. (See note 2) P26 pin is also used as sub-clock input pin XCIN. P27 pin is also used as sub-clock output pin XCOUT. VCC, AVCC, Power source VSS CNVSS RESET CNVSS Reset input XIN XOUT Clock input Clock output Input Output I/O P00/PWM0– I/O port P0 P05/PWM5, P06/INT2/AD4, P07/INT1 PWM output External interrupt input Analog input P10/OUT2, I/O port P1 P11/SCL1, P12/SCL2, OSD output P13/SDA1, P14/SDA2, P15/AD1/INT3, P16/AD2, P17/AD3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25, P26/OSC1/ XCIN, P27/OSC2/ XCOUT Multi-master I2C-BUS interface Analog input External interrupt input I/O port P2 Serial I/O synchronous clock input/output port Serial I/O data output Serial I/O data input External clock input for timer Clock input for OSD Clock output for OSD Sub-clock input Sub-clock output Output Input Input I/O Output I/O Input Input I/O I/O I/O Input Input Input Output Input Output Rev. 1.4 7 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Table 7.2 Pin Description (continued) Pin P30/AD5, P31/AD6 Name I/O port P3 Input/ Output I/O Functions Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port 0. The output structure can be selected either CMOS output or N-channel open-drain output structure. (See notes 1, 3) Pins P30 and P31 are also used as analog input pins AD5 and AD6 respectively. Pin P50 and P51 are 2-bit input ports. Pin P50 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD. Pin P51 is also used as VSYNC input. This is a vertical synchronous signal input for OSD. Ports P52–P55 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output structure is CMOS output. Input composite video signal through a capacitor. Connect a capacitor between VHOLD and Vss. Connect a filter using of a capacitor and a resistor between HLF and Vss. Analog input P50/HSYNC, Input port P5 P51/VSYNC P52/R, P53/G, P54/B, P55/OUT1 CVIN VHOLD HLF HSYNC input VSYNC input Output port P5 OSD output I/O for data slicer Input Input Input Input Output Output Input Input I/O Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 2: To switch output functions, set the raster color register and OSD control register. When pins P26 and P27 are used as the OSD clock input/output pins, set the corresponding bits of the port P2 direction register to “0” (input mode). 3: To switch output structures, set bits 2 and 3 of the port P3 direction register, When “0,” CMOS output ; when “1,” N-channel open-drain output. Rev. 1.4 8 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Ports P00–P05 N-channel open-drain output Direction register Ports P00–P05 Data bus Port latch Note : Each port is also used as follows : P0 0–P05 : PWM0–PWM5 Ports P1, P2, P30, P31 Direction register CMOS output Data bus Port latch Ports P1, P2, P30, P31 Notes 1: Each port is also used as follows : P10 : OUT2 P20 : SCLK P11 : SCL1 P21 : SOUT P12 : SCL2 P22 : SIN P13 : SDA15 P23 : TIM3 P14 : SDA2 P24 : TIM2 P15 : AD1/INT3 P30 : AD5 P16 : AD2 P31 : AD6 P17 : AD3 2: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel opendrain output structure (when selecting N-channel open-drain, it is the same with P06 and P07). 3: The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master I2C-BUS interface (it is the same with P06 and P07). 4: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial output (it is the same as P06 and P07). Fig. 7.1 I/O Pin Block Diagram (1) Rev. 1.3 9 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Ports P06, P07 N-channel open-drain output Direction register Ports P06, P07 Data bus Port latch Note : Each port is also used as follows : P06 : INT2/AD4 P07 : INT1 P50, P51 P52–P55 CMOS input Internal circuit CMOS output Ports P50, P51 Internal circuit Note : Each pin is also used as follows : P50 : HSYNC P51 : VSYNC Ports P52–P55 Note : Each pin is also used as follows : P52 : R P53 : G P54 : B P55 : OUT1 Fig. 7.2 I/O Pin Block Diagram (2) Rev. 1.4 10 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8. FUNCTIONAL DESCRIPTION 8.1 CENTRAL PROCESSING UNIT (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used. 8.1.1 CPU Mode Register The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16. CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00 11 CPU mode register (CM) [Address 00FB16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions b1 b0 After reset R W 0 RW 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW RW 2 Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page 3, 4 Fix these bits to “1.” 5 XCOUT drivability selection bit (CM5) 6 Main Clock (XIN–XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: XIN–XOUT selected (high-speed mode) 1: XCIN–XCOUT selected (high-speed mode) 1 0 0 RW Note: This bit is set to “1” after the reset release. Fig. 8.1.1 CPU Mode Register Rev. 1.3 11 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.2 MEMORY 8.2.1 Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. 8.2.6 Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. 8.2.7 Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. 8.2.2 RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 ROM ROM is used for storing user programs as well as the interrupt vector area. 8.2.8 Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 8.2.4 OSD RAM RAM for display is used for specifying the character codes and colors to display. 8.2.5 OSD ROM ROM for display is used for storing character data. 8.2.9 ROM Correction Memory (RAM) This is used as the program area for ROM correction. s M37272M6/M8-XXXSP/FP, M37272E8SP/FP 000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 053F16 05BF16 Not used OSD RAM (128 bytes) (See note) 080016 087F16 Not used OSD ROM (10K bytes) 140016 3BFF16 Not used Zero page SFR1 area 1000016 M37272M6XXXSP/FP RAM (1024 bytes) M37272M8XXXSP/FP, M37272E8SP/FP RAM (1152 bytes) SFR2 area Not used ROM correction function Vector 1: address 030016 Vector 2: address 032016 M37272M8XXXSP/FP, M37272E8SP/FP ROM (32K bytes) M37272M6XXXSP/FP ROM (24K bytes) Not used 800016 A00016 FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.3 OSD RAM. Fig. 8.2.1 Memory Map (M37272M6/M8-XXXSP/FP, M37272E8SP/FP) Rev. 1.4 12 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s M37272MA-XXXSP, M37272EFSP 000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 Zero page SFR1 area 1000016 RAM (1472 bytes) SFR2 area Not used ROM correction functrion Vector 1: address 030016 Vector 2: address 032016 Not used Not used 06FF16 OSD RAM (128 bytes) (See note) 080016 087F16 Not used 100016 OSD ROM (10K bytes) M37272EFSP ROM (60K bytes) 1140016 13BFF16 600016 Not used M37272MA-XXXSP ROM (40K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.3 OSD RAM. Fig. 8.2.2 Memory Map (M37272MA-XXXSP, M37272EFSP) Rev. 1.3 13 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s SFR1 Area (addresses C016 to DF16) 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Indeterminate immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register b7 Bit allocation b0 b7 State immediately after reset b0 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) T3SC P31 P30 P31CP30C P31D P30D 0 0 0 Port P5 (P5) OSD port control register (PF) PF7 PF5 PF4 PF3 PF2 0 0 0016 Caption data register 3 (CD3) Caption data register 4 (CD4) OSD control register (OC) Horizontal position register (HP) Block control register 1 (BC1) Block control register 2 (BC2) Vertical position register 1 (VP1) Vertical position register 2 (VP2) Window register 1 (WN1) Window register 2 (WN2) I/O polarity control register (PC) Raster color register (RC) CDL27 CDL26 CDL25 CDL24 CDL23CDL22 CDL21 CDL20 CDH27CDH26CDH25CDH24CDH23CDH22CDH21CDH20 0 OC6 OC5 OC4 OC3 OC2 OC1 OC0 HP 6 HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 BC17 BC16 BC15 BC14 BC13BC12 BC11 BC10 BC27 BC26 BC25 BC24 BC23BC22 BC21 BC20 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20 WN17 WN16 WN15 WN14 WN13WN12 WN11 WN10 WN27 WN26 WN25 WN24 WN23WN22 WN21 WN20 0 RC7 P C6 P C5 P C4 P C3 P C2 P C1 P C0 0 0 RC4 RC3 RC2 RC1 RC0 Interrupt input polarity control register (RE) INT3 INT2 INT1 0016 0016 ) 0016 (See note 1 ? 0016 ? 0016 ? 0016 000?? 0016 ? ? ? 0016 0016 ? ? ? 0016 0016 ? ? ? ? ? ? 4016 0016 ? ? 0016 0016 0016 0016 (See note 2 ) Notes 1: This is only M37272MA-XXXSP and M37272EFSP. 2: As for M37272M6/M8-XXXSP/FP and M37272E8SP/FP, the reset value is ? (indeterminate). Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (1) Rev. 1.4 14 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s SFR1 Area (addresses E016 to FF16) 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Indeterminate immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Bit allocation 1 0 1 0 0 1 b0 b7 DSC20 State immediately after reset 0 ? 0016 0? 0016 0016 0016 0916 00 0016 0016 0016 ? 0016 ?0 0016 0716 FF16 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 3C16 0016 0016 0016 0016 ? 0 b0 Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) Caption data register 1 (CD1) Caption data register 2 (CD2) Clock run-in detect register (CRD) Data clock position register (DPS) Caption position register (CPS) Data slicer test register 2 Data slicer test register 1 0 DSC12DSC11DSC10 DSC25 DSC24 DSC23 ? ? CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17CDH16CDH15CDH14CDH13CDH12CDH11CDH10 CRD7 CRD6 CRD 5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3 0 1 0 0 0 ? CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0 0 0 0 Synchronous signal counter register (HC) Serial I/O register (SIO) Serial I/O mode register (SM) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 5 (T5) Timer 6 (T6) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) HC5 HC4 HC3 HC2 HC1 HC0 0 SM6 SM5 0 ADC14 SM3 SM2 SM1 SM0 ADC12 ADC11 ADC10 0 0 0 0 0 0 ADC25 ADC24 ADC23 ADC22ADC21 ADC20 TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB 0 0 0 0 0 ? I2C clock control register (S2) CM7 CM6 CM5 1 1 CM2 0 0 CPU mode register (CPUM) IN3R VSCR OSDRTM4R TM3R TM2R TM1R Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD ACK ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE 0 TM56RIICR IN2R CKR S1R DSR IN1R CK 0 IN3E VSCEOSDE TM4E TM3E TM2E TM1E TM56CTM56E IICE IN2E CKE S1E DSE IN1E Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (2) Rev. 1.3 15 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s SFR2 Area (addresses 20016 to 20F16) 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Indeterminate immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address Register b7 Bit allocation b0 b7 State immediately after reset ? ? ? ? ? ? ? ? b0 20016 PWM0 register (PWM0) 20116 PWM1 register (PWM1) 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) 0016 0016 PWM mode register 1 (PM1) PWM mode register 2 (PM2) ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) RC1 RC0 PM13 PM10 ? ? ? 0 0 PM25 PM24 PM23 PM22 PM21 PM20 ?0 0016 0016 0016 0016 0016 0016 ? ? ? 0 Fig. 8.2.5 Memory Map of Special Function Register 2 (SFR2) Rev. 1.3 16 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation N V T B D I Z C State immediately after reset b0 b7 b0 ?????1?? Contents of address FFFF16 Contents of address FFFE16 Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset Rev. 1.3 17 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.3 INTERRUPTS Interrupts can be caused by 17 different sources consisting of 4 external, 11 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, x The contents of the program counter and processor status register are automatically stored into the stack.  The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” Ž The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control. 8.3.1 Interrupt Causes (1) VSYNC, OSD interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1 to INT3 external interrupts The INT1 to INT3 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00DC16) : when this bit is “0,” a change from LOW to HIGH is detected; when it is “1,” a change from HIGH to LOW is detected. Note that both bits are cleared to “0” at reset. (3) Timers 1 to 4 interrupts An interrupt is generated by an overflow of timers 1 to 4. Table 8.3.1 Interrupt Vector Addresses and Priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Reset OSD interrupt INT1 external interrupt Data slicer interrupt Serial I/O interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt INT3 external interrupt INT2 external interrupt Multi-master I2C-BUS interface interrupt Timer 5 • 6 interrupt BRK instruction interrupt Interrupt Source Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Source switch by software (see note) Non-maskable Active edge selectable Active edge selectable Active edge selectable Non-maskable Remarks Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program. Rev. 1.3 18 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.” Interrupt request bit Interrupt enable bit (6) Data slicer interrupt An interrupt occurs when slicing data is completed. Interrupt disable flag I (7) Multi-master I2C-BUS interface interrupt BRK instruction Reset Interrupt request This is an interrupt request related to the multi-master I2C-BUS interface. (8) Timer 5 • 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. Fig. 8.3.1 Interrupt Control (9) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Rev. 1.3 19 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 : No interrupt request issued Timer 1 interrupt request bit (TM1R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 2 interrupt request bit (TM2R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 3 interrupt request bit (TM3R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 4 interrupt request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit (OSDR) 0 : No interrupt request issued VSYNC interrupt request bit (VSCR) 1 : Interrupt request issued INT3 external interrupt 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV R— V: “0” can be set by software, but “1” cannot be set. Fig. 8.3.2 Interrupt Request Register 1 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B 0 1 2 Name INT1 external interrupt request bit (INIR) Data slicer interrupt request bit (DSR) Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV RW Serial I/O interrupt request bit (S1R) 3 f(XIN)/4096 interrupt request bit (CKR) 4 INT2 external interrupt request bit (IN2R) 5 Multi-master I2C-BUS interrupt request bit (IICR) 6 Timer 5 • 6 interrupt request bit (TM56R) 7 Fix this bit to “0.” V: “0” can be set by software, but “1” cannot be set. Fig. 8.3.3 Interrupt Request Register 2 Rev. 1.3 20 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (OSDE) 5 VSYNC interrupt enable bit (VSCE) 6 INT3 external interrupt enable bit (IN3E) 0 Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R— 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Fig. 8.3.4 Interrupt Control Register 1 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 Name INT1 external interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I/O interrupt enable bit (S1E) f(XIN)/4096 interrupt enable bit (CKE) INT2 external interrupt enable bit (IN2E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6 After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW 5 Multi-master I2C-BUS interface interrupt enable bit (IICE) 6 Timer 5 • 6 interrupt enable bit (TM56E) 7 Timer 5 • 6 interrupt switch bit (TM56C) 0 0 RW RW Fig. 8.3.5 Interrupt Control Register 2 Rev. 1.3 21 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) [Address 00DC 16] B 0 4 5 4 to 7 Name INT1 polarity switch bit (INT1) INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3) Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity After reset 0 0 0 0 RW RW RW RW R— Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fig. 8.3.6 Interrupt Input Polarity Register Rev. 1.3 22 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.4 TIMERS This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse, after the count value reaches “0016”. 8.4.5 Timer 5 Timer 5 can select one of the following count sources: • f(XIN)/16 or f(XCIN)/16 • Timer 2 overflow signal • Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of the timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow. 8.4.6 Timer 6 8.4.1 Timer 1 Timer 1 can select one of the following count sources: • f(XIN)/16 or f(XCIN)/16 • f(XIN)/4096 or f(XCIN)/4096 • External clock from the TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow. Timer 6 can select one of the following count sources: • f(XIN)/16 or f(XCIN)/16 • Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) V /16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN) V /16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before the execution of the STP instruction (f(XIN) V /16 is selected as timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. V: When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes f(XCIN). The timer-related registers is shown in Figures 8.4.1 and 8.4.2. 8.4.2 Timer 2 Timer 2 can select one of the following count sources: • f(XIN)/16 or f(XCIN)/16 • Timer 1 overflow signal • External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 Timer 3 Timer 3 can select one of the following count sources: • f(XIN)/16 or f(XCIN)/16 • f(XCIN) • External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 Timer 4 Timer 4 can select one of the following count sources: • f(XIN)/16 or f(XCIN)/16 • f(XIN)/2 or f(XCIN)/2 • f(XCIN) The count source of timer 3 is selected by setting bits 1 and 4 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. Rev. 1.3 23 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F4 16] B Name 0 Timer 1 count source selection bit 1 (TM10) 1 2 3 4 Timer 2 count source selection bit 1 (TM11) Timer 1 count stop bit (TM12) Timer 2 count stop bit (TM13) Timer 2 count source selection bit 2 (TM14) Timer 1 count source selection bit 2 (TM15) Timer 5 count source selection bit 2 (TM16) Timer 6 internal count source selection bit (TM17) After reset R W Functions 0: f(XIN)/16 or f(X CIN)/16 (See note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 1 overflow 0: f(XIN)/4096 or f(X CIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 5 overflow 0 RW 0 0 0 RW RW RW 5 0 RW 6 0 0 RW RW 7 Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Fig. 8.4.1 Timer Mode Register 1 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F5 16] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C7 16) 0 0 1 1 1, 4 Timer 4 count source selection bits (TM21, TM24) b4 0 0 1 1 b0 0 : f(X IN)/16 or f(X CIN)/16 (See note) 1 : f(X CIN) 0: 1 : External clock from TIM3 pin b1 0 : Timer 3 overflow signal 1 : f(X IN)/16 or f(X CIN)/16 (See note) 0 : f(X IN)/2 or f(X CIN)/2 (See note) 1 : f(X CIN) 0 RW After reset R W 0 RW 2 3 5 6 7 Timer 3 count stop bit (TM22) Timer 4 count stop bit (TM23) Timer 5 count stop bit (TM25) Timer 6 count stop bit (TM26) Timer 5 count source selection bit 1 (TM27) 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Count source selected by bit 6 of TM1 0 0 0 0 0 RW RW RW RW RW Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Fig. 8.4.2 Timer Mode Register 2 Rev. 1.3 24 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Data bus 8 X CIN CM7 TM15 1/4096 Timer 1 latch (8) 8 XIN 1/2 1/8 TM10 TM12 TM14 Timer 1 (8) 8 8 Timer 1 interrupt request Timer 2 latch (8) 8 TIM2 TM11 TM13 Timer 2 (8) 8 8 Timer 2 interrupt request FF16 T3SC Timer 3 latch (8) 8 Reset STP instruction TIM3 TM20 TM22 Timer 3 (8) 8 8 Timer 3 interrupt request TM21 07 16 Timer 4 latch (8) 8 Timer 4 (8) TM21 TM24 TM23 TM16 Selection gate: Connected to black side at reset TM1 : Timer mode register 1 TM2 : Timer mode register 2 T3SC : Timer 3 count source switch bit (address 00C7 16) CM : CPU mode register TM27 TM25 8 8 Timer 4 interrupt request Timer 5 latch (8) 8 Timer 5 (8) 8 8 Timer 5 interrupt request Timer 6 latch (8) 8 Timer 6 (8) TM17 TM26 8 Timer 6 interrupt request Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 8.4.3 Timer Block Diagram Rev. 1.3 25 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.5 SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P20–P22. Bit 3 of the serial I/O mode register (address 00EB16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C516) to “0.” The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock. XCIN 1/2 XIN 1/2 CM7 Synchronous circuit Data bus 1/2 Frequency divider 1/2 1/4 1/8 1/16 SM2 S SM1 SM0 Selection gate: Connect to black side at reset. P20 Latch SCLK SM3 P21 Latch SOUT SIN SM6 SM3 SM5 : LSB MSB (See note) Serial I/O shift register (8) 8 Serial I/O counter (8) CM : CPU mode register SM : Serial I/O mode register Serial I/O interrupt request Note : When the data is set in the serial I/O register (address 00EA 16), the register functions as the serial I/O shift register. Fig. 8.5.1 Serial I/O Block Diagram Rev. 1.3 26 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 00EA16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” External clock : The an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH. Synchronous clock Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7 Interrupt request bit is set to “1” Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Fig. 8.5.2 Serial I/O Timing (for LSB first) Rev. 1.3 27 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Serial I/O mode register (SM) [Address 00EB16] B Name 0, 1 Internal synchronous clock selection bits (SM0, SM1) After reset R W Functions 0 RW b1 b0 0 0: f(XIN)/4 or f(XCIN)/4 0 1: f(XIN)/16 or f(XCIN)/16 1 0: f(XIN)/32 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/64 2 3 Synchronous clock selection bit (SM2) Port function selection bit (SM3) 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT 0 0 RW RW 4 Fix this bit to “0.” 5 Transfer direction selection bit (SM5) 0: LSB first 1: MSB first 0 0 0 0 RW RW RW RW 6 Transfer clock input 0: Input signal from SIN pin pin selection bit (SM6) 1: Input signal from SOUT pin 7 Fix this bit to “0.” Fig. 8.5.3 Serial I/O Mode Register Rev. 1.3 28 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6 MULTI-MASTER I2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). b7 I2C address register (S0D) b0 Interrupt generating circuit Interrupt request signal (IICIRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I C data shift register S0 2 b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB AL circuit Internal data bus I C status register (S1) 2 BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT b7 BSEL1 BSEL0 10BIT SAD ALS b0 ESO BC2 BC1 BC0 I2C clock control register (S2) Clock division I2C control register (S1D) System clock (φ) Bit counter Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface Rev. 1.3 29 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.1 I2C Data Shift Register The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616] 2 B 0 to 7 Name D0 to D7 Functions This is an 8-bit shift register to store receive data and write transmit data. After reset RW Indeterminate R W Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 8.6.2 Data Shift Register Rev. 1.3 30 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.2 I2C Address Register The I2C address register (address 00F716) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. (2) Bits 1 to 7: slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00F716] B 0 Name Read/write bit (RBW) Functions The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) After reset R W 0 R— 1 to 7 Slave address (SAD0 to SAD6) The address data is compared. 0 RW Fig. 8.6.3 I2C Address Register Rev. 1.3 31 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.3 I2C Clock Control Register The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. (1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clockV is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). VACK clock: Clock for acknowledgement I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2 : address 00FA 16) B 0 to 4 Name Functions After reset R W 0 SCL frequency control Setup value Standard clock High speed mode clock mode of CCR4– bits CCR0 (CCR0 to CCR4) Setup disabled Setup disabled 00 to 02 03 04 05 06 1D 1E 1F Setup disabled Setup disabled RW 333 250 400 (See note) 100 83.3 17.2 16.6 16.1 166 34.5 33.3 32.3 0 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) (at φ = 4 MHz, unit : kHz) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock ... 500/CCR value 1000/CCR value RW RW RW 6 7 0 0 Note: At 4000kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Fig. 8.6.4 I2C Address Register Rev. 1.3 32 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.4 I2C Control Register The I2C control register (address 00F916) controls the data communication format. (3) Bit 4: data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “8.6.5 I2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. (1) Bits 0 to 2: bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C interface use enable bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed. • PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00F816 ). • Writing data to the I2C data shift register (address 00F616) is disabled. (4) Bit 5: addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. (5) Bits 6 and 7: connection control bits between I 2 C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5). “0” “1” BSEL0 SCL/P11 SCL Multi-master I2C-BUS interface SDA “0” “1” BSEL1 SCL2/P12 “0” “1” BSEL0 SDA1/P13 “0” “1” BSEL1 SDA2/P14 Note: Set the corresponding direction register to “1” to use the port as multi-master I2C-BUS interface. Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1 Rev. 1.3 33 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D address 00F916) B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 :8 1 :7 0 :6 1 :5 0 :4 1 :3 0 :2 1 :1 After reset R W 0 RW 3 4 5 I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD) 0 :Disabled 1 :Enabled 0 :Addressing mode 1 :Free data format 0 :7-bit addressing format 1 :10-bit addressing format b7 b6 Connection port (See note) 0 0 :None 0 1 :SCL1, SDA1 1 0 :SCL2, SDA2 1 1 :SCL1, SDA1 SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. Fig. 8.6.6 I2C Control Register Rev. 1.3 34 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.5 I2C Status Register The I2C status register (address 00F816) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions. • Executing a write instruction to the I2C data shift register (address 00F616). • When the ESO bit is “0” • At reset The conditions in which the PIN bit is set to “0” are shown below: • Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). (2) Bit 1: general call detecting flag (AD0) This bit is set to “1” when a general callV whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. VGeneral call: The master transmits the general call address “0016” to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. s In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions. • The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). • A general call is received. s In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition. • When the address data is compared with the I2C address register (8 bits consists of slave address and RBW), the first bytes match. s The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00F616). (6) Bit 5: bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I2C control register (address 00F916) is “0” and at reset, the BB flag is kept in the “0” state. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00F916) is “0” in the slave reception mode is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions. • When arbitration lost is detected. • When a STOP condition is detected. • When occurence of a START condition is disabled by the START condition duplication prevention function (Note). • With MST = “0” and when a START condition is detected. • With MST = “0” and when ACK non-return is detected. • At reset (4) Bit 3: arbitration lostV detecting flag (AL) n the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. VArbitration lost: The status in which communication as a master is disabled. Rev. 1.3 35 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to “0” in one of the following conditions. • Immediately after completion of 1-byte data transmission when arbitration lost is detected • When a STOP condition is detected. • When occurence of a START condition is disabled by the START condition duplication preventing function (Note). • At reset Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device. I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00F816] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = “0 ” 1 : Last bit = “1 ” (See note) After reset R W Indeterminate 0 0 R— R— R— R— RW RW RW 0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note) 0 1 0 0 (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Fig. 8.6.7 I2C Status Register SCL PIN IICIRQ Fig. 8.6.8 Interrupt Request Signal Generation Timing Rev. 1.3 36 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.6 START Condition Generation Method When the ESO bit of the I2C control register (address 00F916) is “1,” execute a write instruction to the I2C status register (address 00F816) to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table. I2C status register write signal SCL SDA BB flag Setup time Hold time Set time for BB flag Fig. 8.6.9 START Condition Generation Timing Diagram 8.6.7 STOP Condition Generation Method When the ESO bit of the I2C control register (address 00F916) is “1,” execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table. I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag Fig. 8.6.10 STOP Condition Generation Timing Diagram Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time 5.0 µs (20 cycles) (START condition) Setup time 4.25 µs (17 cycles) (STOP condition) 5.0 µs (20 cycles) Hold time Set/reset time 3.0 µs (12 cycles) for BB flag High-speed Clock Mode 2.5 µs (10 cycles) 1.75 µs (7 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles) Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev. 1.3 37 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.8 START/STOP Condition Detect Conditions The START/STOP condition detect conditions are shown in Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START/STOP condition can be detected. Note: W hen a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. 8.6.9 Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. (1) 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time (2) 10-bit addressing format Hold time To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00F716) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4). Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode 6.5 µs (26 cycles) < SCL release time 3.25 µs (13 cycles) < Setup time 3.25 µs (13 cycles) < Hold time High-speed Clock Mode 1.0 µs (4 cycles) < SCL release time 0.5 µs (2 cycles) < Setup time 0.5 µs (2 cycles) < Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev. 1.3 38 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.6.10 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Œ Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit.  Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00FA16). Ž Set “1016” in the I2C status register (address 00F816) and hold the SCL at the HIGH.  Set a communication enable status by setting “4816” in the I2C control register (address 00F916).  Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set “0” in the least significant bit. ‘ Set “F016” in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ’ Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. “ When transmitting control data of more than 1 byte, repeat step ’. ” Set “D016” in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition will be generated. 8.6.11 Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Œ Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and “0” in the RBW bit.  Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00FA16). Ž Set “1016” in the I2C status register (address 00F816) and hold the SCL at the HIGH.  Set a communication enable status by setting “4816” in the I2C control register (address 00F916).  When a START condition is received, an address comparison is made. ‘ •When all transmitted address are“0” (general call): AD0 of the I2C status register (address 00F816) is set to “1”and an interrupt request signal occurs. •When the transmitted addresses match the address set in Œ: ASS of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs. •In the cases other than the above: AD0 and AAS of the I2C status register (address 00F816) are set to “0” and no interrupt request signal occurs. ’ Set dummy data in the I2C data shift register (address 00F616). “ When receiving control data of more than 1 byte, repeat step ’. ” When a STOP condition is detected, the communication ends. Rev. 1.3 39 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER S Slave address R/W A Data A Data A/A P 7 bits “ 0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W A Data A Data A P 7 bits “ 1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte S A A Data A Data A/A P 1 to 8 bits 7 bits “ 0” 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2 n d b yt e Slave address R/W 1st 7 bits S A A Sr Data A Data 1 to 8 bits A P 7 bits “ 0” 8 bits 7 bits “1” 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master Fig. 8.6.12 Address Data Communication Format 8.6.12 Precautions when using multi-master I2C-BUS interface (1) Read-modify-write instruction The precautions when the raead-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. •I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. •I2C address register (S0D) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because hardware changes the read/write bit (RBW) at the above timing. •I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. •I2C control register (S1D) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because hardware changes the bit counter (BC0–BC2) at the above timing. •I2C clock control register (S2) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master ŒProcedure example (The necessary conditions of the generating procedure are described as the following  to ). • • — LDA SEI BBS 5,S1,BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI • • BUSBUSY: CLI • • (Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled) (Interrupt enabled) Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing the slave address value to the I2C data shift register. ŽUse “LDM” instruction for setting trigger of START condition generating. Write the slave address value of above  and set trigger of START condition generating of above Ž continuously shown the above procedure example. Disable interrupts during the following three process steps: • BB flag confirming • Writing of slave address value • Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. Rev. 1.3 40 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (3) RESTART condition generating procedure ŒProcedure example (The necessary conditions of the generating procedure are described as the following  to ‘.) Execute the following procedure when the PIN bit is “0.” • • #$00, S1 — S0 #$F0, S1 • • Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. ŽThe SCL pin is released by writing the slave address value to the I2C data shift register. Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing. Use “LDM” instruction for setting trigger of RESTART condition generating. Write the slave address value of above Ž and set trigger of RESTART condition generating of above  continuously shown the above procedure example. ‘Disable interrupts during the following two process steps: • Writing of slave address value • Trigger of RESTART condition generating (4) STOP condition generating procedure ŒProcedure example (The necessary conditions of the generating procedure are described as the following  to .) • • LDM LDA SEI STA LDM CLI (Select slave receive mode) (Taking out of slave address value) (Interrupt disabled) (Writing of slave address value) (Trigger of RESTART condition generating) (Interrupt enabled) SEI LDM #$C0, S1 NOP LDM #$D0, S1 CLI • • (Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger of STOP condition generating) (Interrupt enabled) Write “0” to the PIN bit when master transmit mode is select. ŽExecute “NOP” instruction after setting of master transmit mode. Also, set trigger of STOP condition generating within 10 cycles after selecting of master trasmit mode. Disable interrupts during the following two process steps: • Select of master transmit mode • Trigger of STOP condition generating (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become the same as above. (6) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem. Rev. 1.3 41 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.7 PWM OUTPUT FUNCTION This microcomputer is equipped with six 8-bit PWMs (PWM0– PWM5). PWM0–PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs (for f(XIN) = 8 MHz) and repeat period of 1024 µs (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM5 using f(XIN) divided by 2 as a reference signal. 8.7.1 Data Setting When outputting PWM0–PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 020016 to 020516). 8.7.2 Transmitting Data from Register to PWM circuit Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. 8.7.3 Operating of 8-bit PWM The following explains PWM operation. First, set the bit 0 of PWM mode register 1 (address 020816) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM5 are also used as pins P00–P05. Set the corresponding bits of the port P0 direction register to “1” (output mode). And select each output polarity by bit 3 of PWM mode register 1 (address 020816). Then, set bits 5 to 0 of PWM mode register 2 (address 020916) to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 17 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 17 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 17 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH cannot be output, i.e. 256/256. 8.7.4 Output after Reset At reset, the output of ports P00–P05 is in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register. Rev. 1.3 42 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Data bus XIN 1/2 PM10 PWM0 register (Address 0200 16) b7 8 PWM timing generating circuit b0 PM13 8-bit PWM circuit P00 PM20 P01 PM21 P02 PM22 P03 PM23 P04 PM24 P05 PM25 D00 PWM0 D01 PWM1 PWM1 register (Address 0201 16) D02 PWM2 PWM2 register (Address 0202 16) D03 PWM3 PWM3 register (Address 0203 16) D04 PWM4 PWM4 register (Address 0204 16) D05 PWM5 PWM5 register (Address 0205 16) Selection gate: Connected to black side at reset. Inside of is as same contents with the others. PM1 : PWM mode register 1 (address 0208 16) PM2 : PWM mode register 2 (address 0209 16) P0 : Port P0 register (address 00C0 16) D0 : Port P0 direction register (address 00C1 16) Fig. 8.7.1 PWM Block Diagram Rev. 1.3 43 44 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Fig. 8.7.2 PWM Timing 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 56 88 120 152 184 216 232 200 168 136 104 72 248 48 80 112 144 176 208 240 96 160 224 64 192 128 13579 20 30 40 Bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 Bit 6 4 12 20 28 36 44 Bit 5 8 24 40 Bit 4 16 Bit 3 32 Bit 2 Bit 1 Bit 0 (a) Pulses showing the weight of each bit 0016 (0) 0116 (1) 1816 (24) FF16 (255) t T = 256 t PWM output t = 4 µs T = 1024 µs f(XIN) = 8 MHz (b) Example of 8-bit PWM MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Rev. 1.3 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PWM Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PM1) [Address 020816] B 0 Name PWM counts source selection bit (PM10) Functions 0 : Count source supply 1 : Count source stop After reset R W 0 RW 1, 2 Nothing is assigned. These bits are write disable bits. Indeterminate R — When these bits are read out, the values are “0.” 3 PWM output polarity selection bit (PM13) 0 : Positive polarity 1 : Negative polarity 0 RW 4 Nothing is assigned. These bits are write disable bits. Indeterminate R — to When these bits are read out, the values are “0.” 7 Fig. 8.7.3 PWM Mode Register 1 PWM Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 PWM mode register 2 (PM2) [Address 0209 16] B Name 0 P00/PWM0 output selection bit (PM20) 1 2 3 4 5 P01/PWM1 output selection bit (PM21) P02/PWM2 output selection bit (PM22) P03/PWM3 output selection bit (PM23) P04/PWM4 output selection bit (PM24) P05/PWM5 output selection bit (PW25) Functions 0 : P0 0 output 1 : PWM0 output 0 : P0 1 output 1 : PWM1 output 0 : P0 2 output 1 : PWM2 output 0 : P0 3 output 1 : PWM3 output 0 : P0 4 output 1 : PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 RW RW RW RW RW RW 6, 7 Fix these bits to “0.” Fig. 8.7.4 PWM Mode Register 2 Rev. 1.3 45 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.8 A-D COMPARATOR A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 8.8.1. The reference voltage “Vref” for D-A conversion is set by bits 0 to 5 of A-D control register 2 (address 00ED16). The comparison result of the analog input voltage and the reference voltage “Vref” is stored in bit 4 of A-D control register 1 (address 00EC16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of A-D control register 1 and write the digital value corresponding to Vref to be compared to the bits 0 to 5 of A-D control register 2. The voltage comparison starts by writing to A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ! 8). Data bus A-D control register 1 Bits 0 to 2 Comparator control AD1 AD2 AD3 AD4 AD5 AD6 A-D control register 1 Analog signal switch Comparator Bit 4 Bit 5 Bit 4 A-D control register 2 Bit 3 Bit 2 Bit 1 Bit 0 Switch tree Resistor ladder Fig. 8.8.1 A-D Comparator Block Diagram Rev. 1.3 46 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EC16] B 0 to 2 Name Analog input pin selection bits (ADC10 to ADC12) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0: Do not set. 1: After reset R W 0 RW 3 4 5 to 7 This bit is a write disable bit. When this bit is read out, the value is “0.” Storage bit of comparison result (ADC14) 0: Input voltage < reference voltage 1: Input voltage > reference voltage 0 Indeterminate 0 R— RW R— Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are “0.” Fig. 8.8.2 A-D Control Register 1 A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00ED 16] B 0 to 5 Name D-A converter set bits (ADC20 to ADC25) b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc After reset 0 RW RW 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R— 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” Fig. 8.8.3 A-D Control Register 2 Rev. 1.3 47 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.9 ROM CORRECTION FUNCTION This can correct program data in ROM. Up to 2 addresses can be corrected, a program for correction is stored in the ROM correction vector in RAM as the top address. The ROM correction vectors are 2 vectors. Vector 1 : address 030016 Vector 2 : address 032016 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction vector as the top address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register. Notes 1: Specify the first address (op code address) of each instruction as the ROM correction address. 2: Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3: Do not set the same ROM correction address to vectors 1 and 2. ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) 020A 16 020B 16 020C 16 020D 16 Fig. 8.9.1 ROM Correction Address Registers ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 ROM correction enable register (RCR) [Address 020E B 0 1 2 to 7 16] Name Vector 1 enable bit (RC0) Vector 2 enable bit (RC1) Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset 0 0 0 RW RW RW R— Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fig. 8.9.2 ROM Correction Enable Register Rev. 1.3 48 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10 DATA SLICER This microcomputer includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip’s polarity negative is input to the CVIN pin. When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00E016) to “0.” These settings can realize the low-power dissipation. Composite video signal 0.1 µF 1 MΩ 470 Ω 560 pF 1 µF 1 kΩ 200 pF Sync pulse counter register (address 00E9 16) HLF CV IN HSYNC Synchronizing signal counter Clamping circuit Low-pass filter Sync slice circuit Synchronizing separation circuit Data slicer control register 2 (address 00E1 16) Data slicer control register 1 (address 00E0 16) Timing signal generating circuit Data slicer ON/OFF Reference voltage generating 1000 pF circuit VHOLD + – Comparator Clock run-in determination circuit Data slice line specification circuit Clock run-in defect register (address 00E4 16) Start bit detecting circuit External circuit Note : Make the length of wiring which is connected to V HOLD , HLF, and CV IN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin. Caption position register (address 00E6 16) Data clock generating circuit Data clock position register (address 00E5 16) 16-bit shift register Interrupt request generating circuit high-order low-order Caption data register 1 (address 00E216) Data slicer interrupt request Caption data register 2 (address 00E316) Caption data register 4 (address 00CF16) Caption data register 3 (address 00CE16) Data bus Fig. 8.10.1 Data Slicer Block Diagram Rev. 1.3 49 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.1 Notes When not Using Data Slicer When bit 0 of data slicer control register 1 (address 00E016) is “0,” terminate the pins as shown in Figure 8.10.2. Apply the same voltage as V CC to AV CC pin. 19 AVCC HLF VHOLD CVIN Leave HLF pin open. Open Open 20 Leave V HOLD pin open. Pull-down CV IN pin to V SS through a resistor of 5 k Ω or more. 21 5 kΩ or more 22 Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State When both bits 0 and 2 of data slicer control register 1 (address 00E016) are “1,” terminate the pins as shown in Figure 8.10.3. Apply the same voltage as V CC to AV CC pin. 19 1 kΩ AV CC HLF Connect the same external circuit as when using data slicer to HLF pin. Leave V HOLD pin open. Pull-up CV IN to V CC through a resistor of 5 kΩ or more. 1 µF 20 200pF Open 21 VHOLD 5 kΩ or more 22 CVIN Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State Rev. 1.3 50 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Figures 8.10.4 and 8.10.5 the data slicer control registers. Data Slicer Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 01100 Data slicer control register 1(DSC1) [Address 00E016] B 0 Name Functions 0: Stopped 1: Operating 0: F2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3, 4 Fix these bits to “0.” 5, 6 Fix these bits to “1.” 7 Fix this bit to “0.” Definition of fields 1 (F 1) and 2 (F 2) F1: Hsep Vsep F2: Hsep Vsep Fig. 8.10.4 Data Slicer Control Register 1 Data Slicer Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 1 Data slicer control register 2 (DSC2) [Address 00E116] B 0 Name Caption data latch completion flag 1 (DSC20) Functions After reset RW 0: Data is not latched yet Indeterminate R — and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) 0: Match 1: Mismatch RW 1 2 3 4 Fix this bit to “1.” Test bit Field determination flag(DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24) V-pulse shape determination flag (DSC25) Fix this bit to “o.” Test bit Read-only Indeterminate R — Indeterminate R — 0 RW 5 6 7 Indeterminate R — 0 RW Indeterminate R — Definition of fields 1 (F 1) and 2 (F 2) F1: Hsep Vsep F2: Hsep Vsep Fig. 8.10.5 Data Slicer Control Register 2 Rev. 1.3 51 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.2 Clamping Circuit and Low-pass Filter The clamp circuit clamps the sync chip part of the composite video signal input from the CVIN pin. The low-pass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video signal is input requires a capacitor (0.1 µF) coupling outside. Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1 MΩ. In addition, we recommend to install externally a simple lowpass filter using a resistor and a capacitor at the CVIN pin (refer to Figure 8.10.1). Composite s Measure LOW period Timing signal 8.10.3 Sync Slice Circuit This circuit takes out a composite sync signal from the output signal of the low-pass filter. Vsep signal 8.10.4 Synchronous Signal Separation Circuit This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1)Horizontal Synchronous Signal (Hsep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal. (2)Vertical Synchronous Signal (Vsep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 00E116). •Method 1 The LOW level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this LOW level. •Method 2 The LOW level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync signal exits or not in the LOW level period of the timing signal immediately after this LOW level. If a falling exists, a Vsep signal is generated in synchronization with the rising of the timing signal (refer to Figure 8.10.6). Figure 8.10.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 8.10.7, when the A level matches the B level, this bit is “0.” In the case of a mismatch, the bit is “1.” A Vsep signal is generated at a rising of the timing signal immediately after the LOW level width of the composite sync signal exceeds a certain time. Fig. 8.10.6 Vsep Generating Timing (method 2) Rev. 1.3 52 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.5 Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 00E016) to “1.” The reference clock can be used as a display clock for OSD function in addition to the data slicer. The HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 00E016). For the pins HLF, connect a resistor and a capacitor as shown in Figure 8.10.1. Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming. Bit 5 of DSC2 0 Composite sync signal 1 1 A B Fig. 8.10.7 Determination of V-pulse Waveform Rev. 1.3 53 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.6 Data Slice Line Specification Circuit (1) Specification of data slice line This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their data. The caption position register (address 00E616) is used for each setting (refer to Table 8.10.1). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is sliced. The values of “0016” to “1F16” can be set in the caption position register (at setting only 1 appropriate line). Figure 8.10.8 shows the signals in the vertical blanking interval. Figure 8.10.9 shows the structure of the caption position register. (3) Field determination The field determination flag can be read out by bit 3 of data slicer control register 2. This flag charge at the falling edge of Vsep. (2) Specification of line to set slice voltage The reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to Table 8.10.1). The field to generate slice voltage is specified by bit 1 of data slicer control register 1. The line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to Table 8.10.1). Video signal Vertical blanking interval Composite video signal Vsep 1 appropriate line is set by the caption position register Line 21 (when setting line 19) Hsep Count value to be set in the caption position register (“0F 16” in this case) Magnified drawing Hsep Clock run-in Start bit + 16-bit data Composite video signal Window for deteminating clock-run-in Start bit Fig. 8.10.8 Signals in Vertical Blanking Interval Rev. 1.3 54 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLA Y CONTROLLER Caption Position Register b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616] B 0 to 4 5 Name Caption position bits(CPS0 to CPS4) Caption data latch completion flag 2 (CPS5) Functions After reset 0 RW RW 0: Data is not latched yet and a Indeterminate R — clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Refer to the corresponding Table (Table 8.10.1). 0 RW 6, 7 Slice line mode specification bits (in 1 field) (CPS6, CPS7) Fig. 8.10.9 Caption Position Register Table 8.10.1 Specification of Data Slice Line CPS b7 0 b6 0 Field and Line to Be Sliced Data • Both fields of F1 and F2 • Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) • Both fields of F1 and F2 • A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3) • Both fields of F1 and F2 • Line 21 (total 1 line) • Both fields of F1 and F2 • Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) Field and Line to Generate Slice V oltage • Field specified by bit 1 of DSC1 • Line 21 (total 1 line) • Field specified by bit 1 of DSC1 • A line specified by bits 4 to 0 of CPS (total 1 line) (See note 3) • Field specified by bit 1 of DSC1 • Line 21 (total 1 line) • Field specified by bit 1 of DSC1 • Line 21 and a line specified by bits 4 to 0 of CPS (total 2 lines) (See note 2) 0 1 1 1 0 1 Notes 1: DSC1 is data slicer control register 1. CPS is caption position register . 2: Set “0016” to “1016” to bits 4 to 0 of CPS. 3: Set “0016” to “1F16” to bits 4 to 0 of CPS. Rev. 1.3 55 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.7 Reference Voltage Generating Circuit and Comparator The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. 8.10.8 Start Bit Detecting Circuit This circuit detects a start bit at line decided in the data slice line specification circuit. The detection of a start bit is described below. Œ A sampling clock is generated by dividing the reference clock output by the timing signal.  A clock run-in pulse is detected by the sampling clock. Ž After detection of the pulse, a start bit pattern is detected from the comparator output. (1) Reference voltage generating circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. 8.10.9 Clock Run-in Determination Circuit This circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. The reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 00E416). Read out these bits after the occurrence of a data slicer interrupt (refer to “8.10.12 Interrupt Request Generating Circuit”). Figure 8.10.10 shows the structure of clock run-in detect register. (2) Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value. Clock Run-in Detect Register b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00E4 16] B 0 to 2 3 to 7 Test bits Name Read-only Functions After reset R W 0 R— Clock run-in detection bit (CRD3 to CRD7) Number of reference clocks to be counted in one clock run-in pulse period. 0 R— Fig. 8.10.10 Clock Run-in Detect Register Rev. 1.3 56 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.10 Data Clock Generating Circuit This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores caption data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. This flag is reset at a falling of the vertical synchronous signal (Vsep). Data Clock Position Register b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 Data clock position register (DPS) [Address 00E516] B 0 1 2 3 4 to 7 Name Fix this bit to “0.” Fix this bit to “1.” Fix this bit to “0.” Data clock position set bits (DPS3 to DPS7) Functions After reset R W 1 0 0 1 0 RW RW RW RW Fig. 8.10.11 Data Clock Position Register Rev. 1.3 57 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.11 16-bit Shift Register The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. The contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00E316) and data register 4 (address 00CF16). The contents of the low-order 8 bits can be obtained by reading out data register 1 (address 00E216) and data register 3 (address 00CE16), respectively. These registers are reset to “0” at a falling of Vsep. Read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to “8.10.12 Interrupt Request Generating Circuit”). 8.10.12 Interrupt Request Generating Circuit The interrupt requests as shown in Table 8.10.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 00E616). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request. Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register Slice Line Specification Mode CPS bit 7 bit 6 0 0 1 1 0 1 0 1 Contents of Caption Data Latch Completion Flag Completion Flag 1 (bit 0 of DSC2) Line 21 A line specified by bits 4 to 0 of CPS Line 21 Line 21 Completion Flag 2 (bit 5 of CPS) A line specified by bits 4 to 0 of CPS Invalid Invalid A line specified by bits 4 to 0 of CPS Contents of 16-bit Shift Register Caption Data Registers 1, 2 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of CPS 16-bit data of line 21 16-bit data of line 21 Caption Data Registers 3, 4 16-bit data of a line specified by bits 4 to 0 of CPS Invalid Invalid 16-bit data of a line specified by bits 4 to 0 of CPS CPS: Caption position register DSC2: Data slicer control register 2 Table 8.10.3 Occurence Sources of Interrupt Request Caption position register b7 b6 0 0 1 0 1 1 Occurence Souces of Interrupt Request at End of Data Slice Line After slicing line 21 After a line specified by bits 4 to 0 of CPS After slicing line 21 After slicing line 21 Rev. 1.3 58 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.10.13 Synchronous Signal Counter The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “1F16,” “1F16” is stored into the latch. The latch value can be obtained by reading out the sync pulse counter register (address 00E916). A count source is selected by bit 5 of the sync pulse counter register. The synchronous signal counter is used when bit 0 of PWM mode register 1 (address 020816). Figure 8.10.12 shows the structure of the sync pulse counter and Figure 8.10.13 shows the synchronous signal counter block diagram. Sync Pulse Counter Register b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E9 16] B 0 to 4 5 Name Count value (HC0 to HC4) Functions After reset 0 RW R— Count source (HC5) 0: HSYNC signal 1: Composite sync signal 0 RW 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 R— Fig. 8.10.12 Sync Pulse Counter Register f(XIN)/213 Composite sync signal HSYNC signal Reset 5-bit counter Counter b5 Latch (5 bits) Sync pulse counter register Selection gate : connected to black side when reset. Data bus Fig. 8.10.13 Synchronous Signal Counter Block Diagram Rev. 1.3 59 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11 OSD FUNCTIONS Table 8.11.1 outlines the OSD functions. This microcomputer incorporates an OSD circuit of 32 characters ! 2 lines. And also, there are 2 display modes and they are selected by a block unit. The display modes are selected by bits 0 and 1 of block control register i (i = 1 and 2). The features of each mode are described below. Table 8.11.1 Features of Each Display Mode Display mode Parameter CC mode (Closed caption mode) 32 characters ! 2 lines 16 ! 26 dots (Character display area : 16 ! 20 dots) 254 kinds 1 kinds ! 2 (fixed) 1TC ! 1/2H Smooth italic, under line, flash 8 kinds ! 2, ! 3 1TC ! 1/2H, 1TC ! 1H, 2TC ! 2H, 3TC ! 3H Border (black) 16 ! 20 dots OSD mode (Border OFF) (On-screen display mode) Number of display characters Dot structure Kinds of characters Kinds of character sizes Pre-divide ratio (See note) Dot size Attribute Character font coloring Character background coloring OSD output Raster coloring Function 1 screen : 8 kinds (per character unit) 1 screen : 8 kinds (per character unit) R, G, B Possible (per character unit) Auto solid space function Window function Display position Display expansion (multiline display) Horizontal: 128 levels, Vertical: 512 levels Possible Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to 8.11.2 Dot Size). Rev. 1.3 60 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The OSD circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 8.11.1 shows the configuration of OSD character. Figure 8.11.2 shows the block diagram of the OSD circuit. Figure 8.11.3 shows the OSD control register. Figure 8.11.4 shows the block control register i. CC mode OSD mode 16 dots 16 dots 'Blank areaV 20 dots 26 dots 20 dots 'Underline areaV 'Blank areaV V: Displayed only in CCD mode. Fig. 8.11.1 Configuration of OSD Character Display Area Rev. 1.3 61 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Clock for OSD OSC1 OSC2 HSYNC VSYNC Data slicer clock Display oscillation circuit Control registers for OSD OSD Control circuit OSD control register Horizontal position register Block control register i Vertical position register i Window register i I/O polarity control register Raster color register (address 00D016) (address 00D116) (addresses 00D216, 00D316) (addresses 00D416, 00D516) (addresses 00D616, 00D716) (address 00D816) (address 00D916) RAM for OSD 2 bytes ! 32 characters ! 2 lines ROM for OSD 16 dots ! 20 dots ! 254 characters Shift register 16-bit Output circuit R G B OUT1 OUT2 Data bus Fig. 8.11.2 Block Diagram of OSD Circuit Rev. 1.3 62 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 OSD control register (OC) [Address 00D0 16] B 0 1 2 3 Name OSD control bit (OC0) (See note) Automatic solid space control bit (OC1) Window control bit (OC2) CC mode clock selection bit (OC3) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : OFF 1 : ON 0 : OFF 1 : ON 0 : Data slicer clock 1 : Clock from OSC1 pin 0 : Data slicer clock 1 : Clock from OSC1 pin b6 b5 After reset R W 0 0 0 0 0 RW RW RW RW RW 4 OSD mode clock selection bit (OC4) 5, 6 OSC1 clock selection bit (OC5, OC6) 0 0: 32 kHz oscillating 0 1: Do not set. 1 0: LC oscillating, Ceramic oscillating 1 1: Do not set. 0 RW 7 Fix this bit to “0.” 0 RW Note: Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next V SYNC. Fig. 8.11.3 OSD Control Register Rev. 1.3 63 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Block Control register i b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1, 2) [Addresses 00D2 B Name b1 b0 16 and 00D3 16] After reset Functions 0 0 1 1 b4 RW 0, 1 Display mode selection bits (BCi0, BCi1) (See note 1) 2, 3 Dot size selection bits (BCi2, BCi3) 0: Display OFF 1: CC mode 0: OSD mode (Border OFF) 1: OSD mode (Border ON) b3 b2 Pre-divide Ratio 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Dot Size Indeterminate R W Indeterminate R W 0 !2 4 Pre-divide ratio selection bit (BCi4) 1 !3 1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H 1Tc ! 1/2H Indeterminate 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H RW 5 OUT1/OUT2 output control 0: OUT1 output control 1: OUT2 output control bit (BCi5) (See note 1) 6 Vertical display start position control bit (BCi6) 7 Window top/bottom boundary control bit (BCi7) BC16: Block 1 BC26: Block 1 BC17: Window top boundary BC27: Window bottom boundary Indeterminate R W Indeterminate R W Indeterminate R W Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.” Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.” 2: Tc is OSD clock cycle divided in pre-divide circuit. 3: H is HSYNC. Fig. 8.11.4 Block Control Register i Rev. 1.3 64 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.1 Display Position The display positions of characters are specified in units called a “block.” There are 2 blocks, blocks 1 and 2. Up to 32 characters can be displayed in each block (refer to “8.11.5 Memory for OSD”). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be selected for all blocks in common from 128-step display positions in units of 4TOSC (TOSC = OSD oscillation cycle). The display start position in the vertical direction for each block can be selected from 512-step display positions in units of 1 TH ( TH = HSYNC cycle). Blocks are displayed in conformance with the following rules: • When the display position of block 1 is overlapped with that of block 2 (Figure 8.11.5 (b)), the block 1 is displayed on the front. • When another block display position appears while one block is displayed (Figure 8.11.5 (c)), the block with a larger set value as the vertical display start position is displayed. (HP) VP1 Block 1 VP2 Block 2 (a) Example when each block is separated (HP) VP1 = VP2 Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1 (HP) VP1 VP2 Block 1 Block 2 (c) Example when block 2 overlaps in process of block 1 Note: VP1 or VP2 indicates the vertical display start position of display block 1 or 2. Fig. 8.11.5 Display Position Rev. 1.3 65 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The vertical display start position is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the I/O polarity control register (address 00D816). 8 machine cycles or more VSYNC signal input 0.25 to 0.50 [µs] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal HSYNC signal input 8 machine cycles or more 1 2 3 4 5 (See note 2) Not count When bits 0 and 1 of the I/O polarity control register (address 00D816) are set to “1” (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more. Fig. 8.11.6 Supplement Explanation for Display Position Rev. 1.3 66 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The vertical display start position for each block can be set in 512 steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in vertical position register i (i = 1 and 2) (addresses 00D416 and 00D516) and values “0” or “1” in bit 6 of block control register i (i = 1 and 2) (addresses 00D216 and 00D316). The vertical position registers is shown in Figure 8.11.7. Vertical Position Register i b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516] B Name Vertical display start position control bits (VPi0 to VPi7) (See note) Functions Vertical display start position = 2 TH ! (BCi6 ! 16 + n) (n: setting value, TH: HSYNC cycle, BCi6: bit 6 of block control register i) After reset RW 0 to 7 Inderterminate R W Note: Set values except “0016” to VPi when BCi6 is “0.” Fig. 8.11.7 Vertical Position Register i (i = 1 and 2) Rev. 1.3 67 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The horizontal display start position is common to all blocks, and can be set in 128 steps (where 1 step is 4TOSC, TOSC being the OSD oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the horizontal position register (address 00D116). The horizontal position register is shown in Figure 8.11.8. Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00D1 16] B Functions Horizontal display start positions 128 steps (00 16 to 7F 16) (1 step is 4T OSC) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Name After reset R W 0 RW 0 Horizontal display start to position control bits 6 (HP0 to HP6) 7 0 R— Note: The setting value synchronizes with the V SYNC. Fig. 8.11.8 Horizontal Position Register Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different pre-divide ratios, their horizontal display start position will not match. 2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their horizontal display start position will not match. 3 : When setting “0016” to the horizontal position register, it needs approximately 62TOSC (= Tdef) interval from a rising edge (when negative polarity is selected) of HSYNC signal to the horizontal display start position. HSYNC Note 1 Tdef 4TOSC ! N 1TC Block 2 (Pre-divide ratio = 2, clock source = data slicer clock) 1TC Block 3 (Pre-divide ratio = 3, clock source = data slicer clock) Tdef’ 4TOSC’ Note 2 !N 1TC Block 4 (Pre-divide ratio = 3, clock source = OSC1) N 1 TC TOSC Tdef : Value of horizontal position register (decimal notation) : OSD clock cycle divided in pre-divide circuit : OSD oscillation cycle : 62 T OSC Fig. 8.11.9 Notes on Horizontal Display Start Position Rev. 1.3 68 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.2 Dot Size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of each block is specified by bits 2 to 4 of the block control register i. Refer to Figure 8.11.4 (the structure of the block control register). The block diagram of dot size control circuit is shown in Figure 8.11.10. OSC1 Synchronous circuit “0” Cycle ! 2 Clock cycle = 1TC Data slicer clock OC3 or OC4 “1” BCi4 Cycle ! 3 Horizontal dot size control circuit Pre-divide circuit HSYNC Vertical dot size control circuit OSD control circuit Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.” Fig. 8.11.10 Block Diagram of Dot Size Control Circuit 1 dot 1TC 1/ H 2 1H 1TC 2TC 3TC S canni g lne ofF1( 2) ni F S canni g lne ofF2( 1) ni F 3H 2H Fig. 8.11.11 Definition of Dot Sizes Rev. 1.3 69 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.3 Clock for OSD As a clock for display to be used for OSD, it is possible to select one of the following 3 types. • Data slicer clock output from the data slicer (approximately 26 MHz) • OSC1 clock supplied from the pins OSC1 and OSC2 • Clock from the ceramic resonator or the LC oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the raster color register (address 00D916), bits 3 to 6 of the clock source control register (addresses 00D016). A variety of character sizes can be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P2. Table 8.11.2 Setting for P26/OSC1/XCIN, P27/OSC2/XCOUT Function Register b7 of raster color register OSD control register b6 b5 1 0 0 0 1 0 OSD clock I/O Pin 0 Sub-clock I/O Pin 0 I/O Port 1 Data slicer circuit Data slicer clock (See note) “0” CC mode block “1” “0” OC3 OSD mode block Ceramic · LC “10” OSC1 clock “1” OC4 OC6, OC5 Oscillating mode for OSD Note : To use data slicer clock, set bit 0 of data slicer control register 1 to “1.” Fig. 8.11.12 Block Diagram of OSD Selection Circuit Rev. 1.3 70 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.4 Field Determination Display To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 8.11.14) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC control signal (refer to Figure 8.11.6) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is regarded as odd field The contents of this field can be read out by the field determination flag (bit 6 of the I/O polarity control register at address 00D816). A dot line is specified by bit 5 of the I/O polarity control register (refer to Figure 8.11.14). However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field, regardless of bit 5. I/O Polarity Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 I/O polarity control register (PC) [Address 00D8 16] B 0 1 2 3 4 5 Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2) OUT1 output polarity switch bit (PC3) OUT2 output polarity switch bit (PC4) Display dot line selection bit (PC5) (See note) Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0:“ “ 1:“ “ ” at even field ” at odd field ” at even field ” at odd field After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW 6 7 Field determination flag (PC6) Fix this bit to “0.” 0 : Even field 1 : Odd field 1 0 R— RW Note: Refer to the corresponding figure (8.11.14). Fig. 8.11.13 I/O Polarity Control Register Rev. 1.3 71 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Both H SYNC signal and V SYNC signal are negative-polarity input Field Display dot line determination selection bit flag(Note) HSYNC Field Display dot line V SYNC and V SYNC control signal in microcomputer Upper : VSYNC signal Lower : VSYNC control signal in microcomputer (n |1) field (Odd-numbered) T1 0.25 to 0.50[ ˚s] at 8 MHz f(XIN ) Odd 0 (n) field (Even-numbered) T2 Even 0 (T2 > T1) 1 Dot line 1 Dot line 0 0 (n {1) field (Odd-numbered) T3 Odd 1 (T3 < T2) 1 16) Dot line 0 Dot line 1 When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CC mode 2345 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OSD mode 12 345 to “0.” 6 7 8 9 10 11 12 13 14 15 16 When the display dot line selection bit is “0,” the “ ” font is displayed at even field, the “ ” font is displayed at odd field. Bit 6 of the I/O polarity control register can be read as the field determination flag : “1” is read at odd field, “0” is read at even field. OSD ROM font configuration diagram Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in the microcomputer. Fig. 8.11.14 Relation between Field Determination Flag and Display Font Rev. 1.3 72 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.5 Memory for OSD There are 2 types of memory for OSD : OSD ROM used to store character dot data and OSD RAM used to specify the characters and colors to be displayed. OSD ROM : addresses 140016 to 3BFF16 OSD RAM : addresses 080016 to 087F16 OSD ROM : addresses 1140016 to 13BFF16 OSD RAM : addresses 080016 to 087F16 (1) OSD ROM (addresses 140016 to 3BFF16) The dot pattern data for OSD characters is stored in OSD ROM. To specify the kinds of the character font, it is necessary to write the character code into the OSD RAM. Data of the character font is specified shown in Figure 8.11.15. OSD ROM address of character font data OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit Line number/character 1 (Note) code/font bit Line number Character code Font bit 0 0 Line number Character code “0A16” to “1D16” “0016” to “FF16” (“7F16” and “8016” cannot be used) 0 : Left area 1 : Right area Note: Only M37272MA-XXXSP and M37272EFSP have AD16. Data in OSD ROM 000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016 Line number 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D b7 Left area b0 b7 Right area b0 Character font Fig. 8.11.15 Character Font Data Storing Address Rev. 1.3 73 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Notes 1 : The 80-byte addresses corresponding to the character code “7F16” and “8016” in OSD ROM are the test data storing area. Set data to the area as follows. s M37272M6/M8-XXXSP/FP, M37272E8SP/FP addresses 100016 + (4 + 2n) ! 10016 + FE16 to 100016 + (5 + 2n) ! 10016 + 0116 (n = 0 to 19) s M37272MA-XXXSP, M37272EFSP addresses 1100016 + (4 + 2n) ! 10016 + FE16 to 1100016 + (5 + 2n) ! 10016 + 0116 (n = 0 to 19) (1)Mask version (M37272M6/M8-XXXSP/FP, M37272MA-XXXSP) Set “FF16” to the area (We stores the test data to this area and the different data from “FF16” is stored for the actual products.) When using our font editor, the test data is written automatically. (2)EPROM version (M37272E8SP/FP, M37272EFSP) Set the test data to the area. When using our font editor, the test data is written automatically. 2 : The character code “0916” is used for “transparent space” when displaying Closed Caption. Therefore, set “0016” to the 40-byte addresses corresponding to the character code “0916.” s M37272M6/M8-XXXSP/FP, M37272E8SP/FP addresses 100016 + (4 + 2n) ! 10016 + 1216 to 100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19)  addresses 141216 and 141316     addresses 161216 and 161316       addresses 381216 and 381316   addresses 3A1216 and 3A1316   s M37272MA-XXXSP, M37272EFSP addresses 1100016 + (4 + 2n) ! 10016 + 1216 to 1100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19) 14FE16 (0916), 14FF16 (5116) 16FE16 (0016), 16FF16 (5216) 18FE16 (1216), 18FF16 (5316) 1AFE16 (0016), 1AFF16 (5416) 1CFE16 (2416), 1CFF16 (5516) 1EFE16 (0016), 1EFF16 (5616) 20FE16 (8816), 20FF16 (5716) 22FE16 (0016), 22FF16 (5816) 24FE16 (9016), 24FF16 (5916) 26FE16 (4816), 26FF16 (5A16) 28FE16 (2416), 28FF16 (5B16) 2AFE16 (0016), 2AFF16 (5C16) 2CFE16 (2416), 2CFF16 (5D16) 2EFE16 (4816), 2EFF16 (5E16) 30FE16 (0016), 30FF16 (5F16) 32FE16 (4816), 32FF16 (5016) 34FE16 (9016), 34FF16 (5116) 36FE16 (0016), 36FF16 (5216) 38FE16 (0116), 38FF16 (5316) 3AFE16 (8016), 3AFF16 (5416) sM37272EFSP address (test data) 150016 (9016), 150116 (A116) 170016 (0016), 170116 (A216) 190016 (4816), 190116 (A316) 1B0016 (0016), 1B0116 (A416) 1D0016 (2416), 1D0116 (A516) 1F0016 (0016), 1F0116 (A616) 210016 (1216), 210116 (A716) 230016 (0016), 230116 (A816) 250016 (0916), 250116 (A916) 270016 (0016), 270116 (AA16) 290016 (8116), 290116 (AB16) 2B0016 (1816), 2B0116 (AC16) 2D0016 (0016), 2D0116 (AD16) 2F0016 (4216), 2F0116 (AE16) 310016 (2416), 310116 (AF16) 330016 (0016), 330116 (B016) 350016 (8116), 350116 (B116) 370016 (0C16), 370116 (B216) 390016 (0616), 390116 (B316) 3B0016 (0016), 3B0116 (B416) address (test data) 114FE16 (0916), 114FF16 (5116) 1150016 (9016), 1150116 (A116) 116FE16 (0016), 116FF16 (5216) 1170016 (0016), 1170116 (A216) 118FE16 (1216), 118FF16 (5316) 1190016 (4816), 1190116 (A316) 11AFE16 (0016), 11AFF16 (5416) 11B0016 (0016), 11B0116 (A416) 11CFE16 (2416), 11CFF16 (5516) 11D0016 (2416), 11D0116 (A516) 11EFE16 (0016), 11EFF16 (5616) 11F0016 (0016), 11F0116 (A616) 120FE16 (8816), 120FF16 (5716) 1210016 (1216), 1210116 (A716) 122FE16 (0016), 122FF16 (5816) 1230016 (0016), 1230116 (A816) 124FE16 (9016), 124FF16 (5916) 1250016 (0916), 1250116 (A916) 126FE16 (4816), 126FF16 (5A16) 1270016 (0016), 1270116 (AA16) 128FE16 (2416), 128FF16 (5B16) 1290016 (8116), 1290116 (AB16) 12AFE16 (0016), 12AFF16 (5C16) 12B0016 (1816), 12B0116 (AC16) 12CFE16 (2416), 12CFF16 (5D16) 12D0016 (0016), 12D0116 (AD16) 12EFE16 (4816), 12EFF16 (5E16) 12F0016 (4216), 12F0116 (AE16) 130FE16 (0016), 130FF16 (5F16) 1310016 (2416), 1310116 (AF16) 132FE16 (4816), 132FF16 (5016) 1330016 (0016), 1330116 (B016) 134FE16 (9016), 134FF16 (5116) 1350016 (8116), 1350116 (B116) 136FE16 (0016), 136FF16 (5216) 1370016 (0C16), 1370116 (B216) 138FE16 (0116), 138FF16 (5316) 1390016 (0616), 1390116 (B316) 13AFE16 (8016), 13AFF16 (5416) 13B0016 (0016), 13B0116 (B416) … sM37272E8SP/FP address (test data) address (test data)    addresses 1141216 and 1141316   addresses 1161216 and 1161316       addresses 1381216 and 1381316     addresses 13A1216 and 13A1316 … Rev. 1.3 74 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (2) OSD RAM The RAM for OSD is allocated at addresses 080016 to 087F16, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Table 8.11.3 shows the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write the color code 1 at 082016. The structure of the OSD RAM is shown in Figure 8.11.16. Table 8.11.3 Contents of OSD RAM Display Position (from left) Block 1st character 2nd character 3rd character Block 1 : 30th character 31st character 32nd character 1st character 2nd character 3rd character : Block 2 30th character 31st character 32nd character Character Code Specification 080016 080116 080216 : 081D16 081E16 081F16 084016 084116 084216 : 085D16 085E16 085F16 Color Code Specification 082016 082116 082216 : 083D16 083E16 083F16 086016 086116 086216 : 087D16 087E16 087F16 Rev. 1.3 75 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Blocks 1, 2 b7 b0 b7 b0 RF0 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RF7 RF6 RF5 RF4 RF3 RF2 RF1 (See note 1) Color code 1 Character code (See note 3) CC mode Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 Control of character color R Control of character color G Control of character color B OUT1/OUT2 control Flash control Underline control Italic control (See note 2) 0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON 0: Italic OFF 1: Italic ON Notes 1: Read value of bits 7 of the color code is “0.” 2: For OUT1/OUT2 control, refer to “8.11.8 OUT1/OUT2 signal.” 3: “7F16” and “8016” cannot be used as character code. OSD mode Function Bit name Function Bit name Character code Character code in OSD ROM Character code Character code in OSD ROM 0: Color signal output OFF 1: Color signal output ON Control of character color R Control of character color G Control of character color B OUT1/OUT2 control Control of background color R Control of background color G Control of background color B 0: Color signal output OFF 1: Color signal output ON (See note 2) 0: Color signal output OFF 1: Color signal output ON Fig. 8.11.16 Bit structure of OSD RAM Rev. 1.3 76 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.6 Character color The color for each character is displayed by the color code. Specified by bits 0 (R), 1 (G), and 2 (B) of the color code 8.11.7 Character background color The character background color can be displayed in the character display area only in the OSD mode. The character background color for each character is specified by the color code. Specified by bits 4 (R), 5 (G), and 6 (B) of the color code Note : The character background color is displayed in the following part : (character display area)–(character font)–(border). Accordingly, the character background color does not mix with these color signal. Rev. 1.3 77 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.8 OUT1, OUT2 signals The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by display mode, bit 5 of the block control register i (refer to Figure 8.11.4) and RA3 of OSD RAM. The setting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 8.11.17. Note : When OUT2 signal is output, set bit 7 of OSD port control register (refer to Figure 8.11.28) to “1.” A A' Block Control OUT1/OUT2 Register i Display Control Mode OUT1/OUT2 Output RA3 of Control Bit (b5) OSD RAM 0 (OUT1 output is controlled by RA3) OSD 1 (OUT2 output is controlled by RA3) 0 0 Output Waveform (A-A') OUT1 = FONT/BORDER OUT2 = “L” OUT1 = AREA OUT2 = “L” OUT1 = FONT/BORDER OUT2 = “L” OUT1 = FONT/BORDER OUT2 = AREA OUT1 = FONT 1 1 0 (OUT1 output is controlled by RA3) CC 1 (OUT2 output is controlled by RA3) 0 OUT2 = “L” OUT1 = AREA OUT2 = “L” OUT1 = FONT OUT2 = “L” OUT1 = FONT 1 0 1 OUT2 = AREA Notes 1 : FONT/BORDER.....In the OSD mode (Border ON), OUT1 outputs to the area of font and border. In the OSD mode (Border OFF), OUT1 outputs to only the font area. AREA..................... OUT1/OUT2 outputs to entire display area of character. FONT..................... In the CC mode, OUT1 outputs to font area. 2 : When the automatic solid space function is OFF in the CC mode, AREA outputs according to bit 3 of color code. When it is ON, the solid space is automatically output by a character code regardless of RA3. Fig. 8.11.17 Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform Rev. 1.3 78 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.9 Attribute The attributes (border, flash, underline, italic) are controlled to the character font. The attributes to be controlled are different depending on each mode. CC mode ..................... Flash, underline, italic (per character unit) OSD mode .................. Border (per character unit) (1) Under line The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by RA5 of OSD RAM. The color of underline is the same color as that of the character font. (2) Flash The character font and the underline are flashed only in the CC mode. The flash is controlled by RA4 of OSD RAM. As for character font part, the character output part is flashed, the character background part is not flashed. The flash cycle bases on the VSYNC count. • VSYNC cycle ! 48 ≈ 800 ms (at display ON) • VSYNC cycle ! 16 ≈ 267 ms (at display OFF) (3) Italic The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic is controlled by RA6 of OSD RAM. The display example of the italic and underline is shown in Figure 8.11.8. In this case, “R” is displayed. Notes 1: When setting both the italic and the flash, the italic character flashes. 2: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 8.11.19). 3: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 8.11.19). Rev. 1.3 79 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Color code Bit 6 (RA6) Bit 5 (RA5) Color code Bit 6 (RA6) Bit 5 (RA5) 0 0 1 0 (a) Ordinary (b) Under line Color code Bit 6 (RA6) Bit 5 (RA5) Color code Bit 6 (RA6) Bit 5 (RA5) 0 1 0 1 (c) Italic (pre-divide ratio = 1) (d) Italic (pre-divide ratio = 2) Color code Bit 6 (RA6) flash flash flash Bit 5 (RA5) Bit 4 (RA4) 1 1 1 ON OFF OFF (e) Under line amd Italic and flash ON Fig. 8.11.18 Example of Attribute Display (in CC Mode) Rev. 1.4 80 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 26th chracter (Refer to “8.11.9 Notes 2, 3”) (Refer to “8.11.9 Notes 2, 3”) RA6 of OSD RAM 1 0 0 1 1 0 1 Notes 1 : The dotted line is the boundary of character color. 2 : When bit 1 of OSD control register is “0.” Fig. 8.11.19 Example of Italic Display Rev. 1.3 81 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (4) Border The border is output around of character font (all bordered) in the OSD mode. The border ON/OFF is controlled by bit 0 and 1 of the block control register i (refer to Figure 8.11.4). The OUT1 signal is used for border output. The horizontal size (x) of border is 1TC (OSD clock cycle divided in pre-divide circuit) regardless of the character font dot size. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font. Notes 1 : The border dot area is the shaded area as shown in Figure 8.11.20. 2 : When the border dot overlaps on the next character font, the character font has priority (refer to Figure 8.11.22 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 8.11.22 B). 3 : The border in vertical out of character area is not displayed (refer to Figure 8.11.22). OSD mode 16 dots Character font area All bordered 1 dot width of border 1 dot width of border Fig. 8.11.20 Example of Border Display y x Vertical dot size of character font 20 dots Border dot size 1/2H 1H, 2H, 3H Horizontal size (x) Vertical size (y) 1Tc (OSD clock cycle divided in pre-divide circuit) 1/2H 1H Fig. 8.11.21 Horizontal and Vertical Size of Border Rev. 1.3 82 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Character boundary B Character boundary A Character boundary B Fig. 8.11.22 Border Priority Rev. 1.3 83 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.10 Multiline Display This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register (addresses 00D216, 00D316), an OSD interrupt request does not occur (refer to Figure 8.11.23 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 8.11.23 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 8.11.23 (C)). Block 1 (on display) Block 2 (on display) Block 1’ (on display) Block 2’ (on display) “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” Block 1 (on display) Block 2 (on display) Block 1’ (off display) Block 2’ (off display) “OSD interrupt request” “OSD interrupt request” No “OSD interrupt request” No “OSD interrupt request” On display (OSD interrupt request occurs at the end of block display) (A) Off display (OSD interrupt request does not occur at the end of block display) Block 1 “OSD interrupt request” Block 1 Block 2 No “OSD interrupt request” “OSD interrupt request” Block 2 “OSD interrupt request” Block 1’ “OSD interrupt request” Window In CC mode (B) (C) Fig. 8.11.23 Note on Occurence of OSD Interrupt Rev. 1.3 84 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.11 Automatic Solid Space Function This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : • Any character area except character code “0916 ” • Character area on the left and right sides of the above character This function is turned on and off by bit 1 of the OSD control register (refer to Figure 8.11.3). Notes : The character code “0916” is used for “transparent space” when displaying Closed Caption. Therefore, set “0016” to the 40-byte addresses corresponding to the character code “0916.” s M37272M6/M8-XXXSP/FP, M37272E8SP/FP addresses 100016 + (4 + 2n) ! 10016 + 1216 to 100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19)  addresses 141216 and 141316     addresses 161216 and 161316       addresses 381216 and 381316   addresses 3A1216 and 3A1316   s M37272MA-XXXSP, M37272EFSP addresses 1100016 + (4 + 2n) ! 10016 + 1216 to 1100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19)    addresses 1141216 and 1141316   addresses 1161216 and 1161316       addresses 1381216 and 1381316   addresses 13A1216 and 13A1316    … When setting the character code “0516” as the character A, “0616” as the character B. (OSD RAM) 05 09 09 09 06 06 16 16 16 16 16 ••• 16 06 09 09 06 16 16 16 … 16 (Display screen) ••• 1st character 2nd character No blank output 31st character 32nd character The solid space is automatically output on the left side of the 1st character and on the right side of the 32nd character by setting the 1st and 32nd of the character code. Fig. 8.11.24 Display Screen Example of Automatic Solid Space Rev. 1.3 85 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.12 Window Function This function sets the top and bottom boundary of display limit on a screen. The window function is valid only in the CC mode. The top boundary is set by the window registers 1 and bit 7 of block control register 1. The bottom boundary is set by window registers 1 and bit 7 of block control register 2. This function is turned on and off by bit 2 of the OSD control register (refer to Figure 8.11.3). The window registers 1 and 2 is shown in Figures 8.11.26 and 8.11.27. ABCDE F GH I J OSD mode Top boundary of window CC mode CC mode CC mode Window KL MNO PQRST UV WX Y Screen OSD mode Bottom boundary of window Fig. 8.11.25 Example of Window Function Rev. 1.3 86 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Window Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Window register 1 (WN1) [Address 00D616] B Name Window top boundary control bits (WN10 to WN17) Functions Window top border position = 2 TH ! (BC17 ! 16 + n) (n: setting value, TH: HSYNC cycle, BC17: bit 7 of block control register 1) After reset RW 0 to 7 Inderterminate R W Notes 1: Set values except “0016” to WN1 when BC17 is “0.” 2: Set values fit for the following condition: WN1 < WN2. Fig. 8.11.26 Window Register 1 Window Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Window register 2 (WN2) [Address 00D716] B Name Window bottom boundary control bits (WN20 to WN27) Functions Window bottom border position = 2 TH ! (BC27 ! 16 + n) (n: setting value, TH: HSYNC cycle, BC27: bit 7 of block control register 2) After reset RW 0 to 7 Inderterminate R W Note: Set values fit for the following condition: WN1 < WN2. Fig. 8.11.27 Window Register 2 Rev. 1.3 87 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.13 OSD Output Pin Control The OSD output pins R, G, B and OUT1 can also function as ports P52–P55. Set corresponding bit of the OSD port control register (address 00CB16) to “0” to specify these pins as OSD output pins, or set it to “1” to specify it as a general-purpose port P5. The OUT2 can also function as port P10. Set bit 0 of the port P1 direction register (address 00C316) to “1” (output mode). After that, set bit 7 of the OSD port control register to “1” to specify the pin as OSD output pin, or set it to “0” to specify as port P10. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the I/O polarity control register (address 00D8) . Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity (refer to Figure 8.11.13). The structure of the OSD port control register is shown in Figure 8.11.28. OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 OSD port control register (PF ) [Address 00CB16] B Name Functions After reset R W 0 R— RW RW RW RW R— RW 0, 1 Fix these bits to “0.” 2 3 4 5 6 7 Port P52 output signal selection bit (PF2) Port P53 output signal selection bit (PF3) Port P54 output signal selection bit (PF4) Port P55 output signal selection bit (PF5) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P53 output 0 0 0 0 0 0 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “0.” Port P10 output signal selection bit (PF7) 0 : Port P10 output 1 : OUT2 signal output Fig. 8.11.28 OSD Port Control Register Rev. 1.3 88 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.11.14 Raster Coloring Function An entire screen (raster) can be colored by setting the bits 4 to 0 of the raster color register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 8 raster colors can be obtained. When the character color/the character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the raster color. This ensures that character color/character background color is not mixed with the raster color. The raster color register is shown in Figure 8.11.29, the example of raster coloring is shown in Figure 8.11.30. Raster Color Register b7 b6 b5 b4 b3 b2 b1 b0 00 Raster color register (RC) [Address 00D9 16] B 0 1 2 3 Name Raster color R control bit (RC0) Raster color G control bit (RC1) Raster color B control bit (RC2) Raster color OUT1 control bit (RC3) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset RW RW RW RW RW RW 0 0 0 0 0 4 Raster color OUT2 control bit (RC4) 5, 6 Fix these bits to “0.” 0 : OSC1/X CIN, OSC2/X COUT 1 : P2 6, P2 7 0 0 RW RW 7 Port function selection bit (RC7) Note: Either OSD clock source or 32 kHz oscillating clock is selected by bits 5 and 6 of the OSD control register. Fig. 8.11.29 Raster Color Register Rev. 1.3 89 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER : Character color “RED” (R + OUT1 + OUT2) : Border color “BLACK” (OUT1 + OUT2) : Background color “MAGENTA” (R + B + OUT1 + OUT2) : Raster color “BLUE” (B + OUT1 + OUT2) A A' HSYNC OUT1 OUT2 R G B Signals across A-A' Fig. 8.11.30 Example of Raster Coloring Rev. 1.3 90 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.12 SOFTWARE RUNAWAY DETECT FUNCTION This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. Œ The CPU generates an undefined instruction decoding signal.  The device is internally reset because of occurrence of the undefined instruction decoding signal. Ž As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be invalid. φ SYNC Address PC ? 01,S 01,S–1 01,S–2 FFFE16 FFFF16 ADH, ADL Data ? PCH PCL PS Reset sequence ADL ADH Undefined instruction decoding signal occurs.Internal reset signal occurs. ? : Undefined instruction decode : Invalid PC : Program counter S : Stack pointer ADL, ADH : Jump destination address of reset Fig.8.12.1 Sequence at Detecting Software Runaway Detection Rev. 1.3 91 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.13. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V ± 10 %, hold the RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 8.13.2, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 8.2.3 to 8.2.6. An example of the reset circuit is shown in Figure 8.13.1. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Poweron 4 .5 V Power source voltage 0 V Reset input voltage 0 V 0 .9 V Vcc 1 5 M51 953AL RESET 4 3 0.1 µF Vss Microcomputer Fig.8.13.1 Example of Reset Circuit XIN φ RESET Internal RESET SYNC Address Data ? ? 32768 count of XIN clock cycle (See note 3) ? ? 01, S 01, S-1 01, S-2 FFFE FFFF ADH, ADL Reset address from the vector table ? ? ? ADL ADH Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal. Fig.8.13.2 Reset Sequence Rev. 1.3 92 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.14 CLOCK GENERATING CIRCUIT This microcomputer has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock, clear bits 5 and 6 of the OSD control register to “0.” To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock φ is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock φ to low-speed operation mode, set bit 7 of the CPU mode register to “1.” (3) Low-speed Mode If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to “1.” When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption. To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to “1” by software before executing. Microcomputer 8.14.1 OSCILLATION CONTROL (1) Stop Mode The built-in clock generating circuit is shown in Figure 120. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF16” is set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or f(XCIN)/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to “0” before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH level until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. XCIN Rf XCOUT XIN XOUT Rd CCIN CCOUT CIN COUT Fig.8.14.1 Ceramic Resonator Circuit Example (2) Wait Mode When the WIT instruction is executed, the internal clock φ stops in the HIGH level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. • VSYNC interrupt • OSD interrupt • All timer interrupts using external clock input from port pin as count source • All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source • All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source • f(XIN)/4096 interrupt • Multi-master I2C-BUS interface interrupt • Data slicer interrupt • A-D conversion interrupt Microcomputer XCIN XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss Fig.8.14.2 External Clock Input Circuit Example Rev. 1.3 93 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER XCIN XCOUT OSC1 clock selection bits (See notes 1, 4) XIN XOUT “1” 1 /2 “0” Internal system clock selection bit (See notes 1, 3) 1 /8 “1” “0” Timer 3 count stop bit (See notes 1, 2) Timer 3 Timer 4 count stop bit (See notes 1, 2) Timer 4 Timer 3 count source selection bit (See notes 1, 2) Timing φ (Internal clock) Main clock (XIN–XOUT) stop bit (See notes 1, 3) Internal system clock selection bit (See notes 1, 3) Q S S Q Q S Reset STP instruction R STP instruction WIT instruction R R Reset Interrupt disable flag I Interrupt request Notes 1 : The value at reset is “0.” 2 : Refer to timer mode register 2. 3 : Refer to the CPU mode register. 4 : Refer to the OSD control register. Fig.8.14.3 Clock Generating Circuit Block Diagram Rev. 1.3 94 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Reset High-speed operation start mode WIT instruction 8 MHz oscillating 32 kHz oscillating φ is stopped (“H”) Timer operating Interrupt External INT, timer interrupt, or SI/O interrupt 8 MHz oscillating 32 kHz oscillating f(φ) = 4 MHz STP instruction 8 MHz stopped 32 kHz stopped φ is stopped (“H”) Interrupt (See note 1) External INT CM7 = 0 CM7 = 1 WIT instruction 8 MHz oscillating 32 kHz oscillating φ is stopped (“H”) Timer operating (See note 3) 8 MHz oscillating 32 kHz oscillating f(φ) = 16kHz Interrupt STP instruction 8 MHz stopped 32 kHz stopped φ is stopped (“H”) Interrupt (See note 2) CM6 = 0 The program must allow time for 8 MHz oscillation to stabilize CM6 = 1 8 MHz stopped 32 kHz oscillating φ is stopped (“H”) Timer operating (See note 3) WIT instruction 8 MHz stopped 32 kHz oscillating f(φ) = 16 kHz Interrupt STP instruction 8 MHz stopped 32 kHz stopped φ = stopped (“H”) Interrupt (See note 2) CPU mode register (Address : 00FB16) CM6 : Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The φ indicates the internal clock. Notes 1: When the STP state is ended, a delay of approximately 8 ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2 kHz. Fig.8.14.4 State Transitions of System Clock Rev. 1.3 95 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 8.15 DISPLAY OSCILLATION CIRCUIT The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 6 of the OSD control register (address 00D016). 8.17 ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User’s Manual for details. 8.18 MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to SERIES 740 User’s Manual for details. 9. PROGRAMMING NOTES • The divide ratio of the timer is 1/(n+1). • Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. • After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. • An NOP instruction is needed immediately after the execution of a PLP instruction. • In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1µF) directly between the VCC pin–VSS pin, AVCC pin–VSS pin, and the VCC pin–CNVSS pin, using a thick wire. OSC1 OSC2 L C1 C2 Fig.8.15.1 Display Oscillation Circuit 8.16 AUTO-CLEAR CIRCUIT When a power source is supplied, the auto-clear function will operate by connecting the following circuit to the RESET pin. Circuit example 1 Vcc RESET Vss Circuit example 2 RESET Vcc Vss Note : Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage. Fig.8.16.1 Auto-clear Circuit Example Rev. 1.3 96 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 10. ABSOLUTE MAXIMUM RATINGS Symbol VCC, AVCC VI VI VO VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg Input voltage Input voltage Parametear Power source voltage VCC, AVCC CNVSS P00–P07, P10–P17, P20–P27, P30, P31, P50, P51, XIN, RESET, CVIN All voltages are based on VSS. Output transistors are cut off. Conditions Ratings –0.3 to 6 –0.3 to 6 –0.3–VCC + 0.3 –0.3–VCC + 0.3 –0.3 to 13 0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 0 to 1 (See note 2) 0 to 10 (See note 3) Ta = 25 °C 550 –10 to 70 –40 to 125 Unit V V V V V mA mA mA mA mA mW °C °C Output voltage P06, P07, P10–P17, P20–P27, P30, P31, P52–P55, XOUT Output voltage P00–P05 Circuit current Circuit current Circuit current Circuit current Circuit current P10–P17, P20–P27, P30, P31 P52–P55 P06, P07, P10, P15–P17, P20–P23, P26, P27, P52–P55 P11–P14 P00–P05 P24, P25, P30, P31 Power dissipation Operating temperature Storage temperature 11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Symbol VCC, AVCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) f(XCIN) fOSC fhs1 fhs2 fhs3 fhs4 VI Parametear Power source voltage (See note 4) Power source voltage HIGH Input voltage HIGH Input voltage LOW Input voltage LOW Input voltage P00–P07, P10–P17, P20–P27, P30, P31, P50, P51, RESET, XIN SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) P00–P07, P10–P17, P20–P27, P30, P31 SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) P50, P51, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK Limits Min. 4.5 0 0.8 VCC 0.7 VCC 0 0 0 Typ. 5.0 0 Max. 5.5 0 VCC VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 1 10 7.9 29 26.5 8.0 32 27.0 8.1 35 27.0 100 1 400 15.262 1.5 15.734 2.0 16.206 2.5 Unit V V V V V V V mA mA mA mA mA MHz kHz MHz kHz MHz kHz kHz V LOW Input voltage (See note 6) HIGH average output current (See note1) P10–P17, P20–P27, P30, P31, P52–P55 LOW average output current (See note 2) P06, P07, P10, P15–P17, P20–P23, P26, P27, P52–P55 LOW average output current (See note 2) P11–P14 LOW average output current (See note 2) P00–P05 LOW average output current (See note 3) P24, P25, P30, P31 Oscillation frequency (for CPU operation) (See note 5) XIN Oscillation frequency (for sub-clock operation) Oscillation frequency (for OSD) Input frequency Input frequency Input frequency Input frequency Input amplitude video signal SCLK SCL1, SCL2 Horizontal sync. signal of video signal CVIN XCIN OSC1 TIM2, TIM3, INT1, INT2, INT3 Rev. 1.4 97 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol Parametear Test conditions OSD OFF Data slicer OFF OSD ON Data slicer ON Min. Limits Typ. 15 30 60 Max. 30 mA 45 200 Unit Test circuit VCC = 5.5V, f(XIN) = 8MHz System operation VCC = 5.5V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = “0”, CM6 = “1”) VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32 kHz, Low-power dissipation mode set (CM5 = “0”, CM6 = “1”) µA 1 ICC Power source current Wait mode 2 25 4 100 mA µA Stop mode VOH VOL HIGH output voltage LOW output voltage P10–P17, P20–P27, P30, P31, P52–P55, P00–P07, P10, P15–P17, P20–P23, P26, P27, P52–P55 P24, P25, P30, P31 P11–P14 VCC = 5.5V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V VCC = 5.0 V IOL = 3 mA IOL = 6 mA 2.4 1 10 V 0.4 V 2 LOW output voltage LOW output voltage VT+ –VT– 3.0 0.4 0.6 0.5 1.3 V 3 Hysteresis (See note 6) RESET, P50, P51, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK, SCL1, SCL2, SDA1, SDA2 HIGH input leak current P06, P07, P10–P17, P20–P27, P30, P31, RESET, P50, P51, HIGH input leak current P00–P07, P10–P17, P20–P27, P30, P31, P50, P51, RESET HIGH output leak current P00–P05 I2C-BUS • BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) IIZH VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VI = 12 V VCC = 4.5 V 5 µA 4 IIZL 5 µA 4 IOZH RBS 10 130 µA Ω 5 6 Notes 1: The total current that flows out of the IC must be 20 mA or less. 2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less. 3: The total average input current for ports P30, P31, P24 and P25 and AVCC–VSS to IC must be 20 mA or less. 4: Connect 0.1 µF or more capacitor externally between the power source pins VCC–VSS and AVCC–VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally between the pins VCC–CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins. 7: Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports • When the same limits: I/O port name. • When the limits of functins except ports are different from I/O port limits: function pin name. Rev. 1.4 98 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER + Power source voltage 1 A Icc XIN 8.00 MHz OSC1 XOUT Vcc 2 4.5 V V cc Each output pin OSC2 VOH Vss Vss IOH or IOL V or VO L Pin VCC is made the operation state and is measured the current, with a ceramic resonator. After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL, each pin is measured. 3 5.0 V 4 5.5 V Vcc Vcc IIZH or IIZL A Each input pin Each input pin Vss Vss 5.5 V 5 6 4.5V Vcc IOZH Each output pin A 12 V Vcc SCL1 or SDA1 A RBS IBS SCL2 or SDA2 Vss Vss VBS After setting each output pin OFF state, each pin is measured RBS = VBS/IBS Fig.12.1 Measure Circuits Rev. 1.3 99 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 13. A-D CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol — — — V0T VFST Resolution Non-linearity error Differencial non-linearity error Zero transition error Full-scale transition error IOL (SUM) = 0 mA Parameter Test conditions Limits Min. Typ. Max. 6 ±1 ±0.9 2 –2 Unit bits LSB LSB LSB LSB 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Symbol tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition 0 4.0 300 250 4.7 4.0 Parameter Standard clock mode High-speed clock mode Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit µs µs µs ns µs µs ns ns µs µs Note: Cb = total capacitance of 1 bus line SDA tHD;STA tSU;STO tBUF tLOW P SCL S tR tF Sr P tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA S : Start condition Sr : Restart condition P : Stop condition Fig.14.1 Definition Diagram of Timing on Multi-master I2C-BUS Rev. 1.3 100 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 15. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37272EFSP M37272E8SP M37272E8FP Name of Programming Adapter PCA7429G02 PCA7429G02 PCA7427 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 15.1 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 15.1 Programming and Testing of One Time PROM Version Rev. 1.3 101 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 16. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: • Mask ROM Order Confirmation Form • Mark Specification Form • Data to be written to ROM, in EPROM form (three identical copies) or FDK When using EPROM: 28-pin DIP Type 27512 32-pin DIP Type 27C101 Rev. 1.4 102 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 17. MASK CONFIRMATION FORM GZZ–SH55–37B < 91A0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC Receipt ) Issuance signature Date: Section head Supervisor signature signature SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP Note : Please fill in all items marked V. Company name Customer Date issued Date : TEL ( Submitted by Supervisor V V1. Confirmation Specify the name of the product being ordered. Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by a floppy disk. Microcomputer name : Ordering by EPROMs If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37272M6-XXXSP M37272M6-XXXFP Checksum code for entire EPROM EPROM type (indicate the type used) 27512 EPROM address (hexadecimal notation) 140016 3BFF16 A00016 FFFF16 (1) Set “FF16” in the shaded area. 1/3 Rev. 1.3 103 6543210987654321 6543210987654321 6543210987654321 6543210987654321 OSDROM 000016 000F16 Product nameASCII code: 'M37272M6-' 6543210987654321 6543210987654321 6543210987654321 6543210987654321 Data ROM (24K) MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH55–37B < 91A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP MITSUBISHI ELECTRIC (2) Write the ASCII codes that indicate the product name of “M37272M6–” to addresses 000016 to 000F16. Addresses 000016 to 000F16 store the product name. Address ASCII codes ‘M37272M6-’ are listed on the right. 000016 The addresses and data are in hexadecimal nota000116 tion. 000216 Note: If the name of the product contained in the 000316 EPROMs does not match the name on the mask 000416 ROM confirmation form, the ROM processing is 000516 disabled. Please make sure the data is written 000616 correctly. 000716 Address ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘2’ = 3216 ‘7’ = 3716 ‘2’ = 3216 ‘M’ = 4D16 ‘6’ = 3616 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘–’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code Mask file name (hexadecimal notation) .MSK (equal or less than eight characters) V2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (42P4B for M37272M6-XXXSP , 42P2R for M37272M6-XXXFP) and attach to the mask ROM confirmation form. V3. Comments 2/3 Rev. 1.3 104 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH55–37B < 91A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP MITSUBISHI ELECTRIC Font data must be stored in the proper OSD ROM address according to the following table. OSD ROM address of character font data OSD ROM address bit Line number / Character code / Font bit AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 Line number Character code Font bit Line number = 0A 16 to 1D16 Character code = 00 16 to FF 16 (Do not set 7F 16 and 80 16.) Font bit = 0: Left font 1: Right font Example) The font data “60” (shaded area ) of the character code “AA 2 16” is stored in address 0010010101010100 =2554 16. Left font Line number 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 Right font DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Character code “AA 16” Notes 1 : The 80-byte addresses corresponding to the character code “7F 16” and “80 16” in OSD ROM are the test data storning area. Set “FF 16” to the area (We stores the test data to this area and the different data from “FF 16” is stored for the actual products.) The test data storing area : addresses 1000 16 + (4 + 2n) ! 10016 + FE 16 to 1000 16 + (5 + 2n) ! 10016 + 0116 (n = 0 to 19) addresses 14FE 16 to 1501 16 addresses 16FE 16 to 1701 16 • • • addresses 38FE 16 to 3901 16 addresses 3AFE 16 to 3B01 16 2 : The character code “09 16” is used for “transparent space” when displaying Closed Caption. Therefore, set “00 16” to the 40-byte addresses corresponding to the character code “09 16.” The transparent space font data storing area : addresses 1000 16 + (4 + 2n) ! 10016 + 1216 to 1000 16 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19) addresses 1412 16 and 1413 16 addresses 1612 16 and 1613 16 • • • addresses 3812 16 and 3813 16 addresses 3A12 16 and 3A13 16 3/3 Rev. 1.3 105 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH55–38B < 91A0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC Receipt ) Issuance signature Date: Section head Supervisor signature signature SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP Note : Please fill in all items marked V. Company name Customer Date issued Date : TEL ( Submitted by Supervisor V V1. Confirmation Specify the name of the product being ordered. Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by a floppy disk. Microcomputer name : Ordering by EPROMs If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used) 27512 EPROM address M37272M8-XXXSP M37272M8-XXXFP (hexadecimal notation) 140016 3BFF16 800016 FFFF16 (1) Set “FF16” in the shaded area. 106 6543210987654321 1 6543210987654321 6543210987654321 654321098765432 OSDROM 000016 000F16 Product nameASCII code: 'M37272M8-' 6543210987654321 6543210987654321 1 6543210987654321 654321098765432 Data ROM (32K) 1/3 Rev. 1.3 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH55–38B < 91A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP MITSUBISHI ELECTRIC (2) Write the ASCII codes that indicate the product name of “M37272M8–” to addresses 000016 to 000F16. Addresses 000016 to 000F16 store the product Address name. 000016 ASCII codes ‘M37272M8-’ are listed on the right. 000116 The addresses and data are in hexadecimal nota000216 tion. Note: If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. 000316 000416 000516 000616 000716 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘2’ = 3216 ‘7’ = 3716 ‘2’ = 3216 ‘M’ = 4D16 ‘8’ = 3816 ‘–’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code Mask file name (hexadecimal notation) .MSK (equal or less than eight characters) V2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (42P4B for M37272M8-XXXSP , 42P2R for M37272M8-XXXFP) and attach to the mask ROM confirmation form. V3. Comments 2/3 Rev. 1.3 107 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH55–38B < 91A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP MITSUBISHI ELECTRIC Font data must be stored in the proper OSD ROM address according to the following table. OSD ROM address of character font data OSD ROM address bit Line number / Character code / Font bit AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 Line number Character code Font bit Line number = 0A 16 to 1D16 Character code = 00 16 to FF 16 (Do not set 7F 16 and 80 16.) Font bit = 0: Left font 1: Right font Example) The font data “60” (shaded area ) of the character code “AA 2 16” is stored in address 0010010101010100 =2554 16. Left font Line number 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 Right font DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Character code “AA 16” Notes 1 : The 80-byte addresses corresponding to the character code “7F 16” and “80 16” in OSD ROM are the test data storning area. Set “FF 16” to the area (We stores the test data to this area and the different data from “FF 16” is stored for the actual products.) The test data storing area : addresses 1000 16 + (4 + 2n) ! 10016 + FE16 to 1000 16 + (5 + 2n) ! 10016 + 01 16 (n = 0 to 19) addresses 14FE 16 to 1501 16 addresses 16FE 16 to 1701 16 • • • addresses 38FE 16 to 3901 16 addresses 3AFE 16 to 3B01 16 2 : The character code “09 16” is used for “transparent space” when displaying Closed Caption. Therefore, set “00 16” to the 40-byte addresses corresponding to the character code “09 16.” The transparent space font data storing area : addresses 1000 16 + (4 + 2n) ! 10016 + 1216 to 1000 16 + (4 + 2n) ! 10016 + 13 16 (n = 0 to 19) addresses 1412 16 and 1413 16 addresses 1612 16 and 1613 16 • • • addresses 3812 16 and 3813 16 addresses 3A12 16 and 3A13 16 3/3 Rev. 1.3 108 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH56–32B < 91A1 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC Receipt ) Issuance signature Date: Section head Supervisor signature signature SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP Note : Please fill in all items marked V. Company name Customer Date issued Date : TEL ( Submitted by Supervisor V V1. Confirmation Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by a floppy disk. Ordering by EPROMs If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used) 27C101 EPROM address (hexadecimal notation) 600016 FFFF16 1140016 13BFF16 1FFFF16 (1) Set “FF16” in the shaded area. Rev. 1.5 109 76543210987654321 76543210987654321 76543210987654321 Data ROM (40K) 000016 000F16 Product nameASCII code: 'M37272MA-' 76543210987654321 6543210987654321 76543210987654321 76543210987654321 7 76543210987654321 76543210987654321 76543210987654321 OSDROM 1/3 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH56–32B < 91A1 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP MITSUBISHI ELECTRIC (2) Write the ASCII codes that indicate the product name of “M37272MA–” to addresses 0000 16 to 000F 16. Addresses 000016 to 000F16 store the product name. ASCII codes ‘M37272MA-’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 0001 16 000216 000316 Note: If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = ‘7’ = ‘2’ = ‘7’ = ‘2’ = ‘A’ = 3316 3716 3216 3716 3216 4116 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘–’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 ‘M’ = 4D16 Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code Mask file name (hexadecimal notation) .MSK (equal or less than eight characters) V2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (42P4B for M37272MA-XXXSP) and attach to the mask ROM confirmation form. V3. Comments 2/3 Rev. 1.5 110 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH56–32B < 91A1 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP MITSUBISHI ELECTRIC Font data must be stored in the proper OSD ROM address according to the following table. OSD ROM address of character font data OSD ROM address bit Line number / Character code / Font bit AD16AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 0 0 Line number Character code Font bit Line number = 0A16 to 1D16 Character code = 0016 to FF16 (Do not set 7F16 and 8016.) Font bit = 0 :Left font : : 1 :Right font Example) The font data “60” (shaded area ) of the character code “AA16” is stored in address 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 =1255416. Left font Line number 0A16 0B16 0C16 0D16 0E16 0 F1 6 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 Right font DB 7 DB 6 DB 5DB 4 DB 3 DB 2 DB 1 DB 0 DB 7 DB 6 DB 5 DB 4 DB 3DB 2 DB 1 DB 0 Character code “AA16” Notes 1 : The 80-byte addresses corresponding to the character code “7F16” and “8016” in OSD ROM are the test data storning area. Set “FF16” to the area (We stores the test data to this area and the different data from “FF16” is stored for the actual products.) The test data storing area : addresses 1100016 + (4 + 2n) ! 10016 + FE16 to 1100016 + (5 + 2n) ! 10016 + 0116 (n = 0 to 19) addresses 114FE16 to 1150116 addresses 116FE16 to 1170116 • • • addresses 138FE16 to 1390116 addresses 13AFE16 to 13B0116 2 : The character code “0916” is used for “transparent space” when displaying Closed Caption. Therefore, set “0016” to the 40-byte addresses corresponding to the character code “0916.” The transparent space font data storing area : addresses 1100016 + (4 + 2n) ! 10016 + 1216 to 1100016 + (4 + 2n) ! 10016 + 1316 (n = 0 to 19) addresses 1141216 and 1141316 addresses 1161216 and 1161316 • • • addresses 1381216 and 1381316 addresses 13A1216 and 13A1316 3/3 Rev. 1.5 111 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 18. MARK SPECIFICATION FORM Rev. 1.3 112 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Rev. 1.3 113 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Rev. 1.3 113 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 20. APPENDIX Pin Configuration (TOP VIEW) P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2 P25 AVCC HLF VHOLD CVIN CNVSS XIN XOUT VSS 1 2 3 4 5 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VC C M37272M6/M8/MA-XXXSP M37272E8/EFSP 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Outline 42P4B P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/AD4 P07/INT1 P23/TIM3 P24/TIM2 P25 AVCC HLF VHOLD CVIN CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/AD1/INT3 P16/AD2 P17/AD3 P30/AD5 P31/AD6 RESET P26/OSC1/XCIN P27/OSC2/XCOUT VCC Outline 42P2R-A/E M37272M6/M8-XXXFP M37272E8FP Rev. 1.4 115 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Memory Map s M37272M6/M8-XXXSP/FP, M37272E8SP/FP 000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 053F16 05BF16 Not used OSD RAM (128 bytes) (See note) 080016 087F16 Not used OSD ROM (10K bytes) 140016 3BFF16 Not used Zero page SFR1 area 1000016 M37272M6XXXSP/FP RAM (1024 bytes) M37272M8XXXSP/FP, M37272E8SP/FP RAM (1152 bytes) SFR2 area Not used ROM correction function Vector 1: address 030016 Vector 2: address 032016 M37272M8XXXSP/FP, M37272E8SP/FP ROM (32K bytes) M37272M6XXXSP/FP ROM (24K bytes) Not used 800016 A00016 FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.3 OSD RAM. Rev. 1.4 116 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s M37272MA-XXXSP, M37272EFSP 000016 00BF16 00C016 00FF16 010016 01FF16 020016 020F16 030016 032016 Zero page SFR1 area 1000016 RAM (1472 bytes) SFR2 area Not used ROM correction functrion Vector 1: address 030016 Vector 2: address 032016 Not used Not used 06FF16 OSD RAM (128 bytes) (See note) 080016 087F16 Not used 100016 OSD ROM (10K bytes) M37272EFSP ROM (60K bytes) 1140016 13BFF16 600016 Not used M37272MA-XXXSP ROM (40K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.3 OSD RAM. Rev. 1.3 117 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Memory Map of Special Function Register (SFR) s SFR1 Area (addresses C016 to DF16) 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Indeterminate immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register b7 Bit allocation b0 b7 State immediately after reset b0 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) T3SC P31 P30 P31CP30C P31D P30D 0 0 0 Port P5 (P5) OSD port control register (PF) PF7 PF5 PF4 PF3 PF2 0 0 0016 Caption data register 3 (CD3) Caption data register 4 (CD4) OSD control register (OC) Horizontal position register (HP) Block control register 1 (BC1) Block control register 2 (BC2) Vertical position register 1 (VP1) Vertical position register 2 (VP2) Window register 1 (WN1) Window register 2 (WN2) I/O polarity control register (PC) Raster color register (RC) CDL27 CDL26 CDL25 CDL24 CDL23CDL22 CDL21 CDL20 CDH27CDH26CDH25CDH24CDH23CDH22CDH21CDH20 0 OC6 OC5 OC4 OC3 OC2 OC1 OC0 HP 6 HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 BC17 BC16 BC15 BC14 BC13BC12 BC11 BC10 BC27 BC26 BC25 BC24 BC23BC22 BC21 BC20 VP17 VP16 VP15 VP14 VP13 VP12 VP11 VP10 VP27 VP26 VP25 VP24 VP23 VP22 VP21 VP20 WN17 WN16 WN15 WN14 WN13WN12 WN11 WN10 WN27 WN26 WN25 WN24 WN23WN22 WN21 WN20 0 RC7 P C6 P C5 P C4 P C3 P C2 P C1 P C0 0 0 RC4 RC3 RC2 RC1 RC0 Interrupt input polarity control register (RE) INT3 INT2 INT1 0016 0016 ) 0016 (See note 1 ? 0016 ? 0016 ? 0016 000?? 0016 ? ? ? 0016 0016 ? ? ? 0016 0016 ? ? ? ? ? ? 4016 0016 ? ? 0016 0016 0016 0016 (See note 2 ) Notes 1: This is only M37272MA-XXXSP and M37272EFSP. 2: As for M37272M6/M8-XXXSP/FP and M37272E8SP/FP, the reset value is ? (indeterminate). Rev. 1.4 118 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s SFR1 Area (addresses E016 to FF16) 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Indeterminate immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Bit allocation 1 0 1 0 0 1 b0 b7 DSC20 State immediately after reset 0 ? 0016 0? 0016 0016 0016 0916 00 0016 0016 0016 ? 0016 ?0 0016 0716 FF16 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 3C16 0016 0016 0016 0016 ? 0 b0 Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) Caption data register 1 (CD1) Caption data register 2 (CD2) Clock run-in detect register (CRD) Data clock position register (DPS) Caption position register (CPS) Data slicer test register 2 Data slicer test register 1 0 DSC12DSC11DSC10 DSC25 DSC24 DSC23 ? ? CDL17 CDL16 CDL15 CDL14 CDL13 CDL12 CDL11 CDL10 CDH17CDH16CDH15CDH14CDH13CDH12CDH11CDH10 CRD7 CRD6 CRD5 CRD4 CRD3 DPS7 DPS6 DPS5 DPS4 DPS3 0 1 0 0 0 ? CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0 0 0 0 Synchronous signal counter register (HC) Serial I/O register (SIO) Serial I/O mode register (SM) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 5 (T5) Timer 6 (T6) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) HC5 HC4 HC3 HC2 HC1 HC0 0 SM6 SM5 0 ADC14 SM3 SM2 SM1 SM0 ADC12 ADC11 ADC10 0 0 0 0 0 0 ADC25 ADC24 ADC23 ADC22ADC21 ADC20 TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB 0 0 0 0 0 ? I2C clock control register (S2) CM7 CM6 CM5 1 1 CM2 0 0 CPU mode register (CPUM) IN3R VSCR OSDRTM4R TM3R TM2R TM1R Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD ACK ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT 0 TM56RIICR IN2R CKR S1R DSR IN1R CK 0 IN3E VSCEOSDE TM4E TM3E TM2E TM1E TM56CTM56E IICE IN2E CKE S1E DSE IN1E Rev. 1.3 119 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER s SFR2 Area (addresses 20016 to 20F16) 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Indeterminate immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 Register b7 Bit allocation b0 b7 State immediately after reset ? ? ? ? ? ? ? ? b0 PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) 0016 0016 PWM mode register 1 (PM1) PWM mode register 2 (PM2) ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) RC1 RC0 PM13 PM10 ? ? ? 0 0 PM25 PM24 PM23 PM22 PM21 PM20 ?0 0016 0016 0016 0016 0016 0016 ? ? ? 0 Rev. 1.3 120 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Internal State of Processor Status Register and Program Counter at Reset : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation N V T B D I Z C State immediately after reset b0 b7 b0 ?????1?? Contents of address FFFF16 Contents of address FFFE16 Rev. 1.3 121 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 11 00 Bit position Bit attributes(Note 2) Values immediately after reset release (Note 1) CPU mode register (CPUM) (CM) [Address 00FB16] Name Processor mode bits 0, 1 (CM0, CM1) B Functions b1 b0 A f t er r e R W RW 0 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 1 0 RW RW RW RW 2 Stack page selection bit (See note) (CM2) 0: 0 page 1: 1 page 3, 4 Fix these bits to “1.” 5 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “1.” b7 b6 6, 7 Clock switch bits (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned Notes 1: Values immediately after reset release 0 ••••••••••••••••••“0” after reset release 1 ••••••••••••••••••“1” after reset release Indeterminate•••Indeterminate after reset release 2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R••••••Read W••••••Write W ••••••Write enabled R ••••••Read enabled – ••••••Read disabled – ••••••Write disabled V ••••••“0” can be set by software, but “1” cannot be set. Rev. 1.3 122 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00C116, 00C316, 00C516 Port Pi Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i=0,1,2) [Addresses 00C1 16, 00C316, 00C516] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Address 00C716 Port P3 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (P3D) [Address 00C7 16] B 0 1 2 3 Name Port P3 direction register Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode After reset R W 0 0 0 0 0 0 RW RW RW RW R— RW Port P30 output structure selection bit (P30C) Port P31 output structure selection bit (P30C) 0 : CMOS output 1 : N-channel open-drain output 0 : CMOS output 1 : N-channel open-drain output 4, 5, Nothing is assigned. These bits are write disable bits. 7 When these bits are read out, the values are “0.” 6 Timer 3 count source selection bit (T3SC) Refer to Timer section. Rev. 1.3 123 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00CB16 OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 OSD port control register (PF ) [Address 00CB16] B Name Functions After reset R W 0 R— RW RW RW RW R— RW 0, 1 Fix these bits to “0.” 2 3 4 5 6 7 Port P52 output signal selection bit (PF2) Port P53 output signal selection bit (PF3) Port P54 output signal selection bit (PF4) Port P55 output signal selection bit (PF5) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P53 output 0 0 0 0 0 0 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “0.” Port P10 output signal selection bit (PF7) 0 : Port P10 output 1 : OUT2 signal output Address 00D016 OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 OSD control register (OC) [Address 00D0 16] B 0 1 2 3 Name OSD control bit (OC0) (See note) Automatic solid space control bit (OC1) Window control bit (OC2) CC mode clock selection bit (OC3) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : OFF 1 : ON 0 : OFF 1 : ON 0 : Data slicer clock 1 : Clock from OSC1 pin 0 : Data slicer clock 1 : Clock from OSC1 pin b6 b5 After reset R W 0 0 0 0 0 RW RW RW RW RW 4 OSD mode clock selection bit (OC4) 5, 6 OSC1 clock selection bit (OC5, OC6) 0 0: 32 kHz oscillating 0 1: Do not set. 1 0: LC oscillating, Ceramic oscillating 1 1: Do not set. 0 RW 7 Fix this bit to “0.” 0 RW Note: Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next V SYNC. Rev. 1.3 124 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00D116 Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00D1 16] Functions 0 Horizontal display start Horizontal display start positions 128 steps (00 16 to 7F 16) to position control bits 6 (HP0 to HP6) (1 step is 4T OSC) 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Note: The setting value synchronizes with the V SYNC. B Name After reset R W 0 RW 0 R— Address 00D216, 00D316 Block Control register i b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1, 2) [Addresses 00D2 B Name b1 b0 16 and 00D3 16] After reset Functions 0 0 1 1 b4 RW 0, 1 Display mode selection bits (BCi0, BCi1) (See note 1) 2, 3 Dot size selection bits (BCi2, BCi3) 0: Display OFF 1: CC mode 0: OSD mode (Border OFF) 1: OSD mode (Border ON) b3 b2 Pre-divide Ratio 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Dot Size Indeterminate R W Indeterminate R W 0 !2 4 Pre-divide ratio selection bit (BCi4) 1 !3 1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H 1Tc ! 1/2H Indeterminate 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H RW 5 OUT1/OUT2 output control 0: OUT1 output control 1: OUT2 output control bit (BCi5) (See note 1) 6 Vertical display start position control bit (BCi6) 7 Window top/bottom boundary control bit (BCi7) BC16: Block 1 BC26: Block 1 BC17: Window top boundary BC27: Window bottom boundary Indeterminate R W Indeterminate R W Indeterminate R W Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.” Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.” 2: Tc is OSD clock cycle divided in pre-divide circuit. 3: H is HSYNC. Rev. 1.3 125 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00D416, 00D516 Vertical Position Register i b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D416, 00D516] B Name Vertical display start position control bits (VPi0 to VPi7) (See note) Functions Vertical display start position = 2 TH ! (BCi6 ! 16 + n) (n: setting value, TH: HSYNC cycle, BCi6: bit 6 of block control register i) After reset RW 0 to 7 Inderterminate R W Note: Set values except “0016” to VPi when BCi6 is “0.” Address 00D616 Window Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Window register 1 (WN1) [Address 00D616] B Name Window top boundary control bits (WN10 to WN17) Functions Window top border position = 2 TH ! (BC17 ! 16 + n) (n: setting value, TH: HSYNC cycle, BC17: bit 7 of block control register 1) After reset RW 0 to 7 Inderterminate R W Notes 1: Set values except “0016” to WN1 when BC17 is “0.” 2: Set values fit for the following condition: WN1 < WN2. Address 00D716 Window Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Window register 2 (WN2) [Address 00D716] B Name Window bottom boundary control bits (WN20 to WN27) Functions Window bottom border position = 2 TH ! (BC27 ! 16 + n) (n: setting value, TH: HSYNC cycle, BC27: bit 7 of block control register 2) After reset RW 0 to 7 Inderterminate R W Note: Set values fit for the following condition: WN1 < WN2. Rev. 1.3 126 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00D816 I/O Polarity Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 I/O polarity control register (PC) [Address 00D8 16] B 0 1 2 3 4 5 Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2) OUT1 output polarity switch bit (PC3) OUT2 output polarity switch bit (PC4) Display dot line selection bit (PC5) (See note) Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0:“ “ 1:“ “ ” at even field ” at odd field ” at even field ” at odd field After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW 6 7 Field determination flag (PC6) Fix this bit to “0.” 0 : Even field 1 : Odd field 1 0 R— RW Note: Refer to the corresponding figure (8.11.14). Address 00D916 Raster Color Register b7 b6 b5 b4 b3 b2 b1 b0 00 Raster color register (RC) [Address 00D9 16] B 0 1 2 3 Name Raster color R control bit (RC0) Raster color G control bit (RC1) Raster color B control bit (RC2) Raster color OUT1 control bit (RC3) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset RW RW RW RW RW RW 0 0 0 0 0 4 Raster color OUT2 control bit (RC4) 5, 6 Fix these bits to “0.” 0 : OSC1/X CIN, OSC2/X COUT 1 : P2 6, P2 7 0 0 RW RW 7 Port function selection bit (RC7) Note: Either OSD clock source or 32 kHz oscillating clock is selected by bits 5 and 6 of the OSD control register. Rev. 1.3 127 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00DC16 Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register (RE) [Address 00DC 16] B 0 4 5 4 to 7 Name INT1 polarity switch bit (INT1) INT2 polarity switch bit (INT2) INT3 polarity switch bit (INT3) Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity After reset 0 0 0 0 RW RW RW RW R— Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Address 00E016 Data Slicer Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 01100 Data slicer control register 1(DSC1) [Address 00E016] B 0 Name Functions 0: Stopped 1: Operating 0: F 2 1: F1 0: Video signal 1: HSYNC signal After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW Data slicer and timing signal generating circuit control bit (DSC10) 1 Selection bit of data slice reference voltage generating field (DSC11) 2 Reference clock source selection bit (DSC12) 3, 4 Fix these bits to “0.” 5, 6 Fix these bits to “1.” 7 Fix this bit to “0.” Definition of fields 1 (F 1) and 2 (F 2) F1: Hsep Vsep F2: Hsep Vsep Rev. 1.3 128 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00E116 Data Slicer Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 1 Data slicer control register 2 (DSC2) [Address 00E116] B 0 Name Caption data latch completion flag 1 (DSC20) Functions After reset RW 0: Data is not latched yet Indeterminate R — and a clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. 0 Read-only 0: F2 1: F1 0: Method (1) 1: Method (2) 0: Match 1: Mismatch RW 1 2 3 4 Fix this bit to “1.” Test bit Field determination flag(DSC23) Vertical synchronous signal (Vsep) generating method selection bit (DSC24) V-pulse shape determination flag (DSC25) Fix this bit to “o.” Test bit Read-only Indeterminate R — Indeterminate R — 0 RW 5 6 7 Indeterminate R — 0 RW Indeterminate R — Definition of fields 1 (F 1) and 2 (F 2) F1: Hsep Vsep F2: Hsep Vsep Address 00E416 Clock Run-in Detect Register b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register (CRD) [Address 00E4 16] B 0 to 2 3 to 7 Test bits Name Read-only Functions After reset R W 0 R— Clock run-in detection bit (CRD3 to CRD7) Number of reference clocks to be counted in one clock run-in pulse period. 0 R— Rev. 1.3 129 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00E516 Data Clock Position Register b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 Data clock position register (DPS) [Address 00E516] B 0 1 2 3 4 to 7 Name Fix this bit to “0.” Fix this bit to “1.” Fix this bit to “0.” Data clock position set bits (DPS3 to DPS7) Functions After reset R W 1 0 0 1 0 RW RW RW RW Address 00E616 Caption Position Register b7 b6 b5 b4 b3 b2 b1 b0 Caption Position Register (CPS) [Address 00E616] B 0 to 4 5 Name Caption position bits(CPS0 to CPS4) Caption data latch completion flag 2 (CPS5) Functions After reset 0 RW RW 0: Data is not latched yet and a Indeterminate R — clock-run-in is not determined. 1: Data is latched and a clock-run-in is determined. Refer to the corresponding Table (Table 8.10.1). 0 RW 6, 7 Slice line mode specification bits (in 1 field) (CPS6, CPS7) Address 00E916 Sync Pulse Counter Register b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (HC) [Address 00E9 16] B 0 to 4 5 Name Count value (HC0 to HC4) Functions After reset 0 RW R— Count source (HC5) 0: HSYNC signal 1: Composite sync signal 0 RW 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 R— Rev. 1.3 130 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00EB16 Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Serial I/O mode register (SM) [Address 00EB16] B Name 0, 1 Internal synchronous clock selection bits (SM0, SM1) After reset R W Functions RW 0 b1 b0 0 0: f(XIN)/4 or f(XCIN)/4 0 1: f(XIN)/16 or f(XCIN)/16 1 0: f(XIN)/32 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/64 2 3 Synchronous clock selection bit (SM2) Port function selection bit (SM3) 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT 0 0 RW RW 4 Fix this bit to “0.” 5 Transfer direction selection bit (SM5) 0: LSB first 1: MSB first 0 0 0 0 RW RW RW RW 6 Transfer clock input 0: Input signal from SIN pin pin selection bit (SM6) 1: Input signal from SOUT pin 7 Fix this bit to “0.” Address 00EC16 A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EC16] B 0 to 2 Name Analog input pin selection bits (ADC10 to ADC12) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0: Do not set. 1: After reset R W 0 RW 3 4 5 to 7 This bit is a write disable bit. When this bit is read out, the value is “0.” Storage bit of comparison result (ADC14) 0: Input voltage < reference voltage 1: Input voltage > reference voltage 0 Indeterminate 0 R— RW R— Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are “0.” Rev. 1.3 131 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00ED16 A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00ED 16] B 0 to 5 Name D-A converter set bits (ADC20 to ADC25) b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc After reset 0 RW RW 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R— 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” Address 00F416 Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F4 16] B Name 0 Timer 1 count source selection bit 1 (TM10) 1 2 3 4 Timer 2 count source selection bit 1 (TM11) Timer 1 count stop bit (TM12) Timer 2 count stop bit (TM13) Timer 2 count source selection bit 2 (TM14) Timer 1 count source selection bit 2 (TM15) Timer 5 count source selection bit 2 (TM16) Timer 6 internal count source selection bit (TM17) After reset R W Functions 0: f(XIN)/16 or f(X CIN)/16 (See note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 1 overflow 0: f(XIN)/4096 or f(X CIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 5 overflow 0 RW 0 0 0 RW RW RW 5 0 RW 6 0 0 RW RW 7 Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Rev. 1.3 132 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00F516 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F5 16] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C7 16) 0 0 1 1 1, 4 Timer 4 count source selection bits (TM21, TM24) b4 0 0 1 1 b0 0 : f(X IN)/16 or f(X CIN)/16 (See note) 1 : f(X CIN) 0: 1 : External clock from TIM3 pin b1 0 : Timer 3 overflow signal 1 : f(X IN)/16 or f(X CIN)/16 (See note) 0 : f(X IN)/2 or f(X CIN)/2 (See note) 1 : f(X CIN) 0 RW After reset R W 0 RW 2 3 5 6 7 Timer 3 count stop bit (TM22) Timer 4 count stop bit (TM23) Timer 5 count stop bit (TM25) Timer 6 count stop bit (TM26) Timer 5 count source selection bit 1 (TM27) 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Count source selected by bit 6 of TM1 0 0 0 0 0 RW RW RW RW RW Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Address 00F616 I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616] 2 B 0 to 7 Name D0 to D7 Functions This is an 8-bit shift register to store receive data and write transmit data. After reset RW Indeterminate R W Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Rev. 1.3 133 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00F716 I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00F716] B 0 Name Read/write bit (RBW) Functions The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) After reset R W 0 R— 1 to 7 Slave address (SAD0 to SAD6) The address data is compared. 0 RW Address 00F816 I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00F816] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = “0 ” 1 : Last bit = “1 ” (See note) After reset R W Indeterminate 0 0 R— R— R— R— RW RW RW 0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note) 0 1 0 0 (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Rev. 1.3 134 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00F916 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D address 00F916) B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 :8 1 :7 0 :6 1 :5 0 :4 1 :3 0 :2 1 :1 After reset R W 0 RW 3 4 5 I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD) 0 :Disabled 1 :Enabled 0 :Addressing mode 1 :Free data format 0 :7-bit addressing format 1 :10-bit addressing format b7 b6 Connection port (See note) 0 0 :None 0 1 :SCL1, SDA1 1 0 :SCL2, SDA2 1 1 :SCL1, SDA1 SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. Address 00FA16 I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2 : address 00FA 16) B 0 to 4 Name Functions After reset R W 0 SCL frequency control Setup value Standard clock High speed mode clock mode of CCR4– bits CCR0 (CCR0 to CCR4) Setup disabled Setup disabled 00 to 02 03 04 05 06 1D 1E 1F Setup disabled Setup disabled RW 333 250 400 (See note) 100 83.3 17.2 16.6 16.1 166 34.5 33.3 32.3 0 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) (at φ = 4 MHz, unit : kHz) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock ... 500/CCR value 1000/CCR value RW RW RW 6 7 0 0 Note: At 4000kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Rev. 1.3 135 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00FB16 CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00 11 CPU mode register (CM) [Address 00FB16] Name 0, 1 Processor mode bits (CM0, CM1) B Functions b1 b0 After reset R W 0 RW 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW RW 2 Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page 3, 4 Fix these bits to “1.” 5 XCOUT drivability selection bit (CM5) 6 Main Clock (XIN–XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: XIN–XOUT selected (high-speed mode) 1: XCIN–XCOUT selected (high-speed mode) 1 0 0 RW Note: This bit is set to “1” after the reset release. Address 00FC16 Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 : No interrupt request issued Timer 1 interrupt request bit (TM1R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 2 interrupt request bit (TM2R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 3 interrupt request bit (TM3R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 4 interrupt request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit (OSDR) 0 : No interrupt request issued VSYNC interrupt request bit (VSCR) 1 : Interrupt request issued INT3 external interrupt 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV R— V: “0” can be set by software, but “1” cannot be set. Rev. 1.3 136 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00FD16 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B 0 1 2 Name INT1 external interrupt request bit (INIR) Data slicer interrupt request bit (DSR) Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV RW Serial I/O interrupt request bit (S1R) 3 f(XIN)/4096 interrupt request bit (CKR) 4 INT2 external interrupt request bit (IN2R) 5 Multi-master I2C-BUS interrupt request bit (IICR) 6 Timer 5 • 6 interrupt request bit (TM56R) 7 Fix this bit to “0.” V: “0” can be set by software, but “1” cannot be set. Address 00FE16 Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name 0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) OSD interrupt enable bit 4 (OSDE) 5 VSYNC interrupt enable bit (VSCE) 6 INT3 external interrupt enable bit (IN3E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R— 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Rev. 1.3 137 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 00FF16 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 Name INT1 external interrupt enable bit (IN1E) Data slicer interrupt enable bit (DSE) Serial I/O interrupt enable bit (S1E) f(XIN)/4096 interrupt enable bit (CKE) INT2 external interrupt enable bit (IN2E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6 After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW 5 Multi-master I2C-BUS interface interrupt enable bit (IICE) 6 Timer 5 • 6 interrupt enable bit (TM56E) 7 Timer 5 • 6 interrupt switch bit (TM56C) 0 0 RW RW Address 020816 PWM Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PM1) [Address 020816] B 0 Name PWM counts source selection bit (PM10) Functions 0 : Count source supply 1 : Count source stop After reset R W 0 RW 1, 2 Nothing is assigned. These bits are write disable bits. Indeterminate R — When these bits are read out, the values are “0.” 3 PWM output polarity selection bit (PM13) 0 : Positive polarity 1 : Negative polarity 0 RW 4 Nothing is assigned. These bits are write disable bits. Indeterminate R — to When these bits are read out, the values are “0.” 7 Rev. 1.3 138 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Address 020916 PWM Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 PWM mode register 2 (PM2) [Address 0209 16] B Name 0 P00/PWM0 output selection bit (PM20) 1 2 3 4 5 P01/PWM1 output selection bit (PM21) P02/PWM2 output selection bit (PM22) P03/PWM3 output selection bit (PM23) P04/PWM4 output selection bit (PM24) P05/PWM5 output selection bit (PW25) Functions 0 : P0 0 output 1 : PWM0 output 0 : P0 1 output 1 : PWM1 output 0 : P0 2 output 1 : PWM2 output 0 : P0 3 output 1 : PWM3 output 0 : P0 4 output 1 : PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 RW RW RW RW RW RW 6, 7 Fix these bits to “0.” Address 020E16 ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 ROM correction enable register (RCR) [Address 020E B 0 1 2 to 7 16] Name Vector 1 enable bit (RC0) Vector 2 enable bit (RC1) Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset 0 0 0 RW RW RW R— Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Rev. 1.3 139 MITSUBISHI MICROCOMPUTERS M37272M6/M8–XXXSP/FP, M37272MA–XXXSP M37272E8SP/FP, M37272EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 21. PACKAGE OUTLINE 42P4B EIAJ Package Code SDIP42-P-600-1.78 JEDEC Code – Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy Plastic 42pin 600mil SDIP 42 22 1 21 Symbol D e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15° A 42P2R-A/E EIAJ Package Code SSOP42-P-450-0.80 42 A1 L A2 Plastic 42pin 450mil SSOP JEDEC Code – Weight(g) 0.63 22 Lead Material Alloy 42 e e1 E c b2 HE E e1 F Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 – Symbol 1 21 A G D A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 L1 c z Z1 Detail G Detail F L I2 Rev. 1.4 140 MITSUBISHI MICROCOMPUTERS M37273M8–XXXSP, M37273MF–XXXSP M37273E8SP, M37273EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • • © 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Dec. 1999. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 1.1 First Edition of PDF File • Delete “PRELIMINALY” • Correct product name (head of P141). 1.3 Updated to Rev.1.3 (all pages) M37272M6/M8-XXXSP/FP, M37272MA-XXXSP, M37272E8SP/FP, M37272EFSP DATA SHEET Revision Description Rev. date 990201 9907 9912 ROM correction memory is included to RAM (P1, 5, 12, 13) ROM correction memory “Block” changed to “Vector” (P5, 12, 13, 48) P42/TIM2 pin changed to TIM2 pin (P23) Clock Run-in Detect Register (address 00EA16) changed to (address 00E416) (P56) OSD Control Register (OC) “f(XIN)” changed to “Do not set.” at OC5, OC6 = “1”, “1” (P63) Changed and added of Notes of OSD memory (P74) OSC1/XIN, OSC2/XOUT changed to OSC1/XCIN, OSC2/XCOUT at RC7 = “0” (P89) 1.4 Updated to Rev.1.4 (Top page and version up pages) PIN DESCRIPTION Outline 42P2R-A changed to 42P2R-A/E(P3, 115) ____________ 0003 PIN DESCRIPTION RESET RESET changed to RESET (P7) P52/R Functions “Ports P52-P57 are a 6-bit” changed to “Ports P52-P55 are a 4-bit” (P8) Figure 7.2 I/O Pin Block Diagram P52-P57, P6 changed to P52-P55 (P10) Figure 8.2.3 SFR1 Area CC16 Port P6 is delated. Add Note 1 (P14, 118) Figure 8.11.18 Color code is changed (P80) ____________ 10.ABSOLUTE MAXIMUM RATINGS VI RESET changed to RESET (P97) ____________ 11.RECOMMENDED OPERATING CONDITIONS VIL3 RESET changed to RESET (P97) ____________ 12.ELECTRIC CHARACTERISTICS VT+-VT- RESET changed to RESET (P98) ____________ IIZL RESET changed to RESET (P98) 16.DATA REQUIRED FOR MASK ORDERS “M37272M6/M8-XXXSP, ” changed to “M37272M6/M8-XXXSP/FP, ” (P102) 21.PACKAGE OUTLINE 42P2R-A changed to 42P2R-A/E(P140) 1.5 Updated to Rev.1.5 (Top page and version up pages) Mask confirmation form of M37272MA is updated (P109 to 111). 0008 (1/1)