To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
3858 Group
REJ03B0139-0111
Rev.1.11
Dec 18, 2008
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
●Clock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Watchdog timer ............................................................ 16-bit ✕ 1
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 12.5 MHz oscillation frequency)
In high-speed mode .................................................. 2.7 to 5.5 V
(at 6 MHz oscillation frequency)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 12.5 MHz oscillation frequency, at middle-speed mode)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Operating temperature range .................................... –20 to 85°C
The 3858 group is the 8-bit microcomputer based on the 740 family core technology.
The 3858 group is designed for the household products and office
automation equipment and includes serial interface functions, 8-bit
timer, 16-bit timer, and A/D converter.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time ................................ 0.32 µs
(at 12.5 MHz oscillation frequency)
●Memory size
ROM ............................................................................ 48 K bytes
RAM ............................................................................ 1.5 K bytes
●Programmable input/output ports ............................................ 34
●On-chip software pull-up resistor ...................................... Built-in
●Interrupts ................................................. 19 sources, 16 vectors
(external 8, internal 10, software 1)
●Timers ............................................................................. 8-bit ✕ 4
...................................................................................... 16-bit ✕ 2
●Serial interface
Serial I/O1 ................... 8-bit ✕ 1 (UART or Clock-synchronized)
Serial I/O2 .................................. 8-bit ✕ 1 (Clock-synchronized)
●PWM ............................................................................... 8-bit ✕ 1
●A/D converter ................................................. 8-bit ✕ 9 channels
APPLICATION
Office automation equipment, Factory automation equipment,
Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
2
42
3
4
5
6
7
8
9
10
40
39
38
37
11
12
13
14
15
16
17
18
19
20
21
41
M3858XGX-XXXSP/FP
VCC
VREF
AVSS
P44/INT3/PWM
P43/INT2/SCMP2
P42/INT1
P41/INT0
P40/CNTR1
P27/CNTR0/SRDY1
P26/SCLK1
P25/TxD
P24/RxD
P23/CNTR3
P22/CNTR2
CNVSS
P21/XCIN
P20/XCOUT
RESET
XIN
XOUT
VSS
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04/AN5
P05/AN6
P06/AN7
P07/AN8
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
P14(LED4)
P15(LED5)
P16(LED6)
P17(LED7)
Package type : PRDP0042BA-A (42P4B)
PRSP0042GA-A/B (42P2R-A/E)
Fig. 1 Pin configuration of M3858XGX-XXXSP/FP
REJ03B0139-0111
page 1 of 73
Rev.1.11
Dec 18, 2008
REJ03B0139-0111
page 2 of 73
Rev.1.11
20
Sub-clock
output
XCOUT
Sub-clock
input
XCIN
Fig. 2 Functional block diagram
Dec 18, 2008
3
AVSS
VREF
2
A/D
converter
(10)
Watchdog
timer
PWM
(8)
Reset
Clock generating circuit
19
Main-clock Main-clock
input
output
XIN
XOUT
I/O port P3
I/O port P4
P3(5)
38 39 40 41 42
INT0–
INT3
QzR O M
21
VSS
4 5 6 7 8
P4(5)
RAM
FUNCTIONAL BLOCK DIAGRAM
PC H
SI/O1(8)
C P U
1
VCC
PS
PC L
S
Y
X
A
18
RESET
CNTR2
CNTR1
CNTR0
Reset input
I/O port P2
9 10 11 12 13 14 16 17
P2(8)
XCIN
P1(8)
I/O port P1
22 23 24 25 26 27 28 29
XCOUT
Timer Z2( 16 )
Timer Z1( 16 )
P0(8)
SI/O2(8)
I/O port P0
30 31 32 33 34 35 36 37
Timer Y( 8 )
Timer X( 8 )
Prescaler X(8)
Prescaler Y(8)
Timer 2( 8 )
Timer 1( 8 )
Prescaler 12(8)
CNTR3
15
CNVSS
3858 Group
3858 Group
PIN DESCRIPTION
Table 1 Pin description
Pin
Functions
Name
Function except a port function
VCC, VSS
Power source
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
CNVSS
CNVSS input
•This pin controls the operation mode of the chip and is shared with the VPP pin which is the
power source input pin for programming the built-in QzROM.
VREF
Reference voltage
•Reference voltage input pin for A/D converter.
AVss
Analog power
source
Reset input
•Analog power source input pin for A/D converter.
•Connect to Vss.
Clock input
•Input and output pins for the clock generating circuit.
•Normally connected to VSS.
RESET
XIN
XOUT
Clock output
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04/AN5–P07/AN8
I/O port P0
•Reset input pin for active “L”.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
• Serial I/O2 function pin
•8-bit I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
• A/D converter input pin
•Pull-up control is enabled in a bit unit.
P10–P17
I/O port P1
P20/XCOUT
P21/XCIN
P22/CNTR2
P23/CNTR3
P24/RxD
P25/TxD
P26/SCLK1
I/O port P2
•P10 to P17 (8 bits) are enabled to output large current
for LED drive.
•8-bit I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS3-state output structure.
• Timer Z1 function pin
• Timer Z2 function pin
• Serial I/O1 function pin
•Pull-up control is enabled in a bit unit.
• Timer X function pin/
Serial I/O1 function pin
P27/CNTR0/
SRDY1
P30/AN0–
P34/AN4
• Sub-clock generating circuit I/O
pins (connect a resonator)
I/O port P3
•5-bit I/O port with the same function as port P0.
• A/D converter input pin
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
I/O port P4
•5-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
P44/INT3/PWM
REJ03B0139-0111
page 3 of 73
• Timer Y function pin
• Interrupt input pins
Rev.1.11
Dec 18, 2008
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
3858 Group
PART NUMBERING
Product name
M3858 8
G
C
–
XXX
SP
Package type
SP : PRDP0042BA-A
FP : PRSP0042GA-A/B
ROM number
–: Standard
Omitted in the shipped in blank version.
QzROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
9 : 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F : 61440 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of RAM is reserved areas;
they cannot be used as a user's ROM area.
Memory type
G : QzROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
Fig. 3 Part numbering
REJ03B0139-0111
page 4 of 73
Rev.1.11
Dec 18, 2008
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
3858 Group
GROUP EXPANSION
Packages
Renesas Technology plans to expand the 3858 group as follows.
PRDP0042BA-A ....................... 42-pin shrink plastic-molded SDIP
PRSP0042GA-A/B ............................. 42-pin plastic-molded SSOP
Memory Type
Support for QzROM version.
Memory Size
QzROM size ................................................................... 48 K bytes
RAM size ....................................................................... 1.5 K bytes
Memory Expansion Plan
ROM size (bytes)
60K
M38588GC
48K
32K
768
1024
1280
1536
3072
RAM size (bytes)
Fig. 4 Memory expansion plan
Table 2 List of products
Part number
M38588GC-XXXSP
M38588GC-XXXFP
M38588GCSP
M38588GCFP
REJ03B0139-0111
page 5 of 73
ROM size (bytes)
ROM size for User in ( )
49152
(49021)
RAM size (bytes)
49152
(49021)
Rev.1.11
Dec 18, 2008
1536
1536
Package
PRDP0042BA-A
PRSP0042GA-A/B
PRDP0042BA-A
PRSP0042GA-A/B
Remarks
Blank
3858 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
[Index Register X (X)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls (see Table 3).
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The 3858 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
REJ03B0139-0111
page 6 of 73
Rev.1.11
Dec 18, 2008
3858 Group
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
REJ03B0139-0111
page 7 of 73
Rev.1.11
Dec 18, 2008
3858 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
REJ03B0139-0111
page 8 of 73
Rev.1.11
I flag
SEC
Z flag
_
SEI
CLC
_
CLI
Dec 18, 2008
D flag
T flag
V flag
SED
B flag
_
SET
_
N flag
_
CLD
_
CLT
CLV
_
3858 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
1
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Fig. 7 Structure of CPU mode register
REJ03B0139-0111
page 9 of 73
Rev.1.11
Dec 18, 2008
3858 Group
MEMORY
Special Function Register (SFR) Area
ROM Code Protect Address (address FFDB16)
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Address FFDB16, which is the reserved ROM area of QzROM, is
the ROM code protect address. "0016" is written into this address
when selecting the protect bit write by using a serial programmer
or selecting protect enabled for writing shipment by Renesas
Technology corp.. When "0016" is set to the ROM code protect address, the protect function is enabled, so that reading or writing
from/to QzROM is disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial programmer.
As for the QzROM product shipped after writing, "0016" (protect
enabled) or "FF16" (protect disabled) is written into the ROM code
protect address when Renesas Technology corp. performs writing.
The writing of “0016 ” or “FF16 ” can be selected as ROM option
setup (“MASK option” written in the mask file converter) when ordering.
■ Notes
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Because the contents of RAM are indefinite at reset, set initial values before using.
RAM area
RAM size
(bytes)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
000016
SFR area
Zero page
004016
RAM
010016
XXXX16
Not used
YYYY16
ROM area
Reserved ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
Fig. 8 Memory map diagram
REJ03B0139-0111
page 10 of 73
Rev.1.11
Dec 18, 2008
(128 bytes)
ZZZZ16
ROM
FF0016
FFDB16
R eserved R O M area
(ROM code protect address)
FFDC16
FFFE16
FFFF16
Interrupt vector area
Reserved ROM area
Special page
3858 Group
000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Timer Z1 mode register (TZ1M)
000916
Port P4 direction register (P4D)
002916
Timer Z1 low-order (TZ1L)
000A16
002A16
Timer Z1 high-order (TZ1H)
000B16
002B16
Timer Z2 mode register (TZ2M)
000C16
002C16
Timer Z2 low-order (TZ2L)
000D16
002D16
Timer Z2 high-order (TZ2H)
000E16
002E16
Timer 12, X count source selection register (T12XCSS)
000F16
002F16
Timer Y, Z1 count source selection register (TYZ1CSS)
Port P0 pull-up control register (PULL0)
003016
Timer Z2 count source selection register (TZ2CSS)
001116
Port P1 pull-up control register (PULL1)
003116
001216
Port P2 pull-up control register (PULL2)
003216
001316
Port P3 pull-up control register (PULL3)
003316
001416
Port P4 pull-up control register (PULL4)
003416
AD control register (ADCON)
001516
Serial I/O2 control register 1 (SIO2CON1)
003516
AD conversion register (AD)
001616
Serial I/O2 control register 2 (SIO2CON2)
003616
Interrupt source selection register (INTSEL)
001716
Serial I/O2 register (SIO2)
003716
Reserved ✽
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O1 status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
PWM control register (PWMCON)
003D16
Interrupt request register 2 (IREQ2)
001E16
PWM prescaler (PREPWM)
003E16
Interrupt control register 1 (ICON1)
001F16
PWM register (PWM)
003F16
Interrupt control register 2 (ICON2)
001016
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
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3858 Group
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
By setting the port P0 pull-up control register (address 001016),
the port P1 pull-up control register (address 001116), the port P2
pull-up control register (address 001216), the port P3 pull-up control register (address 0013 16 ), or the port P4 pull-up control
register (address 001416 ), ports can control pull-up with a program. However, the contents of these registers do not affect ports
programmed as the output ports.
Table 5 I/O port function
Pin
Name
Input/Output
I/O Structure
Non-Port Function
Related SFRs
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04/AN5–P07AN8
Port P0
Input/output,
individual
bits
CMOS compatible
input level
CMOS 3-state output
Serial I/O2 function I/O
Serial I/O2 control register
A/D converter input
AD control register
AD input selection register
P10–P17
P20/XCOUT
P21/XCIN
P22/CNTR2
P23/CNTR3
P24/RxD
P25/TxD
P26/SCLK1
P27/CNTR0/SRDY1
Port P1
Port P2
Sub-clock generating
circuit
Timer Z1 function I/O
Timer Z2 function I/O
Serial I/O1 function I/O
CPU mode register
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
Port P3
(Note)
Port P4
(Note)
Timer X function I/O
Serial I/O1 function I/O
A/D converter input
Timer XY mode register
Serial I/O1 control register
AD control register
AD input selection register
Timer XY mode register
Interrupt edge selection
register
Interrupt edge selection
register
Serial I/O2 control register
Interrupt edge selection
register
PWM control register
Timer Y function I/O
External interrupt input
External interrupt input
SCMP2 output
P44/INT3/PWM
External interrupt input
PWM output
Note: When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
REJ03B0139-0111
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Rev.1.11
Dec 18, 2008
Timer Z1 mode register
Timer Z2 mode register
Serial I/O1 control register
Ref.No.
(1)
(2)
(3)
(4)
(13)
(5)
(6)
(7)
(8)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
3858 Group
(2) Port P01
(1) Port P00
Pull-up control bit
Pull-up control bit
P01/SOUT2 P-channel output disable bit
Direction
register
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(3) Port P02
(4) Port P03
Pull-up control bit
Pull-up control bit
P02/SCLK2 P-channel output disable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 port selection bit
SRDY2 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(6) Port P20
(5) Port P1
Pull-up control bit
Pull-up control bit
Port XC switch bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Oscillator
Port P21
(7) Port P21
Port XC switch bit
Pull-up control bit
Port XC switch bit
Direction
register
Data bus
(8) Ports P22,P23
Timer Z operating
mode bits
Bit 2
Bit 1
Bit 0
Pull-up control bit
Port latch
Direction
register
Data bus
Port latch
Sub-clock generating circuit input
Timer output
CNTR interrupt input
Fig. 10 Port block diagram (1)
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3858 Group
(9) Port P24
(10) Port P25
Pull-up control bit
Serial I/O1 enable bit
Receive enable bit
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus
Pull-up control bit
Direction
register
Port latch
Data bus
Port latch
Serial I/O1 input
Serial I/O1 output
(12) Port P27
(11) Port P26
Pull-up control bit
Pull-up control bit
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Pulse output mode
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Serial ready output
Serial I/O1 clock output
Timer output
External clock input
(14) Port P40
(13) Ports P04-P07, P30-P34
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Pulse output mode
Timer output
A/D converter input
CNTR1 interrupt
input
Analog input pin selection bit
Analog input port selection switch bit
(15) Ports P41,P42
(16) Port P43
Pull-up control bit
Serial I/O2 I/O
comparison signal control bit
Pull-up control bit
Direction
register
Data bus
CNTR0 interrupt
input
Direction
register
Port latch
Data bus
Interrupt input
Port latch
Serial I/O2 I/O
comparison signal output
Interrupt input
Fig. 11 Port block diagram (2)
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3858 Group
(17) Port P44
Pull-up control bit
PWM output enable bit
Direction
register
Data bus
Port latch
PWM output
Interrupt input
Fig. 12 Port block diagram (3)
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3858 Group
b7
b0
b7
Port P1 pull-up control register
(PULL1: address 001116)
P00 pull-up control bit
0: No pull-up
1: Pull-up
P01 pull-up control bit
0: No pull-up
1: Pull-up
P02 pull-up control bit
0: No pull-up
1: Pull-up
P03 pull-up control bit
0: No pull-up
1: Pull-up
P04 pull-up control bit
0: No pull-up
1: Pull-up
P05 pull-up control bit
0: No pull-up
1: Pull-up
P06 pull-up control bit
0: No pull-up
1: Pull-up
P07 pull-up control bit
0: No pull-up
1: Pull-up
P10 pull-up control bit
0: No pull-up
1: Pull-up
P11 pull-up control bit
0: No pull-up
1: Pull-up
P12 pull-up control bit
0: No pull-up
1: Pull-up
P13 pull-up control bit
0: No pull-up
1: Pull-up
P14 pull-up control bit
0: No pull-up
1: Pull-up
P15 pull-up control bit
0: No pull-up
1: Pull-up
P16 pull-up control bit
0: No pull-up
1: Pull-up
P17 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding bit of
the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set to
the port of which pull-up is selected.
b7
b0
Port P2 pull-up control register
(PULL2: address 001216)
P20 pull-up control bit
0: No pull-up
1: Pull-up
P21 pull-up control bit
0: No pull-up
1: Pull-up
P22 pull-up control bit
0: No pull-up
1: Pull-up
P23 pull-up control bit
0: No pull-up
1: Pull-up
P24 pull-up control bit
0: No pull-up
1: Pull-up
P25 pull-up control bit
0: No pull-up
1: Pull-up
P26 pull-up control bit
0: No pull-up
1: Pull-up
P27 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding bit of
the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set to
the port of which pull-up is selected.
Fig. 13 Structure of port registers (1)
REJ03B0139-0111
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Rev.1.11
b0
Port P0 pull-up control register
(PULL0: address 001016)
Dec 18, 2008
Note: Pull-up control is valid when the corresponding bit of
the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set to
the port of which pull-up is selected.
3858 Group
b7
b0
Port P3 pull-up control register
(PULL3: address 001316)
P30 pull-up control bit
0: No pull-up
1: Pull-up
P31 pull-up control bit
0: No pull-up
1: Pull-up
P32 pull-up control bit
0: No pull-up
1: Pull-up
P33 pull-up control bit
0: No pull-up
1: Pull-up
P34 pull-up control bit
0: No pull-up
1: Pull-up
Fix these bits to “0”.
Note: Pull-up control is valid when the corresponding bit of
the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set to
the port of which pull-up is selected.
b7
b0
Port P4 pull-up control register
(PULL4: address 001416)
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
Fix these bits to “0”.
Note: Pull-up control is valid when the corresponding bit of
the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set to
the port of which pull-up is selected.
Fig. 14 Structure of port registers (2)
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3858 Group
INTERRUPTS
The 3858 group's interrupts are a type of vector and occur by 16
sources among 19 sources: eight external, ten internal, and one
software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts except the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the interrupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Which of each combination of the following interrupt sources can
be selected by the interrupt source selection register (address
003916).
1. INT3 or Serial I/O2
2. Timer Z1 or CNTR2
3. Timer Z2 or CNTR3
4. CNTR0 or CNTR2
5. CNTR1 or CNTR3
REJ03B0139-0111
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Rev.1.11
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3858 Group
Table 6 Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
Reset (Note 2)
1
INT0
2
FFFB16
FFFA16
Timer Z1
3
FFF916
FFF816
CNTR2
Interrupt Request
Generating Conditions
Remarks
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
At timer Z1 underflow
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR2 input
INT1
4
FFF716
FFF616
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
INT2
5
FFF516
FFF416
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3
6
FFF316
FFF216
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
At completion of serial I/O2 data
transmission or reception
At timer Z2 underflow
Valid when serial I/O2 is selected
At detection of either rising or
falling edge of CNTR3 input
External interrupt
(active edge selectable)
Serial I/O2
Timer Z2
7
FFF116
FFF016
CNTR3
Timer X
8
FFEF16
FFEE16
At timer X underflow
Timer Y
9
10
FFED16
FFEC16
At timer Y underflow
FFEB16
FFEA16
At timer 1 underflow
STP release timer underflow
11
FFE916
FFE816
12
FFE716
FFE616
At timer 2 underflow
At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Serial I/O1
transmission
13
FFE516
FFE416
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
Valid when serial I/O1 is selected
CNTR0
14
FFE316
FFE216
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
Timer 1
Timer 2
Serial I/O1
reception
CNTR2
CNTR1
At detection of either rising or
falling edge of CNTR2 input
15
FFE116
FFE016
At detection of either rising or
falling edge of CNTR1 input
At detection of either rising or
falling edge of CNTR3 input
CNTR3
A/D converter
16
FFDF16
FFDE16
At completion of A/D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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External interrupt
(active edge selectable)
Non-maskable software interrupt
3858 Group
■ Notes
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 003A16)
Timer XY mode register (address 002316)
Timer Z1 mode register (address 002816)
Timer Z2 mode register (address 002B16)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 003616)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit
to “1”.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
④Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Fig. 15 Interrupt control
REJ03B0139-0111
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Dec 18, 2008
Interrupt request
3858 Group
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
Not used (returns “0” when read)
b7
b0
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C16)
b7
INT0 interrupt request bit
Timer Z1/CNTR2 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
INT3/Serial I/O2 interrupt request bit
Timer Z2/CNTR3 interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
b0
Interrupt control register 1
(ICON1 : address 003E16)
b7
INT0 interrupt enable bit
Timer Z1/CNTR2 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3/Serial I/O2 interrupt enable bit
Timer Z2/CNTR3 interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
b7
b0
Interrupt source selection register
(INTSEL: address 003616)
INT3/Serial I/O2 interrupt source selection bit
0 : INT3 interrupt
1 : Serial I/O2 interrupt
Timer Z1/CNTR2 interrupt source selection bit
0 : Timer Z1 interrupt
1 : CNTR2 interrupt
Timer Z2/CNTR3 interrupt source selection bit
0 : Timer Z2 interrupt
1 : CNTR3 interrupt
CNTR0/CNTR2 interrupt source selection bit
0 : CNTR0 interrupt
1 : CNTR2 interrupt
CNTR1/CNTR3 interrupt source selection bit
0 : CNTR1 interrupt
1 : CNTR3 interrupt
Not used (returns “0” when read)
Fig. 16 Structure of interrupt-related registers
REJ03B0139-0111
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Interrupt request register 2
(IREQ2 : address 003D16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
CNTR0/CNTR2 interrupt request bit
CNTR1/CNTR3 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b0
Interrupt control register 2
(ICON2 : address 003F16)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR0/CNTR2 interrupt enable bit
CNTR1/CNTR3 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
3858 Group
TIMERS
●8-bit Timers
Timer X and Timer Y
The 3858 group has four 8-bit timers: timer 1, timer 2, timer X, and
timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “00 16”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
●Timer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B 16). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), X IN is selected. When these bits are “10”
(low-speed mode), XCIN is selected.
●Prescaler 12
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register (address 002E16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN).
Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit.
●Prescaler X and prescaler Y
The prescaler X and prescaler Y count the output of the timer
divider or f(XCIN). The count source is selected by the timer 12, X
count source selection register (address 002E16) and the timer Y,
Z1 count source selection register (address 002F16) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN)
or f(XCIN); and f(XCIN).
REJ03B0139-0111
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The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 002316).
(1) Timer mode
●Mode selection
This mode can be selected by setting “00” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316).
When the timer reaches “0016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
(2) Pulse output mode
●Mode selection
This mode can be selected by setting “01” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR0/CNTR1 pin. Regardless of the timer counting or not
the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer.
When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address
002316) is “0”, the output starts with “H” level. When it is “1”, the
output starts with “L” level.
Switching the CNTR0 or CNTR1 active edge switch bit will reverse
the output level of the corresponding CNTR0 or CNTR1 pin.
■Precautions
Set the double-function port of CNTR0/CNTR1 pin and port P2 7/
P40 to output in this mode.
3858 Group
(3) Event counter mode
●Mode selection
This mode can be selected by setting “10” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR 0 or CNTR 1 pin. The
valid edge for the count operation depends on the CNTR0 active
edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6)
of the timer XY mode register (address 002316). When it is “0”, the
rising edge is valid. When it is “1”, the falling edge is valid.
■Precautions
Set the double-function port of CNTR0/CNTR1 pin and port P27/
P40 to input in this mode.
(4) Pulse width measurement mode
●Mode selection
This mode can be selected by setting “11” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
●Explanation of operation
When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address
002316) is “1”, the timer counts during the term of one falling edge
of CNTR0/CNTR1 pin input until the next rising edge of input (“L”
term). When it is “0”, the timer counts during the term of one rising
edge input until the next falling edge input (“H” term).
■Precautions
Set the double-function port of CNTR0/CNTR1 pin and port P27/
P40 to input in this mode.
The count operation can be stopped by setting “1” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316). The interrupt request bit
is set to “1” each time the timer underflows.
•Precautions when switching count source
When switching the count source by the timer 12, X and Y count
source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count
input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
REJ03B0139-0111
page 23 of 73
Rev.1.11
Dec 18, 2008
3858 Group
XIN
“00”
“01”
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
Clock for timer Y
Clock for timer 12
XCIN
Main clock
division ratio
selection bits
Count source
selection bit
Clock for timer X
“10”
Data bus
Prescaler X latch (8)
f(XCIN)
Pulse width
measurement
mode
Prescaler X (8)
CNTR0 active edge
switch bit
“0”
P27/CNTR0
Event
counter
mode
Timer X latch (8)
Timer mode
Pulse output mode
Timer X (8)
Timer X count stop bit
To CNTR0 interrupt
request bit
“1”
CNTR0 active
“1”
edge switch bit
“0”
Port P27
latch
Port P27
direction register
Pulse output mode
To timer X interrupt
request bit
Q
Toggle flip-flop T
Q
R
Timer X latch write pulse
Pulse output mode
Data bus
Count source selection bit
Clock for timer Y
Prescaler Y latch (8)
Pulse width
measurement
mode
f(XCIN)
Prescaler Y (8)
P40/CNTR1
CNTR1 active edge
switch bit
“0”
Event
counter
mode
Timer Y latch (8)
Timer mode
Pulse output mode
Timer Y (8)
To timer Y interrupt
request bit
Timer Y count stop bit
To CNTR1 interrupt
request bit
“1”
CNTR1 active
“1”
edge switch bit
Q
Toggle flip-flop T
Q
“0”
Port P40
latch
R
Timer Y latch write pulse
Pulse output mode
Port P40
direction register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Clock for timer 12
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt
request bit
To timer 1 interrupt
request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
REJ03B0139-0111
page 24 of 73
Rev.1.11
Dec 18, 2008
3858 Group
b7
b0
Timer XY mode register
(TM : address 002316)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge in event counter mode
1 : Interrupt at rising edge
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR1 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge in event counter mode
1 : Interrupt at rising edge
Count at falling edge in event counter mode
Timer Y count stop bit
0 : Count start
1 : Count stop
Fig. 18 Structure of timer XY mode register
REJ03B0139-0111
page 25 of 73
Rev.1.11
Dec 18, 2008
3858 Group
b7
b0
b7
b0
Timer 12, X count source selection register
(T12XCSS : address 002E16)
b7
Timer 12 count source selection bits
b3b2b1b0
0 0 0 0 : f(XIN)/2 or f(XCIN)/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCIN)/64
0 1 1 0 : f(XIN)/128 or f(XCIN)/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCIN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1 0 1 0:
1 0 1 1:
1 1 0 0:
Not used
1 1 0 1:
1 1 1 0:
1 1 1 1:
Timer Y count source selection bits
b3b2b1b0
0 0 0 0 : f(XIN)/2 or f(XCIN)/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCIN)/64
0 1 1 0 : f(XIN)/128 or f(XCIN)/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCIN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1 0 1 0 : f(XCIN)
1 0 1 1:
1 1 0 0:
Not used
1 1 0 1:
1 1 1 0:
1 1 1 1:
Timer X count source selection bits
b7b6b5b4
0 0 0 0 : f(XIN)/2 or f(XCIN)/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCIN)/64
0 1 1 0 : f(XIN)/128 or f(XCIN)/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCIN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1 0 1 0 : f(XCIN)
1 0 1 1:
1 1 0 0:
Not used
1 1 0 1:
1 1 1 0:
1 1 1 1:
Timer Z1 count source selection bits
b7b6b5b4
0 0 0 0 : f(XIN)/2 or f(XCIN)/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCIN)/64
0 1 1 0 : f(XIN)/128 or f(XCIN)/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCIN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1 0 1 0 : f(XCIN)
1 0 1 1:
1 1 0 0:
Not used
1 1 0 1:
1 1 1 0:
1 1 1 1:
b0
Timer Z2 count source selection register
(TZ2CSS : address 003016)
Timer Z2 count source selection bits
b3b2b1b0
0 0 0 0 : f(XIN)/2 or f(XCIN)/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCIN)/8
0 0 1 1 : f(XIN)/16 or f(XCIN)/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCIN)/64
0 1 1 0 : f(XIN)/128 or f(XCIN)/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCIN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1 0 1 0 : f(XCIN)
1 0 1 1:
1 1 0 0:
Not used
1 1 0 1:
1 1 1 0:
1 1 1 1:
Not used (returns “0” when read)
Fig. 19 Structure of timer 12, X, timer Y, Z1 and timer Z2 count source selection registers
REJ03B0139-0111
page 26 of 73
Timer Y, Z1 count source selection register
(TYZ1CSS : address 002F16)
Rev.1.11
Dec 18, 2008
3858 Group
Timer Z1
●16-bit Timer
(2) Event counter mode
The timer Z1 is a 16-bit timer. When the timer reaches “0000 16”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is
continued. When the timer underflows, the interrupt request bit
corresponding to the timer Z1 is set to “1”.
When reading/writing to the timer Z1, perform reading/writing to
both the high-order byte and the low-order byte. When reading the
timer Z1, read from the high-order byte first, followed by the loworder byte. Do not perform the writing to the timer Z1 between
read operation of the high-order byte and read operation of the
low-order byte. When writing to the timer Z1, write to the low-order
byte first, followed by the high-order byte. Do not perform the
reading to the timer Z1 between write operation of the low-order
byte and write operation of the high-order byte.
The timer Z1 can select the count source by the timer Z1 count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F16).
Timer Z1 can select one of seven operating modes by setting the
timer Z1 mode register (address 002816).
(1) Timer mode
●Mode selection
This mode can be selected by setting “000” to the timer Z1 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z1 mode register (address 002816).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
When an underflow occurs, the timer Z1/CNTR2 interrupt request
bit (bit 0) of the interrupt request register 1 (address 003C16) is set
to “1”.
●Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The timer count operation is started by setting “0” to the timer Z1
count stop bit (bit 6) of the timer Z1 mode register (address
002816).
When the timer reaches “000016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
REJ03B0139-0111
page 27 of 73
Rev.1.11
Dec 18, 2008
●Mode selection
This mode can be selected by setting “000” to the timer Z1 operating mode bits (bits 2 to 0) and setting “1” to the timer/event
counter mode switch bit (bit 7) of the timer Z1 mode register (address 002816).
The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z1 mode register (address
002816). When it is “0”, the rising edge is valid. When it is “1”, the
falling edge is valid.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR2 pin and port P22 to input in
this mode.
Figure 22 shows the timing chart of the timer/event counter mode.
(3) Pulse output mode
●Mode selection
This mode can be selected by setting “001” to the timer Z1 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z1 mode register (address 002816).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of
the timer Z1 mode register (address 0028 16) is “0”, the output
starts with “H” level. When it is “1”, the output starts with “L” level.
■Precautions
The double-function port of CNTR2 pin and port P22 is automatically set to the timer pulse output port in this mode.
The output from CNTR2 pin is initialized to the level depending on
CNTR2 active edge switch bit by writing to the timer.
When the value of the CNTR2 active edge switch bit is changed,
the output level of CNTR2 pin is inverted.
Figure 23 shows the timing chart of the pulse output mode.
3858 Group
(4) Pulse period measurement mode
(5) Pulse width measurement mode
●Mode selection
This mode can be selected by setting “010” to the timer Z1 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z1 mode register (address 002816).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse period measurement is completed, the timer Z1/
CNTR2 interrupt request bit (bit 1) of the interrupt request register
1 (address 003C16) is set to “1”.
●Explanation of operation
The cycle of the pulse which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer
Z1 mode register (address 002816) is “0”, the timer counts during
the term from one falling edge of CNTR2 pin input to the next falling edge. When it is “1”, the timer counts during the term from one
rising edge input to the next rising edge input.
When the valid edge of measurement completion/start is detected,
the 1’s complement of the timer value is written to the timer latch
and “FFFF16” is set to the timer.
Furthermore when the timer underflows, the timer Z1 interrupt request occurs and “FFFF 16” is set to the timer. When reading the
timer Z1, the value of the timer latch (measured value) is read.
The measured value is retained until the next measurement
completion.
■Precautions
Set the double-function port of CNTR2 pin and port P22 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse period).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during measurement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement
depends on the timer value just before measurement start.
Figure 24 shows the timing chart of the pulse period measurement
mode.
●Mode selection
This mode can be selected by setting “011” to the timer Z1 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z1 mode register (address 002816).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse widths measurement is completed, the timer Z1/
CNTR2 interrupt request bit (bit 1) of the interrupt request register
2 (address 003C16) is set to “1”.
●Explanation of operation
The pulse width which is input from the CNTR2 pin is measured.
When the CNTR 2 active edge switch bit (bit 5) of the timer Z1
mode register (address 002816) is “0”, the timer counts during the
term from one rising edge input to the next falling edge input (“H”
term). When it is “1”, the timer counts during the term from one
falling edge of CNTR2 pin input to the next rising edge of input (“L”
term).
When the valid edge of measurement completion is detected, the
1’s complement of the timer value is written to the timer latch.
When the valid edge of measurement completion/start is detected,
“FFFF16” is set to the timer.
When the timer Z1 underflows, the timer Z1 interrupt occurs and
“FFFF16” is set to the timer Z1. When reading the timer Z1, the
value of the timer latch (measured value) is read. The measured
value is retained until the next measurement completion.
■Precautions
Set the double-function port of CNTR2 pin and port P22 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse
widths).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during measurement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement
depends on the timer value just before measurement start.
Figure 25 shows the timing chart of the pulse width measurement
mode.
REJ03B0139-0111
page 28 of 73
Rev.1.11
Dec 18, 2008
3858 Group
(6) Programmable waveform generating mode
●Mode selection
This mode can be selected by setting “100” to the timer Z1 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z1 mode register (address 002816).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z1 mode register (address 002816) from the CNTR2 pin each
time the timer underflows.
Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform
from the CNTR2 pin.
■Precautions
The double-function port of CNTR2 pin and port P22 is automatically set to the programmable waveform generating port in this
mode.
Figure 26 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
●Mode selection
This mode can be selected by setting “101” to the timer Z1 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z1 mode register (address 002816).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the
INT1 active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1 interrupt
request bit (bit 1) of the interrupt request register 1 (address
003C16) is set to “1”.
●Explanation of operation
•“H” one-shot pulse; Bit 5 of timer Z1 mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at mode selection. When trigger generation (input signal to INT 1 pin) is
detected, “H” is output from the CNTR2 pin. When an underflow
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z1 register low-order and high-order.
When trigger generating is detected during timer count stop, al-
REJ03B0139-0111
page 29 of 73
Rev.1.11
Dec 18, 2008
though “H” is output from the CNTR2 pin, “H” output state continues because an underflow does not occur.
•“L” one-shot pulse; Bit 5 of timer Z1 mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at mode selection. When trigger generation (input signal to INT 1 pin) is
detected, “L” is output from the CNTR2 pin. When an underflow
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z1 low-order and high-order. When trigger generating is detected during timer count stop, although “L” is
output from the CNTR2 pin, “L” output state continues because an
underflow does not occur.
■Precautions
Set the double-function port of INT1 pin and port P42 to input in
this mode.
Set the double function port of CNTR2 pin and port P22 is automatically set to the programmable one-shot generating port in this mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR2 active edge switch bit is changed during
one-shot generating enabled or generating one-shot pulse, then
the output level from CNTR2 pin changes.
Figure 27 shows the timing chart of the programmable one-shot
generating mode.
■Notes regarding all modes
●Timer Z1 write control
Which write control can be selected by the timer Z1 write control
bit (bit 3) of the timer Z1 mode register (address 002816), writing
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected, the
value is set to the timer latch by writing data to the address of timer
Z1 and the timer is updated at next underflow. After reset release, the
operation “writing data to both the latch and the timer at the same
time” is selected, and the value is set to both the latch and the timer
at the same time by writing data to the address of timer Z1.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
●Timer Z1 read control
A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
However, a read-out of timer latch value is impossible.
●Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit.
●Switch of count source
When switching the count source by the timer Z1 count source selection bits, the value of timer count is altered in inconsiderable amount
owing to generating of thin pulses on the count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
●Usage of CNTR2 pin as normal I/O port P22
To use the CNTR2 pin as normal I/O port P22, set timer Z1 operating mode bits (b2, b1, b0) of timer Z1 mode register (address
002816) to “000”.
3858 Group
CNTR2 active edge
Data bus
switch bit
Programmable one-shot
“1”
P42/INT1
Programmable one-shot
generating circuit
Programmable one-shot
generating mode
generating mode
“0”
To INT1 interrupt
request bit
Programmable waveform
generating mode
D
Output level latch
Q
T
Pulse output mode
CNTR2 active edge
switch bit
S
Q
T
“0”
Q
“1”
Pulse output mode
“001”
“100”
“101”
Timer Z1 operating
mode bits
Timer Z1 low-order latch Timer Z1 high-order latch
Port P22
latch
Timer Z1 low-order
Timer Z1 high-order
To timer Z1 interrupt
request bit
Port P22
direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
“1”
P22/CNTR2
f(XCIN)
“0”
“0”
CNTR2 active edge
switch bit
Clock for
timer Z1
X IN
XCIN
Rev.1.11
Timer/Event
counter mode
switch bit
Timer Z1 count stop bit
Count source
Divider
selection bit
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Fig. 20 Block diagram of timer Z1
REJ03B0139-0111
page 30 of 73
To CNTR2 interrupt
request bit
“1”
Dec 18, 2008
3858 Group
b7
b0
Timer Z1 mode register
(TZ1M : address 002816)
Timer Z1 operating mode bits
b2b1b0
0 0 0 : Timer/Event counter mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform generating mode
1 0 1 : Programmable one-shot generating mode
1 1 0 : Not available
1 1 1 : Not available
Timer Z1 write control bit
0 : Writing data to both latch and timer simultaneously
1 : Writing data only to latch
Output level latch
0 : “L” output
1 : “H” output
CNTR2 active edge switch bit
0 : •Event counter mode: Count at rising edge
•Pulse output mode: Start outputting “H”
•Pulse period measurement mode: Measurement
between two falling edges
•Pulse width measurement mode: Measurement of
“H” term
•Programmable one-shot generating mode: After
start outputting “L”, “H” one-shot pulse generated
•Interrupt at falling edge
1 : •Event counter mode: Count at falling edge
•Pulse output mode: Start outputting “L”
•Pulse period measurement mode: Measurement
between two rising edges
•Pulse width measurement mode: Measurement of
“L” term
•Programmable one-shot generating mode: After
start outputting “H”, “L” one-shot pulse generated
•Interrupt at rising edge
Timer Z1 count stop bit
0 : Count start
1 : Count stop
Timer/Event counter mode switch bit (Note)
0 : Timer mode
1 : Event counter mode
Note: When selecting the modes except the timer/event
counter mode, set “0” to this bit.
Fig. 21 Structure of timer Z1 mode register
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3858 Group
FFFF16
TL
000016
TR
TR
TR
TL : Value set to timer latch
TR : Timer interrupt request
Fig. 22 Timing chart of timer/event counter mode
FFFF16
TL
000016
TR
TR
TR
TR
Waveform output
from CNTR2 pin
CNTR2
CNTR2
TL : Value set to timer latch
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig. 23 Timing chart of pulse output mode
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3858 Group
000016
T3
T2
T1
FFFF16
TR
FFFF16 + T1
TR
T2
T3
FFFF16
Signal input from
CNTR2 pin
CNTR2 CNTR2
CNTR2
CNTR2
CNTR2 of rising edge active
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
Fig. 24 Timing chart of pulse period measurement mode (Measuring term between two rising edges)
000016
T3
T2
T1
FFFF16
TR
Signal input from
CNTR2 pin
FFFF16 + T2
T3
T1
CNTR2
CNTR2
CNTR2
CNTR2 interrupt of rising edge active; Measurement of “L” width
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
Fig. 25 Timing chart of pulse width measurement mode (Measuring “L” term)
REJ03B0139-0111
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Dec 18, 2008
3858 Group
FFFF16
T3
L
T2
T1
000016
Signal output
from CNTR2 pin
L
T3
T1
T2
TR
TR
TR
TR
CNTR2
CNTR2
L : Timer initial value
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig. 26 Timing chart of programmable waveform generating mode
FFFF16
L
TR
Signal input from
INT1 pin
Signal output
from CNTR2 pin
L
TR
L
CNTR2
TR
L
CNTR2
L : One-shot pulse width
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig. 27 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating)
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3858 Group
Timer Z2
●16-bit Timer
(2) Event counter mode
The timer Z2 is a 16-bit timer. When the timer reaches “0000 16”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is
continued. When the timer underflows, the interrupt request bit
corresponding to the timer Z2 is set to “1”.
When reading/writing to the timer Z2, perform reading/writing to
both the high-order byte and the low-order byte. When reading the
timer Z2, read from the high-order byte first, followed by the loworder byte. Do not perform the writing to the timer Z2 between
read operation of the high-order byte and read operation of the
low-order byte. When writing to the timer Z2, write to the low-order
byte first, followed by the high-order byte. Do not perform the
reading to the timer Z2 between write operation of the low-order
byte and write operation of the high-order byte.
The timer Z2 can select the count source by the timer Z2 count
source selection bits of timer Z2 count source selection register
(bits 7 to 4 at address 003016).
Timer Z2 can select one of seven operating modes by setting the
timer Z2 mode register (address 002B16).
(1) Timer mode
●Mode selection
This mode can be selected by setting “000” to the timer Z2 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (address 002B16).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
When an underflow occurs, the timer Z2/CNTR3 interrupt request
bit (bit 5) of the interrupt request register 1 (address 003C16) is set
to “1”.
●Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The timer count operation is started by setting “0” to the timer Z2
count stop bit (bit 6) of the timer Z2 mode register (address
002B16).
When the timer reaches “000016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
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Rev.1.11
Dec 18, 2008
●Mode selection
This mode can be selected by setting “000” to the timer Z2 operating mode bits (bits 2 to 0) and setting “1” to the timer/event
counter mode switch bit (bit 7) of the timer Z2 mode register (address 002B16).
The valid edge for the count operation depends on the CNTR3 active edge switch bit (bit 5) of the timer Z2 mode register (address
002B16). When it is “0”, the rising edge is valid. When it is “1”, the
falling edge is valid.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR3 pin and port P23 to input in
this mode.
Figure 30 shows the timing chart of the timer/event counter mode.
(3) Pulse output mode
●Mode selection
This mode can be selected by setting “001” to the timer Z2 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (address 002B16).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR3 pin. When the CNTR3 active edge switch bit (bit 5) of
the timer Z2 mode register (address 002B16) is “0”, the output
starts with “H” level. When it is “1”, the output starts with “L” level.
■Precautions
The double-function port of CNTR3 pin and port P23 is automatically set to the timer pulse output port in this mode.
The output from CNTR3 pin is initialized to the level depending on
CNTR3 active edge switch bit by writing to the timer.
When the value of the CNTR3 active edge switch bit is changed,
the output level of CNTR3 pin is inverted.
Figure 31 shows the timing chart of the pulse output mode.
3858 Group
(4) Pulse period measurement mode
(5) Pulse width measurement mode
●Mode selection
This mode can be selected by setting “010” to the timer Z2 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (address 002B16).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse period measurement is completed, the timer Z2/
CNTR3 interrupt request bit (bit 1) of the interrupt request register
1 (address 003C16) is set to “1”.
●Explanation of operation
The cycle of the pulse which is input from the CNTR3 pin is measured. When the CNTR3 active edge switch bit (bit 5) of the timer
Z2 mode register (address 002B16) is “0”, the timer counts during
the term from one falling edge of CNTR3 pin input to the next falling edge. When it is “1”, the timer counts during the term from one
rising edge input to the next rising edge input.
When the valid edge of measurement completion/start is detected,
the 1’s complement of the timer value is written to the timer latch
and “FFFF16” is set to the timer.
Furthermore when the timer underflows, the timer Z2 interrupt request occurs and “FFFF 16” is set to the timer. When reading the
timer Z2, the value of the timer latch (measured value) is read.
The measured value is retained until the next measurement
completion.
■Precautions
Set the double-function port of CNTR3 pin and port P23 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse period).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during measurement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement
depends on the timer value just before measurement start.
Figure 32 shows the timing chart of the pulse period measurement
mode.
●Mode selection
This mode can be selected by setting “011” to the timer Z2 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (address 002B16).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse widths measurement is completed, the timer Z2/
CNTR3 interrupt request bit (bit 1) of the interrupt request register
1 (address 003C16) is set to “1”.
●Explanation of operation
The pulse width which is input from the CNTR3 pin is measured.
When the CNTR 3 active edge switch bit (bit 5) of the timer Z2
mode register (address 002B16) is “0”, the timer counts during the
term from one rising edge input to the next falling edge input (“H”
term). When it is “1”, the timer counts during the term from one
falling edge of CNTR3 pin input to the next rising edge of input (“L”
term).
When the valid edge of measurement completion is detected, the
1’s complement of the timer value is written to the timer latch.
When the valid edge of measurement completion/start is detected,
“FFFF16” is set to the timer.
When the timer Z2 underflows, the timer Z2 interrupt occurs and
“FFFF16” is set to the timer Z2. When reading the timer Z2, the
value of the timer latch (measured value) is read. The measured
value is retained until the next measurement completion.
■Precautions
Set the double-function port of CNTR3 pin and port P23 to input in
this mode.
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse
widths).
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during measurement.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement
depends on the timer value just before measurement start.
Figure 33 shows the timing chart of the pulse width measurement
mode.
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3858 Group
(6) Programmable waveform generating mode
●Mode selection
This mode can be selected by setting “100” to the timer Z2 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (address 002B16).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(X CIN); or f(XCIN) can be selected as the count
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z2 mode register (address 002B 16) from the CNTR 3 pin
each time the timer underflows.
Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform
from the CNTR3 pin.
■Precautions
The double-function port of CNTR3 pin and port P23 is automatically set to the programmable waveform generating port in this
mode.
Figure 34 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
●Mode selection
This mode can be selected by setting “101” to the timer Z2 operating mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z2 mode register (address 002B16).
●Count source selection
In high-, or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the
INT2 active edge selection bit (bit 2) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT2 pin is detected, the INT2 interrupt
request bit (bit 2) of the interrupt request register 1 (address
003C16) is set to “1”.
●Explanation of operation
•“H” one-shot pulse; Bit 5 of timer Z2 mode register = “0”
The output level of the CNTR3 pin is initialized to “L” at mode selection. When trigger generation (input signal to INT 2 pin) is
detected, “H” is output from the CNTR3 pin. When an underflow
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z2 register low-order and high-order.
When trigger generating is detected during timer count stop, al-
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Rev.1.11
Dec 18, 2008
though “H” is output from the CNTR3 pin, “H” output state continues because an underflow does not occur.
•“L” one-shot pulse; Bit 5 of timer Z2 mode register = “1”
The output level of the CNTR3 pin is initialized to “H” at mode selection. When trigger generation (input signal to INT 2 pin) is
detected, “L” is output from the CNTR3 pin. When an underflow
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z2 low-order and high-order. When trigger generating is detected during timer count stop, although “L” is
output from the CNTR3 pin, “L” output state continues because an
underflow does not occur.
■Precautions
Set the double-function port of INT2 pin and port P4 3 to input in
this mode.
Set the double function port of CNTR3 pin and port P23 is automatically set to the programmable one-shot generating port in this mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR3 active edge switch bit is changed during
one-shot generating enabled or generating one-shot pulse, then
the output level from CNTR3 pin changes.
Figure 35 shows the timing chart of the programmable one-shot
generating mode.
■Notes regarding all modes
●Timer Z2 write control
Which write control can be selected by the timer Z2 write control
bit (bit 3) of the timer Z2 mode register (address 002B16), writing
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected, the
value is set to the timer latch by writing data to the address of timer
Z2 and the timer is updated at next underflow. After reset release, the
operation “writing data to both the latch and the timer at the same
time” is selected, and the value is set to both the latch and the timer
at the same time by writing data to the address of timer Z2.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
●Timer Z2 read control
A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
However, a read-out of timer latch value is impossible.
●Switch of interrupt active edge of CNTR3 and INT2
Each interrupt active edge depends on setting of the CNTR3 active edge switch bit and the INT2 active edge selection bit.
●Switch of count source
When switching the count source by the timer Z2 count source selection bits, the value of timer count is altered in inconsiderable amount
owing to generating of thin pulses on the count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
●Usage of CNTR3 pin as normal I/O port P23
To use the CNTR3 pin as normal I/O port P23, set timer Z2 operating mode bits (b2, b1, b0) of timer Z2 mode register (address
002B16) to “000”.
3858 Group
CNTR3 active edge
Data bus
switch bit
Programmable one-shot
“1”
P43/INT2
Programmable one-shot
generating circuit
Programmable one-shot
generating mode
generating mode
“0”
To INT2 interrupt
request bit
Programmable waveform
generating mode
D
Output level latch
Q
T
Pulse output mode
CNTR3 active edge
switch bit
S
Q
T
“0”
Q
“1”
Pulse output mode
“001”
“100”
“101”
Timer Z2 operating
mode bits
Timer Z2 low-order latch Timer Z2 high-order latch
Port P23
latch
Timer Z2 low-order
Timer Z2 high-order
To timer Z2 interrupt
request bit
Port P23
direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
“1”
P23/CNTR3
f(XCIN)
“0”
“0”
CNTR3 active edge
switch bit
Clock for
timer Z2
X IN
XCIN
Rev.1.11
Timer/Event
counter mode
switch bit
Timer Z2 count stop bit
Count source
Divider
selection bit
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Fig. 28 Block diagram of timer Z2
REJ03B0139-0111
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To CNTR3 interrupt
request bit
“1”
Dec 18, 2008
3858 Group
b7
b0
Timer Z2 mode register
(TZ2M : address 002B16)
Timer Z2 operating mode bits
b2b1b0
0 0 0 : Timer/Event counter mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform generating mode
1 0 1 : Programmable one-shot generating mode
1 1 0 : Not available
1 1 1 : Not available
Timer Z2 write control bit
0 : Writing data to both latch and timer simultaneously
1 : Writing data only to latch
Output level latch
0 : “L” output
1 : “H” output
CNTR3 active edge switch bit
0 : •Event counter mode: Count at rising edge
•Pulse output mode: Start outputting “H”
•Pulse period measurement mode: Measurement
between two falling edges
•Pulse width measurement mode: Measurement of
“H” term
•Programmable one-shot generating mode: After
start outputting “L”, “H” one-shot pulse generated
•Interrupt at falling edge
1 : •Event counter mode: Count at falling edge
•Pulse output mode: Start outputting “L”
•Pulse period measurement mode: Measurement
between two rising edges
•Pulse width measurement mode: Measurement of
“L” term
•Programmable one-shot generating mode: After
start outputting “H”, “L” one-shot pulse generated
•Interrupt at rising edge
Timer Z2 count stop bit
0 : Count start
1 : Count stop
Timer/Event counter mode switch bit (Note)
0 : Timer mode
1 : Event counter mode
Note: When selecting the modes except the timer/event
counter mode, set “0” to this bit.
Fig. 29 Structure of timer Z2 mode register
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Dec 18, 2008
3858 Group
FFFF16
TL
000016
TR
TR
TR
TL : Value set to timer latch
TR : Timer interrupt request
Fig. 30 Timing chart of timer/event counter mode
FFFF16
TL
000016
TR
TR
TR
TR
Waveform output
from CNTR3 pin
CNTR3
CNTR3
TL : Value set to timer latch
TR : Timer interrupt request
CNTR3 : CNTR3 interrupt request
(CNTR3 active edge switch bit = “0”; Falling edge active)
Fig. 31 Timing chart of pulse output mode
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Dec 18, 2008
3858 Group
000016
T3
T2
T1
FFFF16
TR
FFFF16 + T1
TR
T2
T3
FFFF16
Signal input from
CNTR3 pin
CNTR3 CNTR3
CNTR3
CNTR3
CNTR3 of rising edge active
TR : Timer interrupt request
CNTR3 : CNTR3 interrupt request
Fig. 32 Timing chart of pulse period measurement mode (Measuring term between two rising edges)
000016
T3
T2
T1
FFFF16
TR
Signal input from
CNTR3 pin
FFFF16 + T2
T3
T1
CNTR3
CNTR3
CNTR3
CNTR3 interrupt of rising edge active; Measurement of “L” width
TR : Timer interrupt request
CNTR3 : CNTR3 interrupt request
Fig. 33 Timing chart of pulse width measurement mode (Measuring “L” term)
REJ03B0139-0111
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Rev.1.11
Dec 18, 2008
3858 Group
FFFF16
T3
L
T2
T1
000016
Signal output
from CNTR3 pin
L
T3
T1
T2
TR
TR
TR
TR
CNTR3
CNTR3
L : Timer initial value
TR : Timer interrupt request
CNTR3 : CNTR3 interrupt request
(CNTR3 active edge switch bit = “0”; Falling edge active)
Fig. 34 Timing chart of programmable waveform generating mode
FFFF16
L
TR
Signal input from
INT2 pin
Signal output
from CNTR3 pin
L
TR
L
CNTR3
TR
L
CNTR3
L : One-shot pulse width
TR : Timer interrupt request
CNTR3 : CNTR3 interrupt request
(CNTR3 active edge switch bit = “0”; Falling edge active)
Fig. 35 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating)
REJ03B0139-0111
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Rev.1.11
Dec 18, 2008
3858 Group
SERIAL INTERFACE
●SERIAL I/O1
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O1. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O1 control register
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive shift register
P24/RXD
Address 001A16
Receive interrupt request (RI)
Shift clock
Clock control circuit
P26/SCLK1
XIN
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
BRG count source selection bit
1/4
P27/SRDY1
F/F
Clock control circuit
Falling-edge detector
Shift clock
P25/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 36 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 37 Operation of clock synchronous serial I/O1 function
REJ03B0139-0111
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Rev.1.11
Dec 18, 2008
3858 Group
(2) Asynchronous Serial I/O (UART) Mode
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
Data bus
Address 001816
P24/RXD
Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Receive buffer register
Character length selection bit
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
P26/SCLK1
XIN
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
1/16
P25/TXD
Transmit shift register
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Data bus
Fig. 38 Block diagram of UART serial I/O1
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Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
3858 Group
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1
ST
D0
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
SP
D1
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
ST
Serial input RXD
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 39 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
REJ03B0139-0111
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[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
3858 Group
b7
b0
Serial I/O1 status register
(SIOSTS : address 001916)
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 40 Structure of serial I/O1 control registers
■Notes on serial interface
When setting the transmit enable bit of serial I/O1 to “1”, the serial
I/O1 transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence.
(1) Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
(2) Set the transmit enable bit to “1”.
(3) Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
REJ03B0139-0111
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b0
Serial I/O1 control register
(SIOCON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P24 to P27 operate as serial I/O1 pins)
3858 Group
●SERIAL I/O2
b7
The serial I/O2 can be operated only as the clock synchronous type.
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P0 1 /S OUT2 , P0 2 /S CLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the SOUT2 pin does
not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control register 2 to “1” when SCLK2 is “H” after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into
the active state.
Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the
transfer direction selection bit is MSB first. For the remaining bits, the
previously received data is shifted.
At transmit operation using the clock synchronous serial I/O, the SCMP2
signal can be output by comparing the state of the transmit pin SOUT2
with the state of the receive pin SIN2 in synchronization with a rise of
the transfer clock. If the output level of the SOUT2 pin is equal to the
input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”
is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16).
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 41.
REJ03B0139-0111
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b0
Serial I/O2 control register 1
(SIO2CON1 : address 001516)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
SRDY2 output enable bit
0: P03 pin is normal I/O pin
1: P03 pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2 ,P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001616)
Optional transfer bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: 1 bit
1: 2 bit
0: 3 bit
1: 4 bit
0: 5 bit
1: 6 bit
0: 7 bit
1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
0: P43 I/O
1: SCMP2 output
SOUT2 pin control bit (P01)
0: Output active
1: Output high-impedance
Fig. 41 Structure of Serial I/O2 control registers 1, 2
3858 Group
Internal synchronous
clock selection bits
1/8
XCIN
1/16
“10”
Divider
Main clock division ratio
selection bits (Note)
“00”
“01”
XIN
Data bus
1/32
1/64
1/128
1/256
P03 latch
Serial I/O2 synchronous
clock selection bit
“0”
SRDY2
“1”
SRDY2 output enable bit
Serial I/O2
synchronous clock
selection bit
“1”
Synchronous circuit
SCLK2
P03/SRDY2
“0”
External clock
P02 latch
Optional transfer bits (3)
“0”
P02/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
“1”
Serial I/O2 port selection bit
P01 latch
“0”
P01/SOUT2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P00/SIN2
P43 latch
“0”
D
P43/SCMP2/INT2
Q
“1”
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 42 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2
D0
D1
.
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 43 Timing chart of Serial I/O2
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3858 Group
SCMP2
SCLK2
SOUT2
SIN2
Judgement of I/O data comparison
Fig. 44 SCMP2 output operation
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3858 Group
PWM (PWM: Pulse Width Modulation )
PWM Operation
The 3858 group has a PWM function with an 8-bit
resolution, based on a signal that is the clock input X IN or that
clock input divided by 2.
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P4 4 . Set the PWM
period by the PWM prescaler, and set the “H” term of output pulse
by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) µs
(when f(XIN) = 8 MHz, count source selection bit = “0”)
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz, count source selection bit = “0”)
31.875 ✕ m ✕ (n+1)
µs
255
PWM output
T = [31.875 ✕ (n+1)] µs
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz,count source
selection bit = “0”)
Fig. 45 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
PWM prescaler
PWM register
Count source
selection bit
“0”
XIN
(XCIN at low-speed mode)
1/2
Port P44
“1”
Port P44 latch
PWM function
enable bit
Fig. 46 Block diagram of PWM function
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Rev.1.11
Dec 18, 2008
3858 Group
b7
b0
PWM control register
(PWMCON : address 001D16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
Fig. 47 Structure of PWM control register
A
B
B = C
T
T2
C
PWM output
T
PWM register
write signal
T
T2
(Changes “H” term from “A” to “B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 48 PWM output timing when PWM register or PWM prescaler is changed
■Note
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n+1
2 ✕ f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
n+1
f(XIN)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
REJ03B0139-0111
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Rev.1.11
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3858 Group
A/D CONVERTER
[AD Conversion Register (ADL)] 003516
b7
b0
AD control register
(ADCON : address 003416, initial value: 1016)
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/
D conversion.
Analog input pin selection bits
0 0 0 0: P30/AN0
0 0 0 1: P31/AN1
0 0 1 0: P32/AN2
0 0 1 1: P33/AN3
0 1 0 0: P34/AN4
0 1 0 1: P04/AN5
0 1 1 0: P05/AN6
0 1 1 1: P06/AN7
1 0 0 0: P07/AN8
[AD Control Register (ADCON)] 003416
The A/D control register controls the A/D converter. Bit 3 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during A/D conversion,
and changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
Fig. 49 Structure of AD control register
■Note on A/D converter
Channel Selector
The channel selector selects one of ports P30 /AN0 to P34 /AN4 ,
P04/AN5 to P07/AN8 and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the AD
conversion registers. When an A/D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A/D conversion.
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500 kHz or more during A/D conversion.
As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage,
accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value..
(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the
low temperature may become extremely low compared with that at
room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended.
Data bus
AD control register b7
(Address 003416)
b0
4
Comparator
AD conversion register
8
Resistor ladder
VREF
Fig. 50 Block diagram of A/D converter
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Rev.1.11
A/D interrupt request
A/D control circuit
Channel selector
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P04/AN5
P05/AN6
P06/AN7
P07/AN8
Dec 18, 2008
VSS
(Address 003516)
3858 Group
WATCHDOG TIMER
dog timer H. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction. Just after
releasing the stop mode, the watchdog timer restarts counting
(Note). When executing the WIT instruction, the watchdog timer
does not stop.
When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to “0”
by program. Bit 6 is “0” at reset.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
003916), each of watchdog timer H and L is set to “FF16”. Any instruction which generates a write signal such as the instructions of
STA, LDM, CLB and others can be used to write. The data of bits
6 and 7 are only valid when writing to the watchdog timer control
register. Each of watchdog timer is set to “FF16” regardless of the
written data of bits 0 to 5.
Bit 6 can be written to only once after reset release. After this bit is
written, it cannot rewritten because it is locked.
The necessary time after writing to the watchdog timer control register to an underflow of the watchdog timer H is shown as follows.
When bit 7 of the watchdog timer control register is “0”:
32 s at XCIN = 32.768 kHz frequency and
131.072 ms at XIN = 8 MHz frequency.
When bit 7 of the watchdog timer control register is “1”:
125 ms at XCIN = 32.768 kHz frequency and
512 µs at XIN = 8 MHz frequency.
Operation of Watchdog Timer
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer H. The reset is
released after waiting for a reset release time and the program is
processed from the reset vector address. Accordingly, programming is usually performed so that writing to the watchdog timer
control register may be started before an underflow of the watch-
Note: The watchdog timer continues to count for waiting for a stop mode release time. Do not generate an underflow of the watchdog timer H
during that time.
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
Data bus
“0”
“10”
Main clock division
ratio selection bits
(Note)
XIN
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer L (8)
1/16
“1”
“00”
“01”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction function selection bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 51 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
0: Entering Stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 52 Structure of Watchdog timer control register
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3858 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage must be between 2.7 V
and 5.5 V, and the oscillation must be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD 16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.54 V for VCC of 2.7 V.
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage; Vcc = 2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 53 Reset circuit example
XIN
φ
RESET
RESETOUT
?
?
Address
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except XIN and RESET are internals.
Fig. 54 Reset sequence
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3858 Group
Address Register contents
Address Register contents
(1)
Port P0 (P0)
000016
0016
(35) Timer Z1 mode register (TZ1M)
002816
0016
(2)
Port P0 direction register (P0D)
000116
0016
(36) Timer Z1 low-order (TZ1L)
002916
FF16
(3)
Port P1 (P1)
000216
0016
(37) Timer Z1 high-order (TZ1H)
002A16
FF16
(4)
Port P1 direction register (P1D)
000316
0016
(38) Timer Z2 mode register (TZ2M)
002B16
0016
(5)
Port P2 (P2)
000416
0016
(39) Timer Z2 low-order (TZ2L)
002C16
FF16
(6)
Port P2 direction register (P2D)
000516
0016
(40) Timer Z2 high-order (TZ2H)
002D16
FF16
(7)
Port P3 (P3)
000616
0016
(41) T im er 12, X count source selection register (T12X C S S) 002E16 0 0 1 1 0 0 1 1
(8)
Port P3 direction register (P3D)
000716
0016
(42) T im er Y, Z 1 count source selection register (TY Z 1C S S) 002F16 0 0 1 1 0 0 1 1
(9)
Port P4 (P4)
000816
0016
(43) T im er Z2 count source selection register (T Z 2C SS )
003016 0 0 0 0 0 0 1 1
(10) Port P4 direction register (P4D)
000916
0016
(44) AD control register (ADCON)
003416 0 0 0 1 0 0 0 0
(11) Port P0 pull-up control register (PULL0)
001016
0016
(45) AD conversion register (AD)
003516 X X X X X X X X
(12) Port P1 pull-up control register (PULL1)
001116
0016
(46) Interrupt source selection register (INTSEL)
003616
0016
(13) Port P2 pull-up control register (PULL2)
001216
0016
(47) MISRG
003816
0016
(14) Port P3 pull-up control register (PULL3)
001316
0016
(48) Watchdog timer control register (WDTCON)
003916 0 0 1 1 1 1 1 1
(15) Port P4 pull-up control register (PULL4)
001416
0016
(49) Interrupt edge selection register (INTEDGE)
003A16
(16) Serial I/O2 control register 1 (SIO2CON1)
001516
0016
(50) CPU mode register (CPUM)
003B16 0 1 0 0 1 0 0 0
(17) Serial I/O2 control register 2 (SIO2CON2)
001616 0 0 0 0 0 1 1 1
(51) Interrupt request register 1 (IREQ1)
003C16
0016
(18) Serial I/O2 register (SIO2)
001716 X X X X X X X X
(52) Interrupt request register 2 (IREQ2)
003D16
0016
(19) Transmit/Receive buffer register (TB/RB)
001816 X X X X X X X X
(53) Interrupt control register 1 (ICON1)
003E16
0016
(20) Serial I/O1 status register (SIOSTS)
001916 1 0 0 0 0 0 0 0
(54) Interrupt control register 2 (ICON2)
003F16
0016
(21) Serial I/O1 control register (SIOCON)
001A16
(22) UART control register (UARTCON)
001B16 1 1 1 0 0 0 0 0
(23) Baud rate generator (BRG)
001C16 X X X X X X X X
(24) PWM control register (PWMCON)
001D16
(25) PWM prescaler (PREPWM)
001E16 X X X X X X X X
(26) PWM register (PWM)
001F16 X X X X X X X X
(27) Prescaler 12 (PRE12)
002016
FF16
(28) Timer 1 (T1)
002116
0116
(29) Timer 2 (T2)
002216
FF16
(30) Timer XY mode register (TM)
002316
0016
(31) Prescaler X (PREX)
002416
FF16
(32) Timer X (TX)
002516
FF16
(33) Prescaler Y (PREY)
002616
FF16
(34) Timer Y (TY)
002716
FF16
0016
0016
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 55 Internal status at reset
REJ03B0139-0111
page 55 of 73
Rev.1.11
Dec 18, 2008
0016
X X X X X 1 X X
Processor status register
(PS)
Program counter
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
3858 Group
CLOCK GENERATING CIRCUIT
(2) Wait mode
The 3858 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT
(XCIN and XCOUT). Use the circuit constants in accordance with the
resonator manufacturer’s recommended values. No external resistor
is needed between XIN and XOUT since a feed-back resistor exists
on-chip. (An external feed-back resistor may be needed depending
on conditions.) However, an external feed-back resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
●Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
The sub-clock XCIN-XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
●Oscillation Control
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction.
When releasing the STP state, the input of the prescaler 12 and
timer 1 is connected to the count source which had set at executing the STP instruction and the prescaler 12 and timer 1 will start
counting. Set the timer 1 interrupt enable bit to “0” before executing
the STP instruction.
■Notes
• If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient
time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When
switching the mode between middle/high-speed and low-speed,
set the frequency on condition that f(XIN) > 3 × f(XCIN).
• When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
XCIN
XCOUT
XIN
XOUT
Rd (Note)
Rf
Rd
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit (bit 0 of
address 003816) is “0”, the prescaler 12 is set to “FF16” and timer
1 is set to “0116”. When the oscillation stabilizing time set after
STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the
prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer
1. Oscillator restarts when an external interrupt is received, but the
internal clock φ is not supplied to the CPU (remains at “H”) until
timer 1 underflows. The internal clock φ is supplied for the first
time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the
oscillator is restarted by reset, apply “L” level to the RESET pin
until the oscillation is stable since a wait time will not be generated.
CCIN
CCOUT
CIN
Notes : Insert a damping resistor if required.
The resistance will vary depending on the oscillator and
the oscillation drive capacity setting.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer's data sheet specifies
that a feedback resistor be added external to the chip
though a feedback resistor exists on-chip, insert a feedback
resistor between XIN and XOUT following the instruction.
Fig. 56 Ceramic resonator circuit
XCIN
XCOUT
Rf
XIN
Open
Rd
CCOUT
Vcc
Vss
Fig. 57 External clock input circuit
Rev.1.11
Dec 18, 2008
XOUT
External oscillation
circuit
CCIN
REJ03B0139-0111
page 56 of 73
COUT
3858 Group
[MISRG (MISRG)] 003816
b0
b7
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middlespeed mode automatic switch set bit to “1”, X IN oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
MISRG
(MISRG : address 003816)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 6.5 to 7.5 machine cycles
1: 4.5 to 5.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Note: When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address 003B16)
changes.
Fig. 58 Structure of MISRG
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note 1)
Low-speed
mode
(Note 4)
1/2
Divider
Prescaler 12
1/4
High-speed or
middle-speed
mode
(Note 3)
Timer 1
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
R
Reset
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source
before executing the STP instruction is supplied as the count source at executing STP instruction.
3: When bit 0 of MISRG = “0”, the prescaler 12 is set to "FF16" and timer 1 is set to "0116".
When bit 0 of MISRG = “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to
the prescaler 12 and timer 1.
4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Fig. 59 System clock generating circuit block diagram (Single-chip mode)
REJ03B0139-0111
page 57 of 73
Rev.1.11
Dec 18, 2008
3858 Group
Reset
”
“0
4
→
M
C ”←
0”
“1 6 → “
CM ” ←
“1
Middle-speed mode
(f(φ) = 1 MHz)
CM
“0 4
CM ” ←
“1 6 → “
”←
1”
→
“0
”
CM6
“1” ←→ “0”
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM
“0 7
”
CM ←
→
“1 6
“1
”←
”
→
“0
”
Middle-speed mode
automatic switch set bit
"1"
Low-speed mode
(f(φ)=16 kHz)
CM7 = 1
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM5
“1” ←→ “0”
Middle-speed mode
automatic switch start bit
"1"
High-speed mode
(f(φ) = 4 MHz)
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7
“1” ←→ “0”
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM4
“1” ←→ “0”
High-speed mode
(f(φ) = 4 MHz)
CM6
“1” ←→ “0”
CM4
“1” ←→ “0”
Middle-speed mode
(f(φ) = 1 MHz)
Low-speed mode
(f(φ)=16 kHz)
CM7 = 1
CM6 = 0
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 ( High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : After STP instruction is released, the count source which had set by bit 2 (timer 12 count source selection bit) of the timer count source set
register at executing the STP instruction is supplied to timer 1. Accordingly, when bit 0 of MISRG is “0” and the timer 12 count source
selection bit is “0” (f(XIN)/16 or f(XCIN)/16), a delay of approximately 1 ms occurs automatically in the high/middle-speed mode. A delay of
approximately 256 ms occurs automatically in the low-speed mode (at f(XIN) = 8 MHz, f(XCIN) = 32 kHz). When the timer 12 count source
selection bit is “1” (f(XCIN)), a delay of approximately 16 ms occurs regardless of the operation mode.
5 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
6 : When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set
by the middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the middlespeed mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 60 State transitions of system clock
REJ03B0139-0111
page 58 of 73
Rev.1.11
Dec 18, 2008
3858 Group
Electrical characteristics
Absolute maximum ratings
Table 7 Absolute maximum ratings
Symbol
Parameter
VCC
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
VI
P24–P27, P30–P34, P40–P44,
VREF
Input voltage P22, P23
VI
Input voltage RESET, XIN
VI
Input voltage CNVSS
VI
Output voltage P00–P07, P10–P17, P20, P21,
VO
P24–P27, P30–P34, P40–P44,
XOUT
Output voltage P22, P23
VO
Power dissipation
Pd
Operating temperature
Topr
Storage temperature
Tstg
Conditions
All voltages are based on VSS.
When an input voltage is measured,
output transistors are cut off.
Ta = 25 °C
Note : The rating becomes 300mW at the PRSP0042GA-A/B (42P2R-A/E) package.
REJ03B0139-0111
page 59 of 73
Rev.1.11
Dec 18, 2008
–
–
Ratings
–0.3 to 6.5
–0.3 to VCC +0.3
Unit
V
V
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to 8.0
–0.3 to VCC +0.3
V
V
V
V
–0.3 to 5.8
1000 (Note)
–20 to 85
–40 to 125
V
mW
°C
°C
3858 Group
Recommended operating conditions
Table 8 Recommended operating conditions
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
Limits
Typ.
Max.
At 12.5 MHz (High-speed mode)
4.0
5.0
5.5
V
At 12.5 MHz (Middle-speed mode), 6 MHz (High-speed mode)
32 kHz (Low-speed mode)
2.7
5.0
5.5
V
Symbol
VCC
Parameter
Power source voltage
VSS
Power source voltage
VREF
A/D convert reference voltage
0
AVSS
Analog power source voltage
VIA
Analog input voltage
AN0–AN8
VIH
“H” input voltage
VIH
2.0
Unit
V
VCC
0
V
V
AVSS
VCC
V
P00–P07, P10–P17, P20–P27,
P30–P34, P40–P44
0.8VCC
VCC
V
“H” input voltage
RESET, XIN, CNVSS
0.8VCC
VCC
V
VIL
“L” input voltage
P00–P07, P10–P17, P20–P27,
P30–P34, P40–P44
0
0.2VCC
V
VIL
“L” input voltage
RESET, CNVSS
0
0.2VCC
V
VIL
“L” input voltage
XIN
0
0.16VCC
V
ΣIOH(peak)
“H” total peak output current (Note 1)
P00–P07, P10–P17, P30–P34
–80
mA
ΣIOH(peak)
“H” total peak output current (Note 1)
P20, P21, P24–P27, P40–P44
–80
mA
ΣIOL(peak)
“L” total peak output current (Note 1)
P00–P07, P30–P34
80
mA
ΣIOL(peak)
“L” total peak output current (Note 1)
P10–P17
120
mA
ΣIOL(peak)
“L” total peak output current (Note 1)
P20–P27, P40–P44
80
mA
ΣIOH(avg)
“H” total average output current (Note 1)
P00–P07, P10–P17, P30–P34
–40
mA
ΣIOH(avg)
“H” total average output current (Note 1)
P20, P21, P24–P27, P40–P44
–40
mA
ΣIOL(avg)
“L” total average output current (Note 1)
P00–P07, P30–P34
40
mA
ΣIOL(avg)
“L” total average output current (Note 1)
P10–P17
60
mA
ΣIOL(avg)
“L” total average output current (Note 1)
40
mA
IOH(peak)
“H” output voltage (Note 2)
P00–P07, P10–P17, P20, P21, P24–P27,
P30–P34, P40–P44
–10
mA
IOL(peak)
“L” output voltage (Note 2)
P00–P07, P20–P27, P30–P34, P40–P44
10
mA
IOL(peak)
“L” output voltage (Note 2)
P10–P17
20
mA
IOH(avg)
“H” average output current (Note 3)
P00–P07, P10–P17, P20, P21, P24–P27,
P30–P34, P40–P44
–5
mA
IOL(avg)
“L” average output current (Note 3)
P00–P07, P20–P27, P30–P34, P40–P44
5
mA
IOL(avg)
“L” average output current (Note 3)
P10–P17
15
mA
12.5
MHz
P20–P27, P40–P44
f(XIN)
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 4)
f(XIN)
Internal clock oscillation frequency (VCC = 2.7 to 4.0V) (Note 4)
f(XCIN)
Sub-clock input oscillation frequency (Note 4, 5)
5VCC–7.5 MHz
32.768
50
kHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
REJ03B0139-0111
page 60 of 73
Rev.1.11
Dec 18, 2008
3858 Group
Electrical characteristics
Table 9 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
Parameter
Test conditions
Min.
Typ.
Max.
Unit
“H” output voltage (Note)
P00–P07, P10–P17, P20,P21
P24–P27, P30–P34, P40–P44
IOH = –10mA
VCC=4.0–5.5V
VCC – 2.0
V
IOH = –1.0mA
VCC=2.7–5.5V
VCC – 1.0
V
“L” output voltage
P00–P07, P20–P27, P30–P34
P40–P44
IOL = 10mA
VCC=4.0–5.5V
2.0
V
IOL = 1.0mA
VCC=2.7–5.5V
1.0
V
“L” output voltage
P10–P17
IOL = 20mA
VCC=4.0–5.5V
2.0
V
IOL = 10mA
VCC=2.7–5.5V
1.0
V
VT+ – VT–
Hysteresis
CNTR0, CNTR1, INT0–INT3
0.4
V
VT+ – VT–
Hysteresis
RxD, SCLK1, SCLK2, SIN2
0.5
V
VT+ – VT–
Hysteresis
____________
RESET
0.5
V
IIH
“H” input current
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
VI=VCC
Pin floating,
Pull-up Transistor "off"
5.0
µA
IIH
“H”____________
input current
RESET, CNVSS
VI=VCC
5.0
µA
IIH
“H” input current
XIN
VI=VCC
“L” input current
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
VI=VSS
Pin floating,
Pull-up Transistor "off"
–5.0
IIL
“L”____________
input current
RESET,CNVSS
VI=VSS
–5.0
IIL
“L” input current
XIN
VI=VSS
IIL
“L” input current (at Pull-up)
P00–P07, P10–P17, P20–P27,
P30–P34, P40–P44
VI=VSS
VCC=5.0V
–25
–65
–120
µA
VI=VSS
VCC=3.0V
–8
–22
–40
µA
RAM hold voltage
When clock stopped
2.0
5.5
V
IIL
VRAM
4
µA
Rev.1.11
Dec 18, 2008
µA
µA
–4
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
REJ03B0139-0111
page 61 of 73
µA
3858 Group
Table 10 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Parameter
Power source current
Test conditions
High-speed mode
f(XIN) = 12.5 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 12.5 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Middle-speed mode
f(XIN) = 12.5 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 12.5 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Low-speed mode (VCC=3V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode (VCC=3V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
REJ03B0139-0111
page 62 of 73
Rev.1.11
Min.
Max.
6.0
12.0
mA
4.0
8.0
mA
1.75
4.5
mA
1.35
4.2
mA
2.7
6.0
mA
2.0
4.5
mA
1.65
4.2
mA
1.3
4.0
mA
40
150
µA
30
100
µA
10
40
µA
5.5
11
µA
Increment when A/D conversion is executed
f(XIN) = 8 MHz
600
All oscillation stopped
(in STP state)
Ta=25°C
0.1
Output transistors “off”
Ta=85°C
Dec 18, 2008
Unit
Typ.
µA
1.0
µA
10
µA
3858 Group
A/D converter characteristics
Table 11 A/D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
–
Parameter
Test conditions
Min.
Typ.
Resolution
Max.
8
ABS
Absolute accuracy
tCONV
Conversion time
RLADDER
Ladder resistor
IVREF
Reference power source input current
II(AD)
A/D port input current
VCC=VREF
Unit
bit
±3
LSB
109
tc(XIN)
µA
37
kΩ
VREF=5.0V
50
135
200
VREF=3.0V
30
80
120
5.0
µA
Note : As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may
become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.
(2) When V REF voltage is less than [ 3.0V ], the accuracy at the time of low temperature may become extremely low compared with the time of room
temperature. The use beyond VREF=3.0V is recommended in the system the use by the side of low temperature is assumed to be.
REJ03B0139-0111
page 63 of 73
Rev.1.11
Dec 18, 2008
3858 Group
Timing requirements
Table 12 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Limits
Min.
20
80
32
32
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Typ.
Max.
Unit
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table13 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
th(SCLK2-SIN2)
Serial I/O2 clock input hold time
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
REJ03B0139-0111
page 64 of 73
Rev.1.11
Dec 18, 2008
Limits
Min.
20
166
66
66
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Typ.
Max.
Unit
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3858 Group
Switching characteristics
Table 14 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
Fig. 61
Limits
Min.
Typ.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Max.
140
–30
30
30
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
0
10
10
CMOS output falling time (Note 3)
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Table 15 Switching characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Test conditions
Fig. 61
Limits
Min.
Typ.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
Max.
350
–30
50
50
tC(SCLK2)/2–240
tC(SCLK2)/2–240
400
0
20
20
50
50
50
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Measurement output pin
100 pF
CMOS output
Fig. 61 Circuit for measuring output switching characteristics
REJ03B0139-0111
page 65 of 73
Rev.1.11
Dec 18, 2008
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3858 Group
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
C N TR 0
C N TR 1
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0 to INT3
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tf
SCLK1
SCLK2
0.2VCC
tC(SCLK1), tC(SCLK2)
tWL(SCLK1), tWL(SCLK2)
tWH(SCLK1), tWH(SCLK2)
tr
0.8VCC
0.2VCC
tsu(RxD-SCLK1),
tsu(SIN2-SCLK2)
RX D
SIN2
0.8VCC
0.2VCC
td(SCLK1-TXD),
td(SCLK2-SOUT2)
TX D
SOUT2
Fig. 62 Timing diagram
REJ03B0139-0111
page 66 of 73
th(SCLK1-RxD),
th(SCLK2-SIN2)
Rev.1.11
Dec 18, 2008
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
3858 Group
PACKAGE OUTLINE
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-SDIP42-13x36.72-1.78
PRDP0042BA-A
42P4B
4.1g
22
1
21
*1
E
42
e1
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas
Technology website.
c
D
A
A2
*2
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Reference
Symbol
*3
e
*3
bp
b3
Nom
Max
14.94
15.24
15.54
D
36.5
36.7
36.9
E
12.85
13.0
13.15
e1
A1
L
SEATING PLANE
Dimension in Millimeters
Min
A
b2
A1
5.5
0.51
3.8
A2
bp
0.35
0.45
0.55
b2
0.63
0.73
1.03
b3
0.9
1.0
1.3
c
0.22
0.27
0.34
e
1.528
1.778
2.028
L
3.0
0°
JEITA Package Code
P-SSOP42-8.4x17.5-0.80
RENESAS Code
PRSP0042GA-B
Previous Code
42P2R-E
MASS[Typ.]
0.6g
E
22
*1
HE
42
15°
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
21
1
Index mark
A2
A1
c
Reference
Symbol
*2
L
A
D
e
y
*3 b
p
Detail F
D
E
A2
A
A1
bp
c
HE
e
y
L
REJ03B0139-0111
page 67 of 73
Rev.1.11
Dec 18, 2008
Dimension in Millimeters
Min Nom Max
17.3 17.5 17.7
8.2 8.4 8.6
2.0
2.4
0.05
0.25 0.3 0.4
0.13 0.15 0.2
0°
10°
11.63 11.93 12.23
0.65 0.8 0.95
0.15
0.3 0.5 0.7
3858 Group
NOTES
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations.
After a reset, the contents of the processor status register (PS)
are undefined except for the I flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig 65.
Execution of decimal calculations
4. JMP instruction
Fig 63.
Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS),
execute the PHP instruction once then read the contents of (S+1).
If necessary, execute the PLP instruction to return the PS to its
original status.
(S)+1
Stored PS
Stack memory contents after PHP instruction execution
2. BRK instruction
(1) Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address
of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
3. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the
SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD
instruction.
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
REJ03B0139-0111
page 68 of 73
5. Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
6. Ports
(S)
Fig 64.
When using the JMP instruction in indirect addressing mode, do not
specify the last address on a page as an indirect address.
Rev.1.11
Dec 18, 2008
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
7. Instruction Execution Time
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned in the 740 Family Software Manual.
The frequency of the internal clock φ is the twice the XIN cycle in
high-speed mode, 8 times the XIN cycle in middle-speed mode,
and the twice the XCIN in low-speed mode.
8. Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and
the special page. (Do not change the contents after reset.)
9. CPU Mode Register
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
“1”.
3858 Group
NOTES ON PERIPHERAL FUNCTIONS
Notes on Input and Output Ports
1. Notes in standby state
state*1
In standby
, do not make input levels of an I/O port “undefined”, especially for I/O ports of the N-channel open-drain. When
setting the N-channel open-drain port as an output, do not make
input levels of an I/O port “undefined”, too.
Pull-up (connect the port to VCC) or pull-down (connect the port to
VSS) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When setting as an input port with its direction register, the transistor becomes the OFF state, which causes the ports to be the
high-impedance state.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port
are “undefined”. This may cause power source current.
In I/O ports of N-channel open-drain, when the contents of the port
latch are “1”, even if it is set as an output port with its direction
register, it becomes the same phenomenon as the case of an input port.
*1
Standby state : stop mode by executing STP instruction
wait mode by executing WIT instruction
2. Modifying output data with bit managing
instruction
When the port latch of an I/O port is modified with the bit managing instruction*2 , the value of the unspecified bit may be changed.
The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit.
Accordingly, when these instructions are executed on a bit of the
port latch of an I/O port, the following is executed to all bits of the
port latch.
• As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit
managing.
• As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit
managing.
Note the following:
• Even when a port which is set as an output port is changed for
an input port, its port latch holds the output data.
• As for a bit of which is set for an input port, its value may be
changed even when not specified with a bit managing instruction
in case where the pin state differs from its port latch contents.
*2
Bit managing instructions : SEB and CLB instructions
REJ03B0139-0111
page 69 of 73
Rev.1.11
Dec 18, 2008
Termination of Unused Pins
1. Terminate unused pins
(1) I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or
VSS through each resistor of 1 kΩ to 10 kΩ. In the port which can
select a internal pull-up resistor, the internal pull-up resistor can
be used.
Set the I/O ports for the output mode and open them at “L” or
“H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched over
to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may
increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program periodically to increase the reliability of program.
(2) The AVSS pin when not using the A/D converter :
• When not using the A/D converter, handle a power source pin for
the A/D converter, AVSS pin as follows:
AVSS: Connect to the VSS pin.
2. Termination remarks
(1) Input ports and I/O ports :
Do not open in the input mode.
• The power source current may increase depending on the
firststage circuit.
• An effect due to noise may be easily produced as compared with
proper termination (1) in 1 shown on the above.
(2) I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur
between a port and VCC (or VSS).
(3) I/O ports :
When setting for the input mode, do not connect multiple ports in
a lump to VCC or VSS through a resistor.
If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur
between ports.
• At the termination of unused pins, perform wiring at the shortest
possible distance (20 mm or less) from microcomputer pins.
3858 Group
Notes on Interrupts
1. Change of relevant register settings
When the setting of the following registers or bits is changed, the
interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the
following sequence.
• Interrupt edge selection register (address 003A16)
• Timer XY mode register (address 002316)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
↓
Set the interrupt edge select bit (active edge switch bit) or
the interrupt (source) select bit to “1”.
↓
NOP (one or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1” (enabled).
Fig 66.
Sequence of changing relevant register
When setting the followings, the interrupt request bit may be set to
“1”.
• When setting external interrupt active edge
Concerned register: Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
• When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated.
Concerned register: Interrupt edge selection register
(address 003A16)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit
is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
*Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig 67.
Sequence of check of interrupt request bit
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”,
the value of the interrupt request bit before being cleared to “0” is
read.
REJ03B0139-0111
page 70 of 73
Rev.1.11
Dec 18, 2008
Notes on Timer
• If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
• When switching the count source by the timer 12, X and Y count
source selection bits, the value of timer count is altered in
unconsiderable amount owing to generating of thin pulses in the
count input signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
Notes on Serial Interface
1. Notes when selecting clock synchronous
serial I/O (Serial I/O1)
(1) Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0”
(Serial I/O1 and transmit disabled).
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S CLK1 , and S RDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O1 enable bit to “0” (Serial I/O1 disabled).
(3) Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception cannot be stopped.)
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (Serial I/O1 disabled) (refer to
(1) in 1).
(4) SRDY1 output of reception side (Serial I/O1)
When signals are output from the SRDY1 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY1 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
3858 Group
2. Notes when selecting clock asynchronous
serial I/O (Serial I/O1)
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S CLK1 , and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
4. Data transmission control with referring to
transmit shift register completion flag
(Serial I/O1)
The transmit shift register completion flag changes from “1” to “0”
with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
5. Transmit interrupt request when transmit
enable bit is set (SerialI/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown in the following sequence.
(1) Set the interrupt enable bit to “0” (disabled) with CLB instruction.
(2) Prepare serial I/O for transmission/reception.
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(Serial I/O1 disabled), the internal transmission is running (in this
case, since pins TxD, RxD, S CLK1 , and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD pin and an operation failure occurs.
(3) Set the interrupt request bit to “0” with CLB instruction after 1
or more instruction has been executed.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
6. Transmission control when external clock
is selected (Serial I/O1 clock synchronous
mode)
3. Setting serial I/O1 control register again
(Serial I/O1)
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK1
input level. Also, write the transmit data to the transmit buffer register (serial I/O shift register) at “H” of the SCLK1 input level.
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0”.
(4) Set the interrupt enable bit to “1” (enabled).
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register completion flag are set to “1”.
The interrupt request is generated and the transmission interrupt
request bit is set regardless of which of the two timings listed below is selected as the timing for the transmission interrupt to be
generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
7. Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external
clock as synchronous clock, write the transmit data to the serial I/
O2 register (serial I/O shift register) at “H” of the transfer clock input level.
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the serial I/O1
control register
Can be set with the
↓
LDM instruction at
Set both the transmit enable bit (TE) and the
the same time
receive enable bit (RE), or one of them to “1”
Fig 68.
Sequence of setting serial I/O1 control register
again
REJ03B0139-0111
page 71 of 73
Rev.1.11
Dec 18, 2008
Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L”
level is output from the PWM pin.
The length of this “L” level output is as follows:
n+1
2 ✕ f(XIN)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
n+1
f(XIN)
(s)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
3858 Group
Notes on A/D Converter
1. Analog input pin
Notes on Using Stop Mode
1. Register setting
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01 µF to 1 µF.
Further, be sure to verify the operation of application products on
the user side.
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high
impedance are input to an analog input pin, charge and discharge
noise generates. This may cause the A/D conversion precision to
be worse.
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode, set them again,
respectively. (When the oscillation stabilizing time set after STP instruction released bit is “0”)
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
2. A/D converter power source pin
The AV SS pin is A/D converter power source pin. Regardless of
using the A/D conversion function or not, connect it as following :
•AVSS : Connect to the VSS line
If the AVSS pin is opened, the microcomputer may have a failure
because of noise or others.
3. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. Thus,
make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more in middle-/high-speed mode.
• Do not execute the STP instruction.
• When the A/D converter is operated at low-speed mode, f(XIN)
do not have the lower limit of frequency, because of the A/D converter has a built-in self-oscillation circuit.
Notes on Watchdog Timer
• Make sure that the watchdog timer does not underflow while
waiting Stop release, because the watchdog timer keeps counting during that term.
• When the STP instruction function selection bit has been set to
“1”, it is impossible to switch it to “0” by a program.
____________
Notes on RESET Pin
1. Connecting capacitor
____________
In case where the RESET signal rise____________
time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin.
Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor
as short as possible.
• Be sure to verify the operation of application products on the
user side.
If the several nanosecond
or several ten nanosecond impulse
____________
noise enters the RESET pin, it may cause a microcomputer failure.
2. Reset release after power on
When releasing the reset after power on, such as power-on reset,
release reset after XIN passes more than 20 cycles in the state
where the power supply voltage is 2.7 V or more and the XIN oscillation is stable.
____________
To release reset, the RESET pin must be held at an “L” level for 20
cycles or more of XIN in the state where the power source voltage
is between 2.7 V and 5.5 V, and XIN oscillation is stable.
REJ03B0139-0111
page 72 of 73
Rev.1.11
Dec 18, 2008
2. Clock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of the CPU mode register previous to
the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the
STP instruction, the oscillation of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system
clock, the oscillation stabilizing time for approximately 8,000
cycles of the X IN input is reserved at restoration from the stop
mode. At this time, note that the oscillation on the sub clock side
may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side.
Notes on Wait Mode
• Clock restoration
If the wait mode is released by a reset when XCIN is set as the
system clock and XIN oscillation is stopped during execution of the
WIT instruction, XCIN oscillation stops, XIN oscillations starts, and
XIN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the
oscillation is stabilized.
Notes on Restarting Oscillation
• Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external
interrupt source, the fixed values of Timer 1 and Prescaler 12
(Timer 1 = “0116 ”, Prescaler 12 = “FF 16 ”) are automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0 of
MISRG (address 003816).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
Oscillation will restart when an external interrupt is received.
However, internal clock φ is supplied to the CPU only when Timer
1 starts to underflow. This ensures time for the clock oscillation using the ceramic resonators to be stabilized.
3858 Group
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (V CC pin) and GND pin (VSS pin) and between power
source pin (V CC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recommended.
The shortest
CNVSS/(VPP)
(Note)
Approx. 5kΩ
VSS
(Note)
The shortest
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Product Shipped in Blank
As for the product shipped in blank, Renesas does not perform the
writing test to user ROM area after the assembly process though
the QzROM writing test is performed enough before the assembly
process. Therefore, a writing error of approx.0.1 % may occur.
Moreover, please note the contact of cables and foreign bodies on
a socket, etc. because a writing environment may cause some
writing errors.
QzROM Version
Connect the CNVSS/VPP pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ resistor in series to
the GND could improve noise immunity. In this case as well as the
above mention, connect the pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
The CNVSS/VPP pin is the power source input pin for the built-in
QzROM. When programming in the QzROM, the impedance of the
VPP pin is low to allow the electric current for writing to flow into
the built-in QzROM. Because of this, noise can enter easily. If
noise enters the VPP pin, abnormal instruction codes or data are
read from the QzROM, which may cause a program runaway.
REJ03B0139-0111
page 73 of 73
Rev.1.11
Dec 18, 2008
Note. Shows the microcomputer's pin.
Fig 68.
Wiring for the CNVSS/VPP
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing, submit
the mask file (extension: .msk) which is made by the mask file
converter MM.
• Be sure to set the ROM option data* setup when making the
mask file by using the mask file converter MM.. The ROM code
protect is specified according to the ROM option data* in the
mask file which is submitted at ordering. Note that the mask file
which has nothing at the ROM option data* or has the data other
than “0016” and “FF16” can not be accepted.
• Set “FF16” to the ROM code protect address in ROM data regardless of the presence or absence of a protect. When data
other than “FF16” is set, we may ask that the ROM data be submitted again.
* ROM option data: mask option noted in MM
DATA REQUIRED FOR QzROM WRITING
ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
3858 Group Data Sheet
REVISION HISTORY
Rev.
Date
1.00 Jan.28, 2005
1.01 May.11, 2005
1.10
Apr.3, 2006
1.11 Dec.18,2008
Page
–
Description
Summary
First edition issued
5
10
Table 2 added
ROM code protect address, Notes added
Fig. 8 partly revised
60
QzROM Version, Notes On QzROM Writing Orders, Notes On ROM Code Protect,
DATA REQUIRED FOR QzROM WRITING ORDERS added
61
Table 7 partly revised
65
Table 12 partly revised
–
“Under development” deleted
–
Package name is revised “42P2R-A/E” → “PRSP0042GA-B”
3
Table 1; CNVSS Functions: “and is shared with ..... the built-in QzROM” added
P3, P4 Functions: “•8-bit I/O port” → “•5-bit I/O port”
10
ROM Code Protect Address; “the Mask option set up when ordering.” →
“ROM option setup ..... when ordering.” revised
12
Table 5 “A/D converter input” → “A/D conversion input”
15
Fig. 12 revised
17
Fig. 14; b7 to b5 of registers PULL3 and PULL4 revised
53
WATCHDOG TIMER revised
56
CLOCK GENERATING CIRCUIT revised
57
Fig. 59 revised
59
Table 7; Input voltage P22, P23 Ratings: “5.8” → “VCC +0.3”
Input voltage CNVSS Ratings: “VCC +0.3” → “8.0”
61
Table 9; f(XCIN), Note 4 added
64
Table 13 “VCC = 4.0 to 5.5 V” → “VCC = 2.7 to 5.5 V”
69
PACKAGE OUTLINE revised
70 to 75 NOTES added (The last NOTES ON PROGRAMMING and NOTES ON
USAGE deleted)
1,4,5,59 PRSP0042GA-B → PRSP0042GA-A/B
23
Fig. 17: Main clock division ration selection bit XIN “1” deleted
52
“Initial Value of Watchdog Timer” partly added
When bit 7 of the watchdog timer control register is
“0”: 65.536 ms at XIN = 16 MHz frequency → 131.072 ms at XIN = 8 MHz frequency
“1”: 256 µs at XIN = 16 MHz frequency → 512 µs at XIN = 8 MHz frequency
55
(2) Wait mode partly revised: “When releasing the STP state, the input of the
prescaler 12 and timer 1 is connected to the count source which had set at executing the STP instruction and the prescaler 12 and timer 1 will start counting”
63
Table 11 A/D converter characteristics: “Ta = 25°C ” deleted from the test conditions of absolute accuracy
72
Notes on Watchdog Timer:
“STP instruction disable bit” → “STP instruction function selection bit”
73
Notes on QzROM Writing Orders revised
(1/ 1)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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