M37560M3A-XXXGP

7560 Group (A version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0039-0102Z Rev.1.02 2003.07.31 DESCRIPTION The 7560 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 7560 group (A version) has the LCD drive control circuit, an 8channel A-D converter, D-A converter, serial I/O and PWM as additional functions. The various microcomputers in the 7560 group (A version) include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 7560 group (A version), refer the section on group expansion. •Timers ............................................................ 8-bit ✕ 3, 16-bit ✕ 2 • Serial I/O1 ..................... 8-bit ✕ 1 (UART or Clock-synchronous) • Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronous) • PWM output .................................................................... 8-bit ✕ 1 • A-D converter ................................................ 10-bit ✕ 8 channels • D-A converter .................................................. 8-bit ✕ 2 channels • LCD drive control circuit Bias ......................................................................... 1/2, 1/3 Duty .................................................................. 1/2, 1/3, 1/4 Common output ................................................................ 4 Segment output .............................................................. 40 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) Watchdog timer ............................................................. 14-bit ✕ 1 Power source voltage In high-speed mode (f(XIN) = 10 MHz) ................... 4.5 V to 5.5 V In high-speed mode (f(XIN) = 8 MHz) ..................... 4.0 V to 5.5 V In middle-speed mode (f(XIN) = 6 MHz) ................. 1.8 V to 5.5 V In low-speed mode .................................................. 1.8 V to 5.5 V Power dissipation In high-speed mode ................................................... Typ. 23 mW (at 10MHz oscillation frequency, VCC = 5 V, Ta = 25 °C) In low-speed mode ...................................................... Typ. 14 µW Operating temperature range ................................... – 20 to 85°C • FEATURES • Basic machine-language instructions ....................................... 71 • The minimum instruction execution time ............................ 0.4 µs • • • • • • (at 10 MHz oscillation frequency) Memory size ROM ................................................................ 32 K to 60 K bytes RAM ............................................................... 1024 to 2560 bytes Programmable input/output ports ............................................. 55 Software pull-up resistors .................................................... Built-in Output ports ................................................................................. 8 Input ports .................................................................................... 1 Interrupts .................................................. 17 sources, 16 vectors External ................ 7 sources (includes key input interrupt) Internal ................................................................ 9 sources Software ................................................................ 1 source • • • • APPLICATIONS Camera, household appliances, consumer electronics, etc. Rev.1.02 Jul 31, 2003 page 1 of 69 7560 Group (A version) PIN CONFIGURATION (TOP VIEW) PIN CONFIGURATION (TOP VIEW) SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 P14/SEG38 P15/SEG39 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 M37560MXA-XXXFP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Fig. 1 Pin configuration (Package type: 100P6S-A) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1 50 49 48 47 46 45 44 43 42 41 40 39 C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/ADT/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ/TOUT P42/INT2 P41/INT1 P40 P77 P76 P75 P74 Package type : 100P6S-A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M37560MXA-XXXGP 38 37 36 35 34 33 32 31 30 29 28 27 26 P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 P74 P75 P76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Fig. 2 Pin configuration (Package type: 100P6Q-A) Rev.1.02 Jul 31, 2003 page 2 of 69 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/ADT/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ/TOUT P42/INT2 P41/INT1 P40 P77 Package type : 100P6Q-A Fig. 3 Functional block diagram Reset input (5V) (0V) VSS 40 D A2 D A1 CNTR0,CNTR1 INT0 SI/O2(8) ADT 36 37 27 28 29 30 31 32 33 34 3 4 5 6 78 9 10 92 93 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 65 66 67 68 69 70 71 72 41 42 43 44 45 46 47 48 Key input (Key-on wake up) interrupt X COUT X CIN φ INT1,INT2 P7(8) P6(8) P5(8) P4(8) P3(8) Real time port function Rev.1.02 RESET 35 91 FUNCTIONAL BLOCK DIAGRAM (Package type: 100P6S-A) Main clock input VC C Main clock output 7560 Group (A version) Jul 31, 2003 Data bus 2 X IN X OUT 38 39 page 3 of 69 CPU A ROM X Y S PC H Timer X (16) Timer Y (16) D-A2 D-A1 Timer 1 (8) Timer 2 (8) Timer 3 (8) PS PCL LCD display RAM (20 bytes) RAM 1 100 99 98 97 96 95 94 Clock generating circuit VL1 C1 C2 VL 2 VL3 COM0 COM1 COM2 COM3 X CIN X COUT φ Subclock input Subclock output LCD drive control circuit 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Watchdog timer Reset A-D converter (8) TOUT PWM(8) SI/O1 (8) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P2(8) P1(8) P0(8) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XCIN XCOUT VREF AVSS Sub-clock Sub-clock I/O port P7 input output I/O port P6 I/O port P5 I/O port P4 Output port P3 I/O port P2 I/O port P1 I/O port P0 7560 Group (A version) PIN DESCRIPTION Table 1 Pin description (1) Pin VCC VSS VREF AVSS Name Power source Analog reference voltage Analog power source Reset input Clock input Clock output Function Function except a port function •Apply voltage of power source to V CC, and 0 V to VSS. (For the limits of VCC, refer to “Recommended operating conditions”. •Reference voltage input pin for A-D converter and D-A converter. •GND input pin for A-D converter and D-A converter. •Connect to VSS. •Reset input pin for active “L”. •Input and output pins for the main clock generating circuit. •Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A feedback resistor is built-in. RESET XIN XOUT VL1–VL3 C1, C2 COM0–COM3 LCD power source Charge-pump capacitor pin Common output •Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage. •Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.) •External capacitor pins for a voltage multiplier (3 times) of LCD control. •LCD common output pins. •COM2 and COM3 are not used at 1/2 duty ratio. •COM3 is not used at 1/3 duty ratio. SEG0–SEG17 P00/SEG26– P07/SEG33 Segment output I/O port P0 •LCD segment output pins. •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled. •I/O direction register allows each 8-bit pin to be programmed as either input or output. •LCD segment output pins P10/SEG34– P15/SEG39 I/O port P1 •6-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled. •I/O direction register allows each 6-bit pin to be programmed as either input or output. P16, P17 •2-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. P20 – P27 I/O port P2 •Key input (key-on wake-up) interrupt input pins P30/SEG18 – P37/SEG25 Output port P3 •8-bit output. •CMOS 3-state output structure. •Port output control is enabled. •LCD segment output pins Rev.1.02 Jul 31, 2003 page 4 of 69 7560 Group (A version) Table 2 Pin description (2) Pin P40 Name I/O port P4 •1-bit I/O port. •CMOS compatible input level. •N-channel open-drain output structure. •I/O direction register allows this pin to be individually programmed as either input or output. P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/DA1 P57/ADT/DA2 P60/SIN2/AN0, P61/SOUT2/AN1, P62/SCLK21/AN2, P63/SCLK22/AN3 P64/AN4– P67/AN7 P70/INT0 P71–P77 •7-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. I/O port P5 •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. •Real time port output pins •Timer X, Y I/O pins •D-A converter output pin •D-A converter output pin •A-D external trigger input pin I/O port P6 •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. Input port P7 I/O port P7 •1-bit input port. •7-bit I/O port. •CMOS compatible input level. •N-channel open-drain output structure. •I/O direction register allows each pin to be individually programmed as either input or output. XCOUT XCIN Sub-clock output Sub-clock input •Sub-clock generating circuit I/O pins. (Connect a oscillator. External clock cannot be used.) •INT0 interrupt input pin •A-D converter input pins •Serial I/O2 I/O pins •A-D converter input pins •PWM output pins •System clock φ output pin •Timer 2 output pin •Serial I/O1 I/O pins •INTi interrupt input pins Function Function except a port function Rev.1.02 Jul 31, 2003 page 5 of 69 7560 Group (A version) PART NUMBERING Product M37560 M F A – XXX FP Package type FP : 100P6S-A GP : 100P6Q-A ROM number Characteristics A : A version ROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M: Mask ROM version Fig. 4 Part numbering Rev.1.02 Jul 31, 2003 page 6 of 69 7560 Group (A version) GROUP EXPANSION Renesas expands the 7560 group (A version) as follows. Packages 100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP 100P6S-A ................................ 0.65 mm-pitch plastic molded QFP Memory Type Support for mask ROM version. Memory Size ROM size ........................................................... 32 K to 60 K bytes RAM size .......................................................... 1024 to 2560 bytes Memory Expansion Plan ROM size (bytes) 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K M37560M8A M37560MFA 192 256 512 768 1024 1280 1536 1792 2048 2304 2560 RAM size (bytes) Produt under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Fig. 5 Memory expansion plan Currently planning products are listed below. Table 3 Support products Part number M37560M8A-XXXFP M37560M8A-XXXGP M37560MFA-XXXFP M37560MFA-XXXGP ROM size (bytes) ROM size for User in ( ) 32768 (32638) 61440 (61310) RAM size (bytes) 1024 2560 Package 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A Mask ROM version Mask ROM version Mask ROM version Mask ROM version Remarks As of Jul. 2003 Rev.1.02 Jul 31, 2003 page 7 of 69 7560 Group (A version) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 7560 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. The central processing unit (CPU) has six registers. Figure 6 shows the 740 Family CPU register structure. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. Figure 9 shows the operations of pushing register contents onto the stack and popping them from the stack. Table 6 shows the push and pop instructions of accumulator or processor status register. Store registers other than those described in Figure 9 with program when the user needs them during interrupts or subroutine calls. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as arithmetic data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 6 740 Family CPU register structure Rev.1.02 Jul 31, 2003 page 8 of 69 7560 Group (A version) On-going Routine Interrupt request (Note) Execute JSR Push return address on stack M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push return address on stack Push contents of processor status register on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt request here Interrupt enable bit corresponding to each interrupt source is “1” Interrupt disable flag is “0” Fig. 7 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.1.02 Jul 31, 2003 page 9 of 69 7560 Group (A version) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. • Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. • Bit 1: Zero flag (Z) The Z flag is set to “1” if the result of an immediate arithmetic operation or a data transfer is “0”, and set to “0” if the result is anything other than “0”. • Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. • Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. • Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. When the BRK instruction is generated, the B flag is set to “1” automatically. When the other interrupts are generated, the B flag is set to “0”, and the processor status register is pushed onto the stack. • Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. • Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set to “1” if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the V flag. • Bit 7: Negative flag (N) The N flag is set to “1” if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Instructions to set each bit of processor status register to “0” or “1” C flag Instruction setting to “1” Instruction setting to “0” SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – Rev.1.02 Jul 31, 2003 page 10 of 69 7560 Group (A version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the system clock control bits, etc. The CPU mode register is allocated at address 003B16. b7 b0 1 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Do not select 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (“1” at reading) (Write “1” to this bit at writing) XC switch bit 0 : Oscillation stop 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) System clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Fig. 8 Structure of CPU mode register Rev.1.02 Jul 31, 2003 page 11 of 69 7560 Group (A version) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page The 256 bytes from addresses 0000 16 t o 00FF 16 a re called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special Page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 2560 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 0A3F16 Not used XXXX16 RAM 004016 005416 010016 000016 SFR area LCD display RAM area Zero page ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFFE16 Reserved ROM area FFFF16 Interrupt vector area Special page ROM FF0016 FFDC16 ZZZZ16 YYYY16 Reserved ROM area (128 bytes) Fig. 9 Memory map diagram Rev.1.02 Jul 31, 2003 page 12 of 69 7560 Group (A version) 000016 Port P0 register (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 register (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 register (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 register (P3) 000716 Port P3 output control register (P3C) 000816 Port P4 register (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 register (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 register (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 register (P7) 000F16 Port P7 direction register (P7D) 001016 001116 001216 001316 001416 A-D conversion low-order register (ADL) 001516 Key input control register (KIC) 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register(TB/RB) 001916 Serial I/O1 status register (SIO1ST S) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART control register (UART CON) 001C16 Baud rate generator (BRG) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Reserved area (Note) 001F16 Serial I/O2 register (SIO2) 002016 Timer X low-order register (TXL) 002116 Timer X high-order register (TXH) 002216 Timer Y low-order register (TYL) 002316 Timer Y high-order register (TYH) 002416 Timer 1 register (T1) 002516 Timer 2 register (T2) 002616 Timer 3 register (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 TOUT/φ output control register (CKOUT) 002B16 PWM control register (PWMCON) 002C16 PWM prescaler (PREPWM) 002D16 PWM register (PWM) 002E16 Reserved area (Note) 002F16 Reserved area (Note) 003016 Reserved area (Note) 003116 Reserved area (Note) 003216 D-A1 conversion register (DA1) 003316 D-A2 conversion register (DA2) 003416 A-D control register (ADCON) 003516 A-D conversion high-order register (ADH) 003616 D-A control register (DACON) 003716 Watchdog timer control register (WDTCON) 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F16 Interrupt control register 2(ICON2) Note: Do not write to the addresses of reserved area. Fig. 10 Memory map of special function register (SFR) Rev.1.02 Jul 31, 2003 page 13 of 69 7560 Group (A version) I/O PORTS Direction Registers The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direction registers. Ports P16, P17, P4, P5, P6, and P71–P77 can be set to input mode or output mode by each pin individually. P00–P07 and P10-P15 are respectively set to input mode or output mode in a lump by bit 0 of the direction registers of ports P0 and P1 (see Figure 11). When “0” is set to the bit corresponding to a pin, that pin becomes an input mode. When “1” is set to that bit, that pin becomes an output mode. If data is read from a port set to output mode, the value of the port latch is read, not the value of the pin itself. A port set to input mode is floating. If data is read from a port set to input mode, the value of the pin itself is read. If a pin set to input mode is written to, only the port latch is written to and the pin remains floating. b7 b0 Port P0 direction register (P0D : address 000116) Ports P00 to P07 direction register 0 : Input mode 1 : Output mode Not used (Undefined at reading) (If writing to these bits, write “0”.) b7 b0 Port P1 direction register (P1D : address 000316) Ports P10 to P15 direction register 0 : Input mode 1 : Output mode Not used (Undefined at reading) (If writing to these bits, write “0”.) Port P16 direction register Port P17 direction register 0 : Input mode 1 : Output mode Port P3 Output Control Register Bit 0 of the port P3 output control register (address 000716) enables control of the output of ports P30–P37. When the bit is set to “1”, the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and pulled up. Note: In ports set to output mode, the pull-up control bit becomes invalid and pull-up resistor is not connected. Fig. 11 Structure of port P0 direction register, port P1 direction register b7 b0 Port P3 output control register (P3C : address 000716) Ports P30 to P37 output control bit 0 : Output function is invalid (Pulled up) 1 : Output function is valid (No pull up) Not used (Undefined at reading) (If writing to these bits, write “0”.) Note: In pins set to segment output by segment output enable bits 0, 1 (bits 0, 1 of segment output enable register (address 3816)), this bit becomes invalid and pull-up resistor is not connected. Fig. 12 Structure of port P3 output control register Rev.1.02 Jul 31, 2003 page 14 of 69 7560 Group (A version) Pull-up Control By setting the PULL register A (address 001616) or the PULL register B (address 0017 16), ports P0 to P2, P4 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports set to output mode and the ports are no pulled up. The PULL register A setting is invalid for pins selecting segment output with the segment output enable register and the pins are not pulled up. b7 b0 PULL register A (PULLA : address 001616) P00, P01 pull-up control bit P02, P03 pull-up control bit P04–P07 pull-up control bit P10–P13 pull-up control bit P14, P15 pull-up control bit P16, P17 pull-up control bit P20–P23 pull-up control bit P24–P27 pull-up control bit b7 b0 PULL register B (PULLB : address 001716) P41–P43 pull-up control bit P44–P47 pull-up control bit P50–P53 pull-up control bit P54–P57 pull-up control bit P60–P63 pull-up control bit P64–P67 pull-up control bit Not used “0” at reading) 0 : Disable 1 : Enable Note: The contents of PULL register A and PULL register B do not affect ports set to output mode. Fig. 13 Structure of PULL register A and PULL register B Rev.1.02 Jul 31, 2003 page 15 of 69 7560 Group (A version) Table 6 List of I/O port function (1) Pin P00/SEG26– P07/SEG33 P10/SEG34– P15/SEG39 Name Port P0 Input/Output Input/output, byte unit Input/output, 6-bit unit I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS 3-state output Key input (key-on wake-up) interrupt input LCD segment output Non-Port Function LCD segment output Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register PULL register A Diagram No. (1) (2) (1) (2) (4) Port P1 LCD segment output P16 , P17 Input/output, individual bits Port P2 Input/output, individual bits P20–P27 PULL register A Interrupt control register 2 Key input control register Segment output enable register Port P3 output control register (3) P30/SEG18– P37/SEG25 Port P3 Output P40 Port P4 Input/output, individual bits CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output INTi interrupt input Timer 2 output System clock φ output Interrupt edge selection register PULL register B Timer 123 mode register TOUT/φ output control register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register (13) P41/INT1, P42/INT2 P43/φ/TOUT (4) (12) P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/DA1 P57/ADT/ DA2 Port P5 Input/output, individual bits CMOS compatible input level CMOS 3-state output Serial I/O1 I/O (5) (6) (7) (8) (10) (9) (11) (14) (15) (15) PWM output Real time port output PULL register B PWM control register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B D-A control register PULL register B D-A control register A-D control register Timer X I/O Timer Y input DA1 output DA2 output A-D external trigger input Rev.1.02 Jul 31, 2003 page 16 of 69 7560 Group (A version) Table 7 List of I/O port function (2) Pin P60/SIN2/AN0 P61/SOUT2/ AN1 P62/SCLK21/ AN2 P63/SCLK22 / AN3 P64/AN4– P67/AN7 P70/INT0 P71–P77 Port P7 Input Input/ output, individual bits Common Segment Output Output CMOS compatible input level CMOS compatible input level N-channel open-drain output LCD common output LCD segment output LCD mode register A-D converter input INT0 interrupt input A-D control register PULL register B Interrupt edge selection register Name Port P6 Input/Output Input/ output, individual bits I/O Format CMOS compatible input level CMOS 3-state output Non-Port Function A-D converter input Serial I/O2 I/O Related SFRS PULL register B A-D control register Serial I/O2 control register Diagram No. (17) (18) (19) (20) (16) (23) (13) COM0–COM3 SEG0–SEG17 (21) (22) Notes 1: How to use double-function ports as function I/O pins, refer to the applicable sections. 2: M ake sure that the input level at each pin is either 0 V or V CC b efore execution of the STP instruction. When an electric potential is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate and power source current may increase. Rev.1.02 Jul 31, 2003 page 17 of 69 7560 Group (A version) (1) Ports P01–P07, P11–P15 LCD drive timing Segment data Data bus Port latch Port direction register Pull-up VL2/VL3/VCC Segment/Port Interface logic level shift circuit Segment VL1/VSS Port Segment output enable bit Port direction register (2) Ports P00, P10 LCD drive timing Direction register Segment data Data bus Port latch Interface logic level shift circuit Pull-up VL2/VL3/VCC Segment/Port Segment VL1/VSS Segment output Port enable bit Port direction register (3) Port P3 LCD drive timing Segment data Data bus Port latch Port P3 output control bit Interface logic level shift circuit Pull-up VL2/VL3/VCC Segment/Port Segment VL1/VSS Port Segment output Port P3 output control bit enable bit (4) Ports P16, P17, P2, P41, P42 Pull-up control (5) Port P44 Serial I/O1 enable bit Receive enable bit Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Key input interrupt input INT1, INT2 interrupt input Except P16, P17 Serial I/O1 input Fig. 14 Port block diagram (1) Rev.1.02 Jul 31, 2003 page 18 of 69 7560 Group (A version) (6) Port P45 Pull-up control P45/TxD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Data bus Port latch (7) Port P46 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch Pull-up control Serial I/O1 output Serial I/O1 clock output Serial I/O1 clock input (8) Port P47 Pull-up control Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Port latch (9) Ports P52,P53 Pull-up control Direction register Data bus Port latch Serial I/O1 ready output Real time port control bit Real time port data (10) Ports P50,P51 Pull-up control (11) Port P54 Direction register Pull-up control Direction register Data bus Data bus Port latch Port latch Pulse output mode Timer output PWM function enable bit PWM output CNTR0 interrupt input Fig. 15 Port block diagram (2) Rev.1.02 Jul 31, 2003 page 19 of 69 7560 Group (A version) (12) Port P43 Pull-up control (13) Ports P40,P71–P77 Direction register Direction register Data bus Port latch Data bus Port latch TOUT/φ output enable bit Timer 2 TOUT output TOUT/φ output selection bit System clock φ output (14) Port P55 (15) Ports P56,P57 Pull-up control Pull-up control Direction register Data bus Direction register Data bus Port latch Port latch CNTR1 interrupt input A-D external trigger input Except P56 D-A converter output DA1, DA2 output enable bits (16) Ports P64–P67 Pull-up control (17) Port P60 Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch A-D converter input Analog input pin selection bit Serial I/O2 input A-D converter input Analog input pin selection bit Fig. 16 Port block diagram (3) Rev.1.02 Jul 31, 2003 page 20 of 69 7560 Group (A version) (18) Port P61 P61/SOUT2 P-channel output disable bit Serial I/O2 transmit end signal Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch Pull-up control (19) Port P62 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register Pull-up control Data bus Port latch Serial I/O2 output A-D converter input Analog input pin selection bit Serial I/O2 clock output Serial I/O2 clock input A-D converter input Analog input pin selection bit (20) Port P63 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register Pull-up control (21) COM0–COM3 VL3 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VL2 Data bus Port latch VL1 Serial I/O2 clock output A-D converter input Analog input pin selection bit VSS (22) SEG0–SEG17 VL2/VL3 The voltage applied to the sources of Pchannel and N-channel transistors is the controlled voltage by the bias value. VL1/VSS (23) Port P70 Data bus INT0 input Fig. 17 Port block diagram (4) Rev.1.02 Jul 31, 2003 page 21 of 69 7560 Group (A version) INTERRUPTS Interrupts occur by seventeen sources: seven external, nine internal, and one software. When an interrupt request is accepted, the program branches to the interrupt jump destination address set in the vector address (see Table 8). Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt jump destination address is read from the vector table into the program counter. 3. The interrupt disable flag is set to “1” and the corresponding interrupt request bit is set to “0”. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt is accepted if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set to “0” or “1” by program. Interrupt request bits can be set to “0” by program, but cannot be set to “1” by program. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. When the interrupt disable (I) flag is set to “1”, all interrupt requests except the BRK instruction interrupt and reset are not accepted. When several interrupt requests occur at the same time, the interrupts are received according to priority. Table 8 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 Serial I/O2 Key input (Key-on wake-up) ADT Priority 1 2 3 4 5 Vector Addresses (Note 1) High Low FFFD16 FFFB16 FFF916 FFF716 FFF516 FFFC16 FFFA16 FFF816 FFF616 FFF416 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At completion of serial I/O2 data transmission or reception At falling of conjunction of input level for port P2 (at input mode) At falling edge of ADT input Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected 6 7 8 9 10 11 12 13 14 15 16 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (valid at falling) Valid when ADT interrupt is selected External interrupt (valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt A-D conversion BRK instruction 17 FFDD16 FFDC16 At completion of A-D conversion At BRK instruction execution Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset is not an interrupt. Reset has the higher priority than all interrupts. Rev.1.02 Jul 31, 2003 page 22 of 69 7560 Group (A version) ■Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”. •When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection bit of A-D control register (bit 6 of address 3416) When not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. ➀Set the corresponding interrupt enable bit to “0” (disabled). ➁Set the interrupt edge select bit (polarity switch bit) or the interrupt source selection bit. ➂Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the corresponding interrupt enable bit to “1” (enabled). Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request acceptance Fig. 18 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit Not used (“0” at reading) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNT R0 interrupt request bit CNT R1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit Serial I/O2 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (“0” at reading) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit Serial I/O2 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (“0” at reading) (Write “0” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 19 Structure of interrupt-related registers Rev.1.02 Jul 31, 2003 page 23 of 69 7560 Group (A version) Key Input Interrupt (Key-on Wake Up) The key input interrupt is enabled when any of port P2 is set to input mode and the bit corresponding to key input control register is set to “1”. A Key input interrupt request is generated by applying “L” level voltage to any pin of port P2 of which key input interrupt is en- abled. In other words, it is generated when AND of input level goes from “1” to “0”. A connection example of using a key input interrupt is shown in Figure 22, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P23. Port PXx “L” level output PULL register A Bit 7 ✽ P27 output P27 key input control bit Port P27 direction register = “1” ✽✽ Port P27 latch Key input interrupt request ✽ P26 output P26 key input control bit Port P26 direction register = “1” ✽ ✽ Port P26 latch P25 key input control bit Port P25 direction register = “1” ✽ P25 output ✽✽ Port P25 latch P24 key input control bit Port P24 direction register = “1” ✽ P24 output ✽✽ Port P24 latch PULL register A Bit 6 = “1” Port P23 P23 key input control bit = “1” direction register = “0” ✽ P23 input ✽✽ Port P23 latch Port P2 Input reading circuit P22 key input control bit = “1” Port P22 direction register = “0” ✽ P22 input ✽✽ Port P22 latch P21 key input control bit = “1” Port P21 direction register = “0” ✽ P21 input ✽✽ Port P21 latch P20 key input control bit = “1” Port P20 direction register = “0” ✽ P20 input ✽✽ Port P20 latch ✽ P-channel transistor for pull-up ✽ ✽ CMOS output buffer Fig. 20 Connection example when using key input interrupt and port P2 block diagram Rev.1.02 Jul 31, 2003 page 24 of 69 7560 Group (A version) The key input interrupt is controlled by the key input control register and the port direction register. When enabling the key input interrupt, set “1” to the key input control bit. A key input can be accepted from pins set as the input mode in ports P20–P27. b7 b0 Key input control register (KIC : address 001516) P20 key input control bit P21 key input control bit P22 key input control bit P23 key input control bit P24 key input control bit P25 key input control bit P26 key input control bit P27 key input control bit 0 : Key input interrupt disabled 1 : Key input interrupt enabled Fig. 21 Structure of key input control register Rev.1.02 Jul 31, 2003 page 25 of 69 7560 Group (A version) TIMERS The 7560 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Real time port control bit “1” P52/RTP0 P52 direction register “0” Data bus QD Latch RTP0 data for real time port P52 latch Real time port control bit “1” P53/RTP1 P53 direction register “0” P53 latch QD Latch RTP1 data for real time port Real time port control bit “0” “1” Timer X mode register write signal P54/CNTR0 f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer X operatCNTR0 active ing mode bits edge switch bit “00”,“01”,“11” “0” “10” Pulse width “1” measurement mode CNTR0 active edge switch bit “0” Q Timer X stop control bit Timer X (low) latch (8) Timer X write control bit Timer X (high) latch (8) Timer X interrupt request Timer X low-order register (8) Timer X high-order register (8) Pulse output mode S T Q Pulse width HL continuously measurement mode Rising edge detection Period measurement mode P54 direction register P54 latch Pulse output mode “1” CNTR1 active edge switch bit P55/CNTR1 “0” Falling edge detection f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer Y stop control bit “00”,“01”,“11” “10” Timer Y operating mode bits Timer Y (low) latch (8) Timer Y low-order register (8) Timer Y (high) latch (8) Timer Y high-order register (8) Timer Y interrupt request “1” f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer 1 count source selection bit “0” Timer 1 latch (8) XCIN “1” Timer 1 register (8) Timer 2 count source selection bit Timer 2 latch (8) “0” Timer 2 register (8) “1” f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer 2 write control bit Timer 1 interrupt request Timer 2 interrupt request TOUT output active edge switch bit “0” P43/φ/TOUT P43 direction register TOUT/φ “1 ” output selection bit TOUT/φ output enable bit QS T Q “0” Timer 3 latch (8) Timer 3 register (8) “1” Timer 3 count source selection bit Timer 3 interrupt request φ TOUT/φ output enable bit P43 latch f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Fig. 22 Timer block diagram Rev.1.02 Jul 31, 2003 page 26 of 69 7560 Group (A version) Timer X Timer X is a 16-bit timer and is equipped with the timer latch. The division ratio of timer X is given by 1/(n+1), where n is the value in the timer latch. Timer X is a down-counter. When the contents of timer X reach “0000 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer X interrupt request bit is set to “1”. Timer X can be selected in one of four modes by the timer X mode register and can be controlled the timer X write and the real time port. ●Timer X Write Control Which write control can be selected by the timer X write control bit (bit 0) of the timer X mode register (address 002716), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the timer X register and the timer is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the timer X register. The write operation is independent of timer X count operation, operating or stopping. When the value is written in latch only, a value is simultaneously set to the timer X and the timer X latch if the writing in the highorder register and the underflow of timer X are performed at the same timing. Unexpected value may be set in the high-order timer on this occasion. ●Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 a nd P5 3 e ach time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1” after set of the real time port data, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the P52/RTP0, P53/RTP1 pins to output mode (set “1” to bits 2, 3 of port P5 direction register). (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the P54/CNTR0 pin to output mode (set “1” to bit 4 of port P5 direction register). (3) Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the P54/ CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction register). (4) Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 a ctive edge switch bit is “0”, the timer counts while the input signal of CNTR 0 p in is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the P54/CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction register). ●Read and write to timer X high-order, low-order registers When reading and writing to the timer X high-order and low-order registers, be sure to read/write both the timer X high- and low-order registers. When reading the timer X high-order and low-order registers, read the high-order register first. When writing to the timer X high-order and low-order registers, write the low-order register first. The timer X cannot perform the correct operation if the next operation is performed. •Write operation to the high- or low-order register before reading the timer X low-order register •Read operation from the high- or low-order register before writing to the timer X high-order register ■Note on CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and timer 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid RTP0 data for real time port RTP1 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNT R0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNT R0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Fig. 23 Structure of timer X mode register Rev.1.02 Jul 31, 2003 page 27 of 69 7560 Group (A version) Timer Y Timer Y is a 16-bit timer and is equipped with the timer latch. The division ratio of timer Y is given by 1/(n+1), where n is the value in the timer latch. Timer Y is a down-counter. When the contents of timer Y reach “0000 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer Y interrupt request bit is set to “1”. Timer Y can be selected in one of four modes by the timer Y mode register. b7 b0 Timer Y mode register (TYM : address 002816) Not used (“0” at reading) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNT R1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNT R1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period measurement mode CNTR1 interrupt request is generated at rising or falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for this, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising or falling of CNTR 1 p in input signal is retained until the next valid edge is input. The rising or falling timing of CNTR 1 p in input signal can be discriminated by CNTR 1 i nterrupt. When using a timer in this mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction register). Fig. 24 Structure of timer Y mode register (3) Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction register). (4) Pulse width HL continuously measurement mode CNTR 1 i nterrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the P5 5 /CNTR 1 p in to input mode (set “0” to bit 5 of port P5 direction register). ■Note on CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the value of the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the value of CNTR1 active edge switch bit. Rev.1.02 Jul 31, 2003 page 28 of 69 7560 Group (A version) Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with the timer latch. The count source for each timer can be selected by the timer 123 mode register. The division ratio of each timer is given by 1/(n+1), where n is the value in the timer latch. All timers are down-counters. When the contents of the timer reach “0016”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. When a value is written to the timer 1 register and the timer 3 register, a value is simultaneously set as the timer latch and the timer. When the timer 1 register, the timer 2 register, or the timer 3 register is read, the count value of the timer can be read. ●Timer 2 Write Control Which write can be selected by the timer 2 write control bit (bit 2) of the timer 123 mode register (address 002916), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer 2 latch by writing data to the timer 2 register and the timer 2 is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the timer 2 latch and the timer 2 at the same time by writing data to the timer 2 register. If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the highorder register and the underflow of timer 2 are performed at the same timing. ●Timer 2 Output Control When the timer 2 (TOUT) output is enabled by the TOUT/φ output enable bit and the TOUT/φ output selection bit, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register). b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT/φ output enablel bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output signal 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output signal 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (“0” at reading) Note: System clock φ is f(XCIN)/2 in the low-speed mode. Fig. 25 Structure of timer 123 mode register ■Note on Timer 1 to Timer 3 When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Rev.1.02 Jul 31, 2003 page 29 of 69 7560 Group (A version) SERIAL I/O Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode is selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O mode, the transmitter and the re- ceiver must use the same clock as an operation clock. When an internal clock is selected as an operation clock, transmit or receive is started by a write signal to the transmit buffer register. When an external clock is selected as an operation clock, serial I/ O1 becomes the state where transmit or receive can be performed by a write signal to the transmit buffer register. Transmit and receive are started by input of an external clock. Data bus Address 001816 Receive buffer register Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request Receive clock control circuit P44/RXD Receive shift register Shift clock P46/SCL K1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator BRG count source selection bit XIN 1/4 P47/SRDY1 F/F Falling-edge detector 1/4 Address 001C16 Transmit clock control circuit Shift clock P45/TXD Transmit shift register Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request Transmit buffer empty flag (TBE) Address 001916 Address 001816 Data bus Serial I/O1 status register Fig. 26 Block diagram of clock synchronous serial I/O1 Transmit and receive shift clock (1/2 to 1/2048 of the internal clock, or an external clock) (Note 1) Serial output TXD Serial input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write signal to receive/transmit buffer register (address 001816) TBE = “0” RBF = “1” (Note 4) TSC = “1” (Note 3) Overrun error (OE) detection TBE = “1” (Note 3) TSC = “0” (Note 2) Notes 1 : After data transferring, the TxD pin keeps D7 output value. 2 : If data is written to the transmit buffer register when TSC = “0”, the transmit clock is generated continuously and serial data can be output continuously from the T XD pin. 3 : Select the serial I/O1 transmit interrupt request factor between when the transmit buffer register has emptied (TBE = “1”) or after the transmit shift operation has ended (T SC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 4 : T he serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”. Fig. 27 Operation of clock synchronous serial I/O1 function Rev.1.02 Jul 31, 2003 page 30 of 69 7560 Group (A version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) is selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address (0018 16 ) in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted during transmitting, and the receive buffer register can hold received one-byte data while the next one-byte data is being received. Data bus Address 001816 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request 1/16 PE FE SP detector Clock control circuit Serial I/O1 synchronization clock selection bit P46/SCL K1 BRG count source selection bit XIN 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator P44/RXD OE Receive buffer register Character length selection bit STdetector 7 bits Receive shift register 8 bits UART control register Address 001B16 1/16 P45/TXD Character length selection bit Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Address 001816 Data bus Fig. 28 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer register write signal TBE = “0” TSC = “0” TBE = “1” Serial output TxD ST D0 TBE = “0” TBE = “1” D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) (Notes 1, 2) RBF = “1” Serial input RxD ST D0 D1 SP ST D0 SP ST D0 D1 ✽ Generated TSC = “1”✽ SP at 2nd bit in 2-stop-bit mode Receive buffer register read signal RBF = “0” (Notes 1, 2) RBF = “1” D1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit for reception). 2 : T he serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”. 3 : Select the serial I/O1 transmit interrupt request occurrence factor between when the transmit buffer register has emptied (TBE = “1”) or after the transmit shift operation has ended (T SC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. Fig. 29 Operation of UART serial I/O1 function Rev.1.02 Jul 31, 2003 page 31 of 69 7560 Group (A version) [Transmit Buffer/Receive Buffer Register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is set to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set to “1”. A write signal to the serial I/O1 status register sets all the error flags (OE, PE, FE, and SE) (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial I/O1 enable bit (SIOE) also sets all the status flags to “0”, including the error flags. All bits of the serial I/O1 status register are set to “0” at reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift register shift completion flag and the transmit buffer empty flag become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of the bits which set the data format of an data transmit and receive, and the bit which sets the output structure of the P45/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator is the 8-bit counter equipped with a reload register. Set the division value of the BRG count source to the baud rate generator. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. ■Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronous with the transmission enabled, take the following sequence. ➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁Set the transmit enable bit to “1”. ➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). Rev.1.02 Jul 31, 2003 page 32 of 69 7560 Group (A version) b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (“1” at reading) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44–P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44–P47 operate as serial I/O pins) b7 b0 UART control regi ster (UART CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (“1” at reading) Fig. 30 Structure of serial I/O1 control registers Rev.1.02 Jul 31, 2003 page 33 of 69 7560 Group (A version) Serial I/O2 Serial I/O2 can be used only for clock synchronous serial I/O. For serial I/O2, the transmitter and the receiver must use the same clock as a synchronous clock. When an internal clock is selected as a synchronous clock, the serial I/O2 is initialized and, transmit and receive is started by a write signal to the serial I/O2 register. When an external clock is selected as an synchronous clock, the serial I/O2 counter is initialized by a write signal to the serial I/O2 register, serial I/O2 becomes the state where transmission or reception can be performed. Write to the serial I/O2 register while SCLK21 is “H” state when an external clock is selected as an synchronous clock. Either P62/SCLK21 or P63/SCLK22 pin can be selected as an output pin of the synchronous clock. In this case, the pin that is not selected as an output pin of the synchronous clock functions as a I/ O port. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock select bits b2 b1 b0 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 0 0: Do not select 1 0 1: 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK21/SCLK22 signal output P61/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock Synchronous clock output pin selection bit 0: SCLK21 1: SCLK22 [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight control bits for the serial I/O2 functions. After setting to this register, write data to the serial I/O2 register and start transmit and receive. Fig. 31 Structure of serial I/O2 control register 1/8 1/16 1/32 1/64 1/128 1/256 Internal synchronous clock select bits Data bus XIN P63 latch (Note) Serial I/O2 synchronous clock selection bit Synchronous circuit “1” P63/SCLK22 Divider SCLK2 External clock P62 latch “0” “0” P62/SCLK21 (Note) “1” P61 latch “0” Serial I/O2 counter (3) Serial I/O2 interrupt request P61/SOUT2 “1” Serial I/O2 port selection bit P60/SIN2 Serial I/O 2 register (8) Note: It is selected by the serial I/O2 synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial I/O2 port selection bit. Fig. 32 Block diagram of serial I/O2 function Rev.1.02 Jul 31, 2003 page 34 of 69 7560 Group (A version) ●Serial I/O2 Operating The serial I/O2 counter is initialized to “7” by writing to the serial I/O2 register. After writing, whenever a synchronous clock changes from “H” to “L”, data is output from the SOUT2 pin. Moreover, whenever a synchronous clock changes from “L” to “H”, data is taken in from the SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out simultaneously. When the internal clock is selected as a synchronous clock, it is as follows if a synchronous clock is counted 8 times. •Serial I/O2 counter = “0” •Synchronous clock stops in “H” state •Serial I/O2 interrupt request bit = “1” The SOUT2 pin is in a high impedance state after transfer is completed. When the external clock is selected as a synchronous clock, if a synchronous clock is counted 8 times, the serial I/O2 interrupt request bit is set to “1”, and the SOUT2 pin holds the output level of D7. However, if a synchronous clock continues being input, the shift of the serial I/O2 register is continued and transmission data continues being output from the SOUT2 pin. Synchronous clock (Note 1) Serial I/O2 register write signal (Notes 2, 3) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 interrupt request bit = “1” Notes 1: When the internal clock is selected as the synchronous clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the synchronous clock, the SOUT2 pin goes to high impedance after transfer completion. 3: When the external clock is selected as the synchronous clock, the SOUT2 pin keeps D7 output level after transfer completion. However, if synchronous clocks input are carried on, the transmit data will be output continuously from the SOUT2 pin because shifts of serial I/O2 shift register is continued as long as synchronous clocks are input. Fig. 33 Timing of serial I/O2 function Rev.1.02 Jul 31, 2003 page 35 of 69 7560 Group (A version) PULSE WIDTH MODULATION (PWM) The 7560 group has a PWM function with an 8-bit resolution, using f(XIN) or f(XIN)/2 as a count source. PWM Operation When either bit 1 (PWM0 function enable bit) or bit 2 (PWM1 function enable bit) of the PWM control register or both bits are enabled, operation starts from initializing status, and pulses are output starting at “H”. When one PWM output is enabled and that the other PWM output is enabled, PWM output which is enabled to output later starts pulse output from halfway of PWM period (see Figure 37). When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pins are shared with ports P50 and P51. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If PWM count source is f(XIN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1)/f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H” period = PWM period ✕ m/255 = 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz) 31.875 ✕ m ✕ (n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(X IN ) = 8 MHz) Fig. 34 Timing of PWM cycle Data bus PWM prescaler pre-latch PWM register pre-latch PWM1 function enable bit Transfer control circuit PWM prescaler latch Count source selection bit “0” XIN 1/2 “1” PWM prescaler PWM register latch Port P51 lacth P51 /PWM1 PWM circuit P50 /PWM0 Port P50 lacth PWM0 function enable bit Fig. 35 Block diagram of PWM function Rev.1.02 Jul 31, 2003 page 36 of 69 7560 Group (A version) b7 b0 PWM control register (PWMCON : address 002B16) Count source selection bit 0 : f(XIN) 1 : f(XIN)/2 PWM0 function enable bit 0 : PWM0 disabled 1 : PWM0 enabled PWM1 function enable bit 0 : PWM1 disabled 1 : PWM1 enabled Not used (“0” at reading) Fig. 36 Structure of PWM control register A B C B=C T2 T PWM (internal) stop T T T2 stop PWM 0 output Port Port PWM 1 output Port Port PWM register write signal (Changes from “A” to “B” during “H” period) PWM prescaler write signal (Changes from “T” to “T2” during PWM period) PWM 0 function enable bit PWM 1 function enable bit When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 37 PWM output timing when PWM register or PWM prescaler is changed Rev.1.02 Jul 31, 2003 page 37 of 69 7560 Group (A version) A-D CONVERTER [A-D Conversion Low-Order Register (ADL)] 001416 [A-D Conversion High-Order Register (ADH)] 003516 The A-D conversion registers are read-only registers that store the result of an A-D conversion . When reading this register during an A-D conversion, the previous conversion result is read. The high-order 8 bits of a conversion result is stored in the A-D conversion high-order register (address 003516), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion low-order register (address 001416). Bit 0 of the A-D conversion low-order register is the conversion mode selection bit. When this bit is set to “0”, that becomes the 10-bit A-D mode. When this bit is set to “1”, that becomes the 8-bit A-D mode. Comparator and Control Circuit The comparator and control circuit compare an analog input voltage with the comparison voltage and store the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD converter interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. Use the clock divided from the main clock f(XIN) as the system clock φ. b7 b0 A-D control register (ADCON : address 003416) Analog input pin selection bits b2b1b0 [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then it is set to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 is the VREF input switch bit which controls connection of the resistor ladder and the reference voltage input pin (VREF). The resistor ladder is always connected to VREF when bit 4 is set to “1”. When bit 4 is set to “0”, the resistor ladder is cut off from VREF except for A-D conversion performed. When bit 5, which is the AD external trigger valid bit, is set to “1”, A-D conversion starts also by a falling edge of an ADT input. When using an A-D external trigger, set the P57/ADT pin to input mode (set “0” to bit 7 of port P5 direction register). 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : P60/AN0 1 : P61/AN1 0 : P62/AN2 1 : P63/AN3 0 : P64/AN4 1 : P65/AN5 0 : P66/AN6 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : AUTO 1 : ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input falling Not used (“0” at reading) b7 b0 A-D conversion low-order register (ADL : address 001416) Conversion mode selection bit 0 : 10-bit A-D mode 1 : 8-bit A-D mode Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF by 256 (when 8-bit A-D mode) or 1024 (when 10bit A-D mode), and outputs the divided voltages. Not used (“0” at reading) •For 10-bit A-D mode A-D conversion result •For 8-bit A-D mode Not used (undefined at reading) Channel Selector The channel selector selects one of the input ports P6 7/AN7–P60/AN0. Fig. 38 Structure of A-D converter-related registers Rev.1.02 Jul 31, 2003 page 38 of 69 7560 Group (A version) •10-bit reading (Read address 003516, then 001416) b7 b0 A-D conversion high-order register b9 b8 b7 b6 b5 b4 b3 b2 (high-order) (ADH: Address 003516) b7 b0 A-D conversion low-order register (ADL: Address 001416) b1 b0 (low-order) Conversion mode selection bit 0 : 10-bit A-D mode 1 : 8-bit A-D mode Note : Bits 0 to 5 of address 001416 become “0” at reading. •8-bit reading (Read only address 003516) b7 b0 A-D conversion high-order register (ADH: Address 003516) b7 b6 b5 b4 b3 b2 b1 b0 Fig. 39 Read of A-D conversion register Data bus b 7 b 0 A-D control register P57/ADT/DA2 3 A-D control circuit A-D conversion high-order register (Address 003516) P60/SIN2/AN0 P61/SOUT2/AN1 P62/SCLK21/AN2 P63/SCLK22/AN3 P64/ AN4 P65/ AN5 P66/ AN6 P67/ AN7 Channel selector ADT/A-D interrupt request A-D conversion low-order register (Address 001416) Comparato r 8 Resistor ladder AVSS VRE Fig. 40 A-D converter block diagram Rev.1.02 Jul 31, 2003 page 39 of 69 7560 Group (A version) D-A Converter The 7560 group has a D-A converter with 8-bit resolution and 2 channels (DA1, DA2). The D-A converter is started by setting the value in the D-A conversion register. When the DA1 output enable bit or the DA2 output enable bit is set to “1”, the result of D-A conversion is output from the corresponding DA pin. When using the D-A converter, set the P56/DA1 pin and the P57/DA2 pin to input mode (set “0” to bits 6, 7 of port P5 direction register) and the pull-up resistor should be in the OFF state (set “0” to bit 3 of PULL register B) previously. The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=VREF ✕ n/256 (n=0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are set to “0016”, the DA1 output enable bit and the DA2 output enable bit are set to “0”, and the P5 6/DA 1 p in and the P5 7/DA 2 p in goes to high impedance state. The DA converter is not buffered, so connect an external buffer when driving a low-impedance load. ■ Note on applied voltage to VREF pin When these pins are used as D-A conversion output pins, the Vcc level is recommended for the applied voltage to VREF pin. When the voltage below Vcc level is applied, the D-A conversion accuracy may be worse. b7 b0 D-A control register (DACON : address 003616) 000000 DA1 output enable bit 0 : Disabled 1 : Enabled DA2 output enable bit 0 : Disabled 1 : Enabled Not used (“0” at reading) (Write “0” to these bits at writing.) Fig. 41 Structure of D-A control register Data bus D-A1 conversion register (8) (DA1: address 003216) DA1 output enable bit R-2R resistor ladder P56/DA1 D-A2 conversion register (8) (DA2: address 003316) DA2 output enable bit R-2R resistor ladder P57/DA2 Fig. 42 Block diagram of D-A converter Rev.1.02 Jul 31, 2003 page 40 of 69 7560 Group (A version) “0” DAi output enable bit R DAi “1” MSB D-Ai conversion register “0” “1” 2R R R R R R R 2R 2R 2R 2R 2R 2R 2R 2R LSB AVSS VREF Fig. 43 Equivalent connection circuit of D-A converter Rev.1.02 Jul 31, 2003 page 41 of 69 7560 Group (A version) LCD DRIVE CONTROL CIRCUIT The 7560 group has the Liquid Crystal Display (LCD) drive control circuit consisting of the following. LCD display RAM Segment output enable register LCD mode register Voltage multiplier Selector Timing controller Common driver Segment driver Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD • • • • • • • • • enable bit is set to “1” (LCD ON) after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 9 Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits b7 b0 Segment output enable register (SEG : address 003816) Segment output enable bit 0 0 : Output ports P30–P35 1 : Segment output SEG18–SEG23 Segment output enable bit 1 0 : Output ports P36, P37 1 : Segment output SEG24,SEG25 Segment output enable bit 2 0 : I/O ports P00–P05 1 : Segment output SEG26–SEG31 Segment output enable bit 3 0 : I/O ports P06,P07 1 : Segment output SEG32,SEG33 Segment output enable bit 4 0 : I/O port P10 1 : Segment output SEG34 Segment output enable bit 5 0 : I/O ports P11–P15 1 : Segment output SEG35–SEG39 LCD output enable bit 0 : Disabled 1 : Enabled Not used (“0” at reading) (Write “0” to this bit at writing.) 0 b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits b1b0 0 0 : Not used 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0–COM2) 1 1 : 4 duty (use COM0–COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disable 1 : Voltage multiplier enable LCD circuit divider division ratio selection bits b6b5 0 0 : Clock input 0 1 : 2 division of Clock input 1 0 : 4 division of Clock input 1 1 : 8 division of Clock input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) Note : LCDCK is a clock for a LCD timing controller. Fig. 44 Structure of segment output enable register and LCD mode register Rev.1.02 Jul 31, 2003 page 42 of 69 Fig. 45 Block diagram of LCD controller/driver Rev.1.02 Jul 31, 2003 page 43 of 69 7560 Group (A version) Data bus LCD enable bit Address 004016 Address 004116 Address 005316 LCD display RAM Duty ratio selection bits LCD circuit divider division ratio selection bits 2 Voltage multiplier control bit Bias control bit 2 LCDCK count source selection bit “0” f(XCIN)/ 32 “1” f(XIN)/8192 (f(XCIN)/8192 in lowspeed mode) LCD divider Selector Selector Selector Selector Selector Selector Timing controller LCDCK Level shift Level shift Level shift Level shift Level shift Level shift Bias control Level Shift VCC Level Shift Level Shift Level Shift Segment Segment Segment Segment driver driver driver driver Segment Segment driver driver LCD output Common Common Common Common enable bit driver driver driver driver SEG0 SEG1 SEG2 SEG3 P30/SEG18 P14/SEG38 P15/SEG39 VSS VL1 VL2 VL3 C1 C2 COM0 COM1 COM2 COM3 7560 Group (A version) Voltage Multiplier (3 Times) The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage multiplier. 1. Set the segment output enable bits (bits 0 to 5) of the segment output enable register to “0” or “1”. 2. Set the duty ratio selection bits (bits 0 and 1), the bias control bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to “0” or “1”. 3. Set the LCD output enable bit (bit 6) of the segment output enable register to “1” (enabled). Apply the limit voltage or less to the VL1 pin. 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to “1” (voltage multiplier enabled). However, be sure to select 1/3 bias for bias control. When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. ■Notes on Voltage Multiplier When using the voltage multiplier, apply the limit voltage or less to the VL1 pin, then set the voltage multiplier control bit to “1” (enabled). When not using the voltage multiplier, set the LCD output enable bit to “1”, then apply proper voltage to the LCD power input pins (VL1–VL3). When the LCD output enable bit is set to “0” (disabled) (during reset is included), the VL3 pin is connected to VCC inside of this microcomputer. When the voltage exceeding VCC is applied to VL3, apply VL3 voltage after setting the LCD output enable bit to “1” (enabled). Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–VL3), apply the voltage shown in Table 10 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 10 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD 1/2 bias Note : V LCD i s the maximum value of supplied voltage for the LCD panel. VCC Contrast control VCC Contrast control VL3 VL2 C2 C1 VL1 1/3 bias when using the voltage multiplier VL3 R1 VL2 C2 C1 VL1 1/3 bias when not using the voltage multiplier Open VL3 R4 VL2 C2 R2 Open Open C1 VL1 1/2 bias Open R3 R5 R1 = R2 = R3 Fig. 46 Example of circuit at each bias R4 = R5 Rev.1.02 Jul 31, 2003 page 44 of 69 7560 Group (A version) Common Pin and Duty Ratio Control The common pins (COM 0–COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). After reset, the VCC (VL3) voltage is output from the common pins. LCD Display RAM Addresses 004016 to 005316 are the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The frequency of internal signal LCDCK decided LCD drive timing and the frame frequency can be determined with the following equation: Table 11 Duty ratio control and common pins used Duty ratio 2 3 4 Duty ratio selection bits Bit 1 0 1 1 Bit 0 1 0 1 Common pins used COM0, COM1 (Note 1) COM0–COM2 (Note 2) COM0–COM3 f(LCDCK)= (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) duty ratio Notes 1: COM2 and COM3 are open. 2: COM3 is open. Frame frequency= Segment Signal Output Pins Segment signal output pins are classified into the segment-only pins (SEG 0–SEG17), the segment or output port pins (SEG18– SEG25), and the segment or I/O port pins (SEG26–SEG39). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset, a V CC (=VL3) voltage is output to the segment-only pins and the segment/output port pins are the high impedance condition and pulled up to VCC (=VL3) voltage. Also, the segment/I/O port pins(SEG26–SEG39) are set to input mode as I/O ports, and VCC (=VL3) is applied to them by pull-up resistor. Bit 7 Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 SEG1 SEG0 SEG3 SEG2 SEG5 SEG4 SEG7 SEG6 SEG9 SEG8 SEG11 SEG10 SEG13 SEG12 SEG15 SEG14 SEG17 SEG16 SEG19 SEG18 SEG21 SEG20 SEG23 SEG22 SEG25 SEG24 SEG27 SEG26 SEG29 SEG28 SEG31 SEG30 SEG33 SEG32 SEG35 SEG34 SEG37 SEG36 SEG39 SEG38 6 5 4 3 2 1 0 Fig. 47 LCD display RAM map Rev.1.02 Jul 31, 2003 page 45 of 69 7560 Group (A version) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 COM1 ON COM0 OFF COM2 COM1 ON COM0 OFF COM2 VL3 VL2=VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 48 LCD drive waveform (1/2 bias) Rev.1.02 Jul 31, 2003 page 46 of 69 7560 Group (A version) Internal signal LCDCK timing 1/4 duty Voltage level COM0 VL3 VL2 VL1 VSS COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 COM1 ON COM0 OFF COM2 COM1 ON COM0 OFF COM2 VL3 VL2 VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 49 LCD drive waveform (1/3 bias) Rev.1.02 Jul 31, 2003 page 47 of 69 7560 Group (A version) Watchdog Timer The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6bit watchdog timer H. At reset or writing to the watchdog timer control register (address 0037 16), the watchdog timer is set to “3FFF16”. When any data is not written to the watchdog timer control register (address 003716) after reset, the watchdog timer is stopped. The watchdog timer starts to count down from “3FFF16” by writing to the watchdog timer control register and an internal reset occurs at an underflow. Accordingly, when using the watchdog timer function, write the watchdog timer control register before an underflow. The watchdog timer does not function when writing to the watchdog timer control register has not been done after reset. When not using the watchdog timer, do not write to it. When the watchdog timer control register is read, the following values are read: “FF16” is set when watchdog timer is written to. Watchdog timer L (8) ● value of high-order 6-bit counter ● value of STP instruction disable bit ● value of count source selection bit. When the STP instruction disable bit is “0”, the STP instruction is enabled. The STP instruction is disabled when this bit is set to “1”. If the STP instruction which is disabled is executed, it is processed as an undefined instruction, so that a reset occurs internally. This bit can be set to “1” but cannot be set to “0” by program. This bit is “0” after reset. When the watchdog timer H count source selection bit is “0”, the detection time is set to 8.19 s at f(XCIN) = 32 kHz and 32.768 ms at f(XIN) = 8 MHz. When the watchdog timer H count source selection bit is “0”, the detection time is set to 32 ms at f(XCIN) = 32 kHz and 128 µs at f(XIN) = 8 MHz. There is no difference in the detection time between the middle-speed mode and the high-speed mode. Data bus Watchdog timer H count source selection bit “0” “1” Watchdog timer H (6) XCIN “1” Internal system clock selection bit (Note) “0” XIN 1/16 Undefined instruction Reset STP instruction disable bit STP instruction RESET “3F16” is set when watchdog timer is written to. Internal reset Reset circuit Reset release time wait Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode. Fig. 50 Block diagram of watchdog timer b7 b0 Watchdog timer register (WDTCON: address 003716) Watchdog timer H (for read-out of high-order 6 bit) “3FFF16” is set to the watchdog timer by writing values to this address. STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selecion bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 or f(XCIN)/16 Fig. 51 Structure of watchdog timer control register f(XIN) Internal reset signal Watchdog timer detection Fig. 52 Timing of reset output Approx. 1 ms (f(XIN) = 8 MHZ) Rev.1.02 Jul 31, 2003 page 48 of 69 7560 Group (A version) TOUT/φ OUTPUT FUNCTION The system clock φ or timer 2 divided by 2 (TOUT output) can be output from port P43 by setting the TOUT/φ output enable bit of the timer 123 mode register and the TOUT/ φ output control register. Set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register) when outputting TOUT/φ. b7 b0 TOUT/φ output control register (CKOUT : address 002A16) TOUT/φ output control bit 0 : System clock φ output 1 : TOUT output Not used (“0” at reading) b7 b0 Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT/φ output enable bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (“0” at reading) Fig. 53 Structure of TOUT/φ output-related registers Rev.1.02 Jul 31, 2003 page 49 of 69 7560 Group (A version) RESET CIRCUIT When the power source voltage is within limits, and main clock XIN-XOUT is stable, or a stabilized clock is input to the XIN pin, if the RESET pin is held at an “L” level for 2 µs or more, the microcomputer is in an internal reset state. Then the RESET pin is returned to an “H” level, reset is released after approximate 8200 cycles of f(XIN), the program in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.2 VCC(min.) for the power source voltage of VCC(min.). *V CC (min.) = Minimum value of power supply voltage limits applied to VCC pin (Note) VCC 0V RESET VCC RESET VCC Power source voltage detection circuit RESET 0V 0.2VCC level 2 µs X IN 0V Power on Oscillation stabilized Note: Reset release voltage Vcc = Vcc (min.) Fig. 54 Example of reset circuit XI N System clock φ RESET Internal reset Reset address from vector table Address Data Undefined Undefined Undefined Undefined FFFC A DL FFFD A D H, A D L A DH SYNC XIN : Approx. 8200 cycles Note : The frequency of system clock φ is f(XIN) divided by 8. Fig. 55 Reset Sequence Rev.1.02 Jul 31, 2003 page 50 of 69 7560 Group (A version) Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 output control register (5) Port P4 direction register (6) Port P5 direction register (7) Port P6 direction register (8) Port P7 direction register 000116 000316 000516 000716 000916 000B16 000D16 000F16 Register contents 0016 0016 0016 0016 0016 0016 0016 0016 (9) AD conversion low-order register 001416 ✕ ✕ 0 0 0 0 0 1 (10) Key input control register (11) PULL register A (12) PULL register B (13) Serial I/O1 status register (14) Serial I/O1 control register (15) UART control register (16) Serial I/O2 control register (17) Timer X low-order register (18) Timer X high-order register (19) Timer Y low-order register (20) Timer Y high-order register (21) Timer 1 register (22) Timer 2 register (23) Timer 3 register (24) Timer X mode register (25) Timer Y mode register (26) Timer 123 mode register (27) TOUT/φ output control register (28) PWM control register (29) D-A1 conversion register (30) D-A2 conversion register (31) A-D control register (32) D-A control register (33) Watchdog timer control register (34) Segment output enable register (35) LCD mode register 001516 001616 001716 0016 3F16 0016 001916 1 0 0 0 0 0 0 0 001A16 0016 001B16 1 1 1 0 0 0 0 0 001D16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 003216 003316 0016 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016 0016 0016 0016 003416 0 0 0 0 1 0 0 0 003616 0016 003716 0 0 1 1 1 1 1 1 003816 003916 0016 0016 0016 (36) Interrupt edge selection register 003A16 (37) CPU mode register (38) Interrupt request register 1 (39) Interrupt request register 2 (40) Interrupt control register 1 (41) Interrupt control register 2 (42) Processor status register (43) Program counter 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0016 0016 0016 0016 (PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕ (PCH) (PCL) Contents of address FFFD16 Contents of address FFFC16 (44) Watchdog timer (high-order) (45) Watchdog timer (low-order) 3F16 FF16 Note: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined Fig. 56 Internal state of microcomputer immediately after reset Rev.1.02 Jul 31, 2003 page 51 of 69 7560 Group (A version) CLOCK GENERATING CIRCUIT The 7560 group has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting an oscillator between X IN a nd X OUT ( X CIN a nd X COUT). Use the circuit constants in accordance with the oscillator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT since a resistor does not exist between them. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external oscillator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high-impedance state. Oscillation Control (1) Stop mode If the STP instruction is executed, the system clock φ stops at an “H” level, and main and sub clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Before the STP instruction, set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits are set to timer 1, high-order 8 bits are set to timer 2). Either f(XIN) or f(XCIN) divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are set to “0”. Set the timer 1 and timer 2 interrupt enable bits to “0” before executing the STP instruction. Oscillation restarts at reset or when an external interrupt is received, but the system clock φ i s not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize when a ceramic resonator is used. Frequency Control (1) Middle-speed mode The clock input to the XIN pin is divided by 8 and it is used as the system clock φ. After reset, this mode is selected. (2) Wait mode If the WIT instruction is executed, only the system clock φ stops at an “H” state. The states of main clock and sub clock are the same as the state before the executing the WIT instruction, and oscillation does not stop. Since supply of internal clock φ is started immediately after the interrupt is received, the instruction can be executed immediately. (2) High-speed mode The clock input to the XIN pin is divided by 2 and it is used as the system clock φ. (3) Low-speed mode • The clock input to the XCIN pin is divided by 2 and it is used as the system clock φ. •A low-power consumption operation can be realized by stopping the main clock in this mode. To stop the main clock, set the main clock stop bit of the CPU mode register to “1”. When the main clock is restarted, after setting the main clock stop bit to “0”, set enough time for oscillation to stabilize by program. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN a nd XCIN o scillations. The sufficient time is required for the sub clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency in the condition that f(XIN) > 3•f(XCIN). XCIN XCOUT Rf CCIN Rd CCOUT XIN XOUT CI N COUT Fig. 57 Oscillator circuit XCIN Rf CCIN XCOUT Rd CCOUT XIN XOUT Open External oscillation circuit VCC VSS Fig. 58 External clock input circuit Rev.1.02 Jul 31, 2003 page 52 of 69 7560 Group (A version) XCIN XCOUT “1” “0” XC switch bit (Note) XIN XOUT System clock selection bit (Note) Low-speed mode 1/2 Middle-/High-speed mode 1/4 1/2 Timer 1 count source selection bit “1” Timer 1 “0” Timer 2 count source selection bit “0” Timer 2 “1” Main clock division ratio selection bit Middle-speed mode System clock φ High-speed mode or Low-speed mode Main clock stop bit Q S R WIT instruction S STP instruction R Q Q S R STP instruction Reset Interrupt disable flag I Interrupt request Note: When using the sub clock for the system clock φ, set the XC switch bit to “1”. Fig. 59 Clock generating circuit block diagram Rev.1.02 Jul 31, 2003 page 53 of 69 7560 Group (A version) Reset Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM6 “1” “0” High-speed mode (f(φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM ” “1 M6 C ” “1 4 ” “0 ” “0 C “0 M4 CM ” “1 6 ” “1 ” “0 ” “0” CM4 “1” CM4 CM7 Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1” “0” High-speed mode (f(φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) “0” CM7 “1” Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1” “0” Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) “1” “0” “1” “0” b7 b4 CPU mode register (CPUM : address 003B16) ” “0 CM” “1 M6 C ” “1 5 CM5 Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) CM6 “1” “0” Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) Notes 1: Switch the mode according to the arrows shown between the mode blocks. (Do not switch between the mode directly without an arrow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3: When the stop mode is ended, a delay time can be set by timer 1 and timer 2. 4: Timer and LCD operate in the wait mode. 5: Wait until oscillation stabilizes after oscillating the main clock before the switching from the low-speed mode to middle-/high-speed mode. 6: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the system clock. Fig. 60 State transitions of system clock Rev.1.02 Jul 31, 2003 page 54 of 69 CM5 “1” ” “0 C “0 M5 CM ” “1 6 ” “1 ” “0 ” CM4 : Xc switch bit 0: Oscillation stop 1: XCIN, XCOUT CM5 : Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : System clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) “0” “1” “0” 7560 Group (A version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags (T flag, D flag, etc.) which affect program execution. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. The TxD pin of serial I/O1 retains the level then after transmission is completed. In serial I/O2 selecting an internal clock, the S OUT2 pin goes to high impedance state after transmission is completed. In serial I/O2 selecting an external clock, the SOUT2 pin retains the level then after transmission is completed. Interrupt When the contents of an interrupt request bits are changed by the program, execute a BBC or BBS instruction after at least one instruction. This is for preventing executing a BBC or BBS instruction to the contents before change. A-D Converter Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The input to the comparator is combined by internal capacitors. Therefore, since conversion accuracy may be worse by losing of an electric charge when the conversion speed is not enough, make sure that f(XIN) is at least 500 kHz during an A-D conversion. The normal operation of A-D conversion cannot be guaranteed when performing the next operation: •When writing to CPU mode register during A-D conversion operation •When writing to A-D control register during A-D conversion operation •When executing STP instruction or WIT instruction during A-D conversion operation Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Instruction Execution Time Ports Use instructions such as LDM and STA, etc., to set the port direction registers. The contents of the port direction registers cannot be read. The following cannot be used: • LDA instruction • The memory operation instruction when the T flag is “1” • The bit-test instruction (BBC or BBS, etc.) • The read-modify-write instruction (calculation instruction such as ROR etc., bit manipulation instruction such as CLB or SEB etc.) • The addressing mode which uses the value of a direction register as an index The instruction execution time is obtained by multiplying the frequency of the system clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the system clock φ depends on the main clock division ratio selection bit and the system clock selection bit. Rev.1.02 Jul 31, 2003 page 55 of 69 7560 Group (A version) NOTES ON USE Countermeasures Against Noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS p in with the shortest possible wiring (within 20 mm). ● Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise XIN XOUT VSS N.G. Fig. 62 Wiring for clock I/O pins XIN XOUT VSS O.K. Noise Reset circuit VSS N.G. RESET VSS (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Reset circuit VSS RESET VSS VCC VCC O.K. Fig. 61 Wiring for the RESET pin ➁ Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. ● Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. VSS VSS N.G. O.K. Fig. 63 Bypass capacitor across the VSS line and the VCC line Rev.1.02 Jul 31, 2003 page 56 of 69 7560 Group (A version) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful especially when range of voltage or/and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. ● Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. ● Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (4) Analog input The analog input pin is connected to the capacitor of a comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A-D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A-D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A-D conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evaluation for each product of every after confirming product specification. ➀ Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M Large current GND ➁ Installing oscillator away from signal lines where potential levels change frequently XIN XOUT VSS N.G. Do not cross CNTR XIN XOUT VSS Fig. 64 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently Rev.1.02 Jul 31, 2003 page 57 of 69 7560 Group (A version) ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. • For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/ Rev.1.02 Jul 31, 2003 page 58 of 69 7560 Group (A version) ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Table 12 Absolute maximum ratings Symbol VCC VI VI VI VI VI VI VI VO VO VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67 Input voltage P70–P77 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 Output voltage P00–P07, P10–P15, P30–P37 Output voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77 Output voltage VL3 Output voltage VL2, SEG0–SEG17 Output voltage XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V V V V V V V V V mW °C °C At output port At segment output Ta = 25°C RECOMMENDED OPERATING CONDITIONS Table 13 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VCC Power source voltage (Note 1) Parameter High-speed mode f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Min. 4.5 4.0 3.0 2.0 3.0 2.0 1.8 1.8 0.15 ✕ f+1.3 1.3 2.0 AVSS Limits Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 1.8 0 VCC Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V V V V Middle-speed mode Low-speed mode At start oscillating (Note 2) VSS VLI VREF AVSS VIA Power source voltage Power source voltage At using voltage multiplier A-D, D-A conversion reference voltage Analog power source voltage Analog input voltage AN0–AN7 2.1 VCC Notes 1: When using the A-D or D-A converter, refer to “A-D Converter Characteristics” or “D-A Converter characteristics”. 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. f: This is an oscillator’s oscillation frequency. For example, when oscillation frequency is 8 MHz, substitute “8”. Rev.1.02 Jul 31, 2003 page 59 of 69 7560 Group (A version) Table 14 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VIH VIH VIH VIH VIL VIL VIL VIL “H” input voltage “H” input voltage “H” input voltage “H” input voltage “L” input voltage “L” input voltage “L” input voltage “L” input voltage Parameter P00–P07, P10–P17, P40, P43, P45, P47, P50–P53, P56, P61, P64–P67, P71–P77 P20–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET XIN P00–P07, P10–P17, P40, P43, P45, P47, P50–P53, P56, P61, P64–P67, P71–P77 P20–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET XIN Min. 0.7 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0 0 0 0 Limits Typ. Max. VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.2 VCC 0.2 VCC Unit V V V V V V V V Table 15 Recommended operating conditions (3) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current “H” peak output current “H” peak output current “L” peak output current “L” peak output current “L” peak output current “H” average output current “H” average output current “L” average output current “L” average output current “L” average output current Parameter P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) P40, P71–P77 (Note 2) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) P40, P71–P77 (Note 3) Limits Min. Typ. Max. –20 –20 20 20 80 –10 –10 10 10 40 –1.0 –5.0 5.0 10 20 –0.5 –2.5 2.5 5.0 10 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. Rev.1.02 Jul 31, 2003 page 60 of 69 7560 Group (A version) Table 16 Recommended operating conditions (4) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol f(CNTR0) f(CNTR1) Parameter Input frequency for timers X and Y (duty cycle 50%) Test conditions (4.5 V ≤ VCC ≤ 5.5 V) (4.0 V ≤ VCC < 4.5 V) (2.0 V ≤ VCC < 4.0 V) (VCC < 2.0 V) High-speed mode (4.5 V ≤ VCC ≤ 5.5 V) High-speed mode (4.0 V ≤ VCC < 4.5 V) High-speed mode (2.0 V ≤ VCC < 4.0 V) Middle-speed mode (Note 3) (3.0 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 3) (2.0 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 3) 32.768 Min. Limits Typ. Max. 5.0 2✕VCC–4 VCC 5✕VCC–8 10.0 4✕VCC–8 2✕VCC 10.0 8.0 6.0 50 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz f(XIN) Main clock input oscillation frequency (Note 1) f(XCIN) Sub-clock input oscillation frequency (At duty 50 %) (Notes 2, 3) Notes 1: When using the A-D or D-A converter, refer to “A-D Converter Characteristics” or “D-A Converter characteristics”. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. Rev.1.02 Jul 31, 2003 page 61 of 69 7560 Group (A version) Table 17 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter “H” output voltage P00–P07, P10–P15, P30–P37 “H” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 Test conditions IOH = –1 mA IOH = –0.25 mA VCC = 2.2 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V IOL = 10 mA IOL = 5 mA VCC = 2.2 V Limits Min. VCC–2.0 VCC–0.8 VCC–2.0 VCC–0.5 VCC–0.8 2.0 0.5 0.8 2.0 0.5 0.8 0.5 0.3 0.5 0.5 0.5 5.0 Typ. Max. Unit V V V V V V V V V V V V V V V V µA VOH VOH VOL “L” output voltage P00–P07, P10–P15, P30–P37 VOL “L” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 “L” output voltage P40, P71–P77 Hysteresis INT0–INT2, ADT, CNTR0, CNTR1, P20–P27 Hysteresis SCLK, RXD, SIN2 Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67, P70–P77 “H” input current RESET “H” input current XIN “L” input current P00–P07,P10–P17, P20–P27,P41–P47, P50–P57, P60–P67 VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL VCC = 2.0 V to 5.0 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” VCC = 2.2 V, VI = VSS Pull-ups “on” VI = VSS VI = VSS VCC = 5.0 V, VO = VCC, Pullup ON Output transistors “off” VCC = 2.2 V,VO = VCC, Pullup ON Output transistors “off” VO = VCC, Pullup OFF Output transistors “off” VO = VSS, Pullup OFF Output transistors “off” 5.0 4.0 –5.0 –60.0 –5.0 –120.0 –20.0 –240.0 –40.0 –5.0 –5.0 –60.0 –5.0 –4.0 –120.0 –20.0 –240.0 –40.0 5.0 –5.0 µA µA µA µA µA µA µA µA µA µA µA µA IIL IIL IIL ILOAD “L” input current P40, P70–P77 “L” input current RESET “L” input current XIN Output load current P30–P37 ILEAK Output leak current P30–P37 Rev.1.02 Jul 31, 2003 page 62 of 69 7560 Group (A version) Table 18 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VRAM ICC Parameter RAM retention voltage Power source current At clock stop mode • High-speed mode, VCC = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter stop • Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” VL1 = 1.8 V Ta = 25 °C Ta = 85 °C 4.0 0.1 1.0 10 µA µA µA 4.5 9.0 µA 9 18 µA 7 14 µA 15 30 µA 0.9 1.8 mA 4.0 8.0 mA Test conditions Min. 1.8 4.5 Limits Typ. Max. 5.5 9.0 Unit V mA IL1 Power source current (VL1) (Note) Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. Rev.1.02 Jul 31, 2003 page 63 of 69 7560 Group (A version) Table 19 A-D converter characteristics (1) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 8-bit A-D mode (when conversion mode selection bit (bit 0 of address 001416) is “1”) Symbol – – tCONV RLADDER IVREF IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current 12 50 35 150 Test conditions Min. Limits Typ. Max. 8 ±2 12.5 (Note) 100 200 5.0 Unit Bits LSB µS kΩ µA µA VCC = VREF = 2.7 to 5.5 V VREF = 5 V Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 14 µS. Table 20 A-D converter characteristics (2) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 10-bit A-D mode (when conversion mode selection bit (bit 0 of address 001416) is “0”) Symbol – – tCONV RLADDER IVREF IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current Analog port input current 12 50 35 150 Test conditions Min. Limits Typ. Max. 10 ±4 15.5 (Note) 100 200 5.0 Unit Bits LSB µS kΩ µA µA VCC = VREF = 2.7 to 5.5 V VREF = 5 V Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 17 µS. Table 21 D-A converter characteristics (VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted) Symbol – – tsu RO IVREF Resolution Absolute accuracy Setting time Output resistor Reference power source input current VCC = VREF = 5 V VCC = VREF = 2.7 V 1 (Note) 3 2.5 Parameter Test conditions Min. Limits Typ. Max. 8 1.0 2.0 4 3.2 Unit Bits % % µs kΩ mA Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through the A-D resistance ladder. Rev.1.02 Jul 31, 2003 page 64 of 69 7560 Group (A version) Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RXD–SCLK2) th(SCLK2–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time Min. (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 100 1000/(4✕Vcc-8) 40 45 40 45 200 1000/(2✕Vcc-4) 85 105 85 105 80 80 800 370 370 220 100 1000 400 400 200 200 Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Rev.1.02 Jul 31, 2003 page 65 of 69 7560 Group (A version) Table 23 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RXD–SCLK2) th(SCLK2–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O2 input set up time Serial I/O2 input hold time Min. Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 (2.0 V ≤ VCC ≤ 4.0 V) 125 (VCC < 2.0 V) 1000/(10✕Vcc-12) (2.0 V ≤ VCC ≤ 4.0 V) 50 (VCC < 2.0 V) 70 (2.0 V ≤ VCC ≤ 4.0 V) 50 (VCC < 2.0 V) 70 (2.0 V ≤ VCC ≤ 4.0 V) 1000/VCC (VCC < 2.0 V) 1000/(5✕Vcc-8) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 2000 950 950 400 200 Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Rev.1.02 Jul 31, 2003 page 66 of 69 7560 Group (A version) Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note) Serial I/O1 output valid time (Note) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time Limits Min. tC (SCLK1)/2–30 tC (SCLK1)/2–30 –30 30 30 tC (SCLK2)/2–160 tC (SCLK2)/2–160 0.2 ✕ tC (SCLK2) 0 40 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns 140 Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Table 25 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time Min. tC (SCLK1)/2–100 tC (SCLK1)/2–100 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) 350 –30 100 100 tC (SCLK2)/2–240 tC (SCLK2)/2–240 0.2 ✕ tC (SCLK2) 0 100 Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. 1 kΩ Measurement output pin 100 pF Measurement output pin 100 pF CMOS output N-channel open-drain output (Note) Note: When P71–P77, P40 and bit 4 of the UART control register (address 001B16 ) is “1” (N-channel opendrain output mode). Fig. 65 Circuit for measuring output switching characteristics Rev.1.02 Jul 31, 2003 page 67 of 69 7560 Group (A version) tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 0.8VCC tWH(INT) tWL(INT) 0.2VCC INT0–INT2 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tf tC(SCLK1), tC(SCLK2) tr tWL(SCLK1), tWL(SCLK2) 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) 0.8VCC tWH(SCLK1), tWH(SCLK2) SCLK1 SCLK2 th(SCLK1-RXD), th(SCLK2-SIN2) RX D SIN2 0.8VCC 0.2VCC td(SCLK1-TXD),td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2) TX D SOUT2 Fig. 66 Timing diagram Rev.1.02 Jul 31, 2003 page 68 of 69 7560 Group (A version) PACKAGE OUTLINE 100P6Q-A MMP JEDEC Code – Weight(g) 0.63 Lead Material Cu Alloy Plastic 100pin 14✕14mm body LQFP MD e EIAJ Package Code LQFP100-P-1414-0.50 D 100 76 1 75 b2 HD l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 A3 25 51 26 50 A e F A2 L1 x y b2 I2 MD ME M Detail F Lp 100P6S-A MMP JEDEC Code – HD D Weight(g) 1.58 Lead Material Alloy 42 c b x y L Dimension in Millimeters Min Nom Max – – 1.7 0.1 0.2 0 – – 1.4 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 – 0.5 – 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 – – 0.75 0.6 0.45 – 0.25 – 0.08 – – 0.1 – – 0° 10° – 0.225 – – – – 0.9 – – 14.4 – – 14.4 HE E A1 Plastic 100pin 14✕20mm body QFP MD e EIAJ Package Code QFP100-P-1420-0.65 1 80 b2 100 81 I2 Recommended Mount Pad Symbol HE E 30 51 31 50 A L1 A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME F b A1 e y x M L Detail F Dimension in Millimeters Min Nom Max – – 3.05 0.1 0.2 0 – – 2.8 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 – 0.65 – 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 – – – – 0.13 0.1 – – 0° 10° – 0.35 – – – – 1.3 – – 14.6 – – 20.6 A2 Rev.1.02 Jul 31, 2003 page 69 of 69 c ME ME REVISION HISTORY Rev. Date Page 1.00 Feb. 18, 2003 1.02 Jul. 31, 2003 – 1 4 7 18 19 20 21 39 44 58 61 63 64 65 66 67 7560 Group (A version) Data Sheet Description Summary First edition issued Power dissipation revised. Table 1 Pin description (1) VCC VSS; Function description revised. Fig.5 Memory expansion plan revised. Fig.14 Port block diagram (1); (4) Ports P16, P17,P2, P41, P42 and (5) Port P44 revised. Fig.15 Port block diagram (2); (7) Port P46 and (11) Port P54 revised. Fig.16 Port block diagram (3); (14) Port P55, (15) Ports P56, P57 and (17) Port P60 revised. Fig.17 Port block diagram (4); (19) Port P62 revised. Fig.40 A-D converter block diagram Voltage Multiplier (3 Times) Description of order for operating the voltage multiplier revised. ROM ORDERING METHOD revised. Table 16 Recommended operating conditions (4); f(CNTR0) f(CNTR1) revised. Table 18 Electrical characteristics (2); ICC revised. Table 19 A-D converter characteristics (1); Note revised. Table 20 A-D converter characteristics (2); Note revised. Table 22 Timing requirements (1); tc(SCLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised. Table 23 Timing requirements (2); tc(SCLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised. Table 25 Switching characteristics (2) ; tr(SCLK1) tf(SCLK1) revised. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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