M37906F8CFP

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 P . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS . M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER DESCRIPTION These are single-chip 16-bit microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash memory and being packaged in 42-pin plastic molded SSOP or shrink plastic molded DIP. These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require high-speed processing of large data. Also, they are suitable for motor-control equipment since each of them includes the motor control circuit. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. Power supply voltage .................................................. 5 V ± 0.5 V Programming/Erase voltage ........................................ 5 V ± 0.5 V Programming method .................... Programming in a unit of word Erase method ............................................ Block erase or Total erase M37906F8CFP, M37906F8CSP ............... 4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1) Programming/Erase control by software command Maximum number of reprograms ............................................ 100 • • • • • • APPLICATION • Control devices for office equipment such as copiers and facsimiles • Control devices for industrial equipment such as communication and measuring instruments • Control devices for equipment, requiring motor control, such as inverter air conditioners and general-purpose inverters DISTINCTIVE FEATURES Number of basic machine instructions .................................... 203 Memory Flash memory (User ROM area) ................................... 60 Kbytes RAM ............................................................................. 3072 bytes Flash memory (Boot ROM area) ..................................... 8 Kbytes Instruction execution time The fastest instruction at 20 MHz frequency ........................ 50 ns Single power supply .................................................... 5 V ± 0.5 V Interrupts ........... 5 external sources, 21 internal sources, 7 levels Multi-functional 16-bit timer ................................................. 10 + 3 (Three-phase motor drive waveform or Pulse motor drive waveform output is available.) Serial I/O (UART or Clock synchronous) ..................................... 2 10-bit A-D converter ............................................ 5-channel inputs 8-bit D-A converter ............................................ 2-channel outputs 12-bit watchdog timer Programmable input/output (ports P1, P2, P5, P6, P7) ............. 30 • • • • • • • • • • • PR e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER M37906F8CFP PIN CONFIGURATION (TOP VIEW) VREF AVSS (Note) P74/AN4/DA1/INT3/RTPTRG0 P73/AN3/DA0 P72/AN2 P71/AN1 P70/AN0 P65/TA2IN/U/RTP11 P64/TA2OUT/V/RTP10 P63/TA1IN/W/RTP03 P62/TA1OUT/U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT/W/RTP00 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV (Note) P55/INT5/TB0IN/IDW P6OUTCUT/INT4 MD0 VCONT RESET VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 AVCC P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RxD0 P13/TxD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RxD1 P17/TxD1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27(/INT3/RTPTRG0) MD1 XOUT XIN VSS Outline 42P2R-E M37906F8CFP (Note) Note: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switched by software. 2 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER M37906F8CSP PIN CONFIGURATION (TOP VIEW) VREF AVSS (Note) P74/AN4/DA1/INT3/RTPTRG0 P73/AN3/DA0 P72/AN2 P71/AN1 P70/AN0 P65/TA2IN/U/RTP11 P64/TA2OUT/V/RTP10 P63/TA1IN/W/RTP03 P62/TA1OUT/U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT/W/RTP00 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV (Note) P55/INT5/TB0IN/IDW P6OUTCUT/INT4 MD0 VCONT RESET VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 AVCC P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RxD0 P13/TxD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RxD1 P17/TxD1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27(/INT3/RTPTRG0) MD1 XOUT XIN VSS Outline 42P4B M37906F8CSP (Note) Note: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switched by software. 3 PR e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Data Bus (Even) Data Bus (Odd) Data Buffer DQ0 (8) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Address Bus Data Buffer DQ3 (8) P6OUTCUT Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Reference Voltage Input Instruction Queue Buffer Q3 (8) VREF Instruction Queue Buffer Q4 (8) D-A1 Converter (8) Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8) Instruction Register (8) AVcc Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) (0V) AVSS Bus Interface Unit (BIU) Watchdog Timer Timer TB2 (16) Program Address Register PA (24) MD1 Data Address Register DA (24) Timer TB0 (16) Timer TB1 (16) UART0 (9) UART1 (9) Incrementer (24) A-D Converter (10) D-A0 Converter (8) Incrementer/Decrementer (24) MD0 Program Counter PC (16) Program Bank Register PG (8) Timer TA9 (16) Timer TA6 (16) Timer TA8 (16) Timer TA7 (16) Timer TA5 (16) (0V) Vss Input Buffer Register IB (16) Timer TA3 (16) Timer TA1 (16) Timer TA4 (16) Timer TA2 (16) Timer TA0 (16) P2(8) Data bank Register DT (8) Processor Status Register PS (11) Vcc Direct Page Register DPR0 (16) Direct Page Register DPR1 (16) Direct Page Register DPR2 (16) RAM 3072 bytes Reset input RESET Direct Page Register DPR3 (16) Central Processing Unit (CPU) Stack Pointer S (16) Index Register Y (16) Clock output Flash Memory 60 Kbytes XOUT Clock Generating Circuit Index Register X (16) Accumulator B (16) Accumulator A (16) BLOCK DIAGRAM Clock input XIN 4 VCONT Arithmetic Logic Unit (16) Input/Output port P7 P7(5) Input/Output port P6 P6(6) Input/Output port P5 P5(3) Input/Output port P2 Input/Output port P1 P1(8) PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER FUNCTIONS (Microcomputer mode) Parameter Number of basic machine instructions Instruction execution time External clock input frequency f(XIN) System clock input frequency f(fsys) Memory size Flash memory (User ROM area) RAM Flash memory (Boot ROM area) Programmable input/output ports P1, P2 P5 P6 P7 Multi-functional timers TA0–TA9 TB0–TB2 Serial I/O A-D converter D-A converter Dead-time timer Watchdog timer Interrupts Maskable interrups Non-maskable interrups Clock generating circuit PLL frequency multiplier Power supply voltage Power dissipation Ports’ input/output characteristics Input/Output withstand voltage Output current UART0 and UART1 Functions 203 50 ns (the fastest instruction at f(fsys) = 20 MHz) 20 MHz (Max.) 20 MHz (Max.) 60 Kbytes 3072 bytes 8 Kbytes 8-bit ✕ 2 3-bit ✕ 1 6-bit ✕ 1 5-bit ✕ 1 16-bit ✕ 10 16-bit ✕ 3 (UART or Clock synchronous serial I/O) ✕ 2 10-bit successive approximation method ✕ 1 (5 channels) 8-bit ✕ 2 8-bit ✕ 3 12-bit ✕ 1 5 external sources, 18 internal sources. Each interrupt can be set to a priority level within the range of 0–7 by software. 3 internal sources Incorporated (externally connected to a ceramic resonator or quartz-crystal resonator). The following multiplication ratios are available: ✕ 2, ✕ 3, ✕ 4 5 V±0.5 V 125 mW (at f(fsys) = 20 MHz, Typ.; the PLL frequency multiplier is inactive.) 5V 5 mA Not available (single-chip mode only). –20 to 85 °C CMOS high-performance silicon gate process (Note) Memory expansion Operating ambient temperature range Device structure Package Note: Packages M37906F8CFP M37906F8CSP 42-pin plastic molded SSOP (42P2R-E) 42-pin shrink plastic molded DIP (42P4B) 5 PR e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER FUNCTIONS (Flash memory mode) Parameter Power supply voltage Programming/Erase voltage Flash memory mode Block division for erasure User ROM area Boot ROM area Programming method Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Erase method Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Programming/Erase control Number of commands Maximum number of reprograms 5 V±0.5 V 5 V±0.5 V 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes 4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1); total of 60 Kbytes 1 block (8 Kbytes ✕ 1) (Note) Programmed per word User ROM area + Boot ROM area User ROM area User ROM area Total erase/Block erase User ROM area + Boot ROM area User ROM area User ROM area Programming/Erase control by software commands 6 commands 100 Functions Note: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area. 6 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER PIN DESCRIPTION (MICROCOMPUTER MODE) Pin Vcc, Vss MD0 MD1 RESET XIN XOUT VCONT AVcc, AVss VREF P10–P17 Name Power supply input MD0 MD1 Reset input Clock input Clock output Filter circuit connection Analog power supply input Reference voltage input I/O port P1 Input/ Output — Input Input Input Input Output — — Input I/O Connect this pin to VSS. Connect this pin to Vss. The microcomputer is reset when “L” level is applied to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz-crystal oscillator between the X IN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. When using the PLL frequency multiplier, connect this pin to the filter circuit. When not using the PLL frequency multiplier, this pin should be left open. Power supply input pins for the A-D converter and the D-A converter. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D converter and the D-A converter. Port P1 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode at reset. These pins also function as I/O port pins of UART0 and UART1. In addition to having the same functions as port P1, these pins also function as I/O pins for timers A4 and A9. By software setting, these pins also function as input pins for timers B0–B2, an input pin for INT3, and a trigger input pin in the pulse output port mode. In addition to having the same functions as port P1, these pins also function as input pins for INT5–INT7, input pins for timers B0–B2, and input pins for positiondata-input pins in the three-phase waveform mode. In addition to having the same functions as port P1, these pins also function as I/O pins for timers A0–A2, and output pins for the motor drive waveform. In addition to having the same functions as port P1, these pins also function as input pins for the A-D converter. P73 functions as an output pin for the D-A converter; P74 functions as an output pin for the D-A converter, an input pin for INT3, and a trigger input pin in the pulse output port mode. This pin has the function to forcibly place port P6 pins in the input mode. Also, this pin functions as an input pin for INT4; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. Functions Apply 5 V±0.5 V to Vcc, and 0 V to Vss. P20–P27 I/O port P2 I/O P50–P57 I/O port P5 I/O P60–P65 P70–P74 I/O port P6 I/O port P7 I/O I/O P6OUTCUT P6OUTCUT input Input 7 PR e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) Pin VCC, VSS MD0 MD1 _____ Name Power supply input MD0 MD1 Reset input Clock input Clock output Analog supply input Reference voltage input Input /Output — Input Input Input Input Output — Input Input Input Input I/O Output Input Input Input Input — Connect this pin to Vss. Functions Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ. The reset input pin. Connect a ceramic oscillator between the XIN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS–VCC. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) This is an input pin for a serial clock. This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ). This is an output pin for the BUSY signal. Input “H”. Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.) RESET XIN XOUT AVcc, AVss VREF Input port P1 P10–P17 P20–P23, P27 Input port P2 P24 P25 P26 P6OUTCUT P55–P57 P60–P65 P70–P74 VCONT SCLK input SDA I/O BUSY output P6OUTCUT input Input port P5 Input port P6 Input port P7 Filter circuit connection 8 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS Each of the M37906F8CFP and M37906F8CSP has the same function as that of the M37906M4C-XXXFP except for the following. Therefore, for details except for the following, refer to the datasheet of the M37906M4C-XXXFP. • Flash memory size • RAM size MEMORY Figure 1 shows the memory map. 00000016 00000016 0000FF16 00010016 0003FF16 00040016 Peripheral devices’ control registers Unused area 00000016 Peripheral devices’ control registers (See Figures 2 and 3.) 0000FF16 Bank 016 Internal RAM 3072 bytes 000FFF16 00100016 00FFFF16 00FFB416 Internal ROM 60 Kbytes Interrupt vector table Reserved area Reserved area Timer A9 Timer A8 Timer A7 Timer A6 Timer A5 INT7 INT6 INT5 Reserved area Address matching detect Reserved area Reserved area 00FFB416 00FFFF16 INT4 INT3 A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Reserved area Reserved area Reserved area Reserved area Watchdog timer DBC BRK instruction Zero divide RESET 00FFFE16 Fig. 1 Memory map of M37906F8CFP, M37906F8CSP (Single-chip mode) 9 PR e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Address (Hexadecimal notation) 00000016 Reserved area (Note) 00000116 Reserved area (Note) 00000216 Reserved area (Note) 00000316 Port P1 register 00000416 Reserved area (Note) 00000516 Port P1 direction register 00000616 Port P2 register 00000716 Reserved area (Note) 00000816 Port P2 direction register 00000916 Reserved area (Note) 00000A16 Reserved area (Note) 00000B16 Port P5 register 00000C16 Reserved area (Note) 00000D16 Port P5 direction register 00000E16 Port P6 register 00000F16 Port P7 register 00001016 Port P6 direction register 00001116 Port P7 direction register 00001216 Reserved area (Note) 00001316 00001416 Reserved area (Note) 00001516 00001616 Reserved area (Note) 00001716 Reserved area (Note) 00001816 Reserved area (Note) 00001916 Reserved area (Note) 00001A16 00001B16 00001C16 00001D16 00001E16 A-D control register 0 00001F16 A-D control register 1 00002016 A-D register 0 00002116 00002216 A-D register 1 00002316 00002416 A-D register 2 00002516 00002616 A-D register 3 00002716 00002816 A-D register 4 00002916 00002A16 Reserved area (Note) 00002B16 Reserved area (Note) 00002C16 Reserved area (Note) 00002D16 Reserved area (Note) 00002E16 Reserved area (Note) 00002F16 Reserved area (Note) 00003016 UART0 transmit/receive mode register 00003116 UART0 baud rate register (BRG0) 00003216 UART0 transmit buffer register 00003316 00003416 UART0 transmit/receive control register 0 00003516 UART0 transmit/receive control register 1 00003616 UART0 receive buffer register 00003716 00003816 UART1 transmit/receive mode register 00003916 UART1 baud rate register (BRG1) 00003A16 UART1 transmit buffer register 00003B16 00003C16 UART1 transmit/receive control register 0 00003D16 UART1 transmit/receive control register 1 00003E16 UART1 receive buffer register 00003F16 Address (Hexadecimal notation) 00004016 Count start register 0 00004116 Count start register 1 00004216 One-shot start register 0 00004316 One-shot start register 1 00004416 Up-down register 0 00004516 Timer A clock division select register 00004616 Timer A0 register 00004716 00004816 Timer A1 register 00004916 00004A16 Timer A2 register 00004B16 00004C16 Timer A3 register 00004D16 00004E16 Timer A4 register 00004F16 00005016 Timer B0 register 00005116 00005216 Timer B1 register 00005316 00005416 Timer B2 register 00005516 00005616 Timer A0 mode register 00005716 Timer A1 mode register 00005816 Timer A2 mode register 00005916 Timer A3 mode register 00005A16 Timer A4 mode register 00005B16 Timer B0 mode register 00005C16 Timer B1 mode register 00005D16 Timer B2 mode register 00005E16 Processor mode register 0 00005F16 Processor mode register 1 00006016 Watchdog timer register 00006116 Watchdog timer frequency select register 00006216 Particular function select register 0 00006316 Particular function select register 1 00006416 Particular function select register 2 00006516 Reserved area (Note) 00006616 Debug control register 0 00006716 Debug control register 1 00006816 00006916 Address comparison register 0 00006A16 00006B16 00006C16 Address comparison register 1 00006D16 00006E16 INT3 interrupt control register 00006F16 INT4 interrupt control register 00007016 A-D conversion interrupt control register 00007116 UART0 transmit interrupt control register 00007216 UART0 receive interrupt control register 00007316 UART1 transmit interrupt control register 00007416 UART1 receive interrupt control register 00007516 Timer A0 interrupt control register 00007616 Timer A1 interrupt control register 00007716 Timer A2 interrupt control register 00007816 Timer A3 interrupt control register 00007916 Timer A4 interrupt control register 00007A16 Timer B0 interrupt control register 00007B16 Timer B1 interrupt control register 00007C16 Timer B2 interrupt control register 00007D16 Reserved area (Note) 00007E16 Reserved area (Note) 00007F16 Reserved area (Note) Note: Do not write to this address. Fig. 2 Location of SFRs (1) 10 PR e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som MI ELI Y NAR MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Address (Hexadecimal notation) 00008016 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C16 00008D16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C16 00009D16 00009E16 00009F16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA16 0000AB16 0000AC16 0000AD16 0000AE16 0000AF16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA16 0000BB16 0000BC16 0000BD16 0000BE16 0000BF16 Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Address (Hexadecimal notation) 0000C016 0000C116 0000C216 0000C316 0000C416 0000C516 0000C616 0000C716 0000C816 0000C916 0000CA16 0000CB16 0000CC16 0000CD16 0000CE16 0000CF16 0000D016 0000D116 0000D216 0000D316 0000D416 0000D516 0000D616 0000D716 0000D816 0000D916 0000DA16 0000DB16 0000DC16 0000DD16 0000DE16 0000DF16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA16 0000EB16 0000EC16 0000ED16 0000EE16 0000EF16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA16 0000FB16 0000FC16 0000FD16 0000FE16 0000FF16 Up-down register 1 Timer A5 register Timer A6 register Timer A7 register Timer A8 register Timer A9 register Timer A01 register Timer A11 register Timer A21 register Timer A5 mode register Timer A6 mode register Timer A7 mode register Timer A8 mode register Timer A9 mode register Reserved area (Note) Comparator function select register 0 Reserved area (Note) Comparator result register 0 Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) External interrupt input read-out register D-A control register D-A register 0 D-A register 1 Reserved area (Note) Reserved area (Note) Flash memory control register Reserved area (Note) Reserved area (Note) Reserved area (Note) Waveform output mode register Dead-time timer Three-phase output data register 0 Three-phase output data register 1 Position-data-retain function control register Serial I/O pin control register Port P2 pin function control register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Clock control register 0 Reserved area (Note) Reserved area (Note) Reserved area (Note) Timer A5 interrupt control register Timer A6 interrupt control register Timer A7 interrupt control register Timer A8 interrupt control register Timer A9 interrupt control register INT5 interrupt control register INT6 interrupt control register INT7 interrupt control register Note: Do not write to this address. Fig. 3 Location of SFRs (2) 11 PRE . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY MODE These microcomputers contain the flash memory; and single-powersupply reprogramming is available to this. These microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory: • Flash memory parallel I/O mode and Flash memory serial I/O mode, where the flash memory is handled by using an external programmer. • CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). As shown in Figure 4, the flash memory is divided into several blocks, and erasure per block is possible. This internal flash memory has the boot ROM area storing the reprogramming control software for reprogramming in the CPU reprogramming mode and flash memory serial I/O mode, as well as the user ROM area storing a certain control software for the normal operation in the microcomputer mode. Although our reprogramming control firmware for the flash memory serial I/O mode has been stored into this boot ROM area on shipment, the user-original reprogramming control software which is more appropriate for the user’s system is reprogrammable into this area, instead. Note that the reprogramming for the boot ROM area is enabled only in the flash memory parallel I/O mode. 00100016 00100016 28 Kbytes 007FFF16 00800016 00FFFF16 00BFFF16 00C00016 16 Kbytes 8 Kbytes 00DFFF16 00E00016 00FFFF16 8 Kbytes Fig. 4 M37906F8CFP, M37906F8CSP: block configuration of internal flash memory 12 PRE e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Flash Memory Parallel I/O Mode The flash memory parallel I/O mode is used to manipulate the internal flash memory with a parallel programmer. This parallel programmer uses the software commands listed in Table 1 to do the flash memory manipulations, such as read/programming/erase operations. User ROM Area and Boot ROM Area The user ROM area and boot ROM area can be reprogrammed in the flash memory parallel I/O mode. The programming and block erase operations can be performed only to these areas. The boot ROM area, 8 Kbytes in size, is assigned to addresses 000016–1FFF16, so that programming and block erase operations can be performed only to this area. (Access to any address out of this area is prohibited). The erasable block in the boot ROM area is only one block, consisting of 8 Kbytes. The reprogramming control firmware to be used in the flash memory serial I/O mode has been stored to this boot ROM area on our shipment. Therefore, do not reprogram the boot ROM area if the user uses the flash memory serial I/O mode. Do not program to addresses FF9016 to FF9F16 because this area is the reserved area for the programmer. Note that, when the boot ROM area is read out from the CPU in the CPU reprogramming mode, described later, its addresses will be shifted to E00016—FFFF16. Table 1. Software commands (flash memory parallel I/O mode) Software Command Read Array Read Status Register Clear Status Register Programming Block Erase Erase All Block Addresses FF9016 to FF9F16 are the reserved area for the parallel programmer. Therefore, when the user uses the flash memory parallel I/O mode, do not program to this area. 13 PRE . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Flash Memory Serial I/O Mode In the flash memory serial I/O mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. In this mode, being different from the flash memory parallel I/O mode, the CPU controls reprogramming of the flash memory (using the CPU reprogramming mode), serial input of the reprogramming data, etc. The reprogramming control firmware for the flash memory serial I/O mode has been stored in the boot ROM area on shipment of the product from us. Note that, then, the flash memory serial I/O mode will become unavailable if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode. Note that, also, this reprogramming control firmware for the flash memory serial I/O mode is subject to change. Figures 5 and 6 show the pin connections in the flash memory serial I/O mode. The three pins, SCLK, SDA, and BUSY, are used to input and output serial data. The SCLK pin is the input pin of external transfer clocks. The SDA pin is the I/O pin of transmit and receive data, and its output acts as the N-channel open-drain output. To the SDA pin, connect an external pullup resistor (about 1 kΩ). The BUSY pin is the output pin of the BUSY flag (CMOS output) and goes “H” during BUSY periods owing to a certain operation, such as transmit, receive, erase, programming, etc. Transmit and receive data are serially transferred 8 bits at a time. In the flash memory serial I/O mode, only the user ROM area can be reprogrammed; the boot ROM area is not accessible. Addresses FF9016 to FF9F16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area. 14 PRE e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER VCC VREF AVss (Note 1) P74/AN4/DA 1/INT3/RTPTRG0 P73/AN3/DA 0 P72/AN2 P71/AN1 P70/AN0 P65/TA2IN/U/RTP1 1 P64/TA2OUT/V/RTP10 P63/TA1IN /W/RTP03 P62/TA1OUT/U/RTP02 P61/TA0IN /V/RTP01 P60/TA0OUT/W/RTP00 P57/INT7/TB2IN/IDU (Note 1) P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW (Note 3) P6OUTCUT/INT4 MD0 VCONT RESET Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 RESET AVcc P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RXD0 P13/TXD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RXD1 P17/TXD1 P20/TA4 OUT P21/TA4 IN P22/TA9 OUT P23/TA9 IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27(/INT3/RTPTRG0) MD1 XOUT (Note 2) XIN Vss Outline 42P2R-E Fig. 5 Pin connection of M37906F8CFP in flash memory serial I/O mode (outline: 42P2R-E) M37906F8CFP SCLK SDA BUSY MD1 (Note 1) VSS Notes 1: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. 15 PRE . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER VCC VREF AVss (Note 1) P74/AN4/DA 1/INT3/RTPTRG0 P73/AN3/DA 0 P72/AN2 P71/AN1 P70/AN0 P65/TA2IN /U/RTP1 1 P64/TA2OUT/V/RTP10 P63/TA1IN /W/RTP03 P62/TA1OUT/U/RTP02 P61/TA0IN /V/RTP01 P60/TA0OUT/W/RTP00 P57/INT7/TB2IN/IDU (Note 1) P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW (Note 3) P6OUTCUT/INT4 MD0 VCONT RESET Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 RESET AVcc P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RXD0 P13/TXD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RXD1 P17/TXD1 P20/TA4 OUT P21/TA4 IN P22/TA9 OUT P23/TA9 IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27(/INT3/RTPTRG0) MD1 XOUT (Note 2) XIN Vss Notes 1: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. Outline 42P4B Fig. 6 Pin connection of M37906F8CSP in flash memory serial I/O mode (outline: 42P4B) M37906F8CSP SCLK SDA BUSY MD1 (Note 1) VSS 16 PRE e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER CPU Reprogramming Mode The CPU reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the CPU. In this mode, only the user ROM area can be reprogrammed; the boot ROM area cannot be reprogrammed. The user-original reprogramming control software for the CPU reprogramming mode can be stored in either the user ROM area or the boot ROM area. Because the CPU cannot read out the flash memory in the CPU reprogramming mode, the above software must be transferred to the internal RAM in advance to be executed. Boot Mode The user-original reprogramming control software for the CPU reprogramming mode must be stored into the user ROM area or the boot ROM area in the flash memory parallel I/O mode in advance. (If this program has been stored into the boot ROM area, the flash memory serial I/O mode will become unavailable). Note that addresses of the boot ROM area depend on the accessing ways to the boot ROM area, When accessing in the flash memory parallel I/O mode, these addresses will be shifted to 000016 to 1FFF16. On the other hand, when accessing with the CPU, these addresses will be shifted to E00016 to FFFF16. Reset removal with both of the MD0 and MD1 pins held “L” invokes the normal microcomputer mode, and the CPU operates using the control software stored in the user ROM area. In this case, the boot ROM area is not accessible. Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the CPU starts its operation using the reprogramming control software stored in the boot ROM area. This mode is called the boot mode. The reprogramming control software in the boot ROM area can also reprogram the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. 7 6 5 4 3 2 1 0 Flash memory control register Address 9E16 RY/BY status bit 0: Busy (Programming or erasing is active.) 1: Ready CPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.) Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area select bit (Note 4) (Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area access Notes 1: The contents of the flash memory control register after reset is removed are “XX000001”. 2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: This bit is valid only when bit 1 = “1”. Before setting this bit to “0”, be sure to confirm that bit 0 = “1” after setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”. 4: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM. Fig. 7 Bit configuration of flash memory control register 17 PRE . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Function overview (CPU reprogramming mode) The CPU reprogramming mode is available in the single-chip mode, memory expansion mode, and boot mode to reprogram the user ROM area only. In the CPU reprogramming mode, the CPU erases, programs, and reads the internal flash memory by writing software commands. Note that the user-original reprogramming control software must be transferred to the internal RAM in advance to be executed. The CPU reprogramming mode becomes active when “1” is written into the flash memory control register ’s bit 1 (the CPU reprogramming mode select bit) shown in Figure 7, and software commands become acceptable. In the CPU reprogramming mode, software commands and data are all written to and read from even addresses (Note that address A0 in byte addresses = “0”.) 16 bits at a time. Therefore, a software command consisting of 8 bits must be written to an even address; therefore, any command written to an odd address will be invalid. Since the write data at the 2nd cycle of a programming command consists of 16 bits, this data must be written to even and odd addresses. The seaquencer in the flash memory controls the erase and programming operations. What the status of the seaquencer operation is and whether the programming or erase operation has been completed normally or terminated by an error can be examined by reading the flash memory control register. Figure 7 shows the bit configuration of the flash memory control register. Bit 0 (the RY/BY status bit) is a read-only bit for indicating the seaquencer operation. This bit goes to “0” (BUSY) while the automatic programming/erase operation is active and goes to “1” (READY) during the other operations. Bit 1 serves as the CPU reprogramming mode select bit. Writing of “1” to this bit selects the CPU reprogramming mode, and software commands will be acceptable. Because the CPU cannot directly access the internal flash memory in the CPU reprogramming mode, writing to this bit 1 must be performed by the user-original reprogramming control software which has been transferred to the internal RAM in advance. To set bit 1 to “1”, it is necessary to write “0” and “1” to this bit 1 successively. On the other hand, to clear this bit to “0”, it is sufficient only to write “0”. Bit 3 (the flash memory reset bit) resets the control circuit of the internal flash memory and is used when the CPU reprogramming mode is terminated or when an abnormal access to the flash memory happens. Writing of “1” to bit 3 with the CPU reprogramming mode select bit = “1” preforms the reset operation. To remove the reset, write “0” to bit 3 after confirming bit 0 (the RY/BY status bit) becomes “1”. Bit 5 serves as the user ROM area select bit and is valid only in the boot mode. Setting this bit to “1” in the boot mode switches an accessible area from the boot ROM area to the user ROM area. To use the CPU reprogramming mode in the boot mode, set this bit to “1”. Note that when the microcomputer is booted up in the user ROM area, only the user ROM area is accessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid independent of the CPU reprogramming mode. To rewrite bit 5, execute the user-original reprogramming control software transferred to the internal RAM in advance. Figure 8 shows the CPU reprogramming mode set/termination flow- chart, and be sure to follow this flowchart. As shown in Note 1 of Figure 8, before selecting the CPU reprogramming mode, set “0” to the processor mode register 1’s bit 7 (the internal ROM bus cycle select bit) and set flag I to “1” to avoid an interrupt request input. When a watchdog timer interrupt request is generated in the CPU reprogramming mode, when an input to the RESET pin is “L”, or when the software reset is performed, the flash memory control circuit and flash memory control register will be reset. When the flash memory is reset during the erase or programming operation, this operation is cancelled and the target block’s data will be invalid. Just before writing a software command related to the erase/programming operation, be sure to write to the watchdog timer. In the CPU reprogramming mode, be sure not to use the STP and WIT instructions. 18 PRE e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Software Commands Start Single-chip mode, Memory expansion mode, or Boot mode Table 2 lists the software commands. By writing a software command after the CPU reprogramming mode select bit has been set to “1”, erasing, programming, etc. can be specified. Note that, at software commands’ input, the high-order byte (D8–D15) is ignored. (Except for the write data at the 2nd cycle of a programming command.) Software commands are explained as below. The processor mode register 1 is set (Note 1). Flag I is set to “1”. Read Array Command (FF16) By writing command code “FF16” at the 1st bus cycle, the microcomputer enters the read array mode. If an address to be read is input in the next or the following bus cycles, the contents at the specified address are output to the data bus (D0 to D15) in a unit of 16 bits. The read array mode is maintained until writing of another software command. The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM. Jump to the above software in the internal RAM. (The operations shown below will be executed by the above software in this RAM.) Read Status Register Command (7016) Writing command code “7016” at the 1st bus cycle outputs the contents of the status register to the data bus (D0-D7) by a read at the 2nd bus cycle. The status register is explained later. (Only in the boot mode.) The user ROM area select bit is set to “1”. Clear Status Register Command (5016) Writing of “1” to the CPU reprogramming mode select bit. (Writing of “0” → Writing of “1”) This command clears two status bits (SR.4, 5) each of which is set to “1” to indicate that the operation has been terminated by an error. To clear these bits, write command code “5016” at the 1st bus cycle. Operations such as erasing, programming are executed by using software commands. Programming Command (4016) This command facilitates programming of 1 word (2 bytes) at a time. To initiate programming, write command code “4016” at the 1st bus cycle; when write data is written in a unit of 16 bits at the 2nd bus cycle, the address is specified at the same time. Upon completion of data writing, automatic programming (data programming and verification) operation is started. The completion of the automatic programming operation is confirmed by a read of the flash memory control register. The RY/BY status bit of the flash memory control register goes “0” during the automatic programming operation; and also, it goes “1” after the end of it. Before execution of the next command, be sure to confirm that the RY/BY status bit is set to “1” (READY). During the automatic programming operation, writing of commands and access to the flash memory must not be performed. When programming continuously, the programming command can be executed with the read status register mode kept if there is no programming error. Simultaneously with start of the automatic programming, the read status register mode is automatically active. In this case, the read status register mode is retained until the next read array command (FF16) is written or until the reset is performed by using the flash memory reset bit. Reading out the status register after the automatic programming operation is completed reports the result of it. For details, refer to the section on the status register. Figure 9 shows an example of the programming flowchart. Additional programming to any word that has already been programmed is prohibited. Read array command is executed, or reset is performed by setting the flash memory reset bit. (Writing of “1” → Writing of “0”) (Note 2) Writing of “0” to the CPU reprogramming mode select bit. (Only in the boot mode.) Writing of “0” to user ROM area select bit (Note 3). Completed Notes 1: The processor mode register 1’s bit 7 (address 5F16, the internal ROM bus cycle select bit) must be “0” (bus cycle = 3φ). 2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: This bit may remain “1”. However, if this bit is “1”, the user ROM area access is specified. Fig. 8 CPU reprogramming mode set/termination flowchart 19 PRE . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Table 2. Software commands (CPU reprogramming mode) 1st cycle Command Mode Read Array Read Status Register Clear Status Register Programming Block Erase Erase All Block Write Write Write Write Write Write Address X (Note 2) X X X X X Data (D0 to D7) FF16 7016 5016 4016 2016 2016 Mode — Read — Write Write Write 2nd cycle Address — X Data — SRD (Note 3) — — WA (Note 4) WD (Note 4) BA (Note 5) D016 X 2016 Notes 1: At software commands’ input, the high-order byte of data (D8–D15) is ignored. 2: X = An arbitrary address in the user ROM area. (Note that A0 = “0”.) 3: SRD = Status Register Data 4: WA = Write Address, WD = Write Data (16 bits). 5: Block address: the maximum address of each block must be input. Note that address A0 = “0”. Block Erase Command (2016/D016) Writing command code “2016” at the 1st bus cycle and writing confirmation command code “D016” and the maximum address of the block (Note that address A0 = “0”.) at the subsequent 2nd bus cycle initiate the automatic erase (erasing and erase verification) operation for the specified block. The completion of the automatic erase operation is confirmed by a read of the flash memory control register. The RY/BY status bit of the flash memory control register goes “0” simultaneously with start of the automatic erase operation; and also, it goes “1” simultaneously with completion of it. Before execution of the next command, be sure to confirm that the RY/BY status bit is set to “1” (READY). During the automatic erase operation, writing of commands and access to the flash memory must not be performed. Simultaneously with start of the automatic erase, the read status register mode is automatically active. In this case, the read status register mode is retained until the next read array command (FF16) is written or until the reset is performed by using the flash memory reset bit. Reading out the status register after the automatic erase operation is completed reports the result of it. For details, refer to the section on the status register. Figure 10 shows an example of the block erase flowchart. 20 PRE e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Erase All Block Command (2016/2016) Start Write 4016 Write, Address, Data Flash memory control register Read NO Writing command code “2016” at the 1st bus cycle and writing command code “2016” at the subsequent 2nd bus cycle initiate the continuous block erase (chip erase) operations for all the blocks. The completion of the chip erase operation, as well as of the block erase operation, is confirmed by a read of the flash memory control register. The result of the automatic erase operation is also reported by a read of the status register. During the automatic erase operation (when the RY/BY status bit = “0”), writing of commands and access to the flash memory must not be performed. RY/BY Status Bit = 1? YES Status Register The status register is used to indicate whether the programming/ erase operation has been completed normally or terminated by an error. By writing the read status register command (7016), the contents of the status register can be read out; by writing the clear status register command (5016), the contents of the status register can be cleared. Table 3 lists the definition of each bit of the status register. The status register outputs “8016” after reset is removed. The status of each bit is described below. Full status check Programming Completed Fig. 9 Programming flowchart Start Write 2016 Write D016, Block address Flash memory control register Read NO RY/BY Status Bit = 1? YES Full status check Block erase Completed Fig. 10 Block erase flowchart 21 PRE . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Erase Status Bit (SR.5) This bit reports the status of the automatic erase operation. This bit is set to “1” if an erase error occurs and returns to “0” if the clear status register command (5016) is written. (1) when data other than “D016” and “FF16” is written to the data in the 2nd bus cycle of the block erase command (2016/D016) (2) when data other than “2016” and “FF16” is written to the data in the 2nd bus cycle of the erase all block command (2016/2016) Note that, writing of “FF16” forces the microcomputer into the read array mode. Simultaneously with this, the command written in the 1st bus cycle will be canceled. Programming Status Bit (SR.4) This bit reports the status of the automatic programming operation. This bit is set to “1” if a programming error occurs and returns to “0” if the clear status register command (5016) is written. Under the condition that any of SR.5, SR.4 = “1”, none of the programming, block erase, and erase all block commands can be accepted. Before execution of these commands, execute the clear status register command (5016), in advance, to clear these status bits. Both of SR.4, SR.5 are set to “1” under the following conditions (Command Sequence Error): Full Status Check The full status check reports the results of the erase or programming operation. Figure 11 shows the full status check flowchart and actions to be taken if an error has occurred. Table 3. Bit definition of status register Symbol SR.7 (D7) SR.6 (D6) SR.5 (D5) SR.4 (D4) SR.3 (D3) SR.2 (D2) SR.1 (D1) SR.0 (D0) Reserved Reserved Erase Status Programming Status Reserved Reserved Reserved Reserved Terminated by error. Terminated by error. Terminated normally. Terminated normally. Status Definition “1” “0” 22 PRE e. n. ang atio cific ct to ch spe inal e subje f ot a its ar is n m This tric li ice: arame Not e p Som L A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Status Register Read SR.4 = 1 and SR.5 = 1 ? NO YES Command Sequence Error ➀ Execute the clear status register command (5016) to clear the status register. ➁ Confirm whether the command has correctly been input or not; and then, start the operation again. NO SR.5 = 0? YES NO SR.4 = 0? YES End (Block erase, Programming) Programming Error Block Erase Error Perform the block erase operation again. If an error occurs even after the above operation is performed, the block cannot be used. Perform the programming operation again. If an error occurs even after the above operation is performed, the word cannot be used. Note: Under the condition that any of SR.5 and SR.4 = “1”, none of the programming, block erase, and erase all block commands can be accepted. Before execution of these commands, execute the clear status register command (5016) in advance. Fig. 11 Full status check flowchart and actions to be taken if an error has ocurred DC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note)) Symbol Icc1 Icc2 Icc3 Icc4 Parameter VCC power source current (at read) VCC power source current (at write) VCC power source current (at programming) VCC power source current (at erasing) Min. Limits Typ. 30 Max. 48 48 54 54 Unit mA mA mA mA Limits of VIH, VIL, VOH, VOL, IIH, and IIL for each pin are the same as those in the microcomputer mode. Note: f(fsys) indicates the system clcok (fsys) frequency. AC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note)) Parameter 256-byte programming time Block erase time Erase all block time n = Number of blocks to be erased The limits of parameters other than the above are same as those in the microcomputer mode. Note: f(fsys) indicates the system clock (fsys) frequency. Min. Limits Typ. 4 0.6 0.6 ✕ n Max. 40 8 8✕n Unit ms s s 23 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol VCC AVCC VI VO Pd Topr Tstg Power source voltage Analog power source voltage Input voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT, VCONT, VREF, XIN, RESET, BYTE, MD0, MD1 Parameter Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to VCC+0.3 –0.3 to VCC+0.3 300 –20 to 85 –40 to 150 Unit V V V V mW °C °C Output voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, XOUT Power dissipation Operating ambient temperature Storage temerature RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VCC AVCC VSS AVSS VIH VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(fsys) Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT, XIN, RESET, MD0, MD1 Low-level input voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT, XIN, RESET, MD0, MD1 High-level peak output current Low-level peak output current Low-level peak output current P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 P10–P17, P20–P27, P55–P57, P70–P74 P60–P65 High-level average output current P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 0.8 Vcc 0 Parameter Min. 4.5 Typ. 5.0 VCC 0 0 Vcc 0.2 VCC –10 –5 10 20 5 15 20 20 Max. 5.5 Unit V V V V V V mA mA mA mA mA mA MHz MHz Low-level average output current P10–P17, P20–P27, P55–P57, P70–P74 Low-level average output current P60–P65 External clock input frequency (Note 1) System clock frequency Notes 1: When using the PLL frequency multiplier, be sure that f(fsys) = 20 MHz or less. 2: The average output current is the average value of an interval of 100 ms. 3: The sum of IOL(peak) must be 110 mA or less, the sum of IOH(peak) must be 80 mA or less. 24 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz) Symbol VOH Parameter High-level output voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 Low-level output voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 Hysteresis TA0IN–TA2IN, TA4IN, TA9IN, TA0OUT–TA2OUT, TA4OUT, TA9OUT, TB0IN–TB2IN, INT3–INT7, CTS0, CTS1, CLK0, CLK1, RxD0, RxD1, RTPTRG0, P6OUTCUT Test conditions IOH = –10 mA Min. 3 Limits Typ. Max. Unit V VOL IOL = 10 mA 2 V VT+ —VT– 0.4 1 V VT+ —VT– VT+ —VT– IIH Hysteresis RESET Hysteresis XIN High-level input current P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT, XIN, RESET, MD0, MD1 Low-level input current P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT, XIN, RESET, MD0, MD1 RAM hold voltage Power source current VI = 5.0 V 0.5 0.1 1.5 0.3 5 V V µA IIL VI = 0 V –5 µA VRAM ICC When clock is inactive. Output-only pins are open, and the other pins are connected to Vss or Vcc. An external square-waveform clock is input. (Pin XOUT is open.) The PLL frequency multiplier is inactive. f(fsys) = 20 MHz. CPU is active. Ta = 25 °C when clock is inactive. Ta = 85 °C when clock is inactive. 2 25 50 V mA 1 µA 20 25 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ————— Parameter Resolution VREF = VCC Test conditions A-D converter Comparator 10-bit resolution mode 8-bit resolution mode Comparater 5 10-bit resolution mode 8-bit resolution mode Comparater 5.9 2.45 (Note) 0.7 (Note) 2.7 0 VCC VREF V V Limits Min. Typ. Max. 10 Unit Bits ————— RLADDER tCONV VREF VIA Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage VREF = VCC VREF = VCC f(fsys) ≤ 20 MHz 1 VREF V 256 ±3 LSB ±2 LSB ± 40 mV kΩ µs Note: This is applied when A-D conversion freguency (φAD) = f1 (φ). D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol —— —— tsu RO IVREF Resolution Absolute accuracy Set time Output resistance Reference power source input current (Note) 2 3.5 Parameter Test conditions Limits Typ. Max. 8 ± 1.0 3 4.5 3.2 Unit Bits % µs kΩ mA Min. Note: The test conditions are as follows: • One D-A converter is used. • The D-A register value of the unused D-A converter is “0016.” • The reference power source input current for the ladder resistance of the A-D converter is excluded. RESET INPUT Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tw(RESETL) Parameter RESET input low-level pulse width Min. 10 Limits Typ. Max. Unit µs RESET input tw(RESETL) 26 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz unless otherwise noted) For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ). ∗ Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 40 40 Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz Limits Min. 16 × 109 f(fsys) 8 × 109 f(fsys) 8× f(fsys) 109 (800) (400) (400) Max. Unit ns ns ns Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz Limits Min. 8 × 109 f(fsys) 80 80 (400) Max. Unit ns ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input and Count input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns 27 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time Parameter Limits Min. 800 200 200 Max. Unit ns ns ns • Gating input in timer mode • Count input in event counter mode • External trigger input in one-shot pulse mode • External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) • Up-down and Count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) TAiIN input (When count by falling) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count by rising) • Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) TAjOUT input tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) tsu(TAjOUT-TAjIN) Test conditions • VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V 28 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz Limits Min. 16 × 109 (800) f(fsys) 8× f(fsys) 8 × 109 f(fsys) 109 (400) (400) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz Limits Min. 16 × f(fsys) 109 (800) (400) (400) Max. Unit ns ns ns 8× f(fsys) 8 × 109 f(fsys) 109 Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 20 90 Parameter Limits Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns 29 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER External interrupt (INTi) input Symbol tw(INH) tw(INL) INTi input high-level pulse width INTi input low-level pulse width Parameter Limits Min. 250 250 Max. Unit ns ns tc(TB) tw(TBH) TBiIN input tw(TBL) tc(CK) tw(CKH) CLKi input tw(CKL) th(C-Q) TxDi output td(C-Q) RxDi input tsu(D-C) th(C-D) tw(INL) INTi input tw(INH) Test conditions • Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 30 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER External clock input Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tc tw(half) tw(H) tw(L) tr tf External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Parameter Limits Min. 50 0.45 tc 0.5 tc – 8 0.5 tc – 8 8 8 0.55 tc Max. Unit ns ns ns ns ns ns External clock input tw(L) XIN tw(H) tr tf tc tw(half) Test conditions • Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf) • Input timing voltage : 2.5 V (tc, tw(half)) 31 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 42P2R-E EIAJ Package Code SSOP42-P-450-0.80 42 Plastic 42pin 450mil SSOP JEDEC Code – Weight(g) 0.63 22 Lead Material Alloy 42/Cu Alloy e b2 HE E e1 F Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.5 0.4 0.35 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 – Symbol 1 21 A G D A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 L1 c z Z1 Detail G Detail F 42P4B EIAJ Package Code SDIP42-P-600-1.78 JEDEC Code – Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy L Plastic 42pin 600mil SDIP 42 22 1 21 Symbol D e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15° A 32 A1 L A2 e1 E c I2 P . . nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som REL A IMIN RY MITSUBISHI MICROCOMPUTERS M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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Specifications subject to change without notice. REVISION HISTORY Rev. 1.0 2.0 Date Page 3/02/01 6/26/01 — — 1 M37906F8CFP/SP DATASHEET Description Summary First Edition Some English expressions and the following are corrected: •DESCRIPTION; line 3 •••• silicon gate technology, being packaged •••• •••• silicon gate technology, including the internal flash memory and being packaged •••• 17 •Figure 7; Note 3 •••• after setting this bit to “1” (reset). •••• after setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”. 19 •Programming Command (4016); lines 18,19 •••• be executed with the read status register mode kept. •••• •••• be executed with the read status register mode kept if there is no programming error. •••• 23 •Figure 11 Status Register Error Status Register Read (1/1)