M38027E8DSP

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3802 group is the 8-bit microcomputer based on the 740 family core technology. The 3802 group is designed for controlling systems that require analog signal processing and include two serial I/O functions, A-D converters, and D-A converters. The various microcomputers in the 3802 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3802 group, refer to the section on group expansion. • Programmable input/output ports ............................................. 56 • Interrupts .................................................. 16 sources, 16 vectors • Timers ............................................................................. 8 bit ! 4 • Serial I/O1 .................... 8-bit ! 1 (UART or Clock-synchronized) • Serial I/O2 .................................... 8-bit ! 1 (Clock-synchronized) • PWM ................................................................................ 8-bit ! 1 • A-D converter .................................................. 8-bit ! 8 channels • D-A converter .................................................. 8-bit ! 2 channels • Clock generating circuit ....................... Internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) • Power source voltage .................................................. 3.0 to 5.5 V (Extended operating temperature version : 4.0 to 5.5 V) FEATURES • Basic machine-language instructions ....................................... 71 • The minimum instruction execution time ............................ 0.5 µ s • (at 8 MHz oscillation frequency) Memory size ROM .................................................................. 8 K to 32 K bytes RAM ................................................................. 384 to 1024 bytes • Power dissipation ............................................................... 32 mW • Memory expansion possible • Operating temperature range .................................... –20 to 85°C (Extended operating temperature version : –40 to 85°C) APPLICATIONS Office automation, VCRs, tuners, musical instruments, cameras, air conditioners, etc. PIN CONFIGURATION (TOP VIEW) P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 41 40 38 37 39 36 35 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 15 14 16 1 3 4 5 7 2 6 8 9 47 43 42 34 33 45 44 46 P37/RD P36/WR P35/SYNC P34/φ P33/RESETOUT P32/ONW P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63 /AN3 32 31 30 29 28 27 26 M38022M4-XXXFP 25 24 23 22 21 20 19 18 17 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40/INT4 P41/INT0 RESET CNVSS P42/INT1 Package type : 64P6N-A 64-pin plastic-molded QFP P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT2 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) VCC VREF AV SS P67/AN 7 P66/AN 6 P65/AN 5 P64/AN 4 P63/AN 3 P62/AN 2 P61/AN 1 P60/AN 0 P57/INT 3 P56/PWM P55/CNTR 1 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT 2 P42/INT 1 CNV SS RESET P41/INT 0 P40/INT 4 XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA 1 P31/DA 2 P32/ONW P33/RESET OUT P34/φ P35/SYNC P36/WR P37/RD P00/AD 0 P01/AD 1 P02/AD 2 P03/AD 3 P04/AD 4 P05/AD 5 P06/AD 6 P07/AD 7 P10/AD 8 P11/AD 9 P12/AD 10 P13/AD 11 P14/AD 12 P15/AD 13 P16/AD 14 P17/AD 15 P20/DB 0 P21/DB 1 P22/DB 2 P23/DB 3 P24/DB 4 P25/DB 5 P26/DB 6 P27/DB 7 Package type : 64P4B 64-pin shrink plastic-molded DIP M38022M4-XXXSP 2 FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B) Reset input VSS VCC RESET 27 26 1 32 Clock input XIN CNVSS Clock output XOUT 30 31 Clock generating circuit CPU RAM ROM X Prescaler 12 (8) Y S PC H PS CNTR0 CNTR1 PC L Prescaler Y (8) Prescaler X (8) A Timer 1 (8) Timer 2 (8) Timer X (8) Timer Y (8) A-D converter (8) SI/O2 (8) SI/O1 (8) D-A converter 2 (8) D-A converter 1 (8) PWM (8) INT0 ~ INT3 INT2 INT4 P6(8) P5(8) P4(8) P3(8) P2(8) P1(8) P0(8) 2 12 13 14 15 16 17 18 19 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VREF AVSS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0 3802 Group 3 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin VCC , VSS CNVSS Name Power source CNVSS Function Function except a port function • Apply voltage of 3.0 V–5.5 V to VCC, and 0 V to VSS. (Extended operating temperature version : 4.0 V to 5.5 V) • This pin controls the operation mode of the chip. • Normally connected to VSS. • If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed. • Reference voltage input pin for A-D and D-A converters • GND input pin for A-D and D-A converters • Connect to VSS . • Reset input pin for active “L” • Input and output signals for the clock generating circuit. • Connect a ceramic resonator or quartz-crystal oscillator between the XIN and X OUT pins to set the oscillation frequency. • If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. • The clock is used as the oscillating source of system clock. • • • • • • 8 bit CMOS I/O port I/O direction register allows each pin to be individually programmed as either input or output. At reset this port is set to input mode. In modes other than single-chip, these pins are used as address, data, and control bus I/O pins. CMOS compatible input level CMOS 3-state output structure • D–A conversion output pins VREF AVSS RESET XIN XOUT Analog reference voltage Analog power source Reset input Clock input Clock output P00–P07 P10–P17 P20–P27 P30 /DA1 , P31/DA2 P32–P37 P40/INT4, P41/INT0, P42/INT1, P43/INT2 P44/RXD, P45/T XD, P46/SCLK1 , P47/SRDY1 P50/SIN2 , P51/SOUT2, P52/SCLK2 , P53/SRDY2 P54/CNTR0, P55/CNTR 1 P56/PWM P57/INT3 P60/AN0– P67/AN7 I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 • 8-bit CMOS I/O port with the same function as port P0 • CMOS compatible input level • CMOS 3-state output structure • External interrupt input pin • Serial I/O1 I/O pins I/O port P5 • 8-bit CMOS I/O port with the same function as port P0 • CMOS compatible input level • CMOS 3-state output structure • Serial I/O2 I/O pins • Timer X and Timer Y I/O pins • PWM output pin • External interrupt input pin I/O port P6 • 8-bit CMOS I/O port with the same function as port P0 • CMOS compatible input level • CMOS 3-state output structure • A-D conversion input pins 4 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 3802 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity ................................... 8 K to 32 K bytes RAM capacity .............................................. 384 to 1024 bytes (2) Packages 64P4B ............................................ Shrink plastic molded DIP 64P6N-A ................................................... Plastic molded QFP 64S1B-E .................................................... Shrink ceramic DIP 64D0 ................................................................... Ceramic LCC Memory Expansion Plan ROM size (bytes) 32K Mass product M38027M8/E8 28K Mass product 24K M38024M6 20K Mass product 16K M38022M4 12K Mass product 8K M38022M2 4K 192 256 384 512 RAM size (bytes) 640 768 896 1024 Currently supported products are listed below Product M38022M2-XXXSP M38022M2-XXXFP M38022M4-XXXSP M38022M4-XXXFP M38024M6-XXXSP M38024M6-XXXFP M38027M8-XXXSP M38027E8-XXXSP M38027E8SP M38027M8-XXXFP M38027E8-XXXFP M38027E8FP M38027E8SS M38027E8FS (P) ROM size (bytes) ROM size for User in ( ) 8192 (8062) 16384 (16254) 24576 (24446) RAM size (bytes) 384 384 640 Package 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 32768 (32638) Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version EPROM version As of May 1996 1024 64P6N-A 64S1B-E 64D0 5 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (Extended operating temperature version) Mitsubishi plans to expand the 3802 group (extended operating temperature version) as follows: (1) Support for mask ROM One Time PROM, and EPROM versions ROM/PROM capacity ................................... 8 K to 32 K bytes RAM capacity .............................................. 384 to 1024 bytes (2) Packages 64P4B ............................................ Shrink plastic molded DIP 64P6N-A ................................................... Plastic molded QFP Memory Expansion Plan (Extended operating temperature version) ROM size (bytes) 32K Mass product M38027M8D/E8D 28K 24K 20K Mass product 16K M38022M4D 12K Mass product 8K M38022M2D 4K 192 256 384 512 RAM size (bytes) 640 768 896 1024 Currently supported products are listed below. Product M38022M2DXXXSP M38022M2DXXXFP M38022M4DXXXSP M38022M4DXXXFP M38027M8DXXXSP M38027E8DXXXSP M38027E8DSP M38027M8DXXXFP M38027E8DXXXFP M38027E8DFP (P) ROM size (bytes) 8192 (8062) 16384 (16254) RAM size (bytes) 384 384 Package 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 32768 (32638) 1024 64P6N-A Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) As of May 1996 6 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M3802 2 M 4 - XXX SP Package type SP : 64P4B package FP : 64P6N-A package SS : 64S1B-E package FS : 64D0 package ROM number Omitted in some types. Normally, using hyphen. When electrical characteristic, or division of quality identification code using alphanumeric character – : standard D : Extended operating temperature version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 7 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3802 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. CPU mode register The CPU mode register is allocated at address 003B 16. The CPU mode register contains the stack page selection bit. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return “0” when read) Fig. 1 Structure of CPU mode register 8 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Memory Special function register (SFR) area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero page The 256 bytes from addresses 0000 16 t o 00FF16 a re called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. RAM area RAM capacity (bytes) Address XXXX16 000016 SFR area 004016 010016 Zero page 192 256 384 512 640 768 896 1024 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 RAM XXXX16 Reserved area 044016 ROM area ROM capacity (bytes) Address YYYY16 Address ZZZZ16 Not used YYYY16 Reserved ROM area (128 bytes) 4096 8192 12288 16384 20480 24576 28672 32768 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page Reserved ROM area Fig. 2 Memory map diagram 9 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) PWM control register (PWMCON) PMW prescaler (PREPWM) PWM register (PWM) AD/DA control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) 003816 003916 003A16 003B16 003C16 003D16 003E16 Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2) Serial I/O2 register (SIO2) 003F16 Fig. 3 Memory map of special function register (SFR) 10 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O Ports Direction registers The 3802 group has 56 programmable I/O pins arranged in seven I/O ports (ports P0 to P6). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Pin P00 –P07 Name Port P0 Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits P10 –P17 Port P1 P20 –P27 P30/DA1 P31/DA2 P32 –P37 P40 /INT4 , P41 /INT0 , P43 /INT2 P44/RXD, P45/TXD, P46 /SCLK1 , P47/SRDY1 P50 /SIN2 , P51 /SOUT2, P52 /SCLK2 , P53/SRDY2 P54 /CNTR0 , P55 /CNTR1 P56 /PWM P57 /INT3 P60 /AN0– P67 /AN7 Port P2 Port P3 I/O Format CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level Non-Port Function Address low-order byte output Address high-order byte output Related SFRs CPU mode register Ref.No. CPU mode register (1) Data bus I/O D-A conversion output Control signal I/O External interrupt input CPU mode register AD/DA control register CPU mode register CPU mode register Interrupt edge selection register Serial I/O1 control register UART control register (2) (1) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (3) (14) Port P4 Input/output, individual bits CMOS 3-state output CMOS compatible input level Serial I/O1 function I/O Serial I/O2 function I/O Port P5 Input/output, individual bits CMOS 3-state output CMOS compatible input level Serial I/O2 control register Timer X and Timer Y function I/O PWM output External interrupt input A-D conversion input Timer XY mode register PWM control register Interrupt edge selection register Port P6 Input/output, individual bits CMOS 3-state output CMOS compatible input level Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. 11 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0, P1, P2, P32–P37 Direction register (2) Ports P30, P31 Direction register Data bus Port latch Data bus Port latch D–A conversion output DA1 output enable bit (P3 0) DA2 output enable bit (P3 1) (3) Ports P40–P43, P57 Direction register (4) Port P44 Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch Data bus Port latch Interrupt input Serial I/O1 input (5) Port P45 P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register (6) Port P46 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O1 output Serial I/O1 clock output Serial I/O1 external clock input (7) Port P47 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register (8) Port P50 Direction register Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O1 ready output Fig. 4 Port block diagram (single-chip mode) (1) 12 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (9) Port P51 P51/SOUT2 P-channel output disable bit Serial I/O2 transmit end signal Serial I/O2 port selection bit Direction register (10) Port P52 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch Data bus Port latch Serial I/O2 output Serial I/O2 clock output Serial I/O2 external clock input (11) Port P53 SRDY2 output enable bit (12) Ports P54, 55 Direction register Direction register Data bus Data bus Port latch Port latch Pulse output mode Serial I/O2 ready output Timer output CNTR0, CNTR1 Interrupt input (13) Port P56 PWM output enable bit (14) Port P6 Direction register Direction register Data bus Data bus Port latch Port latch A-D conversion input PWM output Analog input pin selection bit Fig. 5 Port block diagram (single-chip mode) (2) 13 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts occur by sixteen sources: seven external, eight internal, and one software. Interrupt operation When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering.The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. Interrupt control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Table 1. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT 0 INT 1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 Serial I/O2 INT 2 INT 3 INT 4 A-D converter BRK instruction Priority 1 2 3 4 Vector Addresses (Note 1) High Low FFFD 16 FFFC16 FFFB16 FFF916 FFF716 FFFA16 FFF816 FFF616 Notes on use When the active edge of an external interrupt (INT 0 t o INT 4, CNTR0 , or CNTR1 ) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected. 5 6 7 8 9 10 11 12 13 14 15 16 17 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB 16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF 16 FFDD16 FFF416 FFF216 FFF016 FFEE16 FFEC 16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE 16 FFDC16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O2 data transfer At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At completion of A-D conversion At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 14 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 6 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit Not used (returns “0” when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Serial I/O2 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Serial I/O2 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 7 Structure of interrupt-related registers 15 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timers The 3802 group has four timers: timer X, timer Y, timer 1, and timer 2. All timers are count down. When the timer reaches “0016 ”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each be selected in one of four operating modes by setting the timer XY mode register. Timer Mode The timer counts f(XIN)/16 in timer mode. Pulse Output Mode Timer X (or timer Y) counts f(XIN )/16. Whenever the contents of the timer reach “0016 ”, the signal output from the CNTR0 ( or CNTR 1 ) pin is inverted. If the CNTR 0 ( or CNTR1 ) active edge switch bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P54 ( or port P5 5) direction register to output mode. Event Counter Mode Operation in event counter mode is the same as in timer mode, except the timer counts signals input through the CNTR 0 o r CNTR1 pin. Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts at the oscillation frequency divided by 16 while the CNTR0 (or CNTR1 ) pin is at “H”. If the CNTR0 ( or CNTR1 ) active edge switch bit is “1”, the count continues during the time that the CNTR0 (or CNTR1 ) pin is at “L”. In all of these modes, the count can be stopped by setting the timer X (timer Y) count stop bit to “1”. Every time a timer underflows, the corresponding interrupt request bit is set. b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b4b5 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig. 8 Structure of timer XY register 16 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus Oscillator f(XIN ) Divider 1/16 Pulse width measurement mode P54/CNTR0 pin CNTR0 active edge switch bit “0” “1” Timer mode Pulse output mode Prescaler X (8) Event counter mode CNTR0 active edge switch bit “1” “0” Q Timer X count stop bit To CNTR 0 interrupt request bit Timer X (8) To timer X interrupt request bit Prescaler X latch (8) Timer X latch (8) Q Toggle flip- flop R Timer X latch write pulse Pulse output mode Data bus T Port P54 direction register Port P5 4 latch Pulse output mode Prescaler Y latch (8) Pulse width measurement mode P55/CNTR1 pin CNTR1 active edge switch bit “0” “1” Timer mode Pulse output mode Prescaler Y (8) Event counter mode CNTR1 active edge switch bit “1” “0” Q Timer Y count stop bit Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit To CNTR 1 interrupt request bit Q Toggle flip- flop R Timer Y latch write pulse Pulse output mode T Port P55 direction register Port P5 5 latch Pulse output mode Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 9 Block diagram of timer X, timer Y, timer 1, and timer 2 17 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 001816). Data bus Serial I/O1 control register Address 001A 16 Address 0018 16 Receive buffer P44/RXD Receive shift register Shift clock P46/SCLK1 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit f(XIN ) X IN BRG count source selection bit 1/4 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C 16 1/4 P47/SRDY1 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 0019 16 P45/TXD Transmit shift register Transmit buffer Address 0018 16 Data bus Fig. 10 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer (address 0018 16) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 11 Operation of clock synchronous serial I/O1 function 18 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous serial I/O (UART) mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received. Data bus Address 0018 16 Receive buffer OE Character length selection bit P44/RXD STdetector 7 bits 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C 16 1/4 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Receive shift register 1/16 UART control register Address 001B16 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) f(XIN) Fig. 12 Block diagram of UART serial I/O 19 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1V Serial output TXD ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 V SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 13 Operation of UART serial I/O function Serial I/O1 control register (SIO1CON) 001A16 The serial I/O control register consists of eight control bits for the serial I/O function. UART control register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/T XD pin. spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit buffer/Receive buffer register (TB/ RB) 001816 The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. Serial I/O1 status register (SIO1STS) 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re- Baud rate generator (BRG) 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 20 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O1 status register (SIO1STS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A 16) BRG count source selection bit (CSS) 0: f(X IN) 1: f(X IN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P4 7 pin operates as ordinaly I/O pin 1: P4 7 pin operates as S RDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P4 4 to P4 7 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P4 4 to P4 7 operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 14 Structure of serial I/O control registers 21 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 Serial I/O2 control register (SIO2CON) 001D16 The serial I/O2 control register contains seven bits which control various serial I/O functions. 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit (SM23) 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit (SM24) 0: I/O port 1: SRDY2 output pin Transfer direction selection bit (SM25) 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit (SM26) 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Fig. 15 Structure of serial I/O2 control register 1/8 1/16 Internal synchronous clock selection bits XIN Divider 1/32 1/64 1/128 1/256 Data bus P53 latch "0" Serial I/O2 synchronous clock selection bit SRDY2 Synchronization circuit "1" "0" P53/SRDY2 SCLK2 "1" SRDY2 output enable bit External clock P52 latch "0" P52/SCLK2 "1" Serial I/O2 port selection bit P51 latch "0" Serial I/O counter 2 (3) Serial I/O2 interrupt request P51/SOUT2 "1" Serial I/O2 port selection bit P50/SIN2 Serial I/O shift register 2 (8) Fig. 16 Block diagram of serial I/O2 function 22 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transfer clock (Note 1) Serial I/O2 register write signal (Note 2) Serial I/O2 output S OUT2 Serial I/O2 input S IN2 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion. Fig. 17 Timing of serial I/O2 function 23 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PULSE WIDTH MODULATION (PWM) The 3802 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input X IN or that clock input divided by 2. PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pin also functions as port P56 . Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ! (n+1)/f(XIN) = 51 ! (n+1) µ s (when XIN = 5 MHz) Output pulse “H” period = PWM period ! m/255 = 0.2 ! (n+1) ! m µs (when XIN = 5 MHz) 51 ! m ! (n+1) µs 255 PWM output T = [51 ! (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when X IN = 5 MHz) Fig. 18 Timing of PWM cycle Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch Count source selection bit X IN 1/2 “0” “1” PWM prescaler PWM register latch Port P56 PWM register Port P56 latch PWM enable bit Fig. 19 Block diagram of PWM function 24 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 PWM control register (PWMCON : address 002B 16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return “0” when read) Fig. 20 Structure of PWM control register A PWM output T PWM register write signal B C B= C T2 T T (Changes from “A” to “B” during “H” period) T2 PWM prescaler write signal (Changes from “T” to “T2” during PWM period) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 21 PWM output timing when PWM register or PWM prescaler is changed 25 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter The functional blocks of the A-D converter are described below. [Comparator and Control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(XIN) to 500 kHz or more during an A-D conversion. [A-D conversion register] The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [AD/DA control register] The AD/DA control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Bits 6 and 7 are used to control the output of the D-A converter. b7 b0 AD/DA control register (ADCON : address 0034 16) Analog input pin selection bits b2 b1 b0 [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF into 256, and outputs the divided voltages. [Channel selector] The channel selector selects one of the ports P6 0/AN0 to P67 /AN7, and inputs the voltage to the comparator. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: P60/AN0 1: P61/AN1 0: P62/AN2 1: P63/AN3 0: P64/AN4 1: P65/AN5 0: P66/AN6 1: P67/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (return "0" When read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Fig.22 Structure of AD/DA control register Data bus AD/DA control register (Address 0034 16) b7 b0 3 P60/AN0 P61/AN 1 P62/AN 2 P63/AN 3 P64/AN 4 P65/AN 5 P66/AN 6 P67/AN 7 A-D control circuit A-D interrupt request Channel selector Comparator A-D conversion register (Address 0035 16 ) 8 Resistor ladder VREF AV SS Fig. 23 Block diagram of A-D converter 26 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A Converter The 3802 group has two internal D-A converters (DA1 and DA2) with 8-bit resolutions. The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from the DA 1 or DA2 pin by setting the DA output enable bit to “1”. When using the D-A converter, the corresponding port direction register bit (P30 /DA1 or P31/DA 2 ) should be set to “0” (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V = VREF ! n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to “0016 ”, the DA output enable bits are cleared to “0”, and the P3 0/DA1 and P31 / DA 2 pins are set to input (high impedance). The D-A output is not buffered, so connect an external buffer when driving a low-impedance load. Set VCC to 3.0 V or more when using the D-A converter. D-A1 conversion register (8) DA1 output enable bit P30/DA1 Data bus R-2R resistor ladder D-A2 conversion register (8) DA2 output enable bit P31/DA2 R-2R resistor ladder Fig. 24 Block diagram of D-A converter "0" DA1 output enable bit R R 2R R 2R R 2R R 2R R 2R R 2R 2R 2R LSB P30/DA1 "1" MSB 2R D-A1 conversion register AV SS VREF "0" "1" Fig. 25 Equivalent connection circuit of D-A converter 27 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Circuit To reset the microcomputer, the RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 4.0 V and 5.5 V), reset is released. Internal operation begin until after 8 to 13 X IN clock cycles are completed. After the reset is completed, the program starts from the address contained in address FFFD 16 (highorder byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.6 V for VCC of 3.0 V (Extended operating temperature version : the reset input voltage is less than 0.8 V for VCC of 4.0 V). Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) Port P5 direction register (7) Port P6 direction register (8) Serial I/O1 status register (9) Serial I/O1 control register (10) UART control register (000116) · · · (000316) · · · (000516) · · · (000716) · · · (000916) · · · (000B16) · · · (000D16) · · · Register contents 0016 0016 0016 0016 0016 0016 0016 (001916) · · · 1 0 0 0 0 0 0 0 (001A16) · · · 0016 (001B16) · · · 1 1 1 0 0 0 0 0 (001D16) · · · (002016) · · · (002116) · · · (002216) · · · (002316) · · · (002416) · · · (002516) · · · (002616) · · · (002716) · · · (002B16) · · · 0016 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 0016 4.0V Power source 0V voltage 0.8V (11) Serial I/O2 control register (12) Prescaler 12 (13) Timer 1 (14) Timer 2 Reset input 0V voltage (15) Timer XY mode register (16) Prescaler X (17) Timer X 1 5 M51953AL 4 0.1 µ F VCC RESET (18) Prescaler Y (19) Timer Y (20) PWM control register (21) AD/DA control register (22) D-A1 conversion register (003416) · · · 0 0 0 0 1 0 0 0 (003616) · · · (003716) · · · 0016 0016 0016 3 VSS 3802 group (23) D-A2 conversion register (24) Interrupt edge selection register (003A16) · · · (25) CPU mode register (003B16) · · · 0 0 0 0 0 0 V 0 (003C16) · · · (003D16) · · · (003E16) · · · (003F16) · · · 0016 0016 0016 0016 Fig. 26 Example of reset circuit (26) Interrupt request register 1 (27) Interrupt request register 2 (28) Interrupt control register 1 (29) Interrupt control register 2 (30) Processor status register (31) Program counter (PS) ! ! ! ! ! 1 ! ! (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16 Note. ! : Undefined V : The initial values of CM 1 are determined by the level at the CNVSS pin. The contents of all other registers and RAM are undefined after a reset, so they must be initialized by software. Fig. 27 Internal status of microcomputer after reset 28 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XIN φ RESET RESETOUT (internal reset) SYNC Address ? ? ? ? ? FFFC FFFD ADH, ADL Reset address from the vector table Data XIN: 8 to 13 clock cycles ? ? ? ? ? ADL ADH Notes 1: f(XIN) and f(φ) are in the relationship: f(X IN)=2 • f(φ). 2: A question mark (?) indicates an undefined status that depends on the previous status. Fig. 28 Timing of reset 29 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to “0” before the STP instruction is executed. Oscillation control Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H”. Timer 1 is set to “0116 ” and prescaler 12 is set to “FF16 ”. Oscillator restarts when an external interrupt is received, but the internal clock φ remains at an “H” until timer 1 underflow. This allows time for the clock circuit oscillation to stabilize. If oscillator is restarted by a reset, no wait time is generated, so keep the RESET pin at an “L” level until oscillation has stabilized. Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator itself does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. XIN XOUT CIN COUT Fig. 29 Ceramic resonator circuit XIN XOUT Open External oscillation circuit Vcc Vss Fig. 30 External clock input circuit Interrupt request Interrupt disable flag (I) Reset STP instruction S Q S Q Q S Reset R WIT instruction R R STP instruction φ output ONW pin Single-chip mode 1/2 Rd Internal clock φ ONW control 1/8 Prescaler 12 FF16 0116 Timer 1 Reset or STP instruction Rf XIN XOUT Fig. 31 Block diagram of clock generating circuit 30 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Processor Modes Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits CM 0 a nd CM 1 ( bits 0 and 1 of address 003B 16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table 2. Functions of ports in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs low-order byte of address. Port P1 Outputs high-order byte of address. Operates as I/O pins for data D7 to D0 Port P2 (including instruction codes). P30 and P31 function only as output pins (except that the port latch cannot be read). P32 is the ONW input pin. P33 is the RESETOUT output pin. (Note) Port P3 P34 is the φ output pin. P35 is the SYNC output pin. P36 is the WR output pin, and P3 7 is the RD output pin. 000016 000816 004016 SFR area Internal RAM reserved area 000016 000816 004016 SFR area Internal RAM reserved area 044016 V 044016 YYYY16 FFFF16 Internal ROM FFFF16 Microprocessor mode The shaded areas are external memory areas. V : YYYY16 is the start address of internal ROM. Memory expansion mode Fig. 32 Memory maps in various processor modes b7 b0 Note: If CNV SS is connected to V SS , the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the RESETOUT output pin. Single-Chip Mode Select this mode by resetting the microcomputer with CNV SS connected to VSS. Memory Expansion Mode Select this mode by setting the processor mode bits to “01” in software with CNVSS connected to VSS . This mode enables external memory expansion while maintaining the validity of the internal ROM. Internal ROM will take precedence over external memory if addresses conflict. Microprocessor Mode Select this mode by resetting the microcomputer with CNV SS connected to V CC, or by setting the processor mode bits to “10” in software with CNVSS connected to VSS . In microprocessor mode, the internal ROM is no longer valid and external memory must be used. CPU mode register (CPUM : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Not used (return “0” when read) Fig. 33 Structure of CPU mode register 31 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bus control with memory expansion The 3802 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. If an “L” level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle is extended by one cycle of φ . During this extended period, the RD or WR signal remains at “L”. This extension period is valid only for writing to and reading from addresses 0000 16 t o 0007 16 a nd 044016 to FFFF 16 in microprocessor mode, 044016 to YYYY16 in memory expansion mode, and only read and write cycles are extended. Read cycle Dummy cycle Write cycle Read cycle Dummy cycle Write cycle φ AD15 to AD0 RD WR ONW V V V V : Period during which ONW input signal is received During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal is received. Fig. 34 ONW function timing 32 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1”. Serial I/O1 continues to output the final bit from the T XD pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before executing a BBC or BBS instruction. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(X IN) is at least 500 kHz during an A-D conversion. (If the ONW pin has been set to “L”, the A-D conversion will take twice as long to match the longer bus cycle, and so f(XIN ) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conversion. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. D-A Converter The accuracy of the D-A converter becomes poor rapidly under the VCC = 3.0 V or less condition. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency. When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock φ may be one fourth the XIN frequency. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Memory Expansion Mode The memory expansion mode is not available in the following microcomputers. • M38024M6-XXXSP • M38024M6-XXXFP Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. Memory Expansion Mode and Microprocessor Mode Execute the LDM or STA instruction for writing to port P3 (address 000616) in memory expansion mode and microprocessor mode. Set areas which can be read out and write to port P3 (address 0006 16) in a memory, using the read-modify-write instruction (SEB, CLB). 33 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Package 64P4B, 64S1B 64P6N 64D0 Name of Programming Adapter PCA4738S-64A PCA4738F-64A PCA4738L-64A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 35 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 35 Programming and testing of One Time PROM version 34 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00 –P07, P10–P17, P2 0–P27, P30 –P37, P40–P47, P5 0–P57, P60 –P67, VREF Input voltage RESET, XIN Input voltage CNV SS Output voltage P00 –P07, P10–P17, P2 0–P27, P30 –P37, P40–P47, P5 0–P57, P60 –P67, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 All voltages are based on VSS . Output transistors are cut off. –0.3 to V CC +0.3 –0.3 to 13 –0.3 to V CC +0.3 Ta = 25 °C 1000 (Note) –20 to 85 –40 to 125 Unit V V V V V mW °C °C Note: 300 mW in case of the flat package. RECOMMENDED OPERATING CONDITIONS Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL Σ I OH(peak) Σ I OH(peak) Σ I OL(peak) Σ I OL(peak) Σ I OH(avg) Σ I OH(avg) Σ I OL(avg) Σ I OL(avg) I OH(peak) I OL(peak) I OH(avg) I OL(avg) f(XIN) Parameter (Vcc = 3.0 to 5.5 V, Ta = –20 to 85° C, unless otherwise noted) Limits Min. 3.0 4.0 2.0 3.0 0 AVSS 0.8 V CC 0.8 VCC 0 0 0 VCC VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC –80 –80 80 80 –40 –40 40 40 –10 10 –5 5 Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC VCC Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA Power source voltage (f(XIN) < 2 MHz) (Note 1) Power source voltage (f(XIN) = 8 MHz) (Note 1) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0–AN 7 “H” input voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 “H” input voltage RESET, XIN, CNVSS “L” input voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 2) “H” total peak output current P40–P47,P50 –P57, P60–P67 (Note 2) “L” total peak output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 2) “L” total peak output current P40–P47,P50 –P57, P60–P67 (Note 2) “H” total average output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 2) “H” total average output current P40–P47,P50 –P57, P60–P67 (Note 2) “L” total average output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 2) “L” total average output current P40–P47,P50 –P57, P60–P67 (Note 2) “H” peak output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 3) “L” peak output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 3) “H” average output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 4) “L” average output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 4) Internal clock oscillation frequency (V CC = 4.0 to 5.5 V) Internal clock oscillation frequency (V CC = 3.0 to 4.0 V) 6 8 MHz 6 VCC–16 Note 1: The minimum power source voltage is X + 16 [V] (f(XIN) = XMHz) on the condition of 2 MHz < f(X IN) < 8 MHz. 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 3: The peak output current is the peak current flowing in each port. 4: The average output current I OL(avg), IOH(avg) in an average value measured over 100 ms. 35 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7,P50–P57, P60–P6 7 Hysteresis Hysteresis Hysteresis “H” input current CNTR0, CNTR 1, INT0–INT 4 RX D, SCLK1, SIN2 , SCLK2 RESET P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 RESET, CNVSS X IN P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, RESET, CNVSS RESET, CNVSS X IN Test conditions IOH = –10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 3.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 3.0 to 5.5 V Limits Min. VCC–2.0 V VCC–1.0 2.0 V 1.0 0.4 0.5 0.5 VI = VCC VI = V CC VI = V CC VI = V SS 5.0 5.0 4 –5.0 V V V µA µA µA µA Typ. Max. Unit VOH VOL VT+ – V T– VT+ – V T– VT+ – V T– I IH I IH I IH I IL I IL I IL VRAM “H” input current “H” input current “L” input current –5.0 µA VI = V SS –4 µA VI = V SS 5.5 2.0 V When clock stopped 13 6.4 f(XIN) = 8 MHz, VCC = 5 V 8 4 f(XIN) = 5 MHz, VCC = 5 V 2.0 0.8 f(XIN) = 2 MHz, VCC = 3 V When WIT instruction is executed with 1.5 mA f(Xin) = 8MHz,VCC=5V When WIT instruction is executed with 1 I CC Power source current f(Xin) = 5MHz,VCC=5V When WIT instruction is executed with 0.2 f(Xin) = 2MHz,VCC=3V T a = 25 ° C When STP instruction 1 0.1 is executed with clock (Note 2) µA stopped, output T a = 85 ° C 10 transistors isolated. (Note 2) Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16 ) is “0”. P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through V REF pin. “L” input current “L” input current RAM hold voltage A–D CONVERTER CHARACTERISTICS Symbol — — t CONV RLADDER I VREF I I(AD) Parameter (VCC = 3.0 to 5.5 V, VSS = AV SS = 0 V, VREF = 2.0 V to VCC, T a = –20 to 85 °C, unless otherwise noted) Test conditions Min. Limits Typ. ±1 35 150 0.5 Max. 8 ±2.5 50 200 5.0 Unit Bits LSB tC (φ ) kΩ µA µA Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current VREF = 5.0 V 50 Note: When D-A conversion registers (addresses 003616 and 003716 ) contain “0016”. 36 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A CONVERTER CHARACTERISTICS Symbol — — t su RO I VREF Resolution Absolute accuracy Parameter (VCC = 3.0 to 5.5 V, V SS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted) Test conditions Min. Limits Typ. Max. 8 1.0 2.5 3 4 3.2 Unit Bits % µs kΩ mA VCC = 4.0 to 5.5 V VCC = 3.0 to 4.0 V 1 2.5 Setting time Output resistor Reference power source input current (Note) Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through the A-D resistance ladder. 37 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1 (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t w(RESET) t c(X IN) t wH(XIN) t wL(XIN) t c(CNTR) t wH(CNTR) t wH(INT) t wL(CNTR) t wL(INT) t c(S CLK1) t c(S CLK2) t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) tsu(R XD–SCLK1) tsu(SIN2–S CLK2) th(S CLK1–RX D) th(S CLK2–SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tw(RESET) tc(X IN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(S CLK1) tc(S CLK2) twH(SCLK1 ) twH(SCLK2 ) twL(SCLK1) twL(SCLK2) tsu(RX D–SCLK1) tsu(SIN2–SCLK2) th(SCLK1–RX D) th(SCLK2–S IN2) Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Parameter Min. 2 500/ (3 V CC–8) 200/ (3 V CC–8) 200/ (3 V CC–8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”. 38 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) td(S CLK1–TXD) td(S CLK2–SOUT2 ) tv(SCLK1–TX D) tv(SCLK2–S OUT2) t r(SCLK1 ) t f(SCLK1) t r(SCLK2 ) t f(SCLK2) t r(CMOS) t f(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Min. tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 140 200 Fig. 36 –30 0 30 30 30 40 30 30 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 Note1: When the P45/T XD P-channel output disable bit of the UART control register (bit 4 of address 001B16 ) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16 ) is “0”. 3: XOUT pin is excluded. SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) td(S CLK1–TXD) td(S CLK2–SOUT2 ) tv(SCLK1–TX D) tv(SCLK2–S OUT2) t r(SCLK1 ) t f(SCLK1) t r(SCLK2 ) t f(SCLK2) t r(CMOS) t f(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Min. tc(SCLK1 )/2–50 tc(SCLK2 )/2–240 tc(SCLK1 )/2–50 tc(SCLK2 )/2–240 350 400 Fig. 36 –30 0 50 50 50 50 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B 16) is “0”. 2: When the P51/S OUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D 16) is “0”. 3: XOUT pin is excluded. 39 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE Symbol t su(ONW–φ) t h(φ–ONW) t su(DB–φ) t h(φ–DB) t su(ONW–RD) t su(ONW–WR) t h(RD–ONW) t h(WR–ONW) t su(DB–RD) t h(RD–DB) Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter Limits Min. –20 –20 60 0 –20 –20 65 0 Typ. Max. (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Unit ns ns ns ns ns ns ns ns SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE Symbol t c(φ) t wH(φ) t wL(φ) t d(φ–AH) t v(φ–AH) t d(φ–AL) t v(φ–AL) t d(φ–SYNC) t v(φ–SYNC) t d(φ–WR) t v(φ–WR) t d(φ–DB) t v(φ–DB) Parameter Test conditions Limits Min. t c(XIN)–10 t c(XIN)–10 6 6 20 10 25 10 20 10 10 5 20 40 45 Typ. 2t c(XIN) Max. (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN)–15 tc(XIN)–20 5 5 15 10 0 200 200 65 ns ns ns ns ns ns ns ns φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD 15–AD 8 delay time After φ AD 15–AD 8 valid time After φ AD 7–AD0 delay time After φ AD 7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width t wL(RD) RD pulse width, WR pulse width t wL(WR) (When one-wait is valid) t d(AH–RD) After AD15 –AD 8 RD delay time t d(AH–WR) After AD15 –AD8 WR delay time t d(AL–RD) After AD7 –AD0 RD delay time t d(AL–WR) After AD7 –AD0 WR delay time t v(RD–AH) After RD AD 15–AD 8 valid time t v(WR–AH) After WR AD 15–AD 8 valid time t v(RD–AL) After RD AD 7–AD 0 valid time t v(WR–AL) After WR AD 7–AD 0 valid time t d(WR–DB) After WR data bus delay time t v(WR–DB) After WR data bus valid time td(RESET–RESETOUT ) RESETOUT output delay time (Note 1) t v(φ–RESET) RESET OUT output valid time (Note 1) 3 15 t c(XIN)–10 3tc(X IN)–10 t c(XIN)–35 t c(XIN)–40 0 0 20 10 70 Fig. 36 Note 1: The RESET OUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. 40 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 ° C, unless otherwise noted) Symbol t su(ONW–φ) t h(φ–ONW) t su(DB–φ) t h(φ–DB) t su(ONW–RD) t su(ONW–WR) th (RD–ONW) t h(WR–ONW) t su(DB–RD) t h(RD–DB) Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter Min. –20 –20 180 0 –20 –20 185 0 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (V CC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t c(φ) Parameter Test conditions Min. Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 195 300 300 ns ns φ clock cycle time 2t c(XIN) φ clock “H” pulse width tc(X IN)–20 φ clock “L” pulse width tc(X IN)–20 After φ AD 15–AD 8 delay time After φ AD 15–AD 8 valid time 10 15 After φ AD 7–AD0 delay time After φ AD 7–AD 0 valid time 10 15 SYNC delay time 40 SYNC valid time 20 RD and WR delay time 15 RD and WR valid time 3 7 After φ data bus delay time After φ data bus valid time 15 Fig. 36 RD pulse width, WR pulse width tc(X IN)–20 t wL(RD) RD pulse width, WR pulse width t wL(WR) 3t c(XIN) –20 (when one-wait is valid) t d(AH–RD) After AD15 –AD 8 RD delay time t c(XIN) –145 t d(AH–WR) After AD15 –AD8 WR delay time t d(AL–RD) After AD7 –AD0 RD delay time t c(XIN) –145 t d(AL–WR) After AD7 –AD0 WR delay time t v(RD–AH) After RD AD 15–AD 8 valid time 10 5 t v(WR–AH) After WR AD 15–AD 8 valid time t v(RD–AL) After RD AD 7–AD 0 valid time 10 5 t v(WR–AL) After WR AD 7–AD 0 valid time t d(WR–DB) After WR data bus delay time t v(WR–DB) After WR data bus valid time 10 td(RESET–RESETOUT ) RESETOUT output delay time (Note 1) t v(φ–RESET) RESET OUT output valid time (Note 1) 0 Note1: The RESET OUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and the RESET input goes “H”. t wH(φ) t wL(φ) t d(φ–AH) t v(φ–AH) t d(φ–AL) t v(φ–AL) t d(φ–SYNC) t v(φ–SYNC) t d(φ–WR) t v(φ–WR) t d(φ–DB) t v(φ–DB) 150 150 25 15 200 ns ns 13 cycles after 41 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS (Extended operating temperature version) Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00 –P07, P10–P17, P2 0–P27, P30 –P37, P40–P47, P5 0–P57, P60 –P67, VREF Input voltage RESET, XIN Input voltage CNV SS Output voltage P00 –P07, P10–P17, P2 0–P27, P30 –P37, P40–P47, P5 0–P57, P60 –P67, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 All voltage are based on VSS . Output transistors are cut off. –0.3 to V CC +0.3 –0.3 to 13 –0.3 to V CC +0.3 Ta = 25 °C 1000 (Note) –40 to 85 –65 to 150 Unit V V V V V mW °C °C RECOMMENDED OPERATING CONDITIONS (Extended operating temperature version) Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL Σ I OH(peak) Σ I OH(peak) Σ I OL(peak) Σ I OL(peak) Σ I OH(avg) Σ I OH(avg) Σ I OL(avg) Σ I OL(avg) I OH(peak) I OL(peak) I OH(avg) I OL(avg) f(XIN ) Parameter Power source voltage (f(XIN) ≤ 2 MHz) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN0–AN 7 “H” input voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 “H” input voltage RESET, XIN, CNVSS “L” input voltage P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 1) “H” total peak output current P40–P47,P50 –P57, P60–P67 (Note 1) “L” total peak output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 1) “L” total peak output current P40–P47,P50 –P57, P60–P67 (Note 1) “H” total average output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 1) “H” total average output current P40–P47,P50 –P57, P60–P67 (Note 1) “L” total average output current P00–P07 , P10 –P17, P2 0–P2 7, P30 –P37 (Note 1) “L” total average output current P40–P47,P50 –P57, P60–P67 (Note 1) “H” peak output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 2) “L” peak output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 2) “H” average output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 3) “L” average output current P00–P07, P10–P17 , P20–P27, P30 –P37, P40–P47 , P50–P57, P60–P67 (Note 3) Internal clock oscillation frequency (V CC = 4.0 to 5.5 V) Limits Min. 4.0 2.0 4.0 0 AVSS 0.8 VCC 0.8 VCC 0 0 0 Typ. 5.0 0 (V CC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) Max. 5.5 VCC VCC VCC VCC VCC 0.2 VCC 0.2 VCC 0.16 VCC –80 –80 80 80 –40 –40 40 40 –10 10 –5 5 8 V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz Unit V V V Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current I OL(avg), IOH(avg) in an average value measured over 100 ms. 42 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Extended operating temperature version) Symbol VOH Parameter “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7,P50–P5 7, P60–P6 7 Hysteresis CNTR0, CNTR 1, INT0–INT 4 Hysteresis RXD, SCLK1, SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, RESET, CNV SS “L” input current XIN RAM hold voltage Test conditions IOH = –10 mA (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Min. VCC–2.0 Typ. Max. Unit V VOL VT+ – VT– VT+ – VT– VT+ – VT– I IH I IH I IH I IL I IL VRAM IOL = 10 mA 0.4 0.5 0.5 VI = VCC VI = V CC VI = V CC VI = VSS VI = VSS When clock stopped f(XIN ) = 8 MHz f(XIN ) = 5 MHz When WIT instruction is executed with f(XIN) = 8 MHz When WIT instruction is executed with f(XIN) = 5 MHz Ta = 25 °C When STP instruction is executed with clock (Note 2) stopped, output Ta = 85 °C transistors isolated. (Note 2) –4 2.0 6.4 4 1.5 1 0.1 2.0 V V V V 5.0 5.0 4 –5.0 µA µA µA µA µA V 5.5 13 8 mA I CC Power source current 1 10 µA Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16 ) is “0”. P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through V REF pin. A-D CONVERTER CHARACTERISTICS (Extended operating temperature version) Symbol — — t CONV RLADDER I VREF I I(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current Test conditions (V CC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted) Min. Limits Typ. ±1 35 150 0.5 Max. 8 ±2.5 50 200 5.0 Unit Bits LSB tC (φ ) kΩ µA µA VREF = 5.0 V 50 Note: When D-A conversion registers (addresses 0036 16 and 0037 16) contain “0016 ”. 43 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A CONVERTER CHARACTERISTICS (Extended operating temperature version) Symbol — — t su RO I VREF Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) Test conditions (V CC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 4.0 V to VCC, Ta = –40 to 85 °C, unless otherwise noted) Min. Limits Typ. Max. 8 1.0 3 4 3.2 Unit Bits % µs kΩ mA 1 2.5 Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016 ”, and excluding currents flowing through the A-D resistance ladder. 44 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS 1 (Extended operating temperature version) Symbol t w(RESET) t c(XIN) t wH(XIN) t wL(XIN) t c(CNTR) t wH(CNTR) t wH(INT) t wL(CNTR) t wL(INT) t c(SCLK1 ) t c(SCLK2 ) t wH(SCLK1) t wH(SCLK2) t wL(SCLK1) t wL(SCLK2) tsu(R XD–SCLK1) tsu(SIN2–S CLK2) th(S CLK1–RXD) th(S CLK2–SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT 0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT 0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 ° C, unless otherwise noted) Min. 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(X IN) = 8 MHz and bit 6 of address 001A16 is “0”. SWITCHING CHARACTERISTICS 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 ° C, unless otherwise noted) Symbol twH(SCLK1 ) twH(SCLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1–TX D) td(SCLK2–S OUT2) tv(SCLK1–TXD) tv(SCLK2–S OUT2) tr(S CLK1) tf(SCLK1 ) tr(S CLK2) tf(SCLK2 ) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Min. tc(SCLK1)/2–30 tc(SCLK2)/2–160 tc(SCLK1)/2–30 tc(SCLK2)/2–160 140 200 Fig. 36 –30 0 30 30 30 40 30 30 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 Note1: When the P45/T XD P-channel output disable bit of the UART control register (bit 4 of address 001B16 ) is “0”. 2: When the P51/S OUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D 16) is “0”. 3: XOUT pin excluded. 45 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version) Symbol t su(ONW–φ) t h( φ–ONW) t su(DB–φ) t h( φ–DB) t su(ONW–RD) t su(ONW–WR) t h(RD–ONW) t h(WR–ONW) t su(DB–RD) t h(RD–DB) Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time Parameter (V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 ° C, unless otherwise noted) Limits Min. –20 –20 60 0 –20 –20 65 0 Typ. Max. Unit ns ns ns ns ns ns ns ns SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol tc(φ) twH(φ) twL(φ) td( φ–AH) tv(φ–AH) td( φ–AL) tv(φ–AL) td( φ–SYNC) tv(φ–SYNC) td( φ–WR) tv(φ–WR) td( φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESETOUT) tv(φ–RESET) Parameter φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15 –AD 8 delay time After φ AD 15–AD 8 valid time After φ AD 7–AD0 delay time After φ AD 7–AD0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (when one wait is valid) After AD 15–AD 8 RD delay time After AD15 –AD 8 WR delay time After AD7–AD 0 RD delay time After AD 7–AD 0 WR delay time After RD AD15 –AD8 valid time After WR AD 15–AD 8 valid time Test conditions Min. t c(XIN) –10 t c(XIN) –10 6 6 20 10 25 10 20 10 10 5 20 40 45 Limits Typ. 2! tc(X IN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(XIN )–15 tc(XIN)–20 5 ns ns ns 3 Fig. 36 15 tc(X IN)–10 3tc(X IN) –10 tc(X IN)–35 tc(X IN)–40 0 20 10 70 After RD AD 7–AD 0 valid time ns 0 5 After WR AD 7–AD 0 valid time ns After WR data bus delay time 65 15 ns After WR data bus valid time 10 ns RESETOUT output delay time 200 ns 200 RESETOUT output valid time (Note 1) 0 Note 1: The RESET OUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. Measurement output pin 100pF CMOS output Fig. 36 Circuit for measuring output switching characteristics 46 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAM (1) Timing Diagram tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2 VCC CNTR0, CNTR1 0.8 VCC tWH(INT) tWL(INT) 0.2 VCC INT0–INT4 0.8 VCC tW(RESET) RESET 0.2 VCC 0.8 VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2 VCC XIN 0.8 VCC tf tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2 VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) 0.8 VCC SCLK1 SCLK2 th(SCLK1-RXD), th(SCLK2- SIN2) RXD SIN2 0.8 VCC 0.2 VCC td(SCLK1-TXD),td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2) TX D SOUT2 47 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2)Timing Diagram in Memory Expansion Mode and Microprocessor Mode (a) tC(φ) tWH(φ) tWL(φ) φ 0.5 VCC td(φ-AH) tv(φ-AH) 0.5 VCC AD15–AD8 td(φ-AL) tv(φ-AL) 0.5 VCC AD7–AD0 td(φ-SYNC) tv(φ-SYNC) SYNC 0.5 VCC td(φ-WR) tv(φ-WR) RD,WR tSU(ONW- φ) 0.5 VCC th(φ-ONW) ONW 0.8 VCC 0.2 VCC tSU(DB- φ) th(φ-DB) DB0–DB7 (At CPU reading) DB0–DB7 (At CPU writing) 0.8 VCC 0.2 VCC td(φ-DB) 0.5 VCC tv(φ-DB) (3)Timing Diagram in Microprocessor Mode RESET φ 0.8 VCC 0.2 VCC 0.5 VCC td(RESET- RESET OUT) tv(φ- RESET OUT) RESETOUT 0.5 VCC 48 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (4) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (b) tWL(RD) tWL(WR) RD,WR td(AH-RD) td(AH-WR) 0.5 VCC tv(RD-AH) tv(WR-AH) AD15–AD8 0.5 VCC td(AL-RD) td(AL-WR) tv(RD-AL) tv(WR-AL) AD7–AD0 0.5 VCC tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) ONW (At CPU reading) RD 0.8 VCC 0.2 VCC tWL(RD) 0.5 VCC tSU(DB-RD) th(RD-DB) DB0–DB7 0.8 VCC 0.2 VCC (At CPU writing) WR td(WR-DB) 0.5 VCC tWL(WR) tv(WR-DB) 0.5 VCC DB0–DB7 49 MITSUBISHI MICROCOMPUTERS 3802 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • © 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Dec. 1997. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition 3802 GROUP DATA SHEET Revision Description Rev. date 971226 (1/1)