To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3850 group is the 8-bit microcomputer based on the 740 family core technology. The 3850 group is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.
FEATURES
q Basic machine-language instructions ...................................... 71 q Minimum instruction execution time .................................. 0.5 µ s (at 8 MHz oscillation frequency) q Memory size ROM ................................................................... 8K to 24K bytes RAM ..................................................................... 512 to 640 byte q Programmable input/output ports ............................................ 34 q Interrupts ................................................. 14 sources, 14 vectors q Timers ............................................................................. 8-bit ! 4 q Serial I/O ....................... 8-bit ! 1(UART or Clock-synchronized) q PWM ............................................................................... 8-bit ! 1 q A-D converter ............................................... 10-bit ! 5 channels q Watchdog timer ............................................................ 16-bit ! 1 q Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator)
q Power source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In high-speed mode .................................................. 2.7 to 5.5 V (at 4 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) q Power dissipation In high-speed mode .......................................................... 34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) q Operating temperature range.................................... –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P44/INT3/PWM P43/INT2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY P26/SCLK P25/TxD P24/RxD P23 P22 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13/(LED0) P14/(LED1) P15/(LED2) P16/(LED3) P17/(LED4)
Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)
Fig. 1 M38503M4-XXXFP/SP pin configuration
M38503M4-XXXFP M38503M4-XXXSP
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
CNVSS
15
RESET
18
PC L
CNTR 0
A
X
Y
CPU
VCC
1
S
VSS
21
ROM
PC H
PS
CNTR 1
FUNCTIONAL BLOCK DIAGRAM
RAM
INT0–
23
Fig. 2 Functional block diagram
2
23
VREF
AV SS
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3850 group as follows:
Packages
42P4B..........................................42-pin shrink plastic molded DIP 42P2R-A ............................................ 42-pin plastic molded SSOP 42S1B-A ................... 42-pin shrink ceramic DIP(EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions.
Memory Size
ROM/PROM size ................................................... 8K to 24K bytes RAM size .............................................................. 512 to 640 bytes
Memory Expansion Plan
Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped the development.
Fig. 4 Memory expansion plan Currently planning products are listed below. Table 2 Support products Product name M38503M2-XXXSP M38503M2-XXXFP M38503M4-XXXSP M38503E4-XXXSP M38503E4SP M38503E4SS M38503M4-XXXFP M38503E4-XXXFP M38503E4FP M38504M6-XXXSP M38504E6-XXXSP M38504E6SP M38504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP (P) ROM size (bytes) ROM size for User in ( ) 8192 (8062) RAM size (bytes) 512 Package Mask ROM version Mask ROM version One Time PROM version One Time PROM version gs02E 6 Remarks As of August 1998
42P2R-A 42P4B
5
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3850 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
6
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
000016 004016 010016
16
FF0016 FFDC16
FFFE16 FFFF16
Fig. 6 Memory map diagram
7
0100
8.37.703Tm68 8.37.70368646T557.70409.0 8.37.704565.6T557.704915( 8.37.7053248 8.37.705731 6T557.7061440 8.348458 1.0203fdj0 00 8.34801 331.08603 217705199 027.10986 j7.507 0 0 5.901 353.56 183150 5.3T/286 515 j7.E 00 8.34801 331.08603 217709m(/286 515 j7.507 0 0 5.901 353.56 183150 5.3T/275.521(00)TjD 00 8.34801 331.08603 21782 T2/275.521(00)Tj507 0 0 5.901 353.56 183150 5.3T/264.7(BT/)TjC 00 8.34801 331.08603 21782 T2/264.7(BT/)Tj507 0 0 5.901 353.56 183150 5.3T/22.1932E)Tj5.B 00 8.34801 331.08603 217709m(/22.1932E)Tj5.507 0 0 5.901 353.56 183150 5.3T/243.137E)Tj5.A 00 8.34801 331.08603 217709m(/243.137E)Tj5.507 0 0 5.901 353.56 183150 5.3T/232 5430
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 7 Memory map of special function register (SFR)
8
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Table 3 I/O port function Pin Name Input/Output I/O Structure Non-Port Function Related SFRs Ref.No.
9
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0, P1
C
P-channel output disable bit
Serial I/O enable bit
Fig. 8 Port block diagram (1)
10
register Direction Port XC switch bit (7) Port P2
ExternalP21 Serial I/O input(6) Port (5) (4) (3) Data busclock Oscillator enable bit P25 (2) Port P20 input P24 P2
Port X bit switch
Serial I/O clock
Serial clock output
32P ,2
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Direction registerData busPort latch
11
Direction PWM Pulse output mode Data bus CNTR1 (10) Port P40enable Interruptinterrupt Port A-D converter input Direction input input bitlatch
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software.
sNotes
When the active edge of an external interrupt (INT0–INT3, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: 1. Disable the interrupt 2. Change the interrupt edge selection register (the timer XY mode register for CNTR0 and CNTR1) 3. Clear the interrupt request bit to “0” 4. Accept the interrupt.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
12
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 4 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 Reserved INT1 INT2 INT3 Reserved Timer X Timer Y Timer 1 Timer 2 Serial I/O reception Serial I/O Transmission CNTR 0 CNTR 1 A-D converter BRK instruction Priority 1 2 3 4 5 6 7 8 9 10 11 12 Vector Addresses (Note 1) High Low FFFD 16 FFFC 16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE 16 FFEC 16 FFEA 16 FFE816 FFE616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input Reserved At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input Reserved At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O data reception At completion of serial I/O transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion At BRK instruction execution Non-maskable software interrupt Valid when serial I/O is selected Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Remarks Non-maskable External interrupt (active edge selectable)
STP release timer underflow
13 14 15 16 17
FFE516
FFE416
FFE316 FFE116 FFDF 16 FFDD16
FFE216 FFE016 FFDE 16 FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
13
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 10 Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit INT2 active edge selection bit INT3 active edge selection bit Reserved(Do not write “1” to this bit) Not used (returns “0” when read)
0 : Falling edge active 1 : Rising edge active
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O reception interrupt request bit Serial I/O transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit Reserved(Do not write "1" to this bit) INT1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Reserved(Do not write "1" to this bit) Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O reception interrupt enable bit Serial I/O transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 11 Structure of interrupt-related registers (1)
14
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3850 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “0016 ”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source selection bit.
b7
b0
Timer XY mode register (TM : address 002316)
Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “0016 ”, the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR 1 ) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40 ) direction register to output mode.
Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode
Timer Y count stop bit 0: Count start 1: Count stop
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 o r CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR 1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR 1) active edge selection bit is “1”, the timer counts it while the CNTR 0 (or CNTR1 ) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.
Fig. 12 Structure of timer XY mode register
b7
b0
Timer count source selection register (TCSS : address 002816)
Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN)
Not used (returns “0” when read)
sNote
When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer.
Fig. 13 Structure of timer count source selection register
15
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P27/CNTR0
77 bit
“1” Q Q
“0”
Fig. 14 Block diagram of timer X, timer Y, timer 1, and timer 2
16
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Fig. 15 Block diagram of clock synchronous serial I/O
Fig. 16 Operation of clock synchronous serial I/O function
17
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit (b6) of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Fig.17 Block diagram of UART serial I/O
18
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TBE=0 TSC=0 TBE=1
TBE=0
RBF=0 RBF=1 RBF=1
ST
D0
D1
SP
ST
D0
D1
SP
Fig. 18 Operation of UART serial I/O function
[Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”.
Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P2 5/T XD pin.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
19
ST
Transmit or42.ceive clock SP D1 D0
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O status register (SIOSTS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read)
b7
b0
Serial I/O control register (SIOCON : address 001A 16) BRG count source selection bit (CSS) 0: f(X IN) 1: f(X IN)/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P2 7 pin operates as ordinary I/O pin 1: P2 7 pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P2 4 to P2 7 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P2 4 to P2 7 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read)
Fig. 19 Structure of serial I/O control registers
20
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 3850 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
Data Setting
The PWM output pin also functions as port P4 4. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ! (n+1) / f(XIN) = 31.875 ! (n+1) µs (when f(X IN) = 8 MHz) Output pulse “H” term = PWM period ! m / 255 = 0.125 ! (n+1) ! m µs (when f(XIN) = 8 MHz)
31.875 ! m ! (n+1) µs 255 PWM output T = [31.875 ! (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X IN) = 8 MHz)
Fig. 20 Timing of PWM period
Data bus
PWM prescaler pre-latch
PWM register pre-latch
Transfer control circuit
PWM prescaler latch Count source selection bit XIN 1/2 “0” “1” PWM prescaler
PWM register latch
Port P44 PWM register
Port P44 latch
PWM enable bit
Fig. 21 Block diagram of PWM function
21
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register (PWMCON : address 001D 16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return “0” when read)
Fig. 22 Structure of PWM control register
A PWM output T PWM register write signal
B
C
B= C T2 T
T (Changes “H” term from “A” to “B”.)
T2
PWM prescaler write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 23 PWM output timing when PWM register or PWM prescaler is changed
sNote
The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows:
n+1 2 • f(XIN ) n+1 f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
22
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616
The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion
b7
b0
AD control register (ADCON : address 0034 16) Analog input pin selection bits
b2 b1 b0
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion.
0 0 0 0 1
0 0 1 1 0
0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4
Not used (returns “0” when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Fig. 24 Structure of AD control register
Channel Selector
The channel selector selects one of ports P30/AN0 to P34 /AN4 and inputs the voltage to the comparator.
10-bit reading (Read address 003616 before 003516)
b7
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
(Address 003616)
b7
b0 b9 b8 b0
(Address 003516) b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 0036 16 become “0” at reading.
8-bit reading (Read only address 003516)
b7 b0
(Address 003516) b9 b8 b7 b6 b5 b4 b3 b2
Fig. 25 Structure of A-D conversion registers
b7
b0
A-D control circuit
A-D interrupt request
Channel selector
Comparator
A-D conversion low-order register
Resistor ladder
VREF AV SS
23
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
24
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an "L" level for 2 µ s or more. Then the RESET pin is returned to an "H" level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V.
XIN
φ
RESET
OUT
Address
Data
SYNC
XIN: 8 to 13 clock cycles
Fig. 30 Reset sequence
• L
MITSUBISHI MICROCOMPUTERS
L
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Poweron
RESET
VCC
Power source voltage 0V Reset input voltage 0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
IN
Notes)=2
Power source voltage detection circuit
Fig. 29 Reset circuit example
25
?
,
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P4 direction register (P4D) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) PWM control register (PWMCON) 000116 000316 000516 000716 000916 0016 0016 0016 0016 0016
001916 1 0 0 0 0 0 0 0 001A16 0016
001B16 1 1 1 0 0 0 0 0 001D16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002C16 002D16 002E16 002F16 003016 0016 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016 Not fixed Not fixed Not fixed Not fixed Not fixed
(10) Prescaler 12 (PRE12) (11) Timer 1 (T1) (12) Timer 2 (T2) (13) Timer XY mode register (TM) (14) Prescaler X (PREX) (15) Timer X (TX) (16) Prescaler Y (PREY) (17) Timer Y (TY) (18) Timer count source select register (19) Reserved (20) Reserved (21) Reserved (22) Reserved (23) Reserved (24) AD control register (ADCON) (25) MISRG (26) Watchdog timer control register (WDTCON) (27) Interrupt edge selection register (INTEDGE) (28) CPU mode register (CPUM) (29) Interrupt request register 1 (IREQ1) (30) Interrupt request register 2 (IREQ2) (31) Interrupt control register 1 (ICON1) (32) Interrupt control register 2 (ICON2) (33) Processor status register (34) Program counter Note : X indicates Not fixed .
003416 0 0 0 1 0 0 0 0 003816 0016
003916 0 0 1 1 1 1 1 1 003A16 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0016 0016 0016 0016
(PS) X X X X X 1 X X (PCH) (PCL)
FFFD16 contents FFFC16 contents
Fig. 31 Internal status at reset
26
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3850 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and X COUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and X COUT pins function as I/O ports.
be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction.
Frequency Control (1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN .
sNote
When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN .
sNote
If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN).
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock XCIN -XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
CCIN CIN COUT
Fig. 32 Ceramic resonator circuit
Oscillation Control (1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF 16” and timer 1 is set to “01 16.” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either XIN or X CIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT Open
External oscillation circuit CCIN Vcc Vss
Fig. 33 External clock input circuit
27
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
IN oscil ation automati-
b7
b0
MISRG (MISRG : address 0038 16) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “01 16 ” to Timer 1, “FF 16 ” to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return “0” when read)
Fig. 34 Structure of MISRG
XCIN
XCOUT
XIN
XOUT
1/2
1/4
Timing φ (internal clock)
Main clock stop bit
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Fig. 35 System clock generating circuit block diagram (Single-chip mode)
28
X Middle-speed mode automatic switch set bitByXCswitch bit.1 Reset FF160116 Main or Port clock division ratio setting the middle-speed mode automatic switch set bit to .1
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (f(φ)=1 MHz) CM 7=0 CM 6=1 CM 5=0(8 MHz oscillating) CM 4=0(32 kHz stopped)
CM 6 “1”←→“0”
High-speed mode (f(φ)=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped)
→ CM ”← 0” “1 M6 →“ C ”← “1
4
“0
”
C “0 M4 ”← C “1 M6 →“ 1” ”← → “0 ”
CM 4 “1”←→“0”
Middle-speed mode (f(φ)=1 MHz) CM 7=0 CM 6=1 CM 5=0(8 MHz oscillating) CM 4=1(32 kHz oscillating)
CM 6 “1”←→“0”
High-speed mode (f(φ)=4 MHz) CM 7=0 CM 6=0 CM 5=0(8 MHz oscillating) CM 4=1(32 kHz oscillating)
→
”
“0
”
Low-speed mode (f(φ)=16 kHz) CM7=1 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
CM 7 “1”←→“0”
“1
”←
C “0 M7 CM ”←→
6
“1
CM 4 “1”←→“0”
b7
b4 CPU mode register (CPUM : address 003B 16)
Low-speed mode (f(φ)=16 kHz) CM7=1 CM6=0 CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating)
CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : X CIN-XCOUT oscillating function CM5 : Main clock (X IN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 16 ms occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock.
Fig. 36 State transitions of system clock
CM 5 “1”←→“0”
29
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency in high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1.” Serial I/O continues to output the final bit from the TXD pin after transmission is completed. When an external clock is used as synchronous clock in serial I/O, write transmission data to the transmit buffer register while the transfer clock is “H.”
30
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 5 Programming adapter
DATA R E QU I R E D F O R RO M W R I T I N G ORDERS
The following are necessary when ordering a ROM writing: 1.ROM Writing Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies)
Package 42P2R-A 42P4B
Name of Programming Adapter PCA4738F-42A PCA4738S-42A
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 49 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours.
Fig. 37 Programming and testing of One Time PROM version
31
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 6 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10 –P17, P20, P21, P24–P27, P30 –P34, P40–P44 , VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10 –P17, P20, P21, P24–P27, P30 –P34, P40–P44 , XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to VCC +0.3 –0.3 to 5.8 300 –20 to 85 –40 to 125 Unit V V V V V V V mW °C °C
Ta = 25 °C
Table 7 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL Σ I OH(peak) Σ I OH(peak) Σ I OL(peak) Σ I OL(peak) Σ I OL(peak) Σ I OH(avg) Σ I OH(avg) Σ I OL(avg) Σ I OL(avg) Σ I OL(avg) Parameter Power source voltage (At 8 MHz) Power source voltage (At 4 MHz) Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage AN 0–AN4 “H” input voltage “H” input voltage “L” input voltage “L” input voltage “L” input voltage “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current P00–P07, P10 –P17, P20–P27 , P30–P34, P40 –P44 RESET, XIN, CNV SS P00–P07, P10 –P17, P20–P27 , P30–P34, P40 –P44 RESET, CNV SS XIN P00–P07 , P10–P17, P3 0–P34 (Note) P20, P2 1, P24–P27, P4 0–P44 (Note) P00–P07 , P10–P12, P3 0–P34 (Note) P13–P17 (Note) P20 –P27 ,P40 –P44 (Note) P00–P07 , P10–P17, P3 0–P34 (Note) P20, P2 1, P24–P27, P4 0–P44 (Note) P00–P07 , P10–P12, P3 0–P34 (Note) P13–P17 (Note) P20 –P27 ,P40 –P44 (Note) Min. 4.0 2.7 2.0 0 AVSS 0.8VCC 0.8VCC 0 0 0 VCC VCC VCC 0.2V CC 0.2V CC 0.16VCC –80 –80 80 80 80 –40 –40 40 40 40 Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
32
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol I OH(peak) I OL(peak) I OL(peak) I OH(avg) I OL(avg) I OL(avg) f(XIN ) f(XIN ) “H” peak output current Parameter P00 –P07, P10–P17 , P20, P21, P2 4–P27, P30–P34 , P40 –P44 (Note 1) “L” peak output current P00 –P07, P10–P12, P2 0–P27, P30 –P34, P40–P44 (Note 1) “L” peak output current P13 –P17 (Note 1) “H” average output current P00 –P07, P10–P17 , P20, P21, P2 4–P27, P30–P34 , P40 –P44 (Note 2) “L” average output current P00 –P07, P10–P12, P2 0–P27, P30 –P34, P40–P44 (Note 2) “L” peak output current P13 –P17 (Note 2) Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Min. Limits Typ. Max. –10 10 20 –5 5 15 8 4 Unit mA mA mA mA mA mA MHz kHz
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current I OL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%.
33
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 Electrical characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter “H” output voltage P00–P07 , P10–P17, P20 , P21, P24–P27 , P30–P34, P40–P44 (Note) “L” output voltage P00–P07 , P10–P12, P20–P27 P30–P34, P4 0–P44 “L” output voltage P13–P17 Test conditions I OH = –10 mA VCC = 4.0–5.5 V I OH = –1.0 mA VCC = 2.7–5.5 V I OL = 10 mA VCC = 4.0–5.5 V I OL = 1.0 mA VCC = 2.7–5.5 V I OL = 20 mA VCC = 4.0–5.5 V I OL = 10 mA VCC = 2.7–5.5 V Min. VCC–2.0 VCC–1.0 2.0 1.0 2.0 1.0 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped 4 –5.0 –5.0 –4 2.0 5.5 5.0 5.0 Typ. Max. Unit V V V V V V V V V µA µA µA µA µA µA V
VOH
VOL
VOL
VT+–VT– VT+–VT– VT+–VT– I IH I IH I IH I IL I IL I IL VRAM
Hysteresis CNTR0, CNTR 1, INT 0–INT3 Hysteresis RxD, SCLK Hysteresis RESET “H” input current P00–P07 , P10–P17, P20 , P21, P24–P27 , P30–P34, P40–P44 “H” input current RESET, CNV SS “H” input current XIN “L” input current P00–P07 , P10–P17, P20–P27 P30–P34, P4 0–P44 “L” input current RESET,CNVSS “L” input current XIN RAM hold voltage
Note: P25 is measured when the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
34
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 10 Electrical characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Limits Parameter Test conditions High-speed mode f(XIN ) = 8 MHz f(XCIN ) = 32.768 kHz Output transistors “off” High-speed mode f(XIN ) = 8 MHz (in WIT state) f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN ) = stopped f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN ) = 32.768 kHz Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN ) = stopped f(XCIN ) = 32.768 kHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN ) = 8 MHz f(XCIN ) = stopped Output transistors “off” Middle-speed mode f(XIN ) = 8 MHz (in WIT state) f(XCIN ) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN ) = 8 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Min. Typ. 6.8 Max. 13 Unit
mA
1.6
mA
60
200
µA
20
40
µA
I CC
Power source current
20
55
µA
5.0
10.0
µA
4.0
7.0
mA
1.5
mA
800 0.1 1.0 10
µA µA µA
35
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 8 MHz, unless otherwise noted) Symbol – – t CONV RLADDER I VREF I I(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current Test conditions Limits Min. Typ. Max. 10 ±4 61 200 5.0 Unit bit LSB tc(φ) kΩ µA µA
VREF = 5.0 V
50
35 150 0.5
36
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 12 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t W(RESET) t C(X IN) t WH (XIN) t WL (XIN) t C(CNTR) t WH (CNTR) t WL(CNTR) t C(S CLK) t WH (SCLK) t WL (SCLK) t su(Rx D-SCLK) t h(S CLK-Rx D) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 , INT0–INT 3 input “H” pulse width CNTR0, CNTR1 , INT0–INT 3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input setup time Serial I/O input hold time Min. 2 125 50 50 200 80 80 800 370 370 220 100 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN ) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN ) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 13 Timing requirements (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t W(RESET) t C(X IN) t WH (XIN) t WL (XIN) t C(CNTR) t WH (CNTR) t WL(CNTR) t C(S CLK) t WH (SCLK) t WL (SCLK) t su(Rx D-SCLK) t h(S CLK-Rx D) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 , INT0–INT 3 input “H” pulse width CNTR0, CNTR1 , INT0–INT 3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input setup time Serial I/O input hold time Limits Min. 2 250 100 100 500 230 230 2000 950 950 400 200 Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN ) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN ) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
37
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t WH (S CLK) t WL (SCLK) t d (SCLK -TXD) t v (S CLK-TXD) t r (SCLK ) t f (S CLK) t r (CMOS) t f (CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. t C(SCLK )/2–30 t C(SCLK )/2–30 140 –30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns
10 10
Notes 1: For t WH(SCLK), tWL (SCLK), when the P51/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: The XOUT pin is excluded.
Table 15 Switching characteristics 2 (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol t WH (S CLK) t WL (SCLK ) t d (SCLK -TXD) t v (S CLK-TXD) t r (SCLK ) t f (S CLK) t r (CMOS) t f (CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. Typ. tC (SCLK)/2–50 tC (SCLK)/2–50 –30 50 50 50 50 Max. Unit ns ns ns ns ns ns ns ns
350
20 20
Notes 1: For t WH(SCLK), tWL (SCLK), when the P51/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: The XOUT pin is excluded.
38
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Measurement output pin Measurement output pin 100pF
1kΩ
100pF CMOS output
N-channel open-drain output
Fig. 38 Circuit for measuring output switching characteristics (1)
Fig. 39 Circuit for measuring output switching characteristics (2)
39
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC
CNTR0, CNTR1
0.8VCC
tWH(INT)
tWL(INT) 0.2VCC
INT0 to INT3
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tC(SCLK) tf tWL(S CLK) 0.2VCC tr 0.8VCC tWH(SCLK)
SCLK
tsu(RxD-SCLK)
th(SCLK-RxD)
RXD
td(SCLK-TXD)
0.8VCC 0.2VCC tv(SCLK-TXD)
TX D
Fig. 40 Timing diagram
40
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH53-11B
Mask ROM number
Note : Please fill in all items marked g.
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
g Customer
)
Date issued
Date:
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM EPROM type (indicate the type used)
Issuance signature
Company name
TEL (
Submitted by
Supervisor
(hexadecimal notation)
27256
EPROM address 000016 Product name 000F16 001016 607F16 608016 7FFD16 7FFE16 7FFF16
ASCII code : ‘M38503M2-’
27512
EPROM address 000016 Product name 000F16 001016 E07F16 E08016 FFFD16 FFFE16 FFFF16
ASCII code : ‘M38503M2-’
In the address space of the microcomputer, the internal ROM area is from address 608016 to FFFD16 . The reset vector is stored in addresses FFFC16 and FFFD16.
data ROM (8K-130) bytes
data ROM (8K-130) bytes
(1) Set the data in the unused area (the shaded area of the diagram) to “FF16 ”. (2) The ASCII codes of the product name “M38503M2–” must be entered in addresses 0000 16 to 0008 16. And set the data “FF 16” in addresses 0009 16 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716 (1/2)
‘M’ = 4D16 ‘3’ = 33 16 ‘8’ = 38 16 ‘5’ = 35 16 ‘0’ = 30 16 ‘3’ = 33 16 ‘M’ = 4D16 ‘2’ = 32 16
Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F 16
‘–’ = 2D16 FF 16 FF 16 FF 16 FF 16 FF 16 FF 16 FF 16
41
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH53-11B
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 0000 16 to 000816 of EPROM. EPROM type The pseudo-command 27256 *= $8000 .BYTE ‘M38503M2–’ 27512 *= $0000 .BYTE ‘M38503M2–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M38503M2-XXXSP, 42P2R-A for M38503M2-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz
(2) Which function will you use the pins P21 /XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ? Ports P21 and P20 function g 4. Comments XCIN and XCOUT function (external resonator)
(2/2)
42
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-40A
Mask ROM number
Note : Please fill in all items marked g.
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
g Customer
)
Date issued
Date:
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
Issuance signature
Company name
TEL (
Submitted by
Supervisor
(hexadecimal notation)
In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16 . The reset vector is stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of the diagram) to “FF16 ”. (2) The ASCII codes of the product name “M38503M4–” must be entered in addresses 000016 to 0008 16. And set the data “FF16” in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
‘M’ = 4D16 ‘3’ = 33 16 ‘8’ = 38 16 ‘5’ = 35 16 ‘0’ = 30 16 ‘3’ = 33 16 ‘M’ = 4D16 ‘4’ = 34 16
Address 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F 16
43
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-40A
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 0008 16 of EPROM. EPROM type The pseudo-command 27256 *= $8000 .BYTE ‘M38503M4–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
(2/2)
44
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-41A
ROM number
Note : Please fill in all items marked g.
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
g Customer
)
Date issued
Date:
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Issuance signature
Company name
TEL (
Submitted by
Supervisor
45
46
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MARK SPECIFICATION FORM
47
MITSUBISHI MICROCOMPUTERS
3850 Group
48
H C C U MH C M M S U
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMO S MICRO CO MP UTER
SHRId (r)Tj 0.3431 185.5 713 Tm (S).50 0.67 0 Td (H)Tj 0.725>DPf BMC /PgfForm 565956595659565956595659565956595659
En ter th e catalo n um b er o th e m i o m puter f r w h i th i m ar specii o i i ten ded. (If y u do n o k n o th e R O M co n um b er g f cr co o ch s k fcati n s n o t w de , en ter XXX i i place.) n ts Th e catalo n um b er o th e m i o m puter g f cr co
A. Stan dar Mi d tsub i iMar sh k Custo er specii par n um b er w i b e prn ted to m fed t ll i geth er w i th e RO M co n um b er o th e to li e. th de n pn En ter th e desied part n um b er lef ali ed i th e b o b elo . (up to10 ch ar r t gn n x w acter s)
49
057001 0.567 Td28 0567Tj ET 1000 0 Td3031 0.567 sC EMC 1401 Td (0)Tj Td (57001 0.567 e0 )Tj 1 0 Td28795659565956595659 556595659E 1 1]>>DP /CharFormat BDC /Pgf BMC BT /T1_0 114.47661 331.00391 00 100 ]>>DP /CharFormat
