✽This data sheet describes Spec. H and Spec. A of 3850 Group. The header of each page shows which specification is explained in the page. The page explaining about both specifications shows the header of “Spec. H/A”.
3850 Group (Spec.H/A)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3850 Group (Spec.H)
REJ03B0036-0301Z Rev.3.01 2003.06.20
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec. H) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.
FEATURES
q Basic machine-language instructions ...................................... 71 q Minimum instruction execution time .................................. 0.5 µs (at 8 MHz oscillation frequency) q Memory size ROM ................................................................... 8K to 32K bytes RAM ................................................................. 512 to 1024 bytes q Programmable input/output ports ............................................ 34 q Interrupts ................................................. 15 sources, 14 vectors q Timers ............................................................................. 8-bit ✕ 4 q Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized) q Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized) q PWM ............................................................................... 8-bit ✕ 1 q A-D converter ............................................... 10-bit ✕ 5 channels q Watchdog timer ............................................................ 16-bit ✕ 1
q Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) q Power source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) q Power dissipation In high-speed mode .......................................................... 34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode Except M38507F8FP/SP ................................................... 60 µW M38507F8FP/SP ............................................................. 450 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) q Operating temperature range .................................... –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/TxD P24/RxD P23 P22 CNVSS VPP P21/XCIN P20/XCOUT RESET XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7)
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38503MXH-XXXFP/SP pin configuration (spec. H)
M38503MXH-XXXFP/SP
: Flash memory version
Rev.3.01
2003.06.20
page 1 of 98
1
3850 Group (Spec.A)
DESCRIPTION
The 3850 group (spec. A) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec. A) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.
FEATURES
q Basic machine-language instructions ...................................... 71 q Minimum instruction execution time ................................ 0.32 µs (at 12.5 MHz oscillation frequency) q Memory size ROM ................................................................... 8K to 16K bytes RAM .............................................................................. 512 bytes q Programmable input/output ports ............................................ 34 q On-chip software pull-up resistor q Interrupts ................................................. 15 sources, 14 vectors q Timers ............................................................................. 8-bit ✕ 4 q Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized) q Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized) q PWM ............................................................................... 8-bit ✕ 1 q A-D converter ............................................... 10-bit ✕ 9 channels q Watchdog timer ............................................................ 16-bit ✕ 1
q Clock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) q Power source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 12.5 MHz oscillation frequency) In high-speed mode .................................................. 2.7 to 5.5 V (at 6 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 12.5 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) q Power dissipation In high-speed mode Except M38507F8FP/SP ................................................ 32.5mW M38507F8FP/SP ............................................................ 37.5mW (at 12.5 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode Except M38507F8FP/SP ................................................... 60 µW M38507F8FP/SP ............................................................. 450 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) q Operating temperature range .................................... –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/TxD P24/RxD P23 P22 CNVSS VPP P21/XCIN P20/XCOUT RESET XIN XOUT VSS P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN5 P05/AN6 P06/AN7 P07/AN8 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 2 M38503MXA-XXXFP/SP pin configuration (spec. A)
M38503MXA-XXXFP/SP
: Flash memory version
Rev.3.01
2003.06.20
page 2 of 98
FUNCTIONAL BLOCK
Rev.3.01
Reset input VS S VC C RESET
18 15 1 21
FUNCTIONAL BLOCK DIAGRAM
3850 Group (Spec.H)
Fig. 3 Functional block diagram (spec. H)
CNVSS
2003.06.20
CPU
Main-clock input XIN
Main-clock output XOUT
19
20
page 3 of 98
ROM
X
Prescaler 12(8)
Sub-clock Sub-clock input output XCIN XCOUT
Clock generating circuit A Timer 1( 8 ) Timer 2( 8 ) Timer X( 8 ) Timer Y( 8 )
RAM
Y
Prescaler X(8)
S PC H PS
CNTR1
PC L
CNTR0
Prescaler Y(8)
Watchdog timer
Reset
A-D converter (10)
P WM (8)
SI/O1(8)
SI/O2(8)
XCOUT INT0– INT3 XCIN
P4(5) P3(5)
P2(8)
P1(8)
P0(8)
23 38 39 40 41 42
45678
9 10 11 12 13 14 16 17
22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37
I/O port P4 I/O port P3
I/O port P2
I/O port P1
I/O port P0
VREF
AVSS
Rev.3.01
Reset input VSS VCC RESET
18 15 1 21
FUNCTIONAL BLOCK DIAGRAM
Main-clock input XIN CNVSS
Main-clock output XOUT
3850 Group (Spec.A)
Fig. 4 Functional block diagram (spec. A)
2003.06.20
CPU
19
20
Sub-clock Sub-clock input output XCIN XCOUT
Clock generating circuit
page 4 of 98
ROM
X
Prescaler 12(8)
RAM
Timer 2( 8 ) Timer X( 8 ) Timer Y( 8 ) Y
Prescaler X(8)
A
Timer 1( 8 )
S PC H PS
CNTR1
PC L
Prescaler Y(8)
CNTR0
Watchdog timer
Reset
A-D converter (10)
PWM (8)
SI/O1(8)
SI/O2(8)
XCOUT INT0– INT3 XCIN
P4(5)
P3(5)
P2(8)
P1(8)
P0(8)
23 38 39 40 41 42
45 678
9 10 11 12 13 1416 17
22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37
I/O port P4 I/O port P3
I/O port P2
I/O port P1
I/O port P0
VREF
AVSS
3850 Group (Spec.H)
Table 1 Pin description (spec. H) Pin VCC, VSS CNVSS RESET XIN XOUT P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10–P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK1 P27/CNTR0/ SRDY1 P30/AN0– P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 I/O port P4 P43/INT2/SCMP2 P44/INT3/PWM I/O port P3 •8-bit CMOS I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. •8-bit CMOS I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. • Interrupt input pin • SCMP2 output pin • Interrupt input pin • PWM output pin • Timer Y function pin • Interrupt input pins • Serial I/O1 function pin/ Timer X function pin • A-D converter input pin I/O port P2 Name Power source CNVSS input Reset input Clock input Clock output Functions •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. I/O port P1 •P10 to P17 (8 bits) are enabled to output large current for LED drive. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •P20, P21, P24 to P27: CMOS3-state output structure. •P22, P23: N-channel open-drain structure. • Serial I/O1 function pin • Sub-clock generating circuit I/O pins (connect a resonator) • Serial I/O2 function pin
Function except a port function
I/O port P0
Rev.3.01
2003.06.20
page 5 of 98
3850 Group (Spec.A)
Table 2 Pin description (spec. A) Pin VCC, VSS CNVSS RESET XIN XOUT P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN5–P07/AN8 P10–P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK1 P27/CNTR0/ SRDY1 P30/AN0– P34/AN4 I/O port P2 Name Power source CNVSS input Reset input Clock input Clock output Functions •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •8-bit CMOS I/O port. I/O port P0 •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a byte unit. I/O port P1 •P10 to P17 (8 bits) are enabled to output large current for LED drive. •8-bit CMOS I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •P20, P21, P24 to P27: CMOS3-state output structure. •P22, P23: N-channel open-drain structure. •Pull-up control of P2 0, P21, P24 –P27 is enabled in a byte unit. •8-bit CMOS I/O port with the same function as port P0. I/O port P3 •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM I/O port P4 •8-bit CMOS I/O port with the same function as port P0. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled in a bit unit. • Interrupt input pin • SCMP2 output pin • Interrupt input pin • PWM output pin • Timer Y function pin • Interrupt input pins • Serial I/O1 function pin • Sub-clock generating circuit I/O pins (connect a resonator) • Serial I/O2 function pin
Function except a port function
• A-D converter input pin
• Serial I/O1 function pin/ Timer X function pin • A-D converter input pin
Rev.3.01
2003.06.20
page 6 of 98
3850 Group (Spec.H/A)
PART NUMBERING
Product name
M3850 3
M
4
A– XXX
SP
Package type SP : 42P4B FP : 42P2R-A/E SS : 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. – : standard Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. H–: Partial specification changed version A–: High-speed version ROM/PROM/Flash memory size 9 : 36864 bytes 1 : 4096 bytes A: 40960 bytes 2 : 8192 bytes B: 45056 bytes 3 : 12288 bytes C: 49152 bytes 4 : 16384 bytes D: 53248 bytes 5 : 20480 bytes E: 57344 bytes 6 : 24576 bytes F : 61440 bytes 7 : 28672 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version E : EPROM or One Time PROM version F : Flash memory version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes
5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 5 Part numbering
Rev.3.01
2003.06.20
page 7 of 98
3850 Group (Spec.H/A)
GROUP EXPANSION
Renesas Technology plans to expand the 3850 group (spec. H/A) as follows.
Packages
42P4B ......................................... 42-pin shrink plastic-molded DIP 42P2R-A/E ........................................... 42-pin plastic-molded SOP 42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and flash memory versions.
Memory Size
Flash memory size ......................................................... 32 K bytes Mask ROM size ................................... 8 K to 32 K bytes (spec. H) 8 K to 16 K bytes (spec. A) RAM size ............................................... 512 to 1 K bytes (spec. H) 512 bytes (spec. A)
Memory Expansion Plan
ROM size (bytes) ROM exteranal 32K 28K
Mass production Mass production
M38507M8/F8
24K 20K
M38504M6/E6
Mass production
16K 12K
M38503M4H M38503M4A
Mass production Mass production
8K
M38503M2H M38503M2A
Mass production
384
512
640
768
896 1024 1152 RAM size (bytes)
1280
1408
1536
2048
Fig. 6 Memory expansion plan
Rev.3.01
2003.06.20
page 8 of 98
3850 Group (Spec.H/A)
Currently planning products are listed below. Table 3 Support products (spec. H) Product name M38503M2H-XXXSP M38503M2H-XXXFP M38503M4H-XXXSP M38503M4H-XXXFP M38504M6-XXXSP M38504E6-XXXSP M38504E6SP M38504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP M38507M8-XXXSP M38507M8-XXXFP M38507F8SP M38507F8FP ROM size (bytes) ROM size for User in ( ) 8192 (8062) 16384 (16254) RAM size (bytes) 512 512 Package 42P4B 42P2R-A/E 42P4B 42P2R-A/E 424P4B 24576 (24446) 640 42S1B-A 42P2R-A/E 42P4B 42P2R-A/E 42P4B 42P2R-A/E Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version Mask ROM version Flash memory version Flash memory version
32768 (32638)
1024
Table 4 Support products (spec. A) Product name M38503M2A-XXXSP M38503M2A-XXXFP M38503M4A-XXXSP M38503M4A-XXXFP M38507F8SP M38507F8FP ROM size (bytes) ROM size for User in ( ) 8192 (8062) 16384 (16254) 32768 RAM size (bytes) 512 512 1024 Package 42P4B 42P2R-A/E 42P4B 42P2R-A/E 42P4B 42P2R-A/E Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Flash memory version Flash memory version
Table 5 Differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A) 3850 group (spec. H) 3850 group (spec. A) 3850 group (standard) 2: Serial I/O1 (UART or Clock-synchronized) 2: Serial I/O1 (UART or Clock-synchronized) Serial I/O 1: Serial I/O Serial I/O2 (Clock-synchronized) Serial I/O2 (Clock-synchronized) (UART or Clock-synchronized) Serviceable in low-speed mode Serviceable in low-speed mode A-D converter Unserviceable in low-speed mode Analog channel ............................. 5 Analog channel ................................ 5 Analog channel ................................ 9 8: P10–P17 8: P10–P17 Large current port 5: P13–P17 Software pull-up Not available resistor Maximum operating 8 MHz frequency
Not available Built-in (Port P0–P4)
8 MHz
12.5 MHz
Notes on differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A)
(1) The absolute maximum ratings of 3850 group (spec. H/A) is smaller than that of 3850 group (standard). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after reset.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins.
Rev.3.01
2003.06.20
page 9 of 98
3850 Group (Spec.H/A)
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H/A) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 8. Store registers other than those described in Figure 8 with program when the user needs them during interrupts or subroutine calls.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL
b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
NVTBD I ZC
Fig. 7 740 Family CPU register structure
Rev.3.01
2003.06.20
page 10 of 98
3850 Group (Spec.H/A)
On-going Routine
Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1
M (S) (S) M (S) (S) M (S) (S)
(PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push contents of processor status register on stack Push return address on stack
Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (S) + 1 M (S) (S) + 1
Interrupt Service Routine
Execute RTI (S) (PS) (S) (PCL) (S) (S) + 1 M (S) (S) + 1 M (S) (S) + 1
I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack
(PCH) M (S)
POP return address from stack
(PCH) M (S)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1” Interrupt disable flag is “0”
Fig. 8 Register push and pop at interrupt generation and subroutine call Table 6 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP
Rev.3.01
2003.06.20
page 11 of 98
3850 Group (Spec.H/A)
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “ 0 ” , arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 7 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag _ _ I flag SEI CLI D flag SED CLD B flag _ _ T flag SET CLT V flag _ CLV N flag _ _
Rev.3.01
2003.06.20
page 12 of 98
3850 Group (Spec.H/A)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16.
b7 1
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available
Fig. 9 Structure of CPU mode register
Rev.3.01
2003.06.20
page 13 of 98
3850 Group (Spec.H/A)
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size (bytes) Address XXXX16
000016 SFR area 004016 010016 Zero page
192 256 384 512 640 768 896 1024 1536 2048
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16
RAM
XXXX16 Not used 0FF016 0FFF16 SFR area (Note) Not used
ROM area
ROM size (bytes) Address YYYY16 Address ZZZZ16
YYYY16 Reserved ROM area
(128 bytes)
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ZZZZ16
ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page
Reserved ROM area
Note: Flash memory version only
Fig. 10 Memory map diagram
Rev.3.01
2003.06.20
page 14 of 98
3850 Group (Spec.H)
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS)
Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽
Reserved ✽ Reserved ✽ Reserved ✽ Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM)
003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 0FFE16 A-D control register (ADCON) A-D conversion low-order register (ADL) A-D conversion high-order register (ADH) Reserved ✽ MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Flash memory control register (FMCR)
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 11 Memory map of special function register (SFR) (spec. H)
Rev.3.01
2003.06.20
page 15 of 98
3850 Group (Spec.A)
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS)
Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽
Port P0, P1, P2 pull-up control register (PULL012) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM)
003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 0FFE16 A-D control register (ADCON) A-D conversion low-order register (ADL) A-D conversion high-order register (ADH) A-D input selection register (ADSEL) MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Flash memory control register (FMCR)
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 12 Memory map of special function register (SFR) (spec. A)
Rev.3.01
2003.06.20
page 16 of 98
3850 Group (Spec.H)
I/O PORTS
The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “ 0 ” i s written to the bit corresponding to a pin, that pin becomes an input pin. When “ 1 ” i s written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 8 I/O port function (spec. H) Pin P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10–P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK1 P27/CNTR0/SRDY1 P30/AN0– P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 Name Input/Output I/O Structure Non-Port Function Related SFRs Ref.No. (1) (2) (3) (4) (5) Sub-clock generating circuit CMOS compatible input level N-channel open-drain output Input/output, individual bits Serial I/O1 function I/O Serial I/O1 function I/O Timer X function I/O Port P3 CMOS compatible input level CMOS 3-state output A-D conversion input Timer Y function I/O External interrupt input External interrupt input SCMP2 output External interrupt input PWM output Serial I/O1 control register Serial I/O1 control register Timer XY mode register A-D control register Timer XY mode register Interrupt edge selection register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register PWM control register CPU mode register (6) (7) (8) (9) (10) (11) (12) (13) (14) (15)
Port P0 CMOS compatible input level CMOS 3-state output Port P1
Serial I/O2 function I/O
Serial I/O2 control register
Port P2
Port P4 P44/INT3/PWM
(16)
(17)
Rev.3.01
2003.06.20
page 17 of 98
3850 Group (Spec.A)
I/O PORTS
The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “ 0 ” i s written to the bit corresponding to a pin, that pin becomes an input pin. When “ 1 ” i s written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 9 I/O port function (spec. A) Pin P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN5–P07AN8 P10–P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK1 P27/CNTR0/SRDY1 P30/AN0– P34/AN4 P40/CNTR1 P41/INT0 P42/INT1 P43/INT2/SCMP2 Name Input/Output I/O Structure
By setting the port P0, P1, P2 pull-up control register (address 001216), the port P3 pull-up control register (address 001316), or the port P4 pull-up control register (address 001416), ports can control pull-up with a program. However, the contents of these registers do not affect ports programmed as the output ports.
Non-Port Function Serial I/O2 function I/O
Related SFRs
Port P0 CMOS compatible input level CMOS 3-state output Port P1
Serial I/O2 control register
Ref.No. (1) (2) (3) (4) (13) (5)
A-D conversion input
A-D control register A-D input selection register
Sub-clock generating circuit CMOS compatible input level N-channel open-drain output Input/output, individual bits Serial I/O1 function I/O Serial I/O1 function I/O Timer X function I/O Port P3 Port P4 (Note) CMOS compatible input level CMOS 3-state output A-D conversion input Timer Y function I/O External interrupt input External interrupt input SCMP2 output
CPU mode register
(6) (7) (8) (9) (10) (11) (12) (13) (14) (15)
Port P2
Serial I/O1 control register Serial I/O1 control register Timer XY mode register A-D control register A-D input selection register Timer XY mode register Interrupt edge selection register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register PWM control register
(16)
P44/INT3/PWM
External interrupt input PWM output
(17)
Note: W hen bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
Rev.3.01
2003.06.20
page 18 of 98
3850 Group (Spec.H)
(1) Port P00
Direction register
(2) Port P01
P01/SOUT2 P-channel output disable bit Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register Data bus Port latch
Data bus
Port latch
Serial I/O2 input Serial I/O2 output
(3) Port P02 (4) Port P03
P02/SCLK2 P-channel output disable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Data bus Port latch SRDY2 output enable bit Direction register
Port latch
Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input
(5) Ports P04-P07,P1
Direction register
(6) Port P20
Port XC switch bit Direction register Data bus Port latch
Data bus
Port latch
Oscillator Port P21
(7) Port P21
Port XC switch bit Direction register Direction register Port latch
Port XC switch bit
(8) Ports P22,P23
Data bus
Port latch Data bus
Sub-clock generating circuit input
Fig. 13 Port block diagram (1) (spec. H)
Rev.3.01
2003.06.20
page 19 of 98
3850 Group (Spec.H)
(9) Port P24
Serial I/O1 enable bit Receive enable bit Direction register Port latch
(10) Port P25
P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register
Data bus
Data bus
Port latch
Serial I/O1 input Serial I/O1 output
(11) Port P26
Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch
(12) Port P27
Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Port latch
Pulse output mode Serial I/O1 clock output External clock input Serial ready output Timer output CNTR0 interrupt input
(13) Ports P30-P34
(14) Port P40
Direction register Direction register
Data bus Data bus Port latch
Port latch
A-D converter input Analog input pin selection bit
Pulse output mode Timer output CNTR1 interrupt input
(16) Port P43 (15) Ports P41,P42
Direction register Serial I/O2 I/O comparison signal control bit Direction register
Data bus
Port latch
Data bus
Port latch
Interrupt input
Serial I/O2 I/O comparison signal output Interrupt input
Fig. 14 Port block diagram (2) (spec. H)
Rev.3.01
2003.06.20
page 20 of 98
3850 Group (Spec.H)
(17) Port P44
PWM output enable bit Direction register
Data bus
Port latch
PWM output Interrupt input
Fig. 15 Port block diagram (3) (spec. H)
Rev.3.01
2003.06.20
page 21 of 98
3850 Group (Spec.A)
(1) Port P00
Pull-up control bit
(2) Port P01
Pull-up control bit P01/SOUT2 P-channel output disable bit Direction register Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register
Data bus
Port latch Data bus Port latch
Serial I/O2 input Serial I/O2 output
(3) Port P02
Pull-up control bit P02/SCLK2 P-channel output disable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register
(4) Port P03
Pull-up control bit
SRDY2 output enable bit Direction register
Data bus Data bus Port latch
Port latch
Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input
(6) Port P20 (5) Port P1
Pull-up control bit Pull-up control bit Port XC switch bit Direction register Data bus Data bus Port latch Port latch
Direction register
Oscillator Port P21
(7) Port P21
Pull-up control bit Port XC switch bit Direction register Data bus Port latch Data bus Direction register
Port XC switch bit
(8) Ports P22,P23
Port latch
Sub-clock generating circuit input
Fig. 16 Port block diagram (1) (spec. A)
Rev.3.01
2003.06.20
page 22 of 98
3850 Group (Spec.A)
(9) Port P24
Pull-up control bit Serial I/O1 enable bit Receive enable bit Direction register Data bus
(10) Port P25
Pull-up control bit P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register
Port latch Data bus
Port latch
Serial I/O1 input Serial I/O1 output
(11) Port P26
Pull-up control bit Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch
(12) Port P27
Pull-up control bit Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Port latch
Pulse output mode Serial I/O1 clock output External clock input Serial ready output Timer output CNTR0 interrupt input
(13) Ports P04-P07, P30-P34
Pull-up control bit
(14) Port P40
Pull-up control bit
Direction register Data bus Data bus Port latch
Direction register
Port latch
A-D converter input Analog input pin selection bit Analog input port selection switch bit
Pulse output mode Timer output CNTR1 interrupt input
(15) Ports P41,P42
Pull-up control bit
(16) Port P43
Pull-up control bit Serial I/O2 I/O comparison signal control bit Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Interrupt input
Serial I/O2 I/O comparison signal output Interrupt input
Fig. 17 Port block diagram (2) (spec. A)
Rev.3.01
2003.06.20
page 23 of 98
3850 Group (Spec.A)
(17) Port P44
Pull-up control bit PWM output enable bit Direction register Data bus Port latch
PWM output Interrupt input
Fig. 18 Port block diagram (3) (spec. A)
Rev.3.01
2003.06.20
page 24 of 98
3850 Group (Spec.A)
b7
b0 Port P0, P1, P2 pull-up control register (PULL012: address 001216) P0 pull-up control bit 0: No pull-up 1: Pull-up P1 pull-up control bit Note: Pull-up control is valid when the corresponding bit 0: No pull-up of the port direction register is “0” (input). 1: Pull-up When that bit is “1” (output), pull-up cannot be set P2 pull-up control bit to the port of which pull-up is selected. 0: No pull-up 1: Pull-up Not used (return “0” when read)
b7
b0 Port P3 pull-up control register (PULL3: address 001316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up P32 pull-up control bit 0: No pull-up 1: Pull-up P33 pull-up control bit 0: No pull-up 1: Pull-up P34 pull-up control bit 0: No pull-up 1: Pull-up Fix these bits to “0”.
Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected.
Fig. 19 Structure of port registers (1) (spec. A)
Rev.3.01
2003.06.20
page 25 of 98
3850 Group (Spec.A)
b7
b0 Port P4 pull-up control register (PULL4: address 001416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up Fix these bits to “0”.
Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected.
Fig. 20 Structure of port registers (2) (spec. A)
Rev.3.01
2003.06.20
page 26 of 98
3850 Group (Spec.H/A)
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software.
sNotes
When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer XY mode register (address 2316) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt edge selection register (address 3A16) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the corresponding interrupt enable bit to “0” (disabled). (2) Set the interrupt edge select bit or the interrupt source select bit to “1”. (3) Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. (4) Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
Rev.3.01
2003.06.20
page 27 of 97
3850 Group (Spec.H/A)
Table 10 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Low 1 FFFD16 FFFC16 Reset (Note 2) INT0 Reserved INT1 INT2 INT3/ Serial I/O2 2 3 4 5 6 FFFB16 FFF916 FFF716 FFF516 FFF316 FFFA16 FFF816 FFF616 FFF416 FFF216
Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input Reserved At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT 3 i nput/ At completion of serial I/O2 data reception/transmission Reserved At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion At BRK instruction execution
Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Switch by Serial I/O2/INT3 interrupt source bit
Reserved Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception Serial I/O1 transmission CNTR0 CNTR1 A-D converter BRK instruction
7 8 9 10 11 12
FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716
FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616
STP release timer underflow
Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt
13 14 15 16 17
FFE516
FFE416
FFE316 FFE116 FFDF16 FFDD16
FFE216 FFE016 FFDE16 FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
Rev.3.01
2003.06.20
page 28 of 97
3850 Group (Spec.H/A)
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 21 Interrupt control
b7
b0
Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit 0 : Falling edge active 1 : Rising edge active INT2 active edge selection bit INT3 active edge selection bit Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns “0” when read)
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit Reserved(Do not write “1” to this bit.) INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit Reserved(Do not write “1” to this bit.) Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 22 Structure of interrupt-related registers
Rev.3.01
2003.06.20
page 29 of 97
3850 Group (Spec.H/A)
TIMERS
The 3850 group (spec. H/A) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “0016”, the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode.
b7
b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.
Fig. 23 Structure of timer XY mode register
b7
b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns “0” when read)
sNote
When switching the count source by the timer 12, X and Y count source bits, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. When timer X/timer Y underflow while executing the instruction which sets “1” to the timer X/timer Y count stop bits, the timer X/ timer Y interrupt request bits are set to “1”. Timer X/Timer Y interrupts are received if these interrupts are enabled at this time. The timing which interrupt is accepted has a case after the instruction which sets “1” to the count stop bit, and a case after the next instruction according to the timing of the timer underflow. When this interrupt is unnecessary, set “0” (disabled) to the interrupt enable bit and then set “1” to the count stop bit.
Fig. 24 Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Rev.3.01
2003.06.20
page 30 of 97
3850 Group (Spec.H/A)
Data bus
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 Pulse width (f(XCIN)/2 at low-speed mode) Timer X count source selection bit measurement mode
Prescaler X latch (8) Timer mode Pulse output mode Prescaler X (8) CNTR0 active edge selection bit “0 ” “1 ” Event counter mode Timer X count stop bit
Timer X latch (8)
Timer X (8)
To timer X interrupt request bit
P27/CNTR0
To CNTR0 interrupt request bit
CNTR0 active edge selection “1” bit “0 ”
Q Q
Toggle flip-flop T R Timer X latch write pulse Pulse output mode
Port P27 direction register
Port P27 latch Pulse output mode Data bus
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit CNTR1 active edge selection bit “0 ” “1 ” Pulse width measurement mode
Prescaler Y latch (8) Timer mode Pulse output mode Prescaler Y (8)
Timer Y latch (8)
Timer Y (8)
To timer Y interrupt request bit
P40/CNTR1
Event counter mode
Timer Y count stop bit To CNTR1 interrupt request bit
CNTR1 active edge selection “1” bit “0 ”
Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode
Port P40 direction register
Port P40 latch
Pulse output mode Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XCIN) Timer 12 count source selection bit
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit To timer 1 interrupt request bit
Fig. 25 Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.3.01
2003.06.20
page 31 of 97
3850 Group (Spec.H/A)
SERIAL I/O qSERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Data bus Address 001816 Receive buffer register P24/RXD Receive shift register Shift clock Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
P26/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 Clock control circuit Shift clock P25/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916
XIN
BRG count source selection bit 1/4
P27/SRDY1
F/F
Falling-edge detector
Fig. 26 Block diagram of clock synchronous serial I/O1
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 27 Operation of clock synchronous serial I/O1 function
Rev.3.01
2003.06.20
page 32 of 97
3850 Group (Spec.H/A)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P26/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) UART control register Address 001B16
P24/RXD
OE Receive buffer register Character length selection bit ST detector 7 bits Receive shift register 8 bits
XIN
Fig. 28 Block diagram of UART serial I/O1
Rev.3.01
2003.06.20
page 33 of 97
3850 Group (Spec.H/A)
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST TBE=0 TBE=1 TSC=1
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
Rev.3.01
2003.06.20
page 34 of 97
3850 Group (Spec.H/A)
b7
b0
Serial I/O1 status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read)
b7
b0
Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins)
b7
b0
UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read)
Fig. 30 Structure of serial I/O1 control registers
sNotes on serial I/O
When setting the transmit enable bit of serial I/O1 to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. (1) Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). (2) Set the transmit enable bit to “1”. (3) Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. (4) Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
Rev.3.01
2003.06.20
page 35 of 97
3850 Group (Spec.H/A)
qSERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P0 1 /S OUT2 , P0 2 /S CLK2 P -channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to “1” automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to “1” when SCLK2 is “H” after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the transfer direction selection bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H” is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16).
b7 b0
Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits
b2 b1 b0
0 0 0 0 1 1
0 0 1 1 1 1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin
SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode )
b7 b0
Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits
b2 b1 b0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: 1 bit 1: 2 bit 0: 3 bit 1: 4 bit 0: 5 bit 1: 6 bit 0: 7 bit 1: 8 bit
Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance
Fig. 31 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 31.
Rev.3.01
2003.06.20
page 36 of 97
3850 Group (Spec.H/A)
1/8
XCIN
Divider
Main clock division ratio selection bits (Note) “10” “00” “01”
Internal synchronous clock selection bits
1/16 1/32 1/64 1/128 1/256
Data bus
XIN
P03 latch
“0 ” Serial I/O2 synchronous clock selection bit SRDY2 “1 ” SRDY2 output enable bit Synchronous circuit
P03/SRDY2
“1” “0”
SCLK2
External clock
P02 latch
“0 ”
Optional transfer bits (3) Serial I/O counter 2 (3) Serial I/O2 interrupt request
P02/SCLK2
“1 ” Serial I/O2 port selection bit
P01 latch
“0 ”
P01/SOUT2
“1 ” Serial I/O2 port selection bit
P00/SIN2
Serial I/O2 register (8)
P43 latch
“0 ”
P43/SCMP2/INT2
“1 ” Serial I/O2 I/O comparison signal control bit
D Q
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 32 Block diagram of Serial I/O2
Transfer clock (Note 1) Write-in signal to serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2 Serial I/O2 input SIN2
D0
D1
.
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 33 Timing chart of Serial I/O2
Rev.3.01
2003.06.20
page 37 of 97
3850 Group (Spec.H/A)
SCMP2 SCLK2 SOUT2 SIN2
Judgement of I/O data comparison
Fig. 34 SCMP2 output operation
Rev.3.01
2003.06.20
page 38 of 97
3850 Group (Spec.H/A)
PULSE WIDTH MODULATION (PWM)
The 3850 group (spec. H/A) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X IN o r that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to “ 1 ” , operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
Data Setting
The PWM output pin also functions as port P4 4 . Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz,count source selection bit = “0”) Output pulse “H” term = PWM period ✕ m / 255 = 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz,count source selection bit = “0”)
31.875 ✕ m ✕ (n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz,count source selection bit = “0”) Fig. 35 Timing of PWM period
Data bus
PWM prescaler pre-latch
PWM register pre-latch
Transfer control circuit
PWM prescaler latch Count source selection bit (XCIN XIN at low-speed mode) 1/2 “0” “1” PWM prescaler
PWM register latch
Port P44 PWM register
Port P44 latch
PWM enable bit
Fig. 36 Block diagram of PWM function
Rev.3.01
2003.06.20
page 39 of 97
3850 Group (Spec.H/A)
b7
b0
PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) (f(XCIN) at low-speed mode) 1: f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return “0” when read)
Fig. 37 Structure of PWM control register
A PWM output T PWM register write signal
B
C
B= C T2 T
T (Changes “H” term from “A” to “B”.)
T2
PWM prescaler write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 38 PWM output timing when PWM register or PWM prescaler is changed
sNote
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows:
n+1 2 • f(XIN) n+1 f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
Rev.3.01
2003.06.20
page 40 of 97
3850 Group (Spec.H)
A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616
The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion.
b7
b0
A-D control register (ADCON : address 003416) Analog input pin selection bits
b2 b1 b0
[A-D Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “ 0 ” d uring an A-D conversion and changes to “ 1 ” w hen an A-D conversion ends. Writing “0” to this bit starts the A-D conversion.
0 0 0 0 1
0 0 1 1 0
0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4
Not used (returns “0” when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Fig. 39 Structure of A-D control register (spec. H)
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator.
10-bit reading (Read address 003616 before 003516)
b7
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(XIN ) and f(XCIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit.
(Address 003616)
b7
b0 b9 b8
(Address 003516)
b0 b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0” at reading.
8-bit reading (Read only address 003516)
b7
(Address 003516)
b0 b9 b8 b7 b6 b5 b4 b3 b2
Fig. 40 Structure of A-D conversion registers (spec. H)
Data bus
A-D control register (Address 003416)
b7
b0
3 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 A-D control circuit A-D interrupt request
Channel selector
Comparator
A-D conversion high-order register (Address 003616) A-D conversion low-order register (Address 003516) 10 Resistor ladder
VREF AVSS Fig. 41 Block diagram of A-D converter (spec. H)
Rev.3.01
2003.06.20
page 41 of 97
3850 Group (Spec.A)
A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616
The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion.
b7
b0
A-D control register (ADCON : address 003416) Analog input pin selection bits
b2 b1 b0
Note 1 Note 2
0 0 0 0 1
0 0 1 1 0
0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4
or or or or
P04/AN5 P05/AN6 P06/AN7 P07/AN8 ––––––
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. By setting a value to these bits, when bit 0 of the A-D input selection register (address 003716) is “0”, P30/AN0-P34/AN4 can be selected, and when bit 0 of the A-D input selection register is “1”, P04/AN5-P07/AN8 can be selected. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion.
Not used (returns “0” when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns “0” when read) Notes 1: This is selected when bit 0 of the A-D input selection register (address 003716) is “0”. 2: This is selected when bit 0 of the A-D input selection register (address 003716) is “1”.
Fig. 42 Structure of A-D control register (spec. A)
b7
b0
[A-D Input Selection Register (ADSEL)] 003716
The analog input port selection switch bit is assigned to bit 0 of the A-D input selection register. When “0” is set to the analog input port selection switch bit, P30/AN0-P34/AN4 can be selected by the analog input pin selection bits (b2, b1, b0) of the A-D control register (address 0034 16). When “1” is set to the analog input port selection switch bit, P04/AN5-P07/AN8 can be selected by the analog input pin selection bits (b2, b1, b0) of the A-D control register (address 003416).
A-D input selection register (ADSEL: address 003716) Analog input port selection switch bit 0: P30/AN0 toP34/AN4 is selected as
analog input pin.
1: P04/AN5 to P07/AN8 is selected as
analog input pin.
Not used (returns “0” when read) Fix this bit to “0”. Not used (returns “0” when read) Fix this bit to “0”.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Fig. 43 Structure of A-D input selection register (spec. A)
Channel Selector
The channel selector selects one of ports P30 /AN0 to P34 /AN4 , P04/AN5 to P07/AN8 and inputs the voltage to the comparator.
10-bit reading (Read address 003616 before 003516)
b7
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(XIN ) and f(XCIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit.
(Address 003616)
b7
b0 b9 b8
(Address 003516)
b0 b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0” at reading.
8-bit reading (Read only address 003516)
b7
(Address 003516)
b0 b9 b8 b7 b6 b5 b4 b3 b2
Fig. 44 Structure of A-D conversion registers (spec. A)
Rev.3.01
2003.06.20
page 42 of 97
3850 Group (Spec.A)
Data bus
A-D control register b7 (Address 003416)
b0
b7
b0 A-D input selection register (Address 003716)
3 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P04/AN5 P05/AN6 P06/AN7 P07/AN8 A-D control circuit
Channel selector
A-D interrupt request
Comparator
A-D conversion high-order register (Address 003616) A-D conversion low-order register (Address 003516) 10 Resistor ladder
VREF AVSS
Fig. 45 Block diagram of A-D converter (spec. A)
Rev.3.01
2003.06.20
page 43 of 97
3850 Group (Spec.H/A)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 0039 16 ) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. qInitial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L are set to “FF16”.
“FF16” is set when watchdog timer control register is written to. “10” Main clock division ratio selection bits (Note) XIN Watchdog timer L (8) 1/16 “00” “01”
qWatchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is set to “ 0 ” , the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to “1”, the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to “0” after reset. qOperation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “ 1 ” , it cannot be rewritten to “ 0 ” b y program. This bit is cleared to “0” after reset.
Data bus “FF16” is set when watchdog timer control register is written to. Watchdog timer H (8)
XCIN
“0 ” “1 ”
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 46 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16
Fig. 47 Structure of Watchdog timer control register
Rev.3.01
2003.06.20
page 44 of 97
3850 Group (Spec.H/A)
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more of XIN. Then the RESET pin is returned to an “H” level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 ( high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage; Vcc = 2.7 V
RESET
VCC Power source voltage detection circuit
Fig. 48 Reset circuit example
XIN
φ
RESET
RESETOUT
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals.
Fig. 49 Reset sequence
Rev.3.01
2003.06.20
page 45 of 98
3850 Group (Spec.H)
Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 001516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) MISRG (35) Watchdog timer control register (WDTCON) (36) Interrupt edge selection register (INTEDGE) (37) CPU mode register (CPUM) (38) Interrupt request register 1 (IREQ1) (39) Interrupt request register 2 (IREQ2) (40) Interrupt control register 1 (ICON1) (41) Interrupt control register 2 (ICON2) (42) Processor status register (43) Program counter
Address Register contents 003816 0016
003916 0 0 1 1 1 1 1 1 003A16 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) 0016 0016 0016 0016 XXXXX1XX
FFFD16 contents FFFC16 contents
(10) Port P4 direction register (P4D) (11) Serial I/O2 control register 1 (SIO2CON1) (12) Serial I/O2 control register 2 (SIO2CON2) (13) Serial I/O2 register (SIO2) (14) Transmit/Receive buffer register (TB/RB) (15) Serial I/O1 status register (SIOSTS) (16) Serial I/O1 control register (SIOCON) (17) UART control register (UARTCON) (18) Baud rate generator (BRG) (19) PWM control register (PWMCON) (20) PWM prescaler (PREPWM) (21) PWM register (PWM) (22) Prescaler 12 (PRE12) (23) Timer 1 (T1) (24) Timer 2 (T2) (25) Timer XY mode register (TM) (26) Prescaler X (PREX) (27) Timer X (TX) (28) Prescaler Y (PREY) (29) Timer Y (TY) (30) Timer count source selection register (TCSS) (31) A-D control register (ADCON) (32) A-D conversion low-order register (ADL) (33) A-D conversion high-order register (ADH)
001616 0 0 0 0 0 1 1 1 001716 X X X X X X X X 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016
001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016
001E16 X X X X X X X X 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 002816 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016
003416 0 0 0 1 0 0 0 0 003516 X X X X X X X X 003616 0 0 0 0 0 0 X X
Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 50 Internal status at reset (spec. H)
Rev.3.01
2003.06.20
page 46 of 98
3850 Group (Spec.A)
Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 001216 001316 001416 001516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) A-D control register (ADCON) (35) A-D conversion low-order register (ADL) (36) A-D conversion high-order register (ADH) (37) A-D input selection register (ADSEL) (38) MISRG (39) Watchdog timer control register (WDTCON) (40) Interrupt edge selection register (INTEDGE) (41) CPU mode register (CPUM) (42) Interrupt request register 1 (IREQ1) (43) Interrupt request register 2 (IREQ2) (44) Interrupt control register 1 (ICON1) (45) Interrupt control register 2 (ICON2) (46) Processor status register (47) Program counter
Address Register contents 003416 0 0 0 1 0 0 0 0 003516 X X X X X X X X 003616 0 0 0 0 0 0 X X 003716 003816 0016 0016
003916 0 0 1 1 1 1 1 1 003A16 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) 0016 0016 0016 0016 XXXXX1XX
FFFD16 contents FFFC16 contents
(10) Port P4 direction register (P4D) (11) Port P0, P1, P2 pull-up control register (PULL012) (12) Port P3 pull-up control register (PULL3) (13) Port P4 pull-up control register (PULL4) (14) Serial I/O2 control register 1 (SIO2CON1) (15) Serial I/O2 control register 2 (SIO2CON2) (16) Serial I/O2 register (SIO2) (17) Transmit/Receive buffer register (TB/RB) (18) Serial I/O1 status register (SIOSTS) (19) Serial I/O1 control register (SIOCON) (20) UART control register (UARTCON) (21) Baud rate generator (BRG) (22) PWM control register (PWMCON) (23) PWM prescaler (PREPWM) (24) PWM register (PWM) (25) Prescaler 12 (PRE12) (26) Timer 1 (T1) (27) Timer 2 (T2) (28) Timer XY mode register (TM) (29) Prescaler X (PREX) (30) Timer X (TX) (31) Prescaler Y (PREY) (32) Timer Y (TY) (33) Timer count source selection register (TCSS)
001616 0 0 0 0 0 1 1 1 001716 X X X X X X X X 001816 X X X X X X X X 001916 1 0 0 0 0 0 0 0 001A16 0016
001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016
001E16 X X X X X X X X 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 002816 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016
Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 51 Internal status at reset (spec. A)
Rev.3.01
2003.06.20
page 47 of 98
3850 Group (Spec.H/A)
CLOCK GENERATING CIRCUIT
The 3850 group (spec. H/A) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer ’s recommended values. No external resistor is needed between X IN a nd X OUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN d ivided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction.
Frequency Control (1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected.
sNote
When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
sNote
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN).
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
CCIN
CI N
COUT
Fig. 52 Ceramic resonator circuit
Oscillation Control (1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the oscillation stabilizing time set after STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either X IN or X CIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “ L ” l evel to the RESET pin until the oscillation is stable since a wait time will not be generated.
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT Open
External oscillation circuit CCIN Vcc Vss
Fig. 53 External clock input circuit
Rev.3.01
2003.06.20
page 48 of 98
3850 Group (Spec.H/A)
[MISRG (MISRG)] 003816
MISRG consists of three control bits (bits 1 to 3) for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic switch start bit to “1” while operating in the low-speed mode and setting the middlespeed mode automatic switch set bit to “ 1 ” , X IN o scillation automatically starts and the mode is automatically switched to the middle-speed mode.
b7
b0
MISRG (MISRG : address 003816) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return “0” when read) Note: W h e n th e mo d e i s a u t o m a ti c a lly s wi tc h e d fr o m t h e lo w- s p e e d m o d e t o the middle-speed mode, the value of CPU mode register (address 003B16) changes.
Fig. 54 Structure of MISRG
XCIN
XCOUT
“1” “0”
Port XC switch bit
XIN
XOUT
Main clock division ratio selection bits (Note 1) Low-speed mode
1/2
High-speed or middle-speed mode
1/4
1/2
Prescaler 12
(Note 3)
Timer 1
Reset or STP instruction (Note 2)
Main clock division ratio selection bits (Note 1) Middle-speed mode High-speed or low-speed mode Main clock stop bit
Timing φ (internal clock)
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset
Reset Interrupt disable flag l Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to “1”. 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG = “0”, the prescaler 12 is set to "FF16" and timer 1 is set to "0116". When bit 0 of MISRG = “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
Rev.3.01
2003.06.20
page 49 of 98
3850 Group (Spec.H/A)
Reset
Middle-speed mode (f(φ) = 1 MHz) C M7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped)
CM6 “1” ←→ “0”
High-speed mode (f(φ) = 4 MHz) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped)
CM4 “1” ←→ “0”
” “0 4 → M C ”← 0” “1 6 → “ CM ” ← “1
CM “0 4 CM ” ← “1 6 → “ ”← 1” → “0 ”
Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 CM6 = 1 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating)
CM6 “1” ←→ “0”
High-speed mode (f(φ) = 4 MHz) CM7 = 0 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating)
Middle-speed mode automatic switch set bit "1"
Middle-speed mode automatic switch start bit "1"
Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating)
CM7 “1” ←→ “0”
CM “0 7 ”← CM → “1 6 “1 ”← ” → “0 ”
CM4 “1” ←→ “0”
b7
b4 CPU mode register (CPUM : address 003B16)
CM5 “1” ←→ “0”
Low-speed mode (f(φ)=16 kHz) CM7 = 1 CM6 = 0 CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating)
CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”. (2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set by the middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the middlespeed mode. 8 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 56 State transitions of system clock
Rev.3.01
2003.06.20
page 50 of 98
3850 Group (Spec.H/A)
FLASH MEMORY MODE
The M38507F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 5 V, and 2 power sources when VPP is 5 V and VCC is 3.0-5.5 V in the CPU rewrite and standard serial I/O modes. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU).
Summary
Table 11 lists the summary of the M38507F8 (flash memory version). The flash memory of the M38507F8 is divided into User ROM area and Boot ROM area as shown in Figure 57. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user ’s application system. This Boot ROM area can be rewritten in only parallel I/O mode.
Table 11 Summary of M38507F8 (flash memory version) Item Power source voltage VPP voltage (For Program/Erase) Flash memory mode Erase block division User ROM area Boot ROM area Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Specifications Vcc = 2.7– 5.5 V (Note 1) Vcc = 2.7–3.6 V (Note 2) 4.5-5.5 V 3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode) 1 block (32 Kbytes) 1 block (4 Kbytes) (Note 3) Byte program Batch erasing Program/Erase control by software command 6 commands 100 times Available in parallel I/O mode and standard serial I/O mode
Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation. 2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation. 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode.
Rev.3.01
2003.06.20
page 51 of 98
3850 Group (Spec.H/A)
(1) CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 57 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be executed before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 57 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P41/INT0 pin high, the CNVss pin high, the CPU starts operating using the control program in the Boot ROM area (program start address is FFFC16, FFFD16 fixation). This mode is called the “Boot” mode.
Block Address
Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. In case of the M38507F8, it has only one block.
Parallel I/O mode 800016 Block 1 : 32 kbyte FFFF16 User ROM area BSEL = 0 CPU rewrite mode, standard serial I/O mode 800016 Block 1 : 32 kbyte
Product name M38507F8 Flash memory start address 800016
F00016 4 kbyte FFFF16 Boot ROM area BSEL = 1
F00016 4 kbyte FFFF16 Boot ROM area User area / Boot area selection bit = 1
FFFF16 User ROM area User area / Boot area selection bit = 0
Notes 1: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block.
Fig. 57 Block diagram of built-in flash memory
Rev.3.01
2003.06.20
page 52 of 98
3850 Group (Spec.H/A)
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory by executing software commands. This rewrite control program must be transferred to the RAM before it can be executed. The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit 1 of address 0FFE16). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 58 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in the RAM for write to bit 1. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing “0”. Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the control circuit. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. To release the reset, it is necessary to set this bit to “0”. Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to “1”, Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in the RAM. Figure 59 shows a flowchart for setting/releasing CPU rewrite mode.
b7
b0
Flash memory control register (address 0FFE16) (Note 1) FMCR
RY/BY status flag 0: Busy (being programmed or erased) 1: Ready CPU rewrite mode select bit (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag 0: Normal mode 1: CPU rewrite mode Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area / Boot ROM area select bit (Note 4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (Indefinite at read/ “0” at write) Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask ROM version, this address is reserved area. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to “1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig.58 Structure of flash memory control register
Rev.3.01
2003.06.20
page 53 of 98
3850 Group (Spec.H/A)
Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program to RAM
Setting
Jump to control program transferred in RAM (Subsequent operations are executed by control program in this RAM)
Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase, program, or other operation
Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3)
Released
Write “0” to CPU rewrite mode select bit
End Notes 1: When starting the MCU in the single-chip mode, supply 4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set bits 6, 7 (main clock division ratio selection bits) at CPU mode register (003B16). 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory.
Fig. 59 CPU rewrite mode set/release flowchart
Rev.3.01
2003.06.20
page 54 of 98
3850 Group (Spec.H/A)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 6.25 MHz or less using the main clock division ratio selection bits (bit 6, 7 at 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = H when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area.
Rev.3.01
2003.06.20
page 55 of 98
3850 Group (Spec.H/A)
Software Commands (CPU Rewrite Mode)
Table 12 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. qRead Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained intact until another command is written. qRead Status Register Command (7016) The read status register mode is entered by writing the command code “7016” in the first bus cycle. The contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. qClear Status Register Command (5016) This command is used to clear the bits SR1, SR4, and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. qProgram Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by _____ reading the status register or the RY/BY Status Flag of the flash memory control register. When the program starts, the read status
register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the next command is written. ____ The RY/BY Status Flag is “0” (busy) during write operation and “1” (ready) when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading bit 4 (SR4) of the status register.
Start Write 4016 Write Write address Write data Status register read
SR7 = 1 ? or RY/BY = 1 ? YES
NO
S R4 = 0 ? YES Program completed (Read array command “FF16” write)
Fig. 60 Program flowchart
NO
Program error
Table 12 List of software commands (CPU rewrite mode)
Command Read array Read status register Clear status register Program Erase all blocks Block erase
Cycle number 1 2 1 2 2 2
Mode Write Write Write Write Write Write
First bus cycle Data Address (D0 to D7) X
(Note 1)
Second bus cycle Mode Address Data (D0 to D7)
FF16 7016 5016 4016 2016 2016 Write Write Write BA WA (Note 3) X
(Note 4)
X X X X X
Read
X
SRD (Note 2)
WD (Note 3) 2016 D016
Notes 1: X denotes a given address in the User ROM area . 2: SRD = Status Register Data 3: WA = Write Address, WD = Write Data 4: BA = Block Address to be erased (Input the maximum address of each block.)
Rev.3.01
2003.06.20
page 56 of 98
3850 Group (Spec.H/A)
qErase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY Status Flag of flash memory control register. When the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode remains active until another command is written. ____ The RY/BY Status Flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7 (SR7). After the erase all blocks end, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. qBlock Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the blobk address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY Status Flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed.
Start
Write 2016
Write
2016/D016 Block address
2016:Erase all blocks command D016:Block erase command
Status register read
SR7 = 1 ? or RY/BY = 1 ?
NO
YES NO
SR5 = 0 ?
Erase error
YES Erase completed (Read comand “FF16” write)
Fig. 61 Erase flowchart
Rev.3.01
2003.06.20
page 57 of 98
3850 Group (Spec.H/A)
Status Register (SRD)
The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 13 shows the status register. Each bit in this register is explained below. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready).
•Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is set to “0” when it is cleared. If “ 1 ” i s written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”.
Table 13 Definition of each bit in status register (SRD)
Symbol SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0)
Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved
Definition “1”
Ready Terminated in error Terminated in error -
“0”
Busy Terminated normally Terminated normally -
Rev.3.01
2003.06.20
page 58 of 98
3850 Group (Spec.H/A)
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 62 shows a
full status check flowchart and the action to be taken when each error occurs.
Read status register
SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES
YES
Command sequence error
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used.
NO
Erase error
NO
Program error
Should a program error occur, the block in error cannot be used.
End (erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the read array, the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands.
Fig. 62 Full status check flowchart and remedial procedure for errors
Rev.3.01
2003.06.20
page 59 of 98
3850 Group (Spec.H/A)
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. qROM Code Protect Function (in Parallel I/O Mode) The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control (address FFDB 16 ) in parallel I/O mode. Figure 63 shows the ROM code protect control (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits.
b7
b0
1 1 ROM code protect control register (address FFDB16) (Note 1)
ROMCP
Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)
b3b2
0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled
ROM code protect reset bits (Note 4)
b5b4
0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 2)
b7b6
0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: This area is on the ROM in the mask ROM version. 2: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 3: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 4: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode.
Fig. 63 Structure of ROM code protect control
Rev.3.01
2003.06.20
page 60 of 98
3850 Group (Spec.H/A)
ID Code Check Function (in Standard serial I/O mode)
Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory.
Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area
Fig. 64 ID code store addresses
Rev.3.01
2003.06.20
page 61 of 98
3850 Group (Spec.H/A)
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the 3850 Group (flash memory version). Refer to each programmer maker ’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 57 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 57. The boot ROM area is 4 Kbytes in size. It is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial I/O mode, you do not need to write to the boot ROM area.
Rev.3.01
2003.06.20
page 62 of 98
3850 Group (Spec.H/A)
(3) Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires the exclusive external equipment (serial programmer). The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the P26 (SCLK1) pin and “H” to the P41 (INT0) pin and “H” to the CNVSS pin (apply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figure 65 shows the pin connection for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four serial I/O pins S CLK1, RxD, TxD and SRDY1 (BUSY). The S CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD pin is for CMOS output. The S RDY1 (BUSY) pin outputs “L” level when ready for reception and “H” level when reception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 44 can be rewritten. The Boot ROM area cannot. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.
Outline Performance (Standard Serial I/O Mode)
In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programmer, etc.) using 4-wire clock-synchronized serial I/O (serial I/O1). In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK1 pin, and are then input to the MCU via the RxD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD pin. The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the SRDY1 (BUSY) pin is “H” level. Accordingly, always start the next transfer after the SRDY1 (BUSY) pin is “L” level. Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc.
Rev.3.01
2003.06.20
page 63 of 98
3850 Group (Spec.H/A)
Table 14 Description of pin function (Standard Serial I/O Mode)
Pin VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00 to P07 P10 to P17 P20 to P23 P24 P25 P26 P27 P30 to P34 P40, P42 to P44 P41
Name Power input CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 RxD input TxD output SCLK1 input BUSY output Input port P3 Input port P4 Input port P4
I/O
Description Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
I I I O
Connect to VCC when VCC = 4.5 V to 5.5 V. Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V. Reset input pin. While reset is “L” level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect AVSS to VSS .
I I I I I O I O I I I
Enter the reference voltage for AD from this pin. Input “H” or “L” level signal or open. Input “H” or “L” level signal or open. Input “H” or “L” level signal or open. Serial data input pin Serial data output pin Serial clock input pin BUSY signal output pin Input “H” or “L” level signal or open. Input “H” or “L” level signal or open. Input “H” level signal, when reset is released.
Rev.3.01
2003.06.20
page 64 of 98
3850 Group (Spec.H/A)
VCC VSS VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/TxD P24/RxD P23/SCL1 P22/SDA1 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P41 BUSY SCLK1 TxD RXD RxD ✽ 2 VPP
RESET ✽1
P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7)
M38507F8SP/FP
Mode setup method
Signal Value 4.5 to 5.5 V VCC ✽ 3 VCC ✽ 3 VSS → VCC Notes 1: Connect oscillator circuit 2: Connect to Vcc when Vcc = 4.5 V to 5.5 V. Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V. 3: It is necessary to apply Vcc only when reset is released.
CNVSS P41 SCLK1 RESET
Fig. 65 Pin connection diagram in standard serial I/O mode
Rev.3.01
2003.06.20
page 65 of 98
3850 Group (Spec.H/A)
Software Commands (Standard Serial I/O Mode)
Table 15 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 15 Software commands (Standard serial I/O mode) Control command 1st byte transfer FF16 2nd byte Address (middle) Address (middle) D016 SRD output SRD1 output 3rd byte Address (high) Address (high)
commands via the RxD pin. Software commands are explained here below.
4th byte Data output Data input
5th byte Data output Data input
6th byte Data output Data input
..... Data output to 259th byte Data input to 259th byte
When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable Not acceptable
1 2 3 4 5 6
Page read Page program Erase all blocks Read status register Clear status register ID code check
4116 A716 7016 5016 F516
Address (low) Size (low)
Address (middle) Size (high)
Address (high) Checksum
ID size Data input
ID1 To required number of times Version data output
To ID7
Acceptable Not acceptable
7
Download function
FA16
8
Version data output function
FB16
Version data output
Version data output
Version data output
Version data output
Version data output to 9th byte
Acceptable
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment (programmer) to the internal flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted when the flash memory is totally blank. 4: Address high must be “0016”.
Rev.3.01
2003.06.20
page 66 of 98
3850 Group (Spec.H/A)
qPage Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0 to D 7) for the page (256 bytes) specified with addresses A8 t o A23 w ill be output sequentially from the smallest address first synchronized with the fall of the clock.
SCLK1
RxD
FF16
A8 to A15
A16 to A23 data0 data255
TxD
SRDY1(BUSY)
Fig. 66 Timing for page read
qRead Status Register Command This command reads status information. When the “70 16” command code is transferred with the 1st byte, the contents of the status register (SRD) with the 2nd byte and the contents of status register 1 (SRD1) with the 3rd byte are read.
SCLK1
RxD
7016
TxD
SRD output
SRD1 output
SRDY1(BUSY)
Fig. 67 Timing for reading status register
Rev.3.01
2003.06.20
page 67 of 98
3850 Group (Spec.H/A)
qClear Status Register Command This command clears the bits (SR4, SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY1 (BUSY) signal changes from “H” to “L” level.
SCLK1
RxD
5016
TxD
SRDY1(BUSY)
Fig. 68 Timing for clear status register
qPage Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0 t o D 7 ) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the SRDY1 (BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
SCLK1
RxD
4116
A8 to A15
A16 to A23
data0
data255
TxD
SRDY1(BUSY)
Fig. 69 Timing for page program
Rev.3.01
2003.06.20
page 68 of 98
3850 Group (Spec.H/A)
qErase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D0 16” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory.
When erase all blocks end, the S RDY1 ( BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the erase operation can be known by reading the status register.
SCLK1
RxD
A716
D016
TxD
SRDY1(BUSY)
Fig. 70 Timing for erase all blocks
Rev.3.01
2003.06.20
page 69 of 98
3850 Group (Spec.H/A)
qDownload Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
SCLK1
RxD
FA16
Data size Data size (high) (low)
Check sum
Program data
TxD
Program data
SRDY1(BUSY)
Fig. 71 Timing for download
Rev.3.01
2003.06.20
page 70 of 98
3850 Group (Spec.H/A)
qVersion Information Output Command This command outputs the version information of the control program stored in the Boot ROM area. Execute the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
SCLK1
RxD
FB16
TxD
‘V’
‘E’
‘R’
‘X’
SRDY1(BUSY)
Fig. 72 Timing for version information output
Rev.3.01
2003.06.20
page 71 of 98
3850 Group (Spec.H/A)
qID Check This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”) of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) Transfer the ID code with the 6th byte onward, starting with the 1st byte of the code.
SCLK1
RxD
F516
D416
FF16
0016
ID size
ID1
ID7
TxD
SRDY1(BUSY)
Fig. 73 Timing for ID check
qID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFD416 to FFDA16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area
Fig. 74 ID code storage addresses
Rev.3.01
2003.06.20
page 72 of 98
3850 Group (Spec.H/A)
qStatus Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16 ). Also, the status register is cleared by writing the clear status register command (5016). Table 16 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”.
•Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready). This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. If a program error occurs, it is set to “1”. When the program status is cleared, it is set to “0”.
Table 16 Definition of each bit of status register (SRD)
Definition
SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved
“1”
Ready Terminated in error Terminated in error -
“0”
Busy Terminated normally Terminated normally -
Rev.3.01
2003.06.20
page 73 of 98
3850 Group (Spec.H/A)
qStatus Register 1 (SRD1) The status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 17 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is maintained even after the reset.
•Boot update completed bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. •Check sum consistency bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. •ID check completed bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID code check. •Data reception time out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command wait state.
Table 17 Definition of each bit of status register 1 (SRD1)
SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2)
Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits
Definition “1” Update completed Match 00 01 10 11 “0” Not Update Mismatch Not verified Verification mismatch Reserved Verified Normal operation -
SR9 (bit1) SR8 (bit0)
Data reception time out Reserved
Time out -
Rev.3.01
2003.06.20
page 74 of 98
3850 Group (Spec.H/A)
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure 75 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES
YES
Command sequence error
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used.
NO
Erase error
NO
Program error
Should a program error occur, the block in error cannot be used.
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks commands is accepted. Execute the clear status register command (5016) before executing these commands.
Fig. 75 Full status check flowchart and remedial procedure for errors
Rev.3.01
2003.06.20
page 75 of 98
3850 Group (Spec.H/A)
Example Circuit Application for Standard Serial I/O Mode
Figure 76 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information.
P41 Clock input BUSY output Data input Data output SCLK1 SRDY1 (BUSY) RXD TXD
M38507F8
VPP power source input
CNVss
Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. 2: In this example, the Vpp power supply is supplied from an external source (writer). To use the user’s power source, connect to 4.5 V to 5.5 V. 3: It is necessary to apply Vcc to SCLK1 pin only when reset is released.
Fig. 76 Example circuit application for standard serial I/O mode
Rev.3.01
2003.06.20
page 76 of 98
3850 Group (Spec.H/A)
Flash memory Electrical characteristics
Table 18 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) 25±5 –40 to 125 Unit V V V V V V V mW °C °C
Ta = 25 °C
Note: The rating becomes 300 mW at the 42P2R-A/E package.
Table 19 Flash memory mode Electrical characteristics (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) Limits Symbol IPP1 IPP2 IPP3 VPP VCC Parameter VPP power source current (read) VPP power source current (program) VPP power source current (erase) VPP power source voltage VCC power source voltage VPP = VCC VPP = VCC VPP = VCC 4.5 Microcomputer mode operation at VCC = 2.7 to 5.5V Microcomputer mode operation at VCC = 2.7 to 3.6V 4.5 3.0 Conditions Min. Typ. Max. 100 60 30 5.5 5.5 3.6 Unit µA mA mA V V V
Rev.3.01
2003.06.20
page 77 of 98
3850 Group (Spec.H/A)
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) in the middle/high-speed mode is at least on 500 kHz during an A-D conversion. Do not execute the STP instruction during an A-D conversion.
Instruction Execution Time Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency in high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
NOTES ON USAGE Differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A)
(1) The absolute maximum ratings of 3850 group (spec. H/A) is smaller than that of 3850 group (standard). •Power source voltage Vcc = –0.3 to 6.5 V •CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H/A). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins.
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC p in) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recommended.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1”. Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed. When an external clock is used as synchronous clock in serial I/ O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is “H”.
EPROM Version/One Time PROM Version/ Flash Memory Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor.
Rev.3.01
2003.06.20
page 78 of 98
3850 Group (Spec.H/A)
Electric Characteristic Differences Among Mask ROM, Flash Memory, and One Time PROM Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM, flash memory, and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with the flash memory, One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version.
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and buitin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 20 Programming adapter Name of Programming Adapter Package PCA4738S-42A 42P4B, 42S1B PCA4738F-42A 42P2R-A/E
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form✽ 2. Mark Specification Form✽ 3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 77 is recommended to verify programming.
DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming service: 1. ROM Programming Confirmation Form✽ 2. Mark Specification Form✽ (only special mark with customer’s trade mark logo) 3. Data to be programmed to PROM, in EPROM form (three identical copies) or one floppy disk. ✽For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology” Homepage Rom ordering (http://www.renesas.com/eng/rom).
Programming with PROM programmer
Screening (Caution) (150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours.
Fig. 77 Programming and testing of One Time PROM version
Rev.3.01
2003.06.20
page 79 of 98
3850 Group (Spec.H/A)
Electrical characteristics Absolute maximum ratings
Table 21 Absolute maximum ratings Symbol Parameter VCC Power source voltage Input voltage P00–P07, P10–P17, P20, P21, VI P24–P27, P30–P34, P40–P44, VREF VI VI VI VO VO Pd Topr Tstg Input voltage Input voltage Input voltage Output voltage P22, P23 RESET, XIN CNVSS P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 All voltages are based on VSS. Output transistors are cut off. –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) –20 to 85 –40 to 125 Unit V V V V V V V mW °C °C
Ta = 25 °C
Note : The rating becomes 300mW at the 42P2R-A/E package.
Rev.3.01
2003.06.20
page 80 of 98
3850 Group (Spec.H)
Recommended operating conditions
Table 22 Recommended operating conditions (1) (spec. H) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) Power source voltage Parameter 8 MHz (high-speed mode) 8 MHz (middle-speed mode), 4 MHz (high-speed mode) Limits Min. 4.0 2.7 2.0 0 AN0–AN4 P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 RESET, XIN, CNVSS P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 RESET, CNVSS XIN AVSS 0.8VCC 0.8VCC 0 0 0 VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC –80 –80 80 120 80 –40 –40 40 60 40 Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage “H” input voltage “H” input voltage “L” input voltage “L” input voltage “L” input voltage
“H” total peak output current (Note) P00–P07, P10–P17, P30–P34 “H” total peak output current (Note) P20, P21, P24–P27, P40–P44 “L” total peak output current (Note) P00–P07, P30–P34 “L” total peak output current (Note) P10–P17 “L” total peak output current (Note) P20–P27,P40–P44 “H” total average output current (Note) P00–P07, P10–P17, P30–P34 “H” total average output current (Note) P20, P21, P24–P27, P40–P44 “L” total average output current (Note) P00–P07, P30–P34 “L” total average output current (Note) P10–P17 “L” total average output current (Note) P20–P27,P40–P44
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
Rev.3.01
2003.06.20
page 81 of 98
3850 Group (Spec.A)
Recommended operating conditions
Table 23 Recommended operating conditions (1) (spec. A) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter 12.5 MHz (high-speed mode) 12.5 MHz (middle-speed mode), 6 MHz (high-speed mode) 32 kHz (low-speed mode) Limits Min. 4.0 2.7 Typ. 5.0 5.0 0 2.0 0 AN0–AN8 P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 RESET, XIN, CNVSS P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 RESET, CNVSS AVSS 0.8VCC 0.8VCC 0 0 0 VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC –80 –80 80 120 80 –40 –40 40 60 40 VCC Max. 5.5 5.5 Unit
VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg)
Power source voltage
V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage “H” input voltage “H” input voltage “L” input voltage “L” input voltage
“L” input voltage XIN “H” total peak output current (Note) P00–P07, P10–P17, P30–P34 “H” total peak output current (Note) P20, P21, P24–P27, P40–P44 “L” total peak output current (Note) P00–P07, P30–P34 “L” total peak output current (Note) P10–P17 “L” total peak output current(Note) P20–P27,P40–P44 “H” total average output current (Note) P00–P07, P10–P17, P30–P34 “H” total average output current (Note) P20, P21, P24–P27, P40–P44 “L” total average output current (Note) P00–P07, P30–P34 “L” total average output current (Note) P10–P17 “L” total average output current (Note) P20–P27,P40–P44
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
Rev.3.01
2003.06.20
page 82 of 98
3850 Group (Spec.H)
Table 24 Recommended operating conditions (2) (spec. H) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) “H” peak output current Parameter P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 1) “L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44 P10–P17 “H” average output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 2) “L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44 P10–P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Min. Limits Typ. Max. –10 10 20 –5 5 15 8 4 Unit mA mA mA mA mA mA MHz MHz
IOH(avg) IOL(avg) f(XIN) f(XIN)
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%.
Electrical characteristics
Table 25 Electrical characteristics (1) (spec. H) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note) “L” output voltage P00–P07, P20–P27, P30–P34, P40–P44 “L” output voltage P10–P17 Test conditions IOH = –10 mA VCC = 4.0–5.5 V IOH = –1.0 mA VCC = 2.7–5.5 V IOL = 10 mA VCC = 4.0–5.5 V IOL = 1.0 mA VCC = 2.7–5.5 V IOL = 20 mA VCC = 4.0–5.5 V IOL = 10 mA VCC = 2.7–5.5 V Min. VCC–2.0 VCC–1.0 2.0 1.0 2.0 1.0 Typ. Max. Unit V V V V V V
VOL
VOL
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Rev.3.01
2003.06.20
page 83 of 98
3850 Group (Spec.A)
Table 26 Recommended operating conditions (2) (spec. A) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) “H” peak output current Parameter P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 1) “L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44 P10–P17 “H” average output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 2) “L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44 P10–P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 4.0 V) (Note 3) Min. Limits Typ. Max. –10 10 20 –5 5 15 12.5
5Vcc-7.5
Unit mA mA mA mA mA mA MHz MHz
IOH(avg) IOL(avg) f(XIN) f(XIN)
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%.
Electrical characteristics
Table 27 Electrical characteristics (1) (spec. A) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note) “L” output voltage P00–P07, P20–P27, P30–P34, P40–P44 “L” output voltage P10–P17 Test conditions IOH = –10 mA VCC = 4.0–5.5 V IOH = –1.0 mA VCC = 2.7–5.5 V IOL = 10 mA VCC = 4.0–5.5 V IOL = 1.0 mA VCC = 2.7–5.5 V IOL = 20 mA VCC = 4.0–5.5 V IOL = 10 mA VCC = 2.7–5.5 V Min. VCC–2.0 VCC–1.0 2.0 1.0 2.0 1.0 Typ. Max. Unit V V V V V V
VOL
VOL
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Rev.3.01
2003.06.20
page 84 of 98
3850 Group (Spec.H)
Table 28 Electrical characteristics (2) (spec.H) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VT+–VT– VT+–VT– VT+–VT– IIH Parameter Hysteresis CNTR0, CNTR1, INT0–INT3 Hysteresis RxD, SCLK1, SCLK2, SIN2 ____________ Hysteresis RESET “H” input current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 ____________ “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P34, P40–P44
____________
Test conditions
Min.
Typ. 0.4 0.5 0.5
Max.
Unit V V V µA
VI = VCC
5.0
IIH IIH IIL
VI = VCC VI = VCC VI = VSS
5.0 4 –5.0
µA µA µA
IIL IIL VRAM
“L” input current RESET,CNVSS “L” input current XIN RAM hold voltage
VI = VSS VI = VSS When clock stopped
–5.0 –4 2.0 5.5
µA µA V
Rev.3.01
2003.06.20
page 85 of 98
3850 Group (Spec.A)
Table 29 Electrical characteristics (2) (spec.A) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VT+–VT– VT+–VT– VT+–VT– IIH Parameter Hysteresis CNTR0, CNTR1, INT0–INT3 Hysteresis RxD, SCLK1, SCLK2, SIN2 ____________ Hysteresis RESET “H” input current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 ____________ “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P34, P40–P44 ____________ “L” input current RESET,CNVSS “L” input current XIN “L” input current (at Pull-up) P00–P07, P10–P17, P20–P27 P30–P34, P40–P44 RAM hold voltage Test conditions Min. Typ. 0.4 0.5 0.5 VI = VCC Pin floating, Pull-up Transistor "off" VI = VCC VI = VCC VI = VSS Pin floating, Pull-up Transistor "off" VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VI = 3.0 V When clock stopped 5.0 Max. Unit V V V µA
IIH IIH IIL
5.0 4 –5.0
µA µA µA
IIL IIL IIL
–5.0 –25 –8 2.0 –4 –65 –22 –120 –40 5.5
µA µA µA µA V
VRAM
Rev.3.01
2003.06.20
page 86 of 98
3850 Group (Spec.H)
Table 30 Electrical characteristics (3) (spec. H) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ICC Parameter Power source current Test conditions Min. High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode Except f(XIN) = stopped M38507F8FP/SP f(XCIN) = 32.768 kHz M38507F8FP/SP Output transistors “off” Low-speed mode Except f(XIN) = stopped M38507F8FP/SP f(XCIN) = 32.768 kHz (in WIT state) M38507F8FP/SP Output transistors “off” Low-speed mode (VCC = 3 V) Except M38507F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz M38507F8FP/SP Output transistors “off” Low-speed mode (VCC = 3 V) Except M38507F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) M38507F8FP/SP Output transistors “off” Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Limits Typ. 6.8 Max. Unit
13
mA
1.6 60 250 20 70 20 150 5.0 20 10.0 55 40 200
mA µA µA µA µA µA µA µA µA
4.0
7.0
mA
1.5
mA
800 0.1 1.0 10
µA µA µA
Rev.3.01
2003.06.20
page 87 of 98
3850 Group (Spec.A)
Table 31 Electrical characteristics (3) (spec. A) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ICC Parameter Power source current Test conditions Min. Except High-speed mode M38507F8FP/SP f(XIN) = 12.5 MHz f(XCIN) = 32.768 kHz M38507F8FP/SP Output transistors “off” Except High-speed mode M38507F8FP/SP f(XIN) = 8 MHz f(XCIN) = 32.768 kHz M38507F8FP/SP Output transistors “off” High-speed mode f(XIN) = 12.5 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” Middle-speed mode Except f(XIN) = 12.5 MHz M38507F8FP/SP f(XCIN) = stopped M38507F8FP/SP Output transistors “off” Except Middle-speed mode M38507F8FP/SP f(XIN) = 8 MHz f(XCIN) = stopped M38507F8FP/SP Output transistors “off” Middle-speed mode f(XIN) = 12.5 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Except Low-speed mode M38507F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz M38507F8FP/SP Output transistors “off” Except Low-speed mode M38507F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) M38507F8FP/SP Output transistors “off” Except Low-speed mode (VCC = 3 V) M38507F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz M38507F8FP/SP Output transistors “off” Except Low-speed mode (VCC = 3 V) M38507F8FP/SP f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) M38507F8FP/SP Output transistors “off” Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Limits Typ. 6.5 7.5 5.0 6.8 Max. 13.0 15.0 10 13 Unit mA mA mA mA
1.6
4.5
mA
1.6
4.2
mA
4.0 4.0 3.0 3.0
7.0 8.5 6.5 7.0
mA mA mA mA
1.5
4.2
mA
1.5
4.0
mA
60 250 40 70 20 150 5 20 800 0.1
200 500 70 150 55 300 10 40
µA µA µA µA µA µA µA µA µA
1.0 10
µA µA
Rev.3.01
2003.06.20
page 88 of 98
3850 Group (Spec.H)
A-D converter characteristics
Table 32 A-D converter characteristics (spec. H) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Symbol – – tCONV Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Test conditions Limits Min. Typ. Max. 10 ±4 61 Unit bit LSB 2tc(XIN) µs kΩ µA µA
High-speed mode, Middle-speed mode Low-speed mode VREF = 5.0 V 50
RLADDER IVREF II(AD)
Ladder resistor Reference power source input current A-D port input current
VREF “on” VREF “off”
40 35 150 0.5
200 5.0 5.0
Rev.3.01
2003.06.20
page 89 of 98
3850 Group (Spec.A)
A-D converter characteristics
Table 33 A-D converter characteristics (spec. A) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 12.5 MHz, unless otherwise noted) Symbol – – tCONV Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Test conditions Limits Min. Typ. Max. 10 ±4 61 Unit bit LSB 2tc(XIN) µs kΩ µA µA
High-speed mode, Middle-speed mode Low-speed mode VREF = 5.0 V 50
RLADDER IVREF II(AD)
Ladder resistor Reference power source input current A-D port input current
VREF “on” VREF “off”
40 35 150 0.5
200 5.0 5.0
Rev.3.01
2003.06.20
page 90 of 98
3850 Group (Spec.H)
Timing requirements
Table 34 Timing requirements (1) (spec. H) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 20 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 35 Timing requirements (2) (spec. H) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 20 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
Rev.3.01
2003.06.20
page 91 of 98
3850 Group (Spec.A)
Timing requirements
Table 36 Timing requirements (1) (spec. A) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 20 80 32 32 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 37 Timing requirements (2) (spec. A) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD-SCLK1) th(SCLK1-RxD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Limits Min. 20 166 66 66 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
Rev.3.01
2003.06.20
page 92 of 98
3850 Group (Spec.H/A)
Switching characteristics
Table 38 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Typ. Min. tC(SCLK1)/2–30 tC(SCLK1)/2–30 –30 30 30 tC(SCLK2)/2–160 tC(SCLK2)/2–160 200 0 10 10 30 30 30 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig. 78
140
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3: The XOUT pin is excluded.
Table 39 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH (SCLK1) tWL (SCLK1) td (SCLK1-TXD) tv (SCLK1-TXD) tr (SCLK1) tf (SCLK1) tWH (SCLK2) tWL (SCLK2) td (SCLK2-SOUT2) tv (SCLK2-SOUT2) tf (SCLK2) tr (CMOS) tf (CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Test conditions Limits Min. Typ. tC(SCLK1)/2–50 tC(SCLK1)/2–50 –30 50 50 tC(SCLK2)/2–240 tC(SCLK2)/2–240 400 0 20 20 50 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Fig. 78
350
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3: The XOUT pin is excluded.
Rev.3.01
2003.06.20
page 93 of 98
3850 Group (Spec.H/A)
Measurement output pin 100 pF
CMOS output
Fig. 78 Circuit for measuring output switching characteristics
Rev.3.01
2003.06.20
page 94 of 98
3850 Group (Spec.H/A)
tC(CNTR)
CNTR0 CNTR1
tWH(CNTR) 0.8VCC 0.2VCC
tWL(CNTR)
tWH(INT)
tWL(INT) 0.2VCC
INT0 to INT3
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XI N
0.8VCC
SCLK1 SCLK2
tf
tC(SCLK1), tC(SCLK2) tWL(SCLK1), tWL(SCLK2) tWH(SCLK1), tWH(SCLK2) tr 0.2VCC tsu(RxD-SCLK1), tsu(SIN2-SCLK2) 0.8VCC th(SCLK1-RxD), th(SCLK2-SIN2)
RX D SIN2
td(SCLK1-TXD), td(SCLK2-SOUT2)
0.8VCC 0.2VCC tv(SCLK1-TXD), tv(SCLK2-SOUT2)
TX D SOUT2
Fig. 79 Timing diagram
Rev.3.01
2003.06.20
page 95 of 98
3850 Group (Spec.H/A)
PACKAGE OUTLINE
42P4B
EIAJ Package Code SDIP42-P-600-1.78
MMP
JEDEC Code – Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 600mil SDIP
42
22
1
21
Symbol
D
e SEATING PLANE
b1
b
b2
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15°
A
42P2R-A/E
EIAJ Package Code SSOP42-P-450-0.80
42
A1
L
A2
Plastic 42pin 450mil SSOP
JEDEC Code – Weight(g) 0.63
22
Lead Material Alloy 42
e
e1
E
c
b2
HE
E
e1
F
Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.75 – – – 0.9 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 –
Symbol
1 21
A
G
D
A2 e y
b
A1
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
L1
c z Z1 Detail G Detail F
Rev.3.01
2003.06.20
page 96 of 98
L
I2
3850 Group (Spec.H/A)
42S1B-A
EIAJ Package Code WDIP42-C-600-1.78 JEDEC Code – Weight(g)
Metal seal 42pin 600mil DIP
D
42 22
c Symbol A A1 A2 b b1 c D E e e1 L Z A2 Dimension in Millimeters Min Nom Max – – 5.0 – – 1.0 3.44 – – 0.38 0.54 0.46 0.7 0.8 0.9 0.17 0.33 0.25 – – 41.1 – 15.8 – – – 1.778 – – 15.24 3.05 – – – – 3.05 A1 e1 E
1
21
L
A
Z
e
b
b1 SEATING PLANE
Rev.3.01
2003.06.20
page 97 of 98
3850 Group (Spec.H/A)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev.3.01
2003.06.20
page 98 of 98
REVISION HISTORY
Rev. 1.0 Date 03/09/00
3850 Group (Spec.H/A) Data Sheet
Description Summary
Page – First edition issued Font errors are revised.
1.00 Mar. 9, 2000 1.10 Mar. 22, 2000
2.00 Dec. 22, 2000 1 1 6 17 23 27 33 36 38 to 71 41 72 73 73 73 77 79 79 3.00 May. 29, 2002 1 7 8 9 9 9 9 10 13 15 27 30 35 49 51 51 52 53 53 54 55 56 56 56 56
“lnterrupts” of “FEATURES” is revised. Figure 1 is partly revised. Table 3 is partly revised. Explanations of “INTERRUPTS” are partly revised. Figure 20 is partly revised. Figure 24 is partly revised. Explanations of “RESET CIRCUIT” are partly revised. Note 1 into Figure 42 is partly revised. Explanations of “FLASH MEMORY VERSION” are added. Figure 45 is partly revised. “EPROM Version/One Time PROM Version/Flash Memory Version” of “NOTES ON USAGE” is added. “DATA REQUIRED FOR MASK ORDERS” is added. “DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS” is added. “ROM PROGRAMMING METHOD” is added. Table 32 is partly revised. Limit of tw(RESET) into Table 34 is revised. Limit of tw(RESET) into Table 35 is revised. qExplanations of “Spec. A” are added. P2, P4, P6, P16, P18, P22-P26, P42,P43, P47, P82, P84, P87, P89, P91 qPower dissipation is partly revised. Figure 5 is partly revised. Figure 6 is partly revised. Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products of Rev.2.0 is eliminated. Table 4 is added. Table 5 is partly added. Clause name and explanations of “Notes on differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A)” are partly added. Explanations of “CENTRAL PROCESSING UNIT (CPU)” are partly added. Figure 9 is partly revised. Figure 11 is partly revised. sNotes is revised. sNotes is partly added. sNotes on serial I/O is added. Figure 55 is partly revised. Explanations of “FLASH MEMORY MODE” is partly revised. Table 11 is partly revised. Clause name of “Microcomputer Mode and Boot Mode” is revised. Explanations of “Outline Performance (CPU Rewrite Mode)” are partly revised. Figure 58 is partly revised. Figure 59 is partly revised. Explanations of “(1) Operation speed” are partly revised. Explanations of “Software Commands (CPU Rewrite Mode)” are partly revised. Explanations of “qRead Array Command (FF16)” are partly eliminated. Explanations of “qRead Status Register Command (7016)” are partly revised. Explanations of “qProgram Command (4016)” are partly revised.
(1/3)
REVISION HISTORY
Rev. Date Page 3.00 May. 29, 2002 57 57 58 59 60 60 62
3850 Group (Spec.H/A) Data Sheet
Description Summary
63 65 77 77 77 78 78 79 86 3.01 Jun. 20, 2003 2
Explanations of “qErase All Blocks Command (2016/2016)” are partly revised. Explanations of “qBlock Erase Command (2016/D016)” are partly revised. Explanations of “Status Register (SRD)” are partly revised. Figure 62 is partly revised. Explanations of “qROM Code Protect Function (in Parallel I/O Mode)” is partly revised. Figure 63 is partly revised. Contents of “(2) Parallel I/O Mode” are revised. (Explanations, figures, and tables of Pages 61–67 in Rev. 2.0 except “Parallel I/O Mode” and “User ROM and Boot ROM Areas” are eliminated.) Explanations of “(3) Standard serial I/O Mode” are partly revised. Figure 65 is partly revised. Limits of VI (CNVss) into Table 18 are revised. Item of VIL, VIH into Table 19 are eliminated. Figures and tables of Pages 79–84 in Rev. 2.0 are eliminated. Explanations of “A-D converter” are partly eliminated. Clause name and explanations of “Differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A)” are partly revised. “Electric Characteristic Differences Among Mask ROM, Flash Memory, and One Time PROM Version MCUs” is added. Test conditions of Low-speed mode of Icc are partly added. SCLK → SCLK1 Power dissipation is partly revised. In high-speed mode .... 34mW → In high-speed mode Except M38507F8FP/SP ... 32.5mW M38507F8/SP.... 37.5mW Mitsubishi → Renesas Technology Delete the following : Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. Fig.55 System clock generating circuit block diagram (Single-chip mode) Note is partly added. Fig.56 State transition of system clock Note is partly added. the “Mitsubishi MCU Technical information ” Homepage (http://www.infomicom.maec.co.jp/indexe.html) →the “Renesas Technology” Homepage Rom ordering (http://www.renesas.com/eng/rom) Table 28 Electrical characteristics (2) Separate spec.H and spec.A VT+–VT- RXD, SCLK → RXD, SCLK1, SCLK2, SIN2 Table 29 Electrical characteristics (2) Limit of “L” input current (at Pull-up) is added Table 31 Electrical characteristics (3) Limit of power source current is partly revised. Limit of M38507F8FP/SP is added Limit of the high-speed mode [f(XIN)=8MHZ] is added. Limit of the high-speed mode [f(XIN)=8MHZ(in WIT state)] is added. Limit of the middle-speed mode [f(XIN)=12.5MHZ] is added. Limit of the middle-speed mode [f(XIN)=12.5MHZ(in WIT state)] is added.
8 8
49 50 79
85 85,86 86 88
(2/3)
REVISION HISTORY
Rev. Date Page 3.01 Jun. 20, 2003 88
3850 Group (Spec.H/A) Data Sheet
Description Summary
Limit of the high-speed mode [f(XIN)=12.5MHZ(in WIT state)] is partly added. Limit of the high-speed mode [f(XIN)=12.5MHZ, Except M38507F8FP/SP] is revised. Typ. : 7.5 mA → 6.5 mA, Max. : 15 mA → 13 mA Limit of the middle-speed mode [f(XIN)=8MHZ, Except M38507F8FP/SP] is revised. Typ. : 4.0 mA → 3.0 mA, Max. : 7.0 mA → 6.5 mA
(3/3)
工商网监
湘ICP备2023018690号
