M38064MCA-XXXFP

3822 Group (A ver.) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0076-0120Z Rev.1.20 2003.12.24 ●LCD drive control circuit Bias ................................................................................... 1/2, 1/3 Duty ........................................................................... 1/2, 1/3, 1/4 Common output .......................................................................... 4 Segment output ........................................................................ 32 ● 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) ● Power source voltage In high-speed mode (at f(XIN) ≤ 10 MHz) ................................................... 4.5 to 5.5 V (at f(XIN) ≤ 8 MHz) ..................................................... 4.0 to 5.5 V In middle-speed mode (at f(XIN) ≤ 6 MHz) ............... 1.8 to 5.5 V In low-speed mode .................................................... 1.8 to 5.5 V ● Power dissipation In high-speed mode ................................................ 15 mW (std.) (at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C) In low-speed mode ................................................... 24 µW (std.) (at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 3 V, Ta = 25 °C) ● Operating temperature range .................................. – 20 to 85 °C DESCRIPTION The 3822 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 3822 group (A version) has the LCD drive control circuit, an 8channel A-D converter, and a serial I/O as additional functions. The various microcomputers in the 3822 group (A version) include variations of internal memory size and packaging. For details, refer to the section on part numbering. FEATURES ● Basic machine-language instructions ...................................... 71 ● The minimum instruction execution time ........................... 0.4 µs (at f(XIN) = 10 MHz, High-speed mode) ● Memory size ROM ............................................................... 16 K to 48 K bytes RAM ................................................................. 512 to 1024 bytes ● Programmable input/output ports ............................................ 49 ● Software pull-up/pull-down resistors (Ports P0-P7 except port P4 0) ● Interrupts ................................................. 17 sources, 16 vectors (includes key input interrupt) ● Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2 ● Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized) ● A-D converter ................................................. 8-bit ✕ 8 channels APPLICATIONS Camera, household appliances, consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SEG8 SEG9 SEG10 SEG11 P34/SEG12 P35/SEG13 P36/SEG14 P37/SEG15 P00/SEG16 P01/SEG17 P02/SEG18 P03/SEG19 P04/SEG20 P05/SEG21 P06/SEG22 P07/SEG23 P10/SEG24 P11/SEG25 P12/SEG26 P13/SEG27 P14/SEG28 P15/SEG29 P16/SEG30 P17/SEG31 40 39 38 37 36 35 34 M3822XMXA-XXXFP 33 32 31 30 29 28 27 26 25 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/φ Package type : 80P6N-A (80-pin plastic-molded QFP) Fig. 1 M3822XMXA-XXXFP pin configuration Rev.1.20 Dec 24, 2003 page 1 of 57 VL2 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/ADT P56/TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/INT1 P42/INT0 3822 Group (A ver.) PIN CONFIGURATION (TOP VIEW) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG10 SEG11 P34/SEG12 P35/SEG13 P36/SEG14 P37/SEG15 P00/SEG16 P01/SEG17 P02/SEG18 P03/SEG19 P04/SEG20 P05/SEG21 P06/SEG22 P07/SEG23 P10/SEG24 P11/SEG25 P12/SEG26 P13/SEG27 P14/SEG28 P15/SEG29 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 VL1 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 19 20 7 8 9 10 11 12 13 14 15 16 17 18 3 4 1 2 5 6 40 39 38 37 36 35 34 33 32 M3822XMXA-XXXHP 31 30 29 28 27 26 25 24 23 22 21 P16/SEG30 P17/SEG31 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P70/XCOUT P71/XCIN RESET P40 P41/φ P42/INT0 P43/INT1 Fig. 2 M3822XMXA-XXXHP pin configuration Rev.1.20 Dec 24, 2003 page 2 of 57 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/ADT P56/TOUT P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/INT3 P50/INT2 P47/SRDY P46/SCLK P45/TXD P44/RXD Package type : 80P6Q-A (80-pin plastic-molded QFP) A-D converter(8) TOUT CNTR0,CNTR1 XCOUT XCIN RTP0,RTP1 SI/O(8) INT2,INT3 INT0,INT1 Real time port function ADT P7(2) P6(8) 26 27 1 2 34 5 6 7 8 72 73 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 φ P5(8) P4(8) P3(4) P2(8) Key on wake up Rev.1.20 Dec 24, 2003 page 3 of 57 Fig. 3 Functional block diagram 3822 Group (A ver.) FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A) Main Clock Main Clock Output XOUT Input XIN 28 29 Reset Input RESET 25 (5V) VCC 71 (0V) VSS 30 Data bus Clock generating circuit CPU A X ROM RAM LCD display RAM (16 bytes) 80 79 78 VL 1 VL 2 VL 3 XCIN XCOUT φ Sub-Clock Sub-Clock Input Output Y S PCH PCL PS Timer X(16) Timer Y(16) Timer 1(8) Timer 2(8) Timer 3(8) LCD drive control circuit COM0 COM1 COM2 74 COM3 77 76 75 SEG0 SEG1 SEG2 67 SEG3 66 SEG4 65 SEG5 64 SEG6 63 SEG7 62 SEG8 61 SEG9 60 SEG10 59 SEG11 70 69 68 P1(8) P0(8) 55 56 57 58 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 I/O Port P7 I/O Port P6 VREF AVSS (0V) I/O Port P5 I/O Port P4 Input Port P3 I/O Port P2 I/O Port P1 I/O Port P0 3822 Group (A ver.) PIN DESCRIPTION Table 1 Pin description (1) Pin VCC, VSS VREF AVSS Name Power source Analog reference voltage Analog power source Reset input Clock input Clock output Function Function except a port function •Apply voltage of power source to V CC, and 0 V to VSS. (For the limits of VCC, refer to “Recommended operating conditions”). •Reference voltage input pin for A-D converter. •GND input pin for A-D converter. •Connect to VSS. •Reset input pin for active “L”. •Input and output pins for the main clock generating circuit. •Feedback resistor is built in between XIN pin and XOUT pin. •Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •This clock is used as the oscillating source of system clock. RESET XIN XOUT VL1–VL3 COM0–COM3 LCD power source Common output •Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage. •Input 0 – VL3 voltage to LCD. •LCD common output pins. •COM2 and COM3 are not used at 1/2 duty ratio. •COM3 is not used at 1/3 duty ratio. SEG0–SEG11 P00/SEG16– P07/SEG23 Segment output I/O port P0 •LCD segment output pins. •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •LCD segment output pins P10/SEG24– P17/SEG31 P20 – P27 I/O port P1 •I/O direction register allows each port to be individually programmed as either input or output. •Pull-down control is enabled. •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. •Key input (key-on wake-up) interrupt input pins I/O port P2 P34/SEG12 – P37/SEG15 Input port P3 •4-bit input port. •CMOS compatible input level. •Pull-down control is enabled. •LCD segment output pins Rev.1.20 Dec 24, 2003 page 4 of 57 3822 Group (A ver.) Table 2 Pin description (2) Pin P40 P41/φ P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK, P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/TOUT P57/ADT P60/AN0– P67/AN7 I/O port P6 •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. P70/XCOUT, P71/XCIN I/O port P7 •2-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. •Sub-clock generating circuit I/O pins. (Connect a resonator. External clock cannot be used.) Name Input port P4 I/O port P4 •1-bit Input port. •CMOS compatible input level. •7-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. I/O port P5 •8-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. •Real time port function pins •Timer X, Y function pins •Timer 2 output pins •A-D trigger input pins •A-D conversion input pins •Interrupt input pins •Serial I/O function pins •φ clock output pin •Interrupt input pins Function Function except a port function Rev.1.20 Dec 24, 2003 page 5 of 57 3822 Group (A ver.) PART NUMBERING Product M3822 4 M 6 A- XXX FP Package type FP : 80P6N-A package HP : 80P6Q-A package ROM number Omitted in One Time PROM version shipped in blank and EPROM version. When electrical characteristic, or division of identification code using alaphanumeric character A– : A version ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9: A: B: C: 36864 bytes 40960 bytes 45056 bytes 49152 bytes The first 128 bites and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes Fig. 4 Part numbering Rev.1.20 Dec 24, 2003 page 6 of 57 3822 Group (A ver.) GROUP EXPANSION (A VERSION) Mitsubishi plans to expand the 3822 group (A version) as follows: Package 80P6N-A .................................... 0.8 mm-pitch plastic molded QFP 80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP Memory Type Support for Mask ROM version. Memory Size ROM size ........................................................... 16 K to 48 K bytes RAM size ............................................................ 512 to 1024 bytes Memory Expansion Plan ROM size (bytes) 48K M38227MCA 32K M38227M8A 28K M38224M6A 24K 20K M38223M4A 16K 12K 8K 4K 192 256 384 512 RAM size (bytes) 640 768 896 1024 Fig. 5 Memory expansion plan for A version Currently products are listed below. Table 3 List of products for H version Part number M38223M4A-XXXFP M38223M4A-XXXHP M38224M6A-XXXFP M38224M6A-XXXHP M38227M8A-XXXFP M38227M8A-XXXHP M38227MCA-XXXFP M38227MCA-XXXHP ROM size (bytes) ROM size for User in ( ) 16384 (16254) 24576 (24446) 32768 (32638) 49152 (49022) RAM size (bytes) 512 640 Package 80P6N-A 80P6Q-A 80P6N-A 80P6Q-A 80P6N-A 80P6Q-A 80P6N-A 80P6Q-A Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Remarks As of Sep. 2002 1024 Rev.1.20 Dec 24, 2003 page 7 of 57 3822 Group (A ver.) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3822 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 6 740 Family CPU register structure Rev.1.20 Dec 24, 2003 page 8 of 57 3822 Group (A ver.) On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 7 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.1.20 Dec 24, 2003 page 9 of 57 3822 Group (A ver.) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – Rev.1.20 Dec 24, 2003 page 10 of 57 3822 Group (A ver.) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16. b7 b0 CPU mode register (CPUM (CM) : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN –XCOUT oscillating function Main clock (X IN – XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN )/2 (high-speed mode) 1 : f(XIN )/8 (middle-speed mode) Internal system clock selection bit 0 : XIN –XOUT selected (middle-/high-speed mode) 1 : XCIN –XCOUT selected (low-speed mode) Fig. 8 Structure of CPU mode register Rev.1.20 Dec 24, 2003 page 11 of 57 3822 Group (A ver.) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function register (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special Page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 084016 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 FFFE16 Reserved ROM area FFFF16 FFDC16 Interrupt vector area Special page ROM FF0016 ZZZZ16 YYYY16 Reserved ROM area (128 bytes) Not used Reserved area XXXX16 RAM 000016 SFR area 004016 005016 010016 LCD display RAM area Zero page Fig. 9 Memory map diagram Rev.1.20 Dec 24, 2003 page 12 of 57 3822 Group (A ver.) 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 output control register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 (P7) 000F16 Port P7 direction register (P7D) 001016 001116 001216 001316 001416 001516 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register (TB/RB) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIO1CON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16 002016 Timer X (low) (TXL) 002116 Timer X (high) (TXH) 002216 Timer Y (low) (TYL) 002316 Timer Y (high) (TYH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 φ output control register (CKOUT) 002B16 002C16 002D16 002E16 002F 16 003016 003116 003216 003316 003416 A-D control register (ADCON) 003516 A-D conversion register (AD) 003616 003716 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F 16 Interrupt control register 2(ICON2) Fig. 10 Memory map of special function register (SFR) Rev.1.20 Dec 24, 2003 page 13 of 57 3822 Group (A ver.) I/O PORTS Direction Registers (ports P2, P41-P47, and P5-P7) The 3822 group has 49 programmable I/O pins arranged in seven I/O ports (ports P0–P2, P41–P4 7 and P5-P7). The I/O ports P2, P41–P47 and P5-P7 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. b7 b0 PULL register A (PULLA: address 001616 ) P00–P07 pull-down P10–P17 pull-down P20–P27 pull-up P34–P37 pull-down P70, P71 pull-up Not used (return “0” when read) b7 b0 PULL register B (PULLB : address 001716) P41–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60–P63 pull-up P64–P67 pull-up Not used (return “0” when read) 0: Disable 1: Enable Direction Registers (ports P0 and P1) Ports P0 and P1 have direction registers which determine the input/output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When “0” is written to the bit 0 of a direction register, that port becomes an input port. When “1” is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used. Note: The contents of PULL register A and PULL register B do not affect ports programmed as the output port. Fig. 11 Structure of PULL register A and PULL register B Ports P3 and P40 These ports are only for input. Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL register B (address 0017 16), ports except for port P40 c an control either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Rev.1.20 Dec 24, 2003 page 14 of 57 3822 Group (A ver.) Table 6 List of I/O port function Pin P00/SEG16– P07/SEG23 P10/SEG24– P17/SEG31 Name Port P0 Input/Output Input/output, individual ports I/O Format CMOS compatible input level CMOS 3-state output Non-Port Function LCD segment output Related SFRs PULL register A Segment output enable register Diagram No. (1) Port P1 P20–P27 Port P2 Input/output, individual bits Input CMOS compatible input level CMOS 3-state output CMOS compatible input level Key input (key-on wake-up) interrupt input LCD segment output PULL register A Interrupt control register 2 PULL register A Segment output enable register (2) P34/SEG12– P37/SEG15 Port P3 (3) P40 P41/φ P42/INT0, P43/INT1 P44/RXD P45/TXD P46/SCLK P47/SRDY P50/INT2, P51/INT3 P52/RTP0, P53/RTP1 P54/CNTR0 P55/CNTR1 P56/TOUT Port P4 Input CMOS compatible input level CMOS compatible input level CMOS 3-state output φ clock output External interrupt input PULL register B φ output control register PULL register B Interrupt edge selection register PULL register B Serial I/O control register Serial I/O status register UART control register PULL register B Interrupt edge selection register PULL register B Timer X mode register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B A-D control register (4) Input/output, individual bits (5) (2) Serial I/O function I/O (6) (7) (8) (9) (2) Port P5 Input/output, individual bits CMOS compatible input level CMOS 3-state output External interrupt input Real time port function output Timer X function I/O Timer Y function input Timer 2 function output A-D trigger input Port P6 Input/output, individual bits Input/output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output LCD segment output A-D conversion input (10) (11) (12) (13) P57/ADT P60/AN0– P67/AN7 P70/XCOUT P71/XCIN COM0–COM3 SEG0–SEG11 (12) (14) Port P7 Sub-clock generating circuit I/O PULL register A CPU mode register LCD mode register (15) (16) (17) (18) Common Segment Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections. 2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Especially, power source current may increase during execution of the STP and WIT instructions. Fix the unused input pins to “H” or “L” through a resistor. Rev.1.20 Dec 24, 2003 page 15 of 57 3822 Group (A ver.) (1) Ports P0, P1 VL2/VL3 (2) Ports P2, P42, P43, P50, P51 Pull-up control VL1/VSS Segment output enable bit (Note) Direction register Direction register Data bus Data bus Port latch Port latch Key input (Key-on wake-up) interrupt input INT0–INT3 interrupt input Pull-down control Segment output enable bit Note: Bit 0 of direction register. (3) Ports P34–P37 VL2/VL3 (4) Port P40 Data bus VL1/VSS Data bus Pull-down control Segment output enable bit (5) Port P41 Pull-up control (6) Port P44 Pull-up control Serial I/O enable bit Receive enable bit Direction register Direction register Data bus Port latch Data bus Port latch φ output control bit φ Serial I/O input Fig. 12 Port block diagram (1) Rev.1.20 Dec 24, 2003 page 16 of 57 3822 Group (A ver.) (7) Port P45 Pull-up control P45/TxD P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register (8) Port P46 Serial I/O clocksynchronized selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Pull-up control Data bus Port latch Data bus Port latch Serial I/O output Serial I/O clock output Serial I/O clock input (9) Port P47 Pull-up control (10) Ports P52, P53 Pull-up control Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O ready output Real time port control bit Data for real time port (11) Port P54 (12) Ports P55, P57 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Timer X operating mode bit (Pulse output mode selection) Timer output CNTR0 interrupt input CNTR1 interrupt input A-D trigger interrupt input Fig. 13 Port block diagram (2) Rev.1.20 Dec 24, 2003 page 17 of 57 3822 Group (A ver.) (13) Port P56 Pul-up control (14) Port P6 Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch TOUT output control bit Timer output A-D conversion input Analog input pin selection bit (15) Port P70 Port XC switch bit + Pull-up control Port XC switch bit Direction register (16) Port P71 Port XC switch bit + Pull-up control Port XC switch bit Direction register Data bus Port latch Data bus Port latch Oscillation circuit Port P71 Port XC switch bit Sub-clock generating circuit input (17) COM0–COM3 (18) SEG0–SEG11 VL2/VL3 VL3 VL1/VSS VL2 VL1 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. Fig. 14 Port block diagram (3) Rev.1.20 Dec 24, 2003 page 18 of 57 3822 Group (A ver.) INTERRUPTS Interrupts occur by seventeen sources: eight external, eight internal, and one software. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. ■Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control regsiter (address 3416) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ➀Set the corresponding interrupt enable bit to “0” (disabled). ➁Set the interrupt edge select bit or the interrupt source select bit. ➂Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the corresponding interrupt enable bit to “1” (enabled). Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. Table 7 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Low Reset (Note 2) 1 FFFD16 FFFC16 2 INT0 FFFB16 FFFA16 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 INT2 INT3 Key input (Key-on wake-up) ADT 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transmit shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At falling of conjunction of input level for port P2 (at input mode) At falling of ADT input Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O is selected Valid when serial I/O is selected 6 7 8 9 10 11 12 13 14 15 16 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (Valid at falling) Valid when ADT interrupt is selected, External interrupt (Valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt A-D conversion BRK instruction 17 FFDD16 FFDC16 At completion of A-D conversion At BRK instruction execution Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Rev.1.20 Dec 24, 2003 page 19 of 57 3822 Group (A ver.) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 15 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A 16) INT0 INT1 INT2 INT3 interrupt edge selection bit interrupt edge selection bit interrupt edge selection bit interrupt edge selection bit Not used (return “0” when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C 16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D 16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit ADT/AD conversion interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E 16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F 16 ) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 16 Structure of interrupt-related registers Rev.1.20 Dec 24, 2003 page 20 of 57 3822 Group (A ver.) Key Input Interrupt (Key-on wake-up) A Key-on wake-up interrupt request is generated by applying a falling edge to any pin of port P2 that have been set to input mode. In other words, it is gener1ated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P23. Port PXX “L” level output PULL register A bit 2 = “1” ✽ ✽✽ Port P27 direction register = “1” Key input interrupt request Port P27 latch P27 output ✽ Port P26 direction register = “1” ✽✽ Port P26 latch P26 output ✽ Port P25 direction register = “1” ✽✽ Port P25 latch P25 output Port P24 direction register = “1” ✽ ✽✽ Port P24 latch P24 output ✽ Port P23 direction register = “0” ✽✽ P23 input Port P23 latch Port P2 Input reading circuit ✽ Port P22 direction register = “0” ✽✽ P22 input Port P22 latch ✽ Port P21 direction register = “0” ✽✽ P21 input Port P21 latch ✽ Port P20 direction register = “0” ✽ P20 input Port P20 latch ✽ P-channel transistor for pull-up ✽✽ CMOS output buffer Fig. 17 Connection example when using key input interrupt and port P2 block diagram Rev.1.20 Dec 24, 2003 page 21 of 57 3822 Group (A ver.) TIMERS The 3822 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Real time port control bit “1” QD P52 P52 direction register Latch “0” P52 latch Real time port control bit “1” QD “0” P53 latch f(XIN)/16 (f(XIN)/16 in low-speed mode✽) Timer X operatCNT R0 active edge switch bit ing mode bits “00”,“01”,“11” “0” Data bus P52 data for real time port P53 P53 direction register Latch P53 data for real time port Real time port control bit “0” “1” Timer X stop control bit Timer X (low) latch (8) Timer X (low) (8) Timer X mode register write signal Timer X write control bit Timer X (high) latch (8) Timer X (high) (8) P54/CNTR0 “10” “1” Pulse width measurement mode CNT R0 active edge switch bit “0” “1” P54 latch Pulse output mode Falling edge detection f(XIN)/16 (f(XCIN)516 in low-speed mode✽) Timer X interrupt request CNT R0 interrupt request Pulse output mode QS T Q Rising edge detection Period measurement mode P54 direction register Timer Y operating mode bits “00”,“01”,“10” Pulse width HL continuously measurement mode CNT R1 interrupt request “11” P55/CNTR1 CNT R1 active edge switch bit “0” “1” Timer Y stop control bit “00”,“01”,“11” Timer Y (low) latch (8) Timer Y (low) (8) Timer Y (high) latch (8) Timer Y (high) (8) “10” Timer Y operating mode bits Timer Y interrupt request f(XIN)/16 (f(XCIN)/16 in low-speed mode]) Timer 1 count source selection bit “0” Timer 1 latch (8) XCIN “1” Timer 1 (8) Timer 2 count source selection bit Timer 2 latch (8) “0” Timer 2 (8) f(XIN)/16 (f(XCIN)/16 in low-speed mode✽) Timer 2 write control bit Timer 1 interrupt request Timer 2 interrupt request “1” TOUT output TOUT output active edge control bit TOUT output switch bit control bit “0” QS P56/TOUT T “1” Q P56 latch P56 direction register f(XIN)/16(f(XCIN)/16 in low-speed ✽ “0” Timer 3 latch (8) Timer 3 (8) mode✽) Internal clock φ =XCIN /2 “1” Timer 3 count source selection bit Timer 3 interrupt request Fig. 18 Timer block diagram Rev.1.20 Dec 24, 2003 page 22 of 57 3822 Group (A ver.) Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse Output Mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to output mode. qReal time port control While the real time port function is valid, data for the real time port are output from ports P5 2 a nd P5 3 e ach time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from “0” to “1”, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. s Note on CNTR 0 i nterrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P54 direction register to input mode. b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P52 data for real time port P53 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNT R0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop (4) Pulse Width Measurement Mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P54 direction register to input mode. qTimer X write control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, when writing in the timer latch at the timer underflow, the value is set in the timer and the latch at one time. Additionally, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Fig. 19 Structure of timer X mode register Rev.1.20 Dec 24, 2003 page 23 of 57 3822 Group (A ver.) Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). b7 b0 Timer Y mode register (TYM : address 002816) Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNT R1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNT R1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop (2) Period Measurement Mode CNTR 1 i nterrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 p in input signal is found by CNTR1 interrupt. When using a timer in this mode, set the corresponding port P55 direction register to input mode. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. Fig. 20 Structure of timer Y mode register (4) Pulse Width HL Continuously Measurement Mode CNTR 1 i nterrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P55 direction register to input mode. sNote on CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. Rev.1.20 Dec 24, 2003 page 24 of 57 3822 Group (A ver.) Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer, rewrite the value of timer whenever the count source is changed. qTimer 2 write control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. qTimer 2 output control When the timer 2 (T OUT) is output enabled, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the port shared with the TOUT pin to the output mode. b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (return “0” when read) Note: Internal clock φ is f(XCIN)/2 in the low-speed mode. sNotes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer . If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 21 Structure of timer 123 mode register Rev.1.20 Dec 24, 2003 page 25 of 57 3822 Group (A ver.) SERIAL I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Address 001816 Receive buffer register Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P44/RXD Receive shift register Shift clock P46/SCLK Serial I/O clock selection bit Frequency division ratio 1/(n+1) Baud rate generator BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY1 F/F Falling-edge detector 1/4 Address 001C16 Clock control circuit Shift clock P45/TXD Transmit shift register Transmit buffer reg ister Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916 Address 001816 Data bus Serial I/O status register Fig. 22 Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Serial output TXD Serial input RXD Receive enable signal SRDY Write signal to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 23 Operation of clock synchronous serial I/O function Rev.1.20 Dec 24, 2003 page 26 of 57 3822 Group (A ver.) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 OE P44/RXD STdetector 7 bits 8 bits Receive buffer register Serial I/O control register Address 001A16 Character length selection bit Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O synchronous clock selection bit P46/SCLK BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Transmit shift register Address 001816 Data bus Fig. 24 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 ✽Generated TSC=1✽ SP at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=1 Serial input RXD ST D0 D1 ST D0 RBF=0 RBF=1 SP SP D1 Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 25 Operation of UART serial I/O function Rev.1.20 Dec 24, 2003 page 27 of 57 3822 Group (A ver.) [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O Status Register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE. Writing “0” to the serial I/O enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O Control Register (SIOCON)] 001A16 The serial I/O control register contains eight control bits for the serial I/O function. [UART Control Register (UARTCON) ]001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P45/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. sNotes on serial I/O When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ➀Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁Set the transmit enable bit to “1”. ➂Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the serial I/O transmit interrupt enable bit to “1” (enabled). Rev.1.20 Dec 24, 2003 page 28 of 57 3822 Group (A ver.) b7 b0 Serial I/O status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Not used (returns “1” when read) b7 b0 Serial I/O control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O synchronization clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronized serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronized serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44–P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) b7 b0 UART control regi ster (UART CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (ST PS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) Fig. 26 Structure of serial I/O control registers Rev.1.20 Dec 24, 2003 page 29 of 57 3822 Group (A ver.) A-D CONVERTER [A-D Conversion Register (AD)] 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. b7 b0 A-D control register (ADCON : address 003416) Analog input pin selection bits 0 0 0 : P60/AN0 0 0 1 : P61/AN1 0 1 0 : P62/AN2 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : ON during conversion 1 : Always ON AD external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Interrupt source selection bit 0 : Interrupt request at A-D conversion completed 1 : Interrupt request at ADT input falling Not used (returns “0” when read) [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 controls the transistor which breaks the through current of the resistor ladder. When bit 5, which is the AD external trigger valid bit, is set to “1”, this bit enables A-D conversion even by a falling edge of an ADT input. Set ports which share with ADT pins to input when using an A-D external trigger. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports P67/AN7–P60/ AN0, and inputs it to the comparator. Fig. 27 Structure of A-D control register [Comparator and Control Circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500 kHz during A-D conversion. Use the clock divided from the main clock XIN as the internal clock φ. Data bus b7 A-D control register P57/ADT 3 b0 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 A-D control circuit ADT/A-D interrupt request Channel selector Comparator A-D conversion register 8 Resistor ladder AVSS VREF Fig. 28 A-D converter block diagram Rev.1.20 Dec 24, 2003 page 30 of 57 3822 Group (A ver.) LCD DRIVE CONTROL CIRCUIT The 3822 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. q LCD display RAM qSegment output enable register q LCD mode register q Selector q Timing controller q Common driver q Segment driver q Bias control circuit A maximum of 32 segment output pins and 4 common output pins can be used. Up to 128 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. Table 8 Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 64 dots or 8 segment LCD 8 digits 96 dots or 8 segment LCD 12 digits 128 dots or 8 segment LCD 16 digits b7 b0 Segment output enable register (SEG : address 003816) Segment output enable bit 0 0 : Input port P34–P37 1 : Segment output SEG12–SEG15 Segment output enable bit 1 0 : I/O port P00,P01 1 : Segment output SEG16, SEG17 Segment output enable bit 2 0 : I/O port P02–P07 1 : Segment output SEG18–SEG23 Segment output enable bit 3 0 : I/O port P10,P11 1 : Segment output SEG24, SEG25 Segment output enable bit 4 0 : I/O port P12 1 : Segment output SEG26 Segment output enable bit 5 0 : I/O port P13–P17 1 : Segment output SEG27–SEG31 Not used (returns “0” when read) (Do not write “1” to this bit.) b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits 0 0 : Not used 0 1 : 2 (use COM0, COM1) 1 0 : 3 (use COM0–COM2) 1 1 : 4 (use COM0–COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Not used (returns “0” when read) (Do not write “1” to this bit) LCD circuit divider division ratio selection bits 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 (or f(XCIN)/8192 in low-speed mode) Note: LCDCK is a clock for a LCD timing controller. Fig. 29 Structure of segment output enable register and LCD mode register Rev.1.20 Dec 24, 2003 page 31 of 57 Rev.1.20 LCD enable bit 3822 Group (A ver.) Fig. 30 Block diagram of LCD controller/driver Dec 24, 2003 Address 004F16 LCD display RAM LCD circuit divider division ratio selection bits 2 Bias control bit “1” 2 LCD divider LCDCK count source selection bit “0” f(XCIN)/32 f(XIN)/8192( or f(XCIN)/8192 in low-speed mode) Duty ratio selection bits Selector Selector Timing controller LCDCK Segment Segment driver driver Data bus page 32 of 57 Bias control Common Common Common Common driver driver driver driver Address 004016 Address 004116 Selector Selector Selector Selector Segment driver Segment Segment Segment driver driver driver SEG0 P16/SEG30 P17/SEG31 SEG1 SEG2 SEG3 P34/SEG12 VSS VL1 VL2 VL3 COM0 COM1 COM2 COM3 3822 Group (A ver.) Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1–VL3), apply the voltage shown in Table 9 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 9 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD 1/2 bias VL3=VLCD VL2=VL1=1/2 VLCD Voltage value Common Pin and Duty Ratio Control The common pins (COM0–COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). Note 1: V LCD i s the maximum value of supplied voltage for the LCD panel. Table 10 Duty ratio control and common pins used Duty ratio 2 3 4 Duty ratio selection bit Bit 1 0 1 1 Bit 0 1 0 1 Common pins used COM0, COM1 (Note 1) COM0–COM2 (Note 2) COM0–COM3 Notes1: COM2 and COM3 are open. 2: COM3 is open. Contrast control Contrast control VL3 R1 VL2 R2 VL1 R3 VL3 R4 VL2 VL1 R5 R1 = R2 = R3 1/3 bias 1/2 bias R4 = R5 Fig. 31 Example of circuit at each bias Rev.1.20 Dec 24, 2003 page 33 of 57 3822 Group (A ver.) LCD Display RAM Address 004016 to 004F16 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK) = (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) (duty ratio) Frame frequency = B it 7 Address 6 5 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG31 4 3 2 1 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 0 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 Fig. 32 LCD display RAM map Rev.1.20 Dec 24, 2003 page 34 of 57 3822 Group (A ver.) Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 COM1 ON COM0 OFF COM2 COM1 ON COM0 OFF COM2 VL3 VL2=VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 33 LCD drive waveform (1/2 bias) Rev.1.20 Dec 24, 2003 page 35 of 57 3822 Group (A ver.) Internal logic LCDCK timing 1/4 duty Voltage level COM0 VL3 VL2 VL1 VSS COM1 COM2 COM3 SEG0 VL3 VSS OFF COM3 COM2 COM1 ON COM0 COM3 OFF COM2 COM1 ON COM0 1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS SEG0 ON COM0 1/2 duty COM0 COM1 SEG0 OFF COM2 COM1 ON COM0 OFF COM2 COM1 ON COM0 OFF COM2 VL3 VL2 VL1 VSS VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 Fig. 34 LCD drive waveform (1/3 bias) Rev.1.20 Dec 24, 2003 page 36 of 57 3822 Group (A ver.) φ CLOCK SYSTEM OUTPUT FUNCTION The internal system clock φ can be output from port P41 by setting the φ output control register. Set bit 1 of the port P4 direction register to “1” when outputting φ clock. b7 b0 φ output control register (CKOUT : address 002A16) φ output control bit 0 : port function 1 : φ clock output Not used (return “0” when read) Fig. 35 Structure of φ output control register Rev.1.20 Dec 24, 2003 page 37 of 57 3822 Group (A ver.) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between VCC(min.) and 5.5 V, and the quartz-crystal oscillator should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 ( low-order byte). Make sure that the reset input voltage meets VIL s pec. when a power source voltage passes VCC(min.). Power on Power source voltage 0V Reset input voltage 0V VIL spec. RESET VCC RESET VCC Power source voltage detection circuit Fig. 36 Reset Circuit Example XIN φ RESET Internal reset Reset address from vector table Address Data ? ? ? ? FFFC ADL FFFD ADH, ADL ADH SYNC XIN : about 8000 cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) =8•f(φ) 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 37 Reset Sequence Rev.1.20 Dec 24, 2003 page 38 of 57 3822 Group (A ver.) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) Port P0 direction register Port P1 direction register Port P2 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register PULL register A PULL register B Sirial I/O status register Sirial I/O control register UART control register Timer X(Low) Timer X(High) Timer Y(Low) Timer Y(High) Timer 1 Timer 2 Timer 3 Timer X mode register Timer Y mode register Timer 123 mode register φ output control register A-D control register Segment output enable register LCD mode register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter Address 000116 000316 000516 000916 000B16 000D16 000F16 001616 001716 001916 001A16 001B16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 003416 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) ✕ 0 1 0 0 1 1 1 0 0 0 Register Contents 0016 0016 0016 0016 0016 0016 0 0 1 0016 0 1 0016 0 0 0 0016 0 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 0016 0 0 1 0016 0016 0016 0 0 1 0016 0016 0016 0016 ✕✕✕✕1 ✕✕ Contents of address FFFD16 Contents of address FFFC16 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Note: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕: undefined Fig. 38 Initial status of microcomputer after reset Rev.1.20 Dec 24, 2003 page 39 of 57 3822 Group (A ver.) CLOCK GENERATING CIRCUIT The 3822 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Oscillation Control (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and X IN a nd X CIN o scillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either X IN o r X CIN d ivided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows timer for the clock circuit oscillation to stabilize. (2) Wait Mode Frequency Control (1) Middle-speed Mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state before the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. (2) High-speed Mode The internal clock φ is half the frequency of XIN. (3) Low-speed Mode q The internal clock φ is half the frequency of XCIN. q A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN a nd X CIN o scillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). XCIN XCOUT Rf CCIN Rd CCOUT XIN XOUT CIN COUT Fig. 39 Ceramic resonator circuit example XCIN XCOUT Rf CCIN Rd CCOUT XIN XOUT Open External oscillation circuit VCC VSS Fig. 40 External clock input circuit Rev.1.20 Dec 24, 2003 page 40 of 57 3822 Group (A ver.) XCIN XCOUT “1” “0” Port XC switch bit XIN XOUT Internal system clock selection bit (Note) Timer 1 count source selection bit “1” Timer 1 “0” Timer 2 count source selection bit “0” Timer 2 “1” Low-speed mode “1” 1/2 “0” Middle-/High-speed mode 1/4 1/2 Main clock division ratio selection bit “1” Middle-speed mode “0” High-speed mode or Low-speed mode Main clock stop bit Timing φ (Internal system clock) Q S R WIT instruction S R Q Q S STP instruction R STP instruction Reset Interrupt disable flag I Interrupt request Note : When using the low-speed mode, set the port XC switch bit to “1” . Fig.41 Clock generating circuit block diagram Rev.1.20 Dec 24, 2003 page 41 of 57 3822 Group (A ver.) Reset Middle-spe ed mode (f(φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz sto pped) CM6 “1” “0” High-sp eed mode (f(φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz sto pped) CM ”6 “1 M C ” “1 4 ” “0 ” “0 C “0 M4 CM” “1 6 ” “1 ” “0 ” “0” CM4 “1” Middle-spe ed mode (f(φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillatin g) CM6 “1” “0” High-sp eed mode (f(φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillatin g) “0” CM7 “1” Low-spee d mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz sele cted) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillatin g) CM6 “1” “0” L ow-speed mode (f(φ) =16 kHz) CM7 = 1 (32 kHz sele cted) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillatin g) CM7 “1” “0” CM4 “1” “0” b7 b4 CPU mode register (CPUM : address 003B16) CM ”6 “1 CM ” “1 5 ” “0 ” “0 C “0 M5 CM” “1 6 ” “1 ” “0 ” “0” “0” Low-speed mode (f(φ) = 1 6 kHz) CM7 = 1 (32 kHz sele cted) CM6 = 1 (Middle-speed) CM5 = 1 (8 MHz stopped ) CM4 = 1 (32 kHz oscillatin g) CM6 “1” L ow-speed mode (f(φ) =16 kHz) “0” CM7=1(3 2 kHz selected) CM6=0(High -spe ed) CM5=1(8 MHz stop ped) CM4=1(3 2 kHz oscillating) CM4 : Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM5 : Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : T he all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : T imer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode. 7 : T he example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 42 State transitions of system clock Rev.1.20 CM5 “1” Dec 24, 2003 page 42 of 57 CM5 “1” 3822 Group (A ver.) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is at least 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion. Interrupt The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN frequency. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the TXD pin after transmission is completed. Rev.1.20 Dec 24, 2003 page 43 of 57 3822 Group (A ver.) NOTES ON USE Countermeasures against noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). q Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise XIN XOUT VSS N.G. Fig. 44 Wiring for clock I/O pins XIN XOUT VSS O.K. Noise Reset circuit VSS N.G. RESET VSS (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Reset circuit VSS RESET VSS VCC VCC O.K. Fig. 43 Wiring for the RESET pin ➁ Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. VSS VSS N.G. O.K. Fig. 45 Bypass capacitor across the VSS line and the VCC line Rev.1.20 Dec 24, 2003 page 44 of 57 3822 Group (A ver.) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful especially when range of votage and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines (4) Analog input The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A-D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A-D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A-D conversion accuracy, and the amount of -proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evaluation for each product of every after confirming product specification. (6) Wiring to VPP pin of One Time PROM version Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the VSS pin. Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM version, the microcomputer operates correctly. q Reason The VPP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the built-in PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. Microcomputer Mutual inductance M Large current GND ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 47 Wiring for the VPP pin of One Time PROM About 5kΩ P40/VPP XIN XOUT VSS VSS Do not cross CNTR XIN XOUT VSS Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One TIme PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. N.G. Fig. 46 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently Rev.1.20 Dec 24, 2003 page 45 of 57 3822 Group (A ver.) DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form✽ 2.Mark Specification Form✽ 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk ✽For the mask ROM confirmation and the mark specifications, ref e r t o t h e “ R e n e s a s Te c h n o l o g y ” H o m e p a g e ( h t t p : / / www.renesas.com/en/rom/). Rev.1.20 Dec 24, 2003 page 46 of 57 3822 Group (A ver.) Table 11 Absolute maximum ratings (A version) Symbol VCC VI Parameter Power source voltage Input voltage P00–P07, P10–P17, P20–P27, P34–P37, P40–P47, P50–P57 P60–P67, P70, P71 Input voltage Input voltage Input voltage Input voltage Output voltage VL1 VL2 VL3 RESET, XIN P00–P07, P10–P17 Conditions All voltages are based on VSS. Output transistors are cut off. Ratings –0.3 to 6.5 –0.3 to VCC +0.3 Unit V V VI VI VI VI VO VO VO VO VO Pd Topr Tstg Output voltage P34–P37 Output voltage P20–P27, P41–P47,P50–P57, P60–P67, P70, P71 Output voltage SEG0–SEG11 Output voltage XOUT Power dissipation Operating temperature Storage temperature At output port At segment output At segment output –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 –0.3 to VL3 –0.3 to VCC +0.3 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 V V V V V V V V V V mW °C °C Ta = 25°C Table 12 Recommended operating conditions (A version) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC Power source voltage (Note 1) Parameter f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz f(XIN) = 4 MHz Middle-speed mode f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Low-speed mode When oscillation starts (Note 2) High-speed mode Limits Min. Typ. 4.5 5.0 4.0 5.0 3.0 5.0 2.0 5.0 3.0 5.0 2.0 5.0 1.8 5.0 1.8 5.0 0.15 ✕ f + 1.3 0 2.0 0 AVSS VCC VCC Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V V V VSS VREF AVSS VIA Power source voltage A-D conversion reference voltage Analog power source voltage Analog input voltage AN0–AN7 Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D converter. 2: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator will require some conditions of oscillation. f : Means an oscillation frequency (MHz) of an oscillator. If it is 8, substitute 8 for “f”. Rev.1.20 Dec 24, 2003 page 47 of 57 3822 Group (A ver.) Table 13 Recommended operating conditions (A version) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VIH VIH VIH VIH VIL VIL VIL VIL “H” input voltage “H” input voltage “H” input voltage “H” input voltage “L” input voltage “L” input voltage “L” input voltage “L” input voltage Parameter P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,P56,P60–P67,P70,P71 (CM4= 0) P20–P27, P42–P44,P46,P50, P51, P54, P55, P57 RESET XIN P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53, P56,P60–P67,P70,P71 (CM4= 0) P20–P27, P42–P44,P46,P50, P51, P54, P55, P57 RESET XIN Min. 0.7VCC 0.8VCC 0.8VCC 0.8VCC 0 0 0 0 Limits Typ. Max. VCC VCC VCC VCC 0.3 VCC 0.2 VCC 0.2 VCC 0.2 VCC Unit V V V V V V V V Rev.1.20 Dec 24, 2003 page 48 of 57 3822 Group (A ver.) Table 14 Recommended operating conditions (A version) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR0) f(CNTR1) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “H” peak output current “H” peak output current “L” peak output current “L” peak output current “H” average output current “H” average output current Parameter P00–P07, P10–P17, P20–P27 (Note 1) P41–P47, P50–P57, P60–P67, P70, P71 (Note 1) P00–P07, P10–P17, P20–P27 (Note 1) P41–P47, P50–P57, P60–P67, P70, P71 (Note 1) P00–P07, P10–P17, P20–P27 (Note 1) P41–P47, P50–P57, P60–P67, P70, P71 (Note 1) P00–P07, P10–P17, P20–P27 (Note 1) P41–P47, P50–P57, P60–P67, P70, P71 (Note 1) P00–P07, P10–P17 (Note 2) P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 (Note 2) P00–P07, P10–P17 (Note 2) P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 (Note 2) P00–P07, P10–P17 (Note 3) Min. Limits Typ. Max. –40 –40 40 40 –20 –20 20 20 –2 –5 5 10 –1.0 –2.5 2.5 5.0 5.0 2 ✕ VCC – 4 VCC 5 ✕ VCC – 8 10.0 4 ✕ VCC – 8 2 ✕ VCC 10.0 8.0 6.0 50 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz f(XIN) P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 (Note 3) “L” average output current P00–P07, P10–P17 (Note 3) P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 “L” average output current (Note 3) (4.5 V ≤ VCC ≤ 5.5 V) Input frequency for timers X and Y (duty cycle 50%) (4.0 V ≤ VCC ≤ 4.5 V) (2.0 V ≤ VCC ≤ 4.0 V) (VCC ≤ 2.0 V) High-speed mode Main clock input oscillation frequency (4.5 V ≤ VCC ≤ 5.5 V) (duty cycle 50%) (Note 4) High-speed mode (4.0 V ≤ VCC ≤ 4.5 V) High-speed mode (2.0 V ≤ VCC ≤ 4.0 V) Middle-speed mode (Note 6) (3.0 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 6) (2.0 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 6) Sub-clock input oscillation frequency (duty cycle 50%) (Notes 5, 6) 32.768 f(XCIN) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the A-D converter is used, refer to the recommended operating condition for A-D converter. 5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 6: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator will require some conditions of oscillation. Rev.1.20 Dec 24, 2003 page 49 of 57 3822 Group (A ver.) Table 15 Electrical characteristics (A version) (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter “H” output voltage P00–P07, P10–P17 “H” output voltage P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 (Note) Test conditions IOH = –2.5 mA IOH = –0.6 mA VCC = 2.5 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V Min. VCC–2.0 VCC–1.0 VCC–2.0 VCC–0.5 VCC–1.0 2.0 0.5 1.0 2.0 0.5 1.0 0.5 0.5 RESET : VCC = 2.2 V to 5.5 V VI = VCC Pull-downs “off” VCC = 5 V, VI = VCC Pull-downs “on” VCC = 3 V, VI = VCC Pull-downs “on” VI = VCC 5.0 VI = VCC VI = VCC VI = VSS VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” VCC = 3 V, VI = VSS Pull-ups “on” VI = VSS VI = VSS µA µA µA µA µA µA µA µA µA 0.5 5.0 30 6.0 70 25 140 45 Limits Typ. Max. Unit V V V V V V V V V V V V V V µA µA µA VOH VOH VOL “L” output voltage P00–P07, P10–P7 VOL “L” output voltage P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 (Note) Hysteresis INT0–INT3, ADT, CNTR0, CNTR1, P20–P27 Hysteresis Hysteresis SCLK, RXD RESET VT+ – VT– VT+ – VT– VT+ – VT– IIH “H” input current P00–P07, P10–P17, P34–P37 IIH “H” input current P20–P27, P40–P47, P50–P57, P60–P67, P70, P71 (Note) “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P17, P34–P37,P40 “L” input current P20–P27, P41–P47, P50–P57, P60–P67, P70, P71 (Note) IIH IIH IIL IIL 5.0 4.0 –5.0 –5.0 –30 –6.0 –70 –25 –140 –45 –5.0 –4.0 IIL IIL “L” input current “L” input current RESET XIN Note: When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. Rev.1.20 Dec 24, 2003 page 50 of 57 3822 Group (A ver.) Table 16 Electrical characteristics (A version) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VRAM Parameter RAM retention voltage Test conditions At clock stop mode • High-speed mode, VCC = 5 V f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A-D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A-D converter stopped ICC Power source current • Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C 0.1 1.0 10 µA µA 4.0 8.0 µA 8.0 16 µA 5.5 11 µA 13 26 µA 0.8 1.6 mA 3.0 6.0 mA 5.0 10 mA Min. 1.8 Limits Typ. Max. 5.5 Unit V Rev.1.20 Dec 24, 2003 page 51 of 57 3822 Group (A ver.) Table 17 A-D converter characteristics (A version) (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 10 MHz, in middle/high-speed mode unless otherwise noted) Symbol – – Parameter Resolution Absolute accuracy (excluding quantization error) Test conditions Min. Limits Typ. Max. 8 ±2 ±3 12.5 (Note) 100 200 5.0 Unit Bits LSB LSB µs kΩ µA µA VCC = VREF = 2.2 V to 5.5 V f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz VCC = VREF < 2.2 V f(XIN) ≤ 12 ✕ VCC – 22 MHz f(XIN) = 8 MHz 12 50 35 150 tCONV RLADDER IVREF IIA Conversion time Ladder resistor Reference power source input current Analog port input current VREF = 5 V Note: When an internal trigger is used in middle-speed mode, it is 14 µs. Rev.1.20 Dec 24, 2003 page 52 of 57 3822 Group (A ver.) Table 18 Timing requirements 1 (A version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD–SCLK) th(SCLK–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 4.0 ≤ 4.5 ≤ 4.0 ≤ 4.5 ≤ 4.0 ≤ 4.5 ≤ 4.0 ≤ 4.5 ≤ 4.0 ≤ 4.5 ≤ 4.0 ≤ 4.5 ≤ Vcc < Vcc ≤ Vcc < Vcc ≤ Vcc < Vcc ≤ Vcc < Vcc ≤ Vcc < Vcc ≤ Vcc < Vcc ≤ 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1000/(4 ✕ VCC–8) 100 45 40 45 40 1000/(2 ✕ VCC–4) 200 105 85 105 85 80 80 800 370 370 220 100 Note: When bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). Table 19 Timing requirements 2 (A version) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RXD–SCLK) th(SCLK–RXD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input set up time Serial I/O input hold time Min. 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V 2.0 ≤ Vcc ≤ 4.0 V Vcc < 2.0 V Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 125 1000/(10 ✕ VCC–12) 50 70 50 70 1000/VCC 1000/(5 ✕ VCC–8) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Note: When bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 is “0” (UART). Rev.1.20 Dec 24, 2003 page 53 of 57 3822 Group (A ver.) Table 20 Switching characteristics 1 (A version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol twH(SCLK) twL(SCLK) td(SCLK–TXD) tv(SCLK–TXD) tr(SCLK) tf(SCLK) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note) Serial I/O output valid time (Note) Serial I/O clock output rising time Serial I/O clock output falling time Min. tC (SCLK)/2–30 tC (SCLK)/2–30 –30 30 30 Limits Typ. Max. Unit ns ns ns ns ns ns 140 Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Table 21 Switching characteristics 2 (A version) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol twH(SCLK) twL(SCLK) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note) Serial I/O output valid time (Note) Serial I/O clock output rising time Serial I/O clock output falling time Min. tC (SCLK)/2–100 tC (SCLK)/2–100 –30 Limits Typ. Max. Unit ns ns ns ns ns ns td(SCLK–TXD) tv(SCLK–TXD) tr(SCLK) tf(SCLK) 350 100 100 Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Measurement output pin 100 pF Measurement output pin 1 kΩ CMOS output 100 pF N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 001B16) is “1”. (N-channel opendrain output mode) Fig. 48 Circuit for measuring output switching characteristics Rev.1.20 Dec 24, 2003 page 54 of 57 3822 Group (A ver.) tC(CNTR) tWH(CNTR) CNTR0, CNTR1 0.8VCC 0.2VCC tWL(CNTR) tWH(INT) INT0–INT3 0.8VCC 0.2VCC tWL(INT) tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) XIN 0.8VCC 0.2VCC tWL(XIN) tC(SCLK) tf SCLK 0.2VCC tWL(SCLK) tr 0.8VCC tWH(SCLK) tsu(RXD-SCLK) RXD td(SCLK-TXD) TXD 0.8VCC 0.2VCC th(SCLK-RXD) tv(SCLK-TXD) Fig. 49 Timing diagram Rev.1.20 Dec 24, 2003 page 55 of 57 3822 Group (A ver.) PACKAGE OUTLINE 80P6N-A EIAJ Package Code QFP80-P-1420-0.80 MMP JEDEC Code – HD D Weight(g) 1.58 Lead Material Alloy 42 Plastic 80pin 14✕20mm body QFP MD e 80 1 65 64 b2 I2 Recommended Mount Pad HE E Symbol A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME 24 41 25 40 A L1 F b A1 e y x M L Detail F Dimension in Millimeters Min Nom Max – – 3.05 0.1 0.2 0 – – 2.8 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 – – 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 – – – – 0.2 0.1 – – 0° 10° – 0.5 – – 1.3 – – 14.6 – – – – 20.6 A2 Rev.1.20 Dec 24, 2003 page 56 of 57 c ME 3822 Group (A ver.) 80P6Q-A EIAJ Package Code LQFP80-P-1212-0.5 HD MMP JEDEC Code – Weight(g) 0.47 Lead Material Cu Alloy Plastic 80pin 12✕12mm body LQFP MD e 80 61 1 60 b2 D l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 A3 20 41 21 40 A F e L1 x y b2 I2 MD ME x M y A1 Detail F Lp Rev.1.20 Dec 24, 2003 page 57 of 57 c b L Dimension in Millimeters Min Nom Max – – 1.7 0.1 0.2 0 – – 1.4 0.13 0.18 0.28 0.105 0.125 0.175 11.9 12.0 12.1 11.9 12.0 12.1 – 0.5 – 13.8 14.0 14.2 13.8 14.0 14.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 – – 0.1 – 0° 10° – – 0.225 0.9 – – 12.4 – – – – 12.4 HE E A2 ME REVISION HISTORY Rev. 1.0 1.1 Date Page 09/26/02 10/10/02 1 4 6 15 30 51 52 53 7 40 46 47 52 First edition 3822 GROUP (A ver.) DATA SHEET Description Summary [FEATURES] Power source voltage: f(XIN) = → f(XIN) ≤ Table 1 P0 and P1 Function: 8-bit output port → 8-bit I/O port Fig. 4: M 6 A → M 6 ATable 6: [Notes] are revised. Fig. 27: The explanation of VREF input switch bit is revised. Table 16: VRAM Limits (Min.) is revised. Table 17: Test conditions of Absolute accuracy are revised. Tables 18, 19: Some parameters are added. Fig. 5: “Under development” eliminated. Fig. 39: a resistor is added to XOUT pin and Fig. title is revised. DATA REQUIRED FOR MASK ORDERS: URL is revised. Table 11: Input voltage VL3 is revised Table 17: Test conditions of Absolute accuracy is revised. 1.20 12/24/03 (1/X) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Renesas Technology Corp., All rights reserved. Printed in Japan.