To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT MICROCOMPUTER
DESCRIPTION
The 3819 group is a 8-bit microcomputer based on the 740 family core technology. The 3819 group has a flourescent display automatic display circuit and an 16-channel 8-bit A-D converter as additional functions. The various microcomputers in the 3819 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3819 group, refer to the section on group expansion.
FEATURES
q Basic machine-language instructions ...................................... 71 q The minimum instruction execution time ......................... 0.48 µs (at 8.4 MHz oscillation frequency) q Memory size ................................................................................. ROM ............................................. 4K to 60 K bytes RAM ........................................... 192 to 2048 bytes q Programmable input/output ports ............................................ 54 q High-breakdown-voltage output ports ...................................... 52 q Interrupts ................................................. 20 sources, 16 vectors q Timers ............................................................................. 8-bit ! 6 q Serial I/O (Serial I/O1 has an automatic transfer function) ...................................................... 8-bit ! 3(clock-synchronized) q PWM output circuit ............... 8-bit ! 1(also functions as timer 6) q A-D converter ............................................... 8-bit ! 16 channels
q D-A converter ................................................. 8-bit ! 1 channels q Zero cross detection input ............................................ 1 channel q Fluorescent display function Segments ........................................................................ 16 to 42 Digits .................................................................................. 6 to 16 q2 Clock generating circuit Clock (XIN-XOUT) ................................. Internal feedback resistor Sub-clock (XCIN-XCOUT) ......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) qPower source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8.4 MHz oscillation frequency and high-speed selected) In middle-speed mode ............................................... 2.8 to 5.5 V (at 8.4 MHz oscillation frequency) In low-speed mode .................................................... 2.8 to 5.5 V (at 32 kHz oscillation frequency) qPower dissipation In high-speed mode .......................................................... 35 mW (at 8.4 MHz oscillation frequency) In low-speed mode ............................................................ 60 µW (at 3 V power source voltage and 32 kHz oscillation frequency ) qOperating temperature range .................................... –10 to 85°C
APPLICATION
Musical Instruments, household appliance, etc.
PIN CONFIGURATION (TOP VIEW)
P90/SEG16 P91/SEG17 P92/SEG18 P93/SEG19 P94/SEG20 P95/SEG21 P96/SEG22 P97 /SEG23 P30 /SEG24 P31 /SEG25 P32/SEG26 P33 /SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 P00/SEG32/DIG0 P01/SEG33/DIG1 P02/SEG34/DIG2 P03 /SEG35/DIG3 P04 /SEG36 /DIG4 P05/SEG37/DIG5 P06/SEG38/DIG6 P07 /SEG39 /DIG7 P10 /SEG40/DIG8 P11/SEG41/DIG9 P12/DIG10 P13/DIG11 P14/DIG12 P15 /DIG13
75 74 60 77 76 61 68 78 80 79 69 62 59 58 57 56 55 54 53 72 73 63 70 71
P87/SEG15 P86/SEG14 P85/SEG13 P84/SEG12 P83/SEG11 P82/SEG10 P81 /SEG9 P80 /SEG8 PA7/SEG7 PA6/SEG6 VCC PA5/SEG5 PA4/SEG4 PA3/SEG3 PA2/SEG2 PA1/SEG1 PA0/SEG0 VEE AVSS VREF
67
66
65
64
52
51
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43
M38197MA-XXXFP
42 41 40 39 38 37 36 35 34 33 32 31
P16/DIG14 P17/DIG15 P20/DIG16 P21/DIG17 P22/DIG18 P23/DIG19 P24 P25 P26 P27 VSS XOUT XIN PB0/XCOUT PB1 /XCIN RESET P40/INT0 P41 P42/INT 2 P43/INT 3
21
20
12
19
22
23
24
25
26
27
18
17
11
10
P77 /AN7 P76/AN6 P75/AN5 P74 /AN4 P73 /AN3 P72 /AN2 P71/AN1 P70/AN0 PB3 PB2/DA P57 /SRDY3 /AN15 P56 /SCLK3 /AN14 P55/SOUT3 /AN13 P54/SIN3 /AN12 P53/SRDY2 /AN11 P52/SCLK2 /AN10 P51/SOUT2 /AN9 P50/SIN2 /AN8 P67/SRDY1 /CS/S CLK12 P66 /SCLK11 P65 /SOUT1 P64/SIN1 P63/CNTR1 P62/CNTR0 P61 /PWM P60 P47 /T3OUT P46 /T1OUT P45/INT1 /ZCR P44/INT4
Package type : 100P6S-A 100-pin plastic-molded QFP
13
14
15
16
28
29
30
1
2
3
4
5
6
7
8
9
9 10 36 37 81 82 83 84 85 86 87 88
89 90 92 93 94 95 96 97 73 74 75 76 77 78 79 80
12345678
99 100
19 20 21 22 23 24 25 26
11 12 13 14 15 16 17 18
27 28 29 30 31 32 33 34
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3819 Group
I/O port PB I/O port P8
I/O port PA
Output port P9
I/O port P7
AVSS VREF
I/O port P6
I/O port P5
INT0
PB (4) P8 (8) P7 (8)
PA (8)
P9 (8)
P6 (8)
P5 (8)
Zero cross detection circuit
P4 (8)
Interrupt interval determination circuit
16
INT3, INT4
XCIN
INT1/ZCR
D-A converter (8) A-D converter (8)
S I/O1(8)
S I/O2(8)
S I/O3(8)
INT2
2
Output port P0 VEE
92 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)
Clock input XIN
Reset input RESET (5 V) VCC
91 40
Clock output XOUT
(0 V) VSS Output port P1 Output port P2(4) I/O port P2(4)
35
38
39
Data bus P0 (8) P1 (8) P2 (8)
Clock generating circuit ROM RAM A X Y S T3OUT PWM CNTR0 CNTR1
FLD automatic display RAM 96 bytes
CPU
Timer 1 (8) Timer 2 (8) Timer 3 (8) Timer 4 (8) Timer 5 (8) Timer 6 (8)
T1OUT
FLD automatic display controller
XCIN XCOUT Sub-clock Sub-clock input output
PCH
PCL PS
SI/O automatic transfer controller SI/O automatic transfer RAM 32 bytes
XCOUT
Local data bus
P3 (8)
65 66 67 68 69 70 71 72
I/O port P4(6) Input port P4(2)
Output port P3
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin VCC, VSS VEE VREF AVSS RESET XIN Name Power source Pull-down Power source Analog reference voltage Analog power source Reset input Clock input Function •Apply voltage of 4.0 to 5.5 V to VCC, and 0 V to VSS. •Applies voltage supplied to pull-down resistors of ports P0, P1, P20–P23, P3, and P9. •Reference voltage input pin for A-D converter and D-A converter •GND input pin for A-D converter and D-A converter •Connect AVSS to VSS. •Reset input pin for active “L” •Input and output pins for the main clock generating circuit •Feedback resistor is built in between XIN pin and XOUT pin. •Connect a ceramic resonator or a quartz-crystal oscillator between the XIN pin and XOUT pin to set oscillation frequency. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •This clock is used as the oscillating source of system clock. •8-bit output port •This port builds in pull-down resistor between port P0 and the VEE pin. •At reset this port is set to VEE level. •The high-breakdown-voltage P-channel open-drain •8-bit output port with the same function as port P0 •4-bit output port with the same function as port P0 Function except a port function
XOUT
Clock output
P00/SEG32/ DIG0–P07/ SEG39/DIG7
Output port P0
FLD automatic display pins
P10/SEG40/ DIG8–P17/ DIG15 P20/DIG16– P23/DIG19
Output port P1
FLD automatic display pins
Output port P2
FLD automatic display pins
P24–P27
I/O port P2
•4-bit I/O port •I/O direction register allows each pin to be individually programmed as either input or output. •At reset this port is set to input mode. •TTL input level •CMOS 3-state output •8-bit output port with the same function as port P0 •2-bit input port •CMOS compatible input level FLD automatic display pins
P30/SEG24– P37/SEG31 P40/INT0, P45/INT1/ ZCR P42/INT2– P44/INT4 P41 P46/T1OUT, P47/T3OUT
Output port P3
Input port P4
External interrupt input pins A zero cross detection circuit input pin (P45)
I/O port P4
•6-bit CMOS I/O port with the same function as ports P24–P27 •CMOS compatible input level •CMOS 3-state output
Timer output pins
3
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (Continued)
Pin P50/SIN2/AN8, P51/SOUT2/AN9, P52/SCLK2/AN10, P53/SRDY2/AN11 P54/SIN3/AN12, P55/SOUT3/AN13, P56/SCLK3/AN14, P57/SRDY3/AN15 P60 P61/PWM P62/CNTR0, P63/CNTR1 P64/SIN1, P65/SOUT1, P66/SCLK11, P67/SRDY1/CS/ SCLK12 P70/AN0– P77/AN7 Name Function Function except a port function Serial I/O2 function pins A-D conversion input pins
I/O port P5
•8-bit CMOS I/O port with the same function as ports P24–P27 •CMOS compatible input level •CMOS 3-state output
Serial I/O3 function pins A-D conversion input pins
PWM output pin (Timer output pin) I/O port P6 •8-bit CMOS I/O port with the same function as ports P24–P47 •CMOS compatible input level •CMOS 3-state output Timer input pins
Serial I/O1 function pins
I/O port P7
•8-bit CMOS I/O port with the same function as ports P24–P27 •CMOS compatible input level •CMOS 3-state output •8-bit I/O port with the same function as ports P24–P27 •CMOS compatible input level •The high-breakdown-voltage P-channel open-drain •8-bit output port with the same function as port P0 •8-bit I/O port with the same function as ports P24–P27 •CMOS compatible input level •The high-breakdown voltage P-channel opendrain •4-bit CMOS I/O port with the same function as ports P24–P27 •CMOS compatible input level •CMOS 3-state output
A-D conversion input pins
P80/SEG8– P87/SEG15
I/O port P8
P90/SEG16– P97/SEG23
Output port P9
FLD automatic display pins
PA0/SEG0– PA7/SEG7
I/O port PA
PB0/XCOUT, PB1/XCIN PB2/DA PB3
I/O port PB
I/O pins for sub-clock generating circuit (connect a ceramic resonator or a quarts-crystal oscillator) D-A conversion output pin
4
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M3819
7
M
A
XXX FP Package type FP : 100P6S-A package FS : 100D0 package ROM number Omitted in some types. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
5
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3819 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity .................................. 40 K to 60 K bytes RAM capacity .............................................. 1024 to 2048 bytes
(2) Packages 100P6S-A ........................... 0.65 mm-pitch plastic molded QFP 100D0 ........................... Ceramic LCC(built-in EPROM version)
Memory Expansion Plan
Under development 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K 256 512 768 1,024 RAM size (bytes) 1,536 2,048 Mass product M38197MA Mass product M38198MC/EC ROM size (bytes) M38199MF/EF
Products under development : the development schedule and specifications may be revised without notice.
Currently supported products are listed below. Product M38197MA-XXXFP M38197MA-XXXKP M38198MC-XXXKP M38199MF-XXXKP M38198MC-XXXFP M38198EC-XXXFP M38198ECFP M38198ECFS M38199MF-XXXFP M38199EF-XXXFP M38199EFFP M38199EFFS (P) ROM size (bytes) ROM size for User in ( ) 40960 (40830) RAM size (bytes) Package 100P6S-A 1024 100P6P-E Remarks
As of May 1996
49152 (49022)
1536
100P6S-A 100D0
61440 (61310)
2048
100P6S-A 100D0
Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version
6
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 3819 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used.
CPU Mode Register
The CPU mode register is allocated at address 003B 16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit.
b7
b0 CPU mode register (CPUM (CM) : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area XCOUT drivability selection bit 0 : Low drive 1 : High drive Port XC switch bit 0 : I/O port function 1 : XCIN -XCOUT oscillating function Main clock (X IN-X OUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN )/2 (high-speed mode) 1 : f(XIN )/8 (middle-speed mode) Internal system clock selection bit 0 : XIN -XOUT selected (middle/high-speed mode) 1 : XCIN -XCOUT selected (low-speed mode)
Fig. BA-1 Structure of CPU mode register
7
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory Special function register (SFR) area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the reset is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area RAM capacity (bytes) 192 256 384 512 640 768 896 1024 1536 2048
000016 SFR area Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 044016 Not used 0F0016 0F1F16
RAM area for serial I/O automatic transfer
004016 010016 RAM
Zero page
XXXX16 Reserved area
Not used ROM area ROM capacity (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFFE16 FFFF16 Reserved ROM area Interrupt vector area RO M FF0016 FFDC16 Special page ZZZZ16 YYYY16 Reserved ROM area (common ROM area,128 bytes) 0F8016 0FDF16
RAM area for FLD automatic display
Not used
Fig. CA-1 Memory map
8
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P1 (P1) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port PA (PA) Port PA direction register (PAD) Port PB (PB) Port PB direction register (PBD)
Serial I/O automatic transfer data pointer (SIODP)
Serial I/O1 control register (SIO1CON)
Serial I/O automatic transfer control register (SIOAC)
Serial I/O1 register (SIO1)
Serial I/O automatic transfer interval register (SIOAI)
Serial I/O2 control register (SIO2CON) Serial I/O3 control register (SIO3CON) Serial I/O2 register (SIO2)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6) Serial I/O3 register (SIO3) Timer 6 PWM register (T6PWM) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M) D-A conversion register (DA) AD-DA control register (ADCON) A-D conversion register (AD)
Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
Port P0 segment/digit switch register (P0SDR) Port P2 digit/port switch register (P2DPR) Port P8 segment/port switch register (P8SPR) Port PA segment/port switch register (PASPR) FLDC mode register 1 (FLDM1) FLDC mode register 2 (FLDM2) FLD data pointer (FLDDP) Zero cross detection control register (ZCRCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. CA-2 Memory map of special function register (SFR)
9
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS Direction Registers
The 3819 group has 54 programmable I/O pins arranged in 8 I/O ports (ports P2 4–P2 7, P41–P4 4, P46 , P47, P5–P8, PA, and PB). The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input or output. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set for output, the value of the port latch is read, not the value of the pin itself. A pin which is set for input the value of the pin itself is read because the pin is in floating state. If a pin set for input is written to, only the port latch is written to and the pin remains floating.
High-Breakdown-Voltage Output Ports
The 3819 group microprocessors have 7 ports with high-breakdown-voltage pins (ports P0, P1, P20–P23, P3, P8, P9, PA). The high-breakdown-voltage ports have P-channel open-drain output with VCC –40 V of breakdown voltage. Each pin in ports P0, P1, P2 0–P23 , P3, and P9 has an internal pull-down resistor connected to VEE. Ports P8 and PA have no internal pull-down resistors, so that connect an external resistor to each port. At reset, the P-channel output transistor of each port latch is turned off, so it becomes V EE level (“L”) by the pull-down resistor. Writing “1” (weak drivability) to bit 7 of the FLDC mode register 1 (address 003616) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode register 1 is set to “0” (strong drivability).
Pin P00/SEG32/ DIG0– P07/SEG39/ DIG7
Name
Input/Output
I/O Format High-breakdownvoltage P-channel open-drain output with pull-down resistor High-breakdownvoltage P-channel open-drain output with pull-down resistor High-breakdownvoltage P-channel open-drain output with pull-down resistor TTL level input CMOS 3-state output High-breakdownvoltage P-channel open-drain output with pull-down resistor CMOS compatible input level
Non-Port Function
Related SFRS FLDC mode register 1 FLDC mode register 2 Port P0 segment/digit switch register FLDC mode register 1 FLDC mode register 2
Diagram No.
Port P0
Output
FLD automatic display function
(1)
P10/SEG40/ DIG8– P17/DIG15
Port P1
Output
FLD automatic display function
(1) (2)
P20/DIG16– P23/DIG19
Output Port P2 Input/output, individual bits
FLD automatic display function
FLDC mode register 1 FLDC mode register 2 Port P2 digit/port switch register
(3)
P24–P27
(4)
P30/SEG24– P37/SEG31
Port P3
Output
FLD automatic display function
FLDC mode register 1 FLDC mode register 2
(5)
P40/INT0 P45/INT1/ ZCR P42/INT2– P44/INT4 P41 P46/T1OUT, P47/T3OUT Port P4
Input
External interrupt input Zero cross detection circuit input (P45)
Interrupt edge selection register Zero cross detection control register
(6)
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
(7) (4)
Timer output
Timer 12 mode register Timer 34 mode register
(8)
10
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pin P50/SIN2/ AN8 P51/SOUT2/ AN9, P52/SCLK2/ AN10 P53/SRDY2/ AN11 P54/SIN3/ AN12 P55/SOUT3/ AN13, P56/SCLK3/ AN14 P57/SRDY3/ AN15 P60 P61/PWM P62/CNTR0, P63/CNTR1 P64/SIN1 P65/SOUT1, P66/SCLK11 P67/SRDY1/ CS/SCLK12 P70/AN0– P77/AN7
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
Diagram No. (9)
Serial I/O2 function I/O A-D conversion input CMOS compatible input level CMOS 3-state output
Serial I/O2 control register AD/DA control register
(10)
(11) (9) Serial I/O3 function I/O A-D conversion input Serial I/O3 control register AD/DA control register (10)
Port P5
(11) Input/output, individual bits PWM (timer) output CMOS compatible input level CMOS 3-state output Timer input Timer 56 mode register Interrupt edge selection register Serial I/O1 control register Serial I/O automatic transfer control register AD/DA control register (4) (8) (7) (9) (10) (11)
Port P6
Serial I/O1 function I/O
Port P7
P80/SEG8– P87/SEG15
Port P8
P90/SEG16– P97/SEG23
Port P9
Output
PA0/SEG0– PA7/SEG7 PB0/XCOUT, PB1/XCIN PB2/DA PB3
Port PA
Input/output, individual bits
CMOS compatible input level CMOS 3-state output CMOS compatible input level High-breakdownvoltage P-channel open-drain output with pull-down resistor High-breakdownvoltage P-channel open-drain output with pull-down resistor CMOS compatible input level High-breakdownvoltage P-channel open-drain output CMOS compatible input level CMOS 3-state output
A-D conversion input
(12)
FLDC mode register Segment/port switch register FLD automatic display function FLDC mode register
(13)
(5)
FLDC mode register Segment/port switch register I/O for sub-clock generating circuit D-A conversion output
(13)
CPU mode register AD/DA control register
Port PB
Input/output, individual bits
(14) (15) (16) (4)
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
11
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P10, P11 Shift signal from previous stage S/D switch register Blanking signal for key-scan Data bus Local data bus Dimmer signal (Note) Port latch
V
Shift signal to next stage
VEE
(2) Ports P12–P17 Shift signal from previous stage Dimmer signal (Note) Data bus Port latch
V
Shift signal to next stage
VEE
(3) Ports P20–P23 Shift signal from previous stage D/P switch register Dimmer signal (Note) Data bus Port latch
V
Blanking signal for key-scan Shift signal to next stage VEE
(4) Ports P24–P27, P41, P60, PB3 Direction register Data bus Port latch
V : High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. UA-2 Port block diagram (1)
12
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(5) Ports P3, P9 Dimmer signal (Note) Port latch
V
Local data bus Data bus
VEE (6) Ports P40, P45 Data bus
INT0, INT1 interrupt input Zero cross detection circuit input (only P4 5) (7) Ports P42–P44, P62, P63 Direction register Data bus Port latch
INT2–INT4 interrupt input CNTR0,CNTR1 input (8) Ports P46, P47, P61 Timer 1 output selection bit Timer 3 output selection bit Timer 6 output selection bit Direction register Data bus Port latch
Timer 1 output Timer 3 output Timer 6 output V : High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. UA-3 Port block diagram (2)
13
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Ports P50 , P54 , P64 Direction register
Data bus
Port latch
Serial I/O input A-D conversion input Analog input pin selection bit (10) Ports P5 1 , P52 , P55, P56 , P65, P66 P-channel output disable signal Output OFF control signal Serial I/O port selection bit Direction register Data bus Port latch
SOUT or SCLK Serial clock input (only P52 , P56 , P66 ) A-D conversion input Analog input pin selection bit (11) Ports P5 3 , P57, P67 SRDY output enable bit Direction register
Data bus
Port latch
Serial ready output or SCLK
CS input (only P67 )
A-D conversion input Analog input pin selection bit (12) Port P7 Direction register
Data bus
Port latch
A-D conversion input Analog input pin selection bit
Fig. UA-4 Port block diagram (3)
14
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Ports P8, PA S/P switch register Dimmer signal (Note) Directionregister Port latch read
V
Local data bus Data bus
(14) Port PB0 Port XC switch bit Direction register Data bus Port latch
Oscillation circuit Port PB1 Port XC switch bit
(15) Port PB1
Port XC switch bit Direction register Data bus Port latch
Sub-clock generating circuit input (16) Port PB2 Direction register Data bus Port latch
D-A conversion output D-A output enable bit V : High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. UA-5 Port block diagram (4)
15
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 20 sources: 5 external, 14 internal, and 1 software.
Interrupt Operation
When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering. The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. Table 1. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1/ZCR INT2 Remote control/ counter overflow Serial I/O1 Serial I/O automatic transfer Serial I/O2 Serial I/O3 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 INT3 5 FFF516 FFF416 4 FFF716 FFF616 Priority 1 2 3 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFFA16 FFF816
Notes on Use
When the active edge of an external interrupt (INT 0 to INT 4) is changed or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected.
Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1/ZCR input At detection of either rising or falling edge of INT2 input At 8-bit counter overflow At completion of data transfer At completion of the last data transfer At completion of data transfer At completion of data transfer At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At timer 5 underflow At timer 6 underflow At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At completion of A-D conversion At falling edge of the last digit immediately before blanking period starts At rising edge of each digit
Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when interrupt interval determination is operating Valid when serial I/O ordinary mode is selected Valid when serial I/O automatic transfer mode is selected Valid when serial I/O2 is selected Valid when serial I/O3 is selected STP release timer underflow
6 7 8 9 10 11 12 13 14
FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316
FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216
INT4
15
FFE116
FFE016
External interrupt (active edge selectable) Valid when INT 4 i nterrupt is selected External interrupt (active edge selectable) Valid when A-D conversion interrupt is selected Valid when FLD blanking interrupt is selected Valid when FLD digit interrupt is selected Non-maskable software interrupt
A-D conversion FLD blanking 16 FLD digit BRK instruction 17 FFDD16 FFDC16 FFDF16 FFDE16
At BRK instruction execution
Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority.
16
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. DD-1 Interrupt control
b7
b0
Interrupt edge selection register (INTEDGE : address 003A 16) INT0 interrupt edge selection bit INT1 /ZCR interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit INT4 /AD conversion interrupt switch bit CNTR0 pin active edge switch bit CNTR1 pin active edge switch bit
0 : Falling edge active 1 : Rising edge active
0 : INT 4 interrupt 1 : A-D conversion interrupt 0 : Rising edge count 1 : Falling edge count
b7
b0
Interrupt request register 1 (IREQ1 : address 003C 16) INT0 interrupt request bit INT1 /ZCR interrupt request bit INT2 interrupt request bit Remote control/counter overflow interrupt request bit Serial I/O1 interrupt request bit Serial I/O automatic transfer interrupt request bit Serial I/O2 interrupt request bit Serial I/O3 interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit
b7
b0
Interrupt request register 2 (IREQ2 : address 003D 16) Timer 3 interrupt request bit Timer 4 interrupt request bit Timer 5 interrupt request bit Timer 6 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD conversion interrupt request bit FLD blanking interrupt request bit FLD digit interrupt request bit Not used (returns “0” when read)
0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E 16) INT0 interrupt enable bit INT1 /ZCR interrupt enable bit INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit Serial I/O1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit Serial I/O2 interrupt enable bit Serial I/O3 interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit
b7
b0
Interrupt control register 2 (ICON2 : address 003F 16) Timer 3 interrupt enable bit Timer 4 interrupt enable bit Timer 5 interrupt enable bit Timer 6 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD conversion interrupt enable bit FLD blanking interrupt enable bit FLD digit interrupt enable bit Not used (returns “0” when read) (do not write “1” to this bit)
0 : Interrupts disabled 1 : Interrupts enabled
Fig. DD-2 Structure of interrupt-related registers
17
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3819 group has 6 built-in timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. Each timer has the 8-bit timer latch. The timers count down. Once a timer reaches 0016, at the next count pulse the contents of each timer latch is loaded into the corresponding timer, and sets the corresponding interrupt request bit to “1”. The count can be stopped by setting the stop bit of each timer to “1”. The internal clock φ can be set to either the high-speed mode or low-speed mode with the CPU mode register. At the same time, timer internal count source is switched to either f(XIN) or f(XCIN).
Timer 1 and Timer 2
The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 is output from the P4 6/T1OUT pin. The waveform polarity changes each time timer 1 overflows. The active edge of the external clock CNTR0 can be switched with the bit 6 of the interrupt edge selection register. At reset or when executing the STP instruction, all bits of the timer 12 mode register are cleared to “0”, timer 1 is set to “FF 16”, and timer 2 is set to “0116”.
Timer 3 and Timer 4
The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 is output from the P4 7/T3OUT pin. The waveform polarity changes each time timer 3 overflows. The active edge of the external clock CNTR 1 can be switched with the bit 7 of the interrupt edge selection register.
Timer 5 and Timer 6
The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 is output from the P6 1/PWM pin. The waveform polarity changes each time timer 6 overflows.
Timer 6 PWM Mode
Timer 6 can output a rectangular waveform with duty cycle n/(n + m) from the P61/PWM pin by setting the timer 56 mode register (refer to fig. FB-3). The n is the value set in timer 6 latch (address 0025 16) and m is the value in the timer 6 PWM register (address 002716). If n is “0”, the PWM output is “L”, if m is “0”, the PWM output is “H”(n=0 is prior than m=0). In the PWM mode, interrupts occur at the rising edge of the PWM output.
18
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus Timer 1 count Timer 1 latch (8) source “1” selection bit FF16 Timer 1 (8) “0” Timer 1 count stop bit
XCIN “1” XIN P46/T1OUT “0”
Internal system clock selection bit 1/16 P46 latch 1/2
RESET STP instruction Timer 1 interrupt request
Timer 1 output selection bit Timer 2 count Timer 2 latch (8) source “00” selection bit 0116 Timer 2 (8) “01” “10” Timer 2 count stop bit
P46 direction register
Timer 2 interrupt request
P62 /CNTR0
Rising/falling edge switch
Timer 3 count Timer 3 latch (8) source “1” selection bit Timer 3 (8) P47/T3OUT P47 latch 1/2 Timer 3 output selection bit “0” Timer 3 count stop bit
Timer 3 interrupt request
P47 direction register
P63 /CNTR1
Rising/falling edge switch
Timer 4 count Timer 4 latch (8) source “01” selection bit Timer 4 (8) “00” “10” Timer 4 count stop bit
Timer 4 interrupt request
Timer 5 count Timer 5 latch (8) source “1” selection bit Timer 5 (8) “0” Timer 5 count stop bit Timer 6 count Timer 6 latch (8) source “01” selection bit Timer 6 (8) “00” “10” Timer 6 count stop bit Timer 6 PWM register (8) P61/PWM P61 latch “1” Timer 6 output selection bit “0” PWM 1/2
Timer 5 interrupt request
Timer 6 interrupt request
Timer 6 operating mode selection bit
P61 direction register
Fig. FB-1 Timer block diagram
19
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer 12 mode register (T12M : address 0028 16) Timer 1 count stop bit 0 : Operating 1 : Stopped Timer 2 count stop bit 0 : Operating 1 : Stopped Timer 1 count source selection bit 0 : f(XIN )/16 or f(XCIN )/16 1 : f(XCIN ) Not used (returns “0” when read) Timer 2 count source selection bits b5 b4 0 0 : Timer 1 underflow 0 1 : f(XCIN ) 1 0 : External count input CNTR 0 1 1 : Not available Timer 1 output selection bit (P4 6 ) 0 : I/O port 1 : Timer 1 output Not used (returns “0” when read)
b7
b0
Timer 34 mode register (T34M : address 0029 16) Timer 3 count stop bit 0 : Operating 1 : Stopped Timer 4 count stop bit 0 : Operating 1 : Stopped Timer 3 count source selection bit 0 : f(XIN )/16 or f(XCIN )/16 1 : Timer 2 underflow Not used (returns “0” when read) Timer 4 count source selection bits b5 b4 0 0 : f(XIN )/16 or f(X CIN )/16 0 1 : Timer 3 underflow 1 0 : External count input CNTR 1 1 1 : Not available Timer 3 output selection bit (P47 ) 0 : I/O port 1 : Timer 3 output Not used (returns “0” when read)
b7
b0
Timer 56 mode register (T56M : address 002A 16) Timer 5 count stop bit 0 : Operating 1 : Stopped Timer 6 count stop bit 0 : Operating 1 : Stopped Timer 5 count source selection bit 0 : f(XIN )/16 or f(XCIN )/16 1 : Timer 4 underflow Timer 6 operation mode selection bit 0 : Timer mode 1 : PWM mode Timer 6 count source selection bits b5 b4 0 0 : f(XIN )/16 or f(X CIN )/16 0 1 : Timer 5 underflow 1 0 : Timer 4 underflow 1 1 : Not available Timer 6 (PWM) output selection bit (P61) 0 : I/O port 1 : Timer 6 output Not used (returns “0” when read) (do not write “1”)
Fig. FB-2 Structure of timer-related registers
20
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts Timer 6 count source
Timer 6 PWM output n ! ts (n + m) ! ts m ! ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: If the value set in timer 6 is n and the value set in the timer 6 PWM register is m, a PWM waveform with duty cycle n/(n + m) and period (n + m) 5 ts (ts : the frequency of the timer 6 count source) is output.
Fig. FB-3 Timing in timer 6 PWM mode
21
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
The 3819 group has built-in 8-bit clock synchronized serial I/O ! 3 channels (serial I/O1, serial I/O2, and serial I/O3). Serial I/O1 builds in the automatic transfer function. The function can be switched to the serial I/O ordinary mode with the serial I/O automatic transfer control register (address 001A 16). Serial I/O2 and Serial I/O3 can be used only in the serial I/O ordinary mode. The I/O pins of the serial I/O function are also used as I/O ports P5 and P64–P67, and their operation is selected with the serial I/O control registers (addresses 001916, 001D16, and 001E16).
Serial I/O Control Registers (SIO1CON, SIO2CON, SIO3CON) 001916, 001D16, 001E16
Each of the serial I/O control registers (addresses 0019 16 , 001D16, and 001E16) consists of 8 selection bits which control the serial I/O function.
22
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Main address bus
Local address bus
SI/O automatic transfer RAM (0F0016 to 0F1F16)
Main data bus
Local data bus
Address decorder
SI/O automatic transfer data pointer SI/O automatic transfer controller Serial I/O automatic transfer interrupt request
Internal system clock “1” selection bit “0” P67 latch (Note) SRDY1
XIN P67/SRDY1/ CS/SCLK12
Synchronization circuit
CS P66 latch “0” P66/SCLK11 “1” Serial I/O1 port selection bit “0” P65 latch
SCLK1
Internal synchronous “0” clock selection bit
External clock
Frequency divider
XCIN
SI/O automatic transfer interval register 1/8 1/16 1/32 1/64 Synchronous 1/128 clock selection 1/256 bit “1”
Serial I/O counter 1(3)
Serial I/O1 interrupt request
P65/SOUT1
“1” Serial I/O1 port selection bit P64/SIN1
Serial I/O shift register 1(8)
P53/SRDY2
SRDY2 output selection bit
P53 latch “0” SRDY2 “1”
Synchronous clock selection bit “1”
Synchronization circuit
“0” P52 latch P52/SCLK2 “1” Serial I/O2 port selection bit “0” P51 latch P51/SOUT2 “1” Serial I/O2 port selection bit P50/SIN2
SCLK2
External clock
“0”
Frequency divider
1/8 1/16 1/32 1/64 1/128 1/256
Internal synchronous clock selection bit Serial I/O2 interrupt request
Serial I/O counter 2(3)
Serial I/O shift register 2(8)
P57/SRDY3
P57 latch “0” SRDY3 “1”
SRDY2 output selection bit
“1”
Synchronization circuit
“0” P56 latch P56/SCLK3 “1” Serial I/O3 port selection bit “0” P55 latch P55/SOUT3 “1” Serial I/O3 port selection bit P54/SIN3
SCLK3
External clock
“0”
Frequency divider
1/8 1/16 1/32 1/64 1/128 1/256
Internal synchronous clock selection bit Serial I/O3 interrupt request
Serial I/O counter 3(3)
Serial I/O shift register 3(8)
Note: Selected with the synchronous clock selection bit, SRDY1 output selection bit, serial I/O1 port selection bit (these 3 bits are of the serial I/O1 control register), automatic transfer control bit, and synchronous clock output pin selection bit (these 2 bits are ofthe serial I/O automatic transfer register).
Fig. GA-1 Serial I/O block diagram
23
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 control register (SIO1CON(SC1) : address 001916) Internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 : f(XIN)/32 or f(XCIN)/32 0 1 1 : f(XIN)/64 or f(XCIN)/64 1 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 1 : f(XIN)/256 or f(XCIN)/256 Serial I/O1 port selection bit (P65, P66, and P67 V) 0 : I/O port 1 : SOUT1,SCLK11,and SCLK12 V output pins SRDY1 output selection bit (P67) 0 : I/O port 1 : SRDY1/CS V output pin (Note) Transfer direction selection bit 0 : LSB first 1 : MSB first Synchronous clock selection bit 0 : External clock 1 : Internal clock P65/SOUT1 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
b7
b0
Serial I/O2 control register (SIO2CON(SC2) : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 : f(XIN)/32 or f(XCIN)/32 0 1 1 : f(XIN)/64 or f(XCIN)/64 1 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 1 : f(XIN)/256 or f(XCIN)/256 Serial I/O2 port selection bit (P51, and P52) 0 : I/O port 1 : SOUT2 and SCLK2 output pins SRDY2 output selection bit (P53) 0 : I/O port 1 : SRDY2 output pin Transfer direction selection bit 0 : LSB first 1 : MSB first Synchronous clock selection bit 0 : External clock 1 : Internal clock P51/SOUT2 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
b7
b0
Serial I/O3 control register (SIO3CON(SC3) : address 001E16) Internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 : f(XIN)/32 or f(XCIN)/32 0 1 1 : f(XIN)/64 or f(XCIN)/64 1 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 1 : f(XIN)/256 or f(XCIN)/256 Serial I/O3 port selection bit (P55 and P56) 0 : I/O port 1 : SOUT3 and SCLK3 output pins SRDY3 output selection bit (P57) 0 : I/O port 1 : SRDY3 and SCLK3 output pins Transfer direction selection bit 0 : LSB first 1 : MSB first Synchronous clock selection bit 0 : External clock 1 : Internal clock P55/SOUT3 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
V
: Valid only in serial I/O automatic transfer mode. Note: When the external clock is selected in the serial I/O1 automatic transfer mode, the SRDY1 signal pin becomes the CS signal input pin.
Fig. GA-2 Structure of serial I/O control registers
24
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Serial I/O Ordinary Mode
Either an internal clock or an external clock can be selected as the synchronous clock for serial I/O transfer. A dedicated divider is built in as the internal clock for selecting of 6 clocks. If internal clock is selected, transfer starts with a write signal to a serial I/O register (addresses 001B 16 , 001F 16 , or 002616). After 8 bits have been transferred, the SOUT pin goes to high impedance state.
If external clock is selected, control the clock externally because the contents of the serial I/O register continue to shift during inputting the transfer clock. In this case, note that the SOUT pin does not go to high impedance state at the completion of data transfer. The interrupt request bit is set at the completion of the transfer of 8 bits, regardless of whether the internal or external clock is selected.
Synchronous clock Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT Serial I/O input SIN Receive enable signal SRDY Interrupt request bit set Note : If internal clock is selected, the S OUT pin goes to high impedance state at the completion of data transfer. D0 D1 D2 D3 D4 D5 D6 D7
Fig. GA-3 Serial I/O timing in the serial I/O ordinary mode (for LSB first)
(2) Serial I/O Automatic Transfer Mode
The serial I/O1 has the automatic transfer function. For automatic transfer, switch to the automatic transfer mode by setting the serial I/O automatic transfer control register (address 001A16). The following memory spaces and registers used to enable automatic transfer mode: • 32-byte serial I/O automatic transfer RAM • A serial I/O automatic transfer control register • A serial I/O automatic transfer interval register • A serial I/O automatic transfer data pointer When using serial I/O automatic transfer, set the serial I/O1 control register (address 001916) in the same way as the serial I/O ordinary mode. However, note that when external clock is selected, port P67 becomes the CS input pin by setting the bit 4 (the SRDY1 output selection bit ) of the serial I/O1 control register to “1”.
b7 b0 Serial I/O automatic transfer control register (SIOAC : address 001A 16) Automatic transfer control bit 0 : Serial I/O ordinary mode (serial I/O1 interrupt) 1 : Automatic transfer mode (serial I/O1 automatic transfer interrupt) Automatic transfer start bit 0 : Transfer completion 1 : Transferring(starts by writing “1”) Transfer mode switch bit 0 : Fullduplex(transmit and receive) mode 1 : Transmit-only mode Synchronous clock output pin selection bit 0 : SCLK11 1 : SCLK12 Not used (return “0” when read)
Serial I/O Automatic Transfer Control Register (SIOAC) 001A16
The serial I/O automatic transfer control register (address 001A16) consists of 4 bits which control automatic transfer.
Fig. GA-4 Structure of serial I/O automatic transfer control register
25
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O Automatic Transfer Data Pointer (SIODP) 001816
The serial I/O automatic transfer data pointer (address 001816) consists of 5 bits which indicate addresses in serial I/O automatic transfer RAM (the value which adds 0F00 16 to the serial I/O automatic transfer data pointer is actual address in memory). Set the value (the number of transfer data-1) to the serial I/O automatic transfer data pointer for specifying the storage address of first data.
q Setting of Serial I/O Automatic Transfer Data
When data is stored in the serial I/O automatic transfer RAM, store the first data at the address set with the serial I/O automatic transfer data pointer so that the last data can be stored at address 0F0016.
Serial I/O Automatic Transfer Interval Register (SIOAI) 001C16
The serial I/O automatic transfer interval register (address 001C16) consists of a 5-bit counter that determines the transfer interval Ti during automatic transfer. When writing the value n to the serial I/O automatic transfer interval register, Ti=(n+2) ! Tc (Tc: the length of one bit of the transfer clock) occurs. However, note that this transfer interval setting is valid only when selecting the internal clock as the clock source.
q Serial I/O Automatic Transfer RAM
The serial I/O automatic transfer RAM is the 32 bytes from address 0F0016 to address 0F1F16.
Address
Bit
7
6
5
4
3
2
1
0
0F00 16 0F0116 0F0216
0F1D16 0F1E16 0F1F16
Fig. GA-5 Bit allocation of serial I/O automatic transfer RAM
Transfer clock
Serial I/O output SOUT Serial I/O input SIN
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DI 0 TC
DI1
DI2
DI3
DI4
DI5
DI6
DI 7
1-byte data
Ti
Fig. GA-6 Serial I/O automatic transfer interval timing
26
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Setting of Serial I/O Automatic Transfer Timing
The timing of serial I/O automatic transfer is set with the serial I/O1 control register (address 001916) and the serial I/O automatic transfer interval register (address 001C16). The serial I/O1 control register sets the transfer clock speed, and the serial I/O automatic transfer interval register sets the serial I/O automatic transfer interval. This setting of transfer interval is valid only when selecting the internal clock as the clock source.
(2.1) Operation in Full Duplex Mode
In full duplex mode, data can be transmitted and received at the same time. Data in the automatic transfer RAM is transmitted in sequence in accordance with the serial I/O automatic transfer data pointer and simultaneously reception data is written to the automatic transfer RAM. The transfer timing of each bit is the same as that in ordinary operation mode, and the transfer clock stops at “H” after eight transfer clocks are counted. When selecting the internal clock, the transfer clock remains at “H” for the time set with the serial I/O automatic transfer interval register, then the data at the next address (the address is indicated with the serial I/O automatic transfer data pointer) are transferred. If when selecting the external clock, the setting of the automatic transfer interval register is invalid, so control the transfer clock externally. The last data transfer completes when the contents of the serial I/O automatic transfer pointer reach “0016”. At that point, the serial I/O automatic transfer interrupt request bit is set to “1” and the bit 1 of the serial I/O automatic transfer control register is cleared to “0” to complete the serial I/O automatic transfer.
q Start of Serial I/O Automatic Transfer
Automatic transfer mode is set by writing “1” to the bit 0 of the serial I/O automatic transfer control register (address 001A16), then automatic transfer starts by writing “1” to the bit 1. The bit 1 of the serial I/O automatic transfer control register is always “1” during automatic transfer; writing “0” can complete the serial I/O automatic transfer.
q Operation in Serial I/O Automatic Transfer Modes
There are two modes for serial I/O automatic transfer: full duplex mode and transmit-only mode. Either internal or external clock can be selected for each of these modes.
(2.2) Operation in Transmit-Only Mode
The operation in transmit-only mode is the same as that in full duplex mode, except for that data is not transferred from the serial I/O1 register to the serial I/O automatic transfer RAM.
Transfer direction selection bit
LSB first (SC1 5 = “0” ) : MSB MSB first (SC1 5 = “1” ) : LSB DO7 DO6 SIN DI0 DO5 DO4
LSB MSB DO3 DO2 DO1 DO0 SOUT DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO7 DO6 DO5 DO4 DO3 DO2
DI 1
DI0
DI2
DI1
DI0
DO7 DO6 DO5 DO4 DO3
• • •
DI 7 Transfer clock
DI6
DI5
DI4
DI 3
DI2
DI1
DI0
Serial I/O1 register
Fig. GA-7 Serial I/O1 register transfer operation in full duplex mode
27
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2.3) When Selecting the Internal Clock
When selecting the internal clock, the P6 7/SRDY1/CS/S CLK12 pin can be used as the SRDY1 pin by setting SC14 to “1”. When selecting the internal clock, the P67 pin can be used as the synchronous clock output pin SCLK12 by setting SIOAC3 to “1”. In this case, the SCLK11 pin goes to high impedance state. Select the function of the P6 7/SRDY1/CS/SCLK12 and P66/SCLK11 with the following registers (refer to Table GA-1): q the bit 3 (SC1 3), the bit 4(SC14), and the bit 6(SC16) of the serial I/O1 control register q the bit 3 (SIOAC 3) of the serial I/O automatic transfer control register
When using both the SCLK11 and SCKL12 by switching, switch the P67/SRDY1/CS/SCLK12 to the P67 (SC14=0) and set the P67 direction register to input mode. Note that switch SIOAC3 during “H” of transfer clock at the completion of automatic transfer. Table GA-1. SCLK11 and SCLK12 selection SC16 1 SC14 0 SC33 1 SIOAC3 P66/SCLK11 P67/SCLK12 0 SCLK11 P67 High 1 impedance SCLK12
Note : SC13: Serial I/O1 port selection bit SC14: SRDY1 output selection bit SC16: Synchronous clock selection bit SIOAC3: Synchronous clock output pin selection bit
Bit 1 write signal of serial I/O automatic transfer control register Bit 1 of serial I/O automatic transfer control register Write signal from RAM to serial I/O1 register Write signal from serial I/O1 register to RAM Data pointer Transfer clock (internal or SCLK output) Receive enabled signal SRDY Serial I/O output Sout Serial I/O input SIN DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DI0 DO6 DO7 DI6 DI7 n n-1 0
Transfer interval
Fig. GA-8 Timing diagram during serial I/O automatic transfer (internal clock selected, SRDY used)
Bit 1 write signal of serial I/O automatic transfer control register Bit 1 of serial I/O automatic transfer control register Write signal from RAM to serial I/O1 register Write signal from serial I/O1 register to RAM Data pointer Bit 3 of serial I/O automatic transfer control register Transfer clock (internal) SCLK11 output SCLK12 output Serial I/O output Sout Serial I/O input SIN
m
m-1
0
n
DO 0 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7
DO 0
DO 6 DO 7
DO 0 DO 1 DO 2 DO 3
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI
7
DI0
DI6
DI7
DI0
DI1
DI2
DI
3
Transfer interval
Fig. GA-9 Timing during serial I/O automatic transfer (internal clock selected, SCLK11 and SCLK12 used)
28
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2.4) When Selecting the External Clock
When selecting the external clock, the internal clock and the setting of transfer interval with the serial I/O automatic transfer interval register are invalid, but the serial I/O output pin SOUT1 and the internal transfer clock can be controlled from the outside by setting the SRDY1 pin to the CS (input) pin. When the CS input is “L”, the SOUT1 pin and the internal transfer clock are enabled. When the CS input is “H”, the SOUT1 pin goes to high impedance state and the internal transfer clock goes to “H”. Select the function of the P67/SRDY1/CS/SCLK12 with the following registers (refer to Table GA-2): q the bit 4 (SC1 4) and the bit 6 (SC16) of the serial I/O1 control register q the bit 0 (SIOAC 0) of the serial I/O automatic transfer control register Switch the CS pin from “L” to “H” or from “H” to “L” during “H” of the transfer clock (SCLK11 input) after transferring 1-byte data. When selecting the external clock, set the external clock to “L” after 9 cycles or more of the internal clock φ after setting the start bit. After transferring 1-byte data, leave 11 cycles or more of the internal clock φ free for the transfer interval.
When not using the CS input, note that the SOUT pin will not go to high impedance state, even after transfer is completed. When not using the CS input, or when CS is “L”, control the external clock because the data in the serial I/O register will continue to shift while the external clock is input, even after the completion of automatic transfer (Note that the automatic transfer interrupt request bit is set and the bit 1 of the serial I/O automatic transfer register is cleared at the point when the specified number of bytes of data have been transferred.) Table GA-2. P67/SRDY1/CS selection SC16 0 SC14 0 1 SIOAC0 ! 0 1 P67/SRDY1/CS P67 SRDY1 CS
Note : SC14: SRDY1 output selection bit SC16: Synchronous clock selection bit SIOAC0: Automatic transfer control bit
Bit 1 write signal of serial I/O automatic transfer control register Bit 1 of serial I/O automatic transfer control register Write signal from RAM to serial I/O1 register Write signal from serial I/O1 register to RAM Data pointer External input CS Transfer clock SCLK input Transfer clock (internal) Serial I/O output SOUT Serial I/O input SIN X DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 X X X X X n n-1
Note: Data marked with X is invalid.
Fig. GA-10 Timing during serial I/O automatic transfer (external clock selected)
29
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The functional blocks of the A-D converter are described below.
b7 b0 AD/DA control register (ADCON : address 002C16) Analog input pin selection bits b3 b2 b1 b0 0 0 0 0 : P70/AN0 0 0 0 1 : P7 1 /AN1 0 0 1 0 : P7 2 /AN2 0 0 1 1 : P7 3 /AN3 0 1 0 0 : P7 4 /AN4 0 1 0 1 : P7 5 /AN5 0 1 1 0 : P7 6 /AN6 0 1 1 1 : P7 7 /AN7 1 0 0 0 : P5 0 /SIN2 /AN8 1 0 0 1 : P5 1 /SOUT2 /AN9 1 0 1 0 : P5 2 /SCLK2 /AN10 1 0 1 1 : P5 3 /SRDY2 /AN11 1 1 0 0 : P5 4 /SIN3 /AN12 1 1 0 1 : P5 5 /SOUT3 /AN13 1 1 1 0 : P5 6 /SCLK3 /AN14 1 1 1 1 : P5 7 /SRDY3 /AN15 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns “0” when read) DA output enable bit 0 : Disable 1 : Enable Not used (returns “0” when read)
A-D Conversion Register (AD) 002D16
The A-D conversion register is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion.
AD/DA Control Register (ADCON) 002C16
The AD/DA control register controls the A-D and the D-A conversion process. Bits 0 to 3 of this register select analog input pins. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. The A-D conversion starts by writing “0” to this bit. Bit 6 controls the output of D-A converter.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P7 7/AN7–P70/ AN0, P57/SRDY3/AN15–P50/SIN2/AN8, and inputs to the comparator.
Fig. JA-1 Structure of A-D control register
Comparator and Control Circuit
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(XIN) to 500 kHz or more during A-D conversion.
Note : When using the A-D conversion interrupt, set the INT 4/AD conversion interrupt switch bit (the bit 5 of the interrupt selection register) to “1”.
30
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
b7 AD-DA control register (address 002C 16 ) 4 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 P50/SIN2 /AN8 P51/Sout2 /AN9 P52/SCLK2 /AN10 P53/SRDY2 /AN11 P54 /SIN3 /AN12 P55/SOUT3 /AN13 P56/SCLK3 /AN14 P57/SRDY3 /AN15 A-D control circuit
b0
A-D conversion interrupt request
Channel selector
Comparator
A-D conversion register (Address 002D 16) 8 Resistor ladder
VREF
AVSS
Fig. JA-2 A-D converter block diagram
D-A CONVERTER
The 3819 group has internal D-A converter with 8-bit resolutions ! 1 channel. D-A conversion is performed by setting the value in the D-A conversion register. The result of D-A conversion is output from the DA pin by setting the DA output enable bit to “1” . At this time, the corresponding bit (PB2/DA) of the port PB direction register should be set to “0” (input status). The output analog voltage V is determined with the value n (n: decimal number) in the D-A conversion register as follows: V=VREF ! n/256 (n=0 to 255) VVREF: the reference voltage At reset, the D-A conversion register is cleared to “0016”, the DA output enable bits are cleared to “0”, and the PB 2/DA pin goes to high impedance state. The D-A output does not build in a buffer, so connect an external buffer when driving a low-impedance load. Set VCC to 3.0 V or more when using the D-A converter.
Data bus
D-A conversion register (8) DA output enable bit R-2R resistor ladder PB2/DA
Fig. JB-1 D-A converter block diagram
"0" DA output enable bit PB2/DA "1" MSB D-A conversion register AVSS VREF "0" "1" 2R
R 2R
R 2R
R 2R
R 2R
R 2R
R 2R
R 2R LSB
2R
Fig. JB-2 Equivalent connection circuit of D-A converter
31
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD CONTROLLER
The 3819 group has fluorescent display (FLD) drive and control circuits. The FLD controller consists of the following components: • 42 pins for segments • 20 pins for digits • FLDC mode register 1 • FLDC mode register 2 • FLD data pointer • FLD data pointer reload register
• Port P0 segment/digit switch register • Port P2 digit/port switch register • Port PA segment/port switch register • Port P8 segment/port switch register • 96-byte FLD automatic display RAM The segment pins can be used from 16 up to 42 pins (maximum) and the digit pins can be used from 6 up to 16 pins (maximum). The segment and the digit pins can be used up to 52 pins (maximum) in total. In the FLD automatic display mode ports P12 to P17 become digit pins DIG10 to DIG15 automatically.
Main address bus
FLD automatic display RAM 0F8016 G1 (SEG PA)
G2 (SEG PA)
Main data bus
Local data bus
S/P S/P S/P S/P S/P S/P S/P S/P PA0 /SEG0 PA1 /SEG1 PA2 /SEG2 PA3 /SEG3 PA4 /SEG4 PA5 /SEG5 PA6 /SEG6 PA7 /SEG7
8
G15 (SEG PA)
0F8F16 G16 (SEG PA) 0F9016 G1 (SEG P8) Local address bus
G2 (SEG P8)
003516
S/P S/P S/P S/P S/P S/P S/P S/P
001416
P80/SEG8 P81/SEG9 P82/SEG10 P83/SEG11 P84/SEG12 P85/SEG13 P86/SEG14 P87/SEG15
G15 (SEG P8)
0F9F16 G16 (SEG P8) 0FA016 G1 (SEG P9)
G2 (SEG P9)
8
003416 0FAF16 0FB016
G15 (SEG P9) G16 (SEG P9) G1 (SEG P3) G2 (SEG P3)
001016
P90/SEG16 P91/SEG17 P92/SEG18 P93/SEG19 P94/SEG20 P95/SEG21 P96/SEG22 P97/SEG23
8
G15 (SEG P3)
0FBF16 G16 (SEG P3) 0FC016 G1 (SEG P0)
G2 (SEG P0)
001216
P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31
8
0FCF16 0FD016
G15 (SEG P0) G16 (SEG P0) G1 (SEG P1) G2 (SEG P1) S/D S/D S/D S/D S/D S/D S/D S/D
000616
G15 (SEG P1) P00/SEG32/DIG0 P01/SEG33/DIG1 P02/SEG34/DIG2 P03/SEG35/DIG3 P04/SEG36/DIG4 P05/SEG37/DIG5 P06/SEG38/DIG6 P07/SEG39/DIG7
0FDF16 G16 (SEG P1)
8
003216 FLD data pointer reload register (address 0038 16)
000016
S/D P10/SEG40/DIG8 S/D P11/SEG41/DIG9 P12/DIG10 P13/DIG11 P14/DIG12 P15/DIG13 P16/DIG14 P17/DIG15
8
Address decoder
FLD data pointer (address 0038 16)
FLDC mode 003716 register 1 (address 0036 16 )
D/P D/P D/P D/P P20/DIG16 P21/DIG17 P22/DIG18 P23/DIG19
000216
4
Timing generator
003316 000416 FLD blanking interrupt FLD digit interrupt
Fig. KA-1 FLD control circuit block diagram
32
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLDC Mode Registers (FLDM 1, FLDM 2) 003616, 003716
The FLDC mode register 1 (address 003616) and FLDC mode register 2 (address 003716) are a seven bit register and an eight bit
b7 b0
register respectively which are used to control the FLD automatic display and set the blanking time Tscan for key-scan.
FLDC mode register 1 (FLDM 1 : address 003616 ) Tscan control bits
b1 b0
0 : 0 FLD digit interrupt (at rising edge of each digit) 1 : 1 ! Tdisp 0 : 2 ! Tdisp FLD blanking interrupt (at falling edge of the last digit) 1 : 3 ! Tdisp Toff control bits (Setting of digit/segment OFF time)
b5 b4 b3 b2
0 0 1 1
0 0 0 0 : 1/16 ! Tdisp 0 0 0 1 : 2/16 ! Tdisp 0 0 1 0 : 3/16 ! Tdisp 0 0 1 1 : 4/16 ! Tdisp 0 1 0 0 : 5/16 ! Tdisp 0 1 0 1 : 6/16 ! Tdisp 0 1 1 0 : 7/16 ! Tdisp 0 1 1 1 : 8/16 ! Tdisp 1 0 0 0 : 9/16 ! Tdisp 1 0 0 1 : 10/16 ! Tdisp 1 0 1 0 : 11/16 ! Tdisp 1 0 1 1 : 12/16 ! Tdisp 1 1 0 0 : 13/16 ! Tdisp 1 1 0 1 : 14/16 ! Tdisp 1 1 1 0 : 15/16 ! Tdisp 1 1 1 1 : 16/16 ! Tdisp Not used (returns “0” when read) High-breakdown-voltage drivability selection bit 0 : Strong drivability 1 : Weak drivability
Fig. KA-2 Structure of FLDC mode register 1
b7
b0 FLDC mode register 2 (FLDM 2 : address 003716 ) Automatic display control bit(P0, P1, P2 0 –P23, P3, P8, P9, PA) 0 : Ordinary mode 1 : Automatic display mode Display start bit 0 : Display stopped 1 : Display in progress (display starts by writing “1” to this bit which is set to “0”) Tdisp control bits (digit time setting, at 8 MHz oscillation frequency) 0 : 128 µs 1 : 256 µs 0 : 384 µs 1 : 512 µs 0 : 640 µs 1 : 768 µs 0 : 896 µs 1 : 1024 µs 0 : 1152 µs 1 : 1280 µs 0 Not available 1111 Pl0 segment/digit switch bit 0 : Digit 1 : Segment Pl1 segment/digit switch bit 0 : Digit 1 : Segment 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1
b5 b4 b3 b2
Fig. KA-3 Structure of FLDC mode register 2
33
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Pins for FLD Automatic Display
Ports P0, P1, P20–P23, P3, P8, P9, and PA is selected for the FLD automatic display function by setting the automatic display control bit of the FLDC mode register 2 (address 003716) to “1”. Table L-1. Pins in FLD automatic display mode Port Name PA0–PA7 Automatic Display Pins SEG0–SEG7 or PA0–PA7 SEG8–SEG15 or P80–P87 SEG16–SEG23 SEG24–SEG31 SEG32–SEG41 or DIG0–DIG9 DIG10–DIG15 DIG16–DIG19 or P20–P23
When using the FLD automatic display mode, set the number of segments and digits for each port.
Setting Method The individual bits of the segment/port switch register (address 003516) can be set each pin to either segment (“1”) or general-purpose I/O port (“0”).
P80–P87 P90–P97 P30–P37 P00–P07 P10, P11 P12–P17 P20–P23
The individual bits of the segment/port switch register (address 003416) can be used to set each pin to either segment (“1”) or general-purpose I/O port (“0”). None (segment only) None (segment only) The individual bits of the segment/digit switch register (address 003216) and the bit 6, 7 of the FLDC mode register 2 can be used to set each pin to segment (“1”) or digit (“0”). (Note) None (digit only) The individual bits of the digit/port switch register (address 003316) can be used to set each pin to digit (“1”) or general-purpose output port (“0”). (Note)
Note : Be sure to set digits in sequence.
Number of segments Number of digits Port PA 0 (has the segment/port 0 switch register) 0 0 0 0 0 0
24 8 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
0 0 0 0 0 0 0 0
30 10 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
1 1 1 1 1 1 1 1
36 16 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
Number of segments Number of digits Port P3 (segment only)
24 8 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
30 10 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
36 16 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
Port P8 0 P80 (has the segment/port 0 P81 switch register) 0 P82 0 P83 0 P84 0 P85 0 P86 0 P87 Port P9 (segment only)
0 0 0 0 1 1 1 1
P80 P81 P82 P83 SEG12 SEG13 SEG14 SEG15
1 1 1 1 1 1 1 1
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
Port P0 1 SEG32 (has the segment/digit 1 SEG33 switch register) 1 SEG34 1 SEG35 1 SEG36 1 SEG37 1 SEG38 1 SEG39 Port P1 0 DIG8 (has the segment/digit 0 DIG9 switch register) DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 Port P2 (has the digit/port switch register) 0 0 0 0 P20 P21 P22 P23
1 1 1 1 1 1 1 1
SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
1 1 1 1 0 0 0 0
SEG32 SEG33 SEG34 SEG35 DIG4 DIG5 DIG6 DIG7
G16 G15 G14 G13
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
G8 G7 G6 G5 G4 G3 G2 G1
1 SEG40 1 SEG41 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 1 1 1 1 DIG16 DIG17 DIG18 DIG19
G10 G9 G8 G7 G6 G5 G4 G3 G2 G1
0 DIG8 0 DIG9 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 1 1 1 1 DIG16 DIG17 DIG18 DIG19
G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1
Fig. KA-4 Segment/digit setting example
34
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q FLD Automatic Display RAM
The FLD automatic display RAM area is the 96 bytes from addresses 0F8016 to 0FDF16. The FLD automatic display RAM area can store 6-byte segment data up to 16 digits (maximum). Addresses 0F8016 to 0F8F 16 are used for PA segment data, addresses 0F9016 to 0F9F 16 are used for P8 segment data, addresses 0FA0 16 to 0FAF16 are used for P9 segment data, addresses 0FB016 to 0FBF16 are used for P3 segment data, addresses 0FC016 to 0FCF16 are used for P0 segment data, and addresses 0FD0 to 0FDF16 are used for P1 segment data.
FLD Data Pointer and FLD Data Pointer Reload Register (FLDDP) 003816
Both the FLD data pointer and FLD data pointer reload register are 7-bit registers allocated at address 003816. When writing data to this address, the data is written to the FLD data pointer reload register, when reading data from this address, the value in the FLD data pointer is read.
The FLD data pointer indicates the data address in the FLD automatic display RAM to be transferred to a segment. The FLD data pointer reload register indicates the first digit address of the most significant segment. The value which adds 0F8016 to these data is actual address in memory. The contents of the FLD data pointer indicate the first address of segment P1(the contents of the FLD data pointer reload register) at the start of automatic display. The FLDC data pointer content changes repeatedly as follows: when transferring the segment P1 data to the segment, the content decreases by –16; when transferring the segment P0 data, it decreases by –16; when transferring the segment P3 data, it decreases by –16; when transferring the segment P9 data, it decreases by –16; when transferring the segment P8 data, it decreases by –16; when transferring the segment PA data, it increases by +79. Once it reaches “00”, at the next timing the value in the FLD data pointer reload register is transferred to the FLD data pointer. In this way, the 6-byte data of P1, P0, P3, P9, P8 and PA segments for 1 digit are transferred.
35
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bit Address 0F8016 0F8116
• • • • • • • • • • • • • • • • • •
7 SEG7 SEG7
6 SEG6 SEG6
5 SEG5 SEG5
4 SEG4 SEG4
• • • • • • • • •
3 SEG3 SEG3
2 SEG2 SEG2
1 SEG1 SEG1
0 SEG0 SEG0 The last digit (The last data of segment PA) Segment PA data area
0F8E16 0F8F16 0F9016 0F9116
• • • • • • • • • • • • • •
SEG7 SEG7 SEG15 SEG15
SEG6 SEG6 SEG14 SEG14
SEG5 SEG5 SEG13 SEG13
SEG4 SEG4 SEG12 SEG12
• • • • • • •
SEG3 SEG3 SEG11 SEG11
SEG2 SEG2 SEG10 SEG10
SEG1 SEG1 SEG9 SEG9
SEG0 SEG0 SEG8 SEG8
The last digit (The last data of segment P8) Segment P8 data area
0F9E16 0F9F16 0FA016 0FA116
• • • • • • • • • • • • • •
SEG15 SEG15 SEG23 SEG23
SEG14 SEG14 SEG22 SEG22
SEG13 SEG13 SEG21 SEG21
SEG12 SEG12 SEG20 SEG20
• • • • • • •
SEG11 SEG11 SEG19 SEG19
SEG10 SEG10 SEG18 SEG18
SEG9 SEG9 SEG17 SEG17
SEG8 SEG8 SEG16 SEG16 The last digit (The last data of segment P9) Segment P9 data area
0FAE16 0FAF16 0FB016 0FB116
• • • • • • • • • • • • • •
SEG23 SEG23 SEG31 SEG31
SEG22 SEG22 SEG30 SEG30
SEG21 SEG21 SEG29 SEG29
SEG20 SEG20 SEG28 SEG28
• • • • • • •
SEG19 SEG19 SEG27 SEG27
SEG18 SEG18 SEG26 SEG26
SEG17 SEG17 SEG25 SEG25
SEG16 SEG16 SEG24 SEG24
The last digit (The last data of segment P3) Segment P3 data area
0FBE16 0FBF16 0FC016 0FC116
• • • • • • • • • • • • • •
SEG31 SEG31 SEG39 SEG39
SEG30 SEG30 SEG38 SEG38
SEG29 SEG29 SEG37 SEG37
SEG28 SEG28 SEG36 SEG36
• • • • • • •
SEG27 SEG27 SEG35 SEG35
SEG26 SEG26 SEG34 SEG34
SEG25 SEG25 SEG33 SEG33
SEG24 SEG24 SEG32 SEG32
The last digit (The last data of segment P0) Segment P0 data area
0FCE 16 0FCF16 0FD016 0FD116
• • • • • • • • • • • • • •
SEG39 SEG39
SEG38 SEG38
SEG37 SEG37
SEG36 SEG36
SEG35 SEG35
SEG34 SEG34
SEG33 SEG33 SEG41 SEG41
SEG32 SEG32 SEG40 SEG40 The last digit (The last data of segment P1) Segment P1 data area
• • • • • • •
0FDE 16 0FDF16
SEG41 SEG41
SEG40 SEG40
Fig. KA-5 FLD automatic display RAM and bit allocation
36
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Data Setup
When data is stored in the FLD automatic display RAM, the last data of segment PA is stored at address 0F8016, the last data of segment P8 is stored at address 0F9016, the last data of segment P9 is stored at address 0FA016 , the last data of segment P3 is stored at address 0FB016, the last data of segment P0 is stored at address 0FC016, and the last data of segment P1 is stored at address 0FD016 t o allocate in se-
quence from the last data respectively. The first data of the segment PA, P8, P9, P3, P0, and P1 is stored at an address which adds the value of (the digit number–1) to the corresponding address 0F8016, 0F9016, 0FA0 16, 0FB016, 0FC016, and 0FD016. Set the low-order 4 bits of the FLD data pointer reload register to the value given by the number of digits–1. “1” is always written to bit 6 and bit 4, and “0” is always written to bit 5. Note that “0” is always read from bits 6, 5 and 4 when reading.
For 30 segments and 15 digits (FLD data pointer reload register = 14)
For 30 segments and 15 digits (FLD data pointer reload register = 14) Bit Address 0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16 Note : 7 6 5 4 3 2 1 0
Bit Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16
7
6
5
4
3
2
1
0
Shaded areas are used.
Fig. KA-6 Example of using the FLD automatic display RAM (1)
37
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
For 42 segments and 8 digits (FLD data pointer reload register = 7) Bit Address 0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16 Note : 7 6 5 4 3 2 1 0
For 42 segments and 8 digits (FLD data pointer reload register = 7) Bit Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16 7 6 5 4 3 2 1 0
Shaded areas are used.
Fig. KA-6 Example of using the FLD automatic display RAM (2) (continued)
38
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Timing Setting
The digit time (Tdisp) can be set with the FLDC mode register 2 (address 003716). The Tscan and digit/segment OFF time (Toff) can be set with the FLDC mode register 1 (address 003616). Note that flickering will occur if the repetition frequency (1/ (Tdisp ! number of digits + Tscan)) is an integral multiple of the digit timing Tdisp.
During automatic display bit 1 of the FLDC mode register 2 always keeps “1”, automatic display can be interrupted by writing “0” to the bit 1.
q Key-scan
If key-scan is performed with the segment during the key-scan blanking period Tscan, take the following sequence: 1. Write “0” to the bit 0 (automatic display control bit) of the FLDC mode register 2 (address 003716). 2. Set the port corresponding to the segment for key-scan to the output port. 3. Perform the key-scan. 4. After the key-scan is performed, write “1” (automatic display mode) to the bit 0 of FLDC mode register 2 (address 003716). Note on performance of key-scan in the above 1 to 4 sequence. 1. Do not write “0” to the bit 1 of FLDC mode register 2 (address 003716). 2. Do not write “1” to the port corresponding to the digit.
q FLD Automatic Display Start
To perform FLD automatic display, set the following registers. • Port P0 segment/digit switch register • Port P2 digit/port switch register • Port P8 segment/port switch register • Port PA segment/port switch register • FLDC mode register 1 • FLDC mode register 2 • FLD data pointer Automatic display mode is selected by writing “1” to the bit 0 of the FLDC mode register 2 (address 003716), and the automatic display is started by writing “1” to the bit 1.
Tdisp
Tscan
Gn G n-1 G n-2
G1
Segment output Segment setting by software FLD digit interrupt occurs at the rising edge of each digit FLD blanking interrupt occurs at the falling edge of the last digit
Digit
Segment
Toff Tdisp
Fig. KA-7 FLDC timing
39
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPT INTERVAL DETERMINATION FUNCTION
The 3819 group builds in an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising transition (falling transition) of an input signal pulse on the P42/INT 2 pin to the rising transition (falling transition) of the signal pulse that is input next. How to determine the interrupt interval is described below. Enable the INT2 interrupt by setting the bit 2 of the interrupt control register 1 (address 003E 16). Select the rising interval or falling interval by setting the bit 2 of the interrupt edge selection register (address 003A16). Set the bit 0 of the interrupt interval determination control register (address 0031 16) to “1” (interrupt interval determination operating). Select the sampling clock of 8-bit binary up counter by setting the bit 1 of the interrupt interval determination control register. When writing “0”, f(XIN)/256 is selected (the sampling interval: 32 µs at f(XIN) = 8.38 MHz) ; when “1”, f(XIN)/512 is selected (the sampling interval: 64 µs at f(XIN) = 8.38 MHz). When the signal of polarity which is set on the INT2 pin (rising or falling transition) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock. When the signal of polarity above is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016), and the remote control interrupt request occurs. Immediately after that, the 8-bit binary up counter is cleared to “0016”. The 8-bit binary up counter continues to count up again from “0016”. When count value reaches “FF16”, the 8-bit binary up counter stops counting up. Then, simultaneously when the next counter sampling clock is input, the counter sets value “FF16” to the interrupt interval determination register to generate the counter overflow interrupt request.
Noise filter
The P42/INT2 pin builds in the noise filter. The noise filter operation is described below. Select the sampling clock of the input signal with the bits 2 and 3 of the interrupt interval determination control register. When not using the noise filter, set “002”. The P42/INT2 input signal is sampled in synchronization with the selected clock. When sampling the same level signal in series, the signal is recognized as the interrupt signal, and the interrupt request occurs. When setting the bit 4 of interrupt interval determination control register to “1”, the interrupt request can occur at both rising and falling edges. When using the noise filter, set the minimum pulse width of the INT2 input signal to 2 cycles or more.
Note : In the low-speed mode (CM7=1), the interrupt interval determination function can not operate.
The counter sampling clock selection bit
f(XIN )/256 f(XIN )/512
8-bit binary up counter
The counter overflow interrupt request or remote control interrupt request
INT2 interrupt input
Noise filter Interrupt interval determination register address 003016
Noise filter sampling clock selection bit 1/64 1/128 Divider
One-sided/both-sided detection selection bit 1/256 Data bus
f(X IN )
Fig. DE-1 Block diagram of interrupt interval datermination circuit
40
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt interval determination control register (IIDCON : address 0031 16) Interrupt interval determination circuit operating selection bit 0 : Stopped 1 : Operating Counter sampling clock selection bit 0 : f(X IN)/256 1 : f(X IN)/512 Noise filter sampling clock selection bits(INT2 ) 0 0 : Filter stop 0 1 : f(X IN)/64 1 0 : f(X IN)/128 1 1 : f(X IN)/256 One-sided/both-sided edge detection selection bit 0 : One-sided edge detection 1 : Both-sided edge detection Not used (return “0” when read)
Fig. DE-2 Structure of interrupt interval determination control register
(When IIDCON 4 = “0”) Noise filter Sampling clock
INT2 pin
Acceptance of interrupt
Counter sampling clock N 8-bit binary up counter value 0 1 2 3 4 5 FE 0 6 Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 6 Remote control interrupt request 1 2 3 0 3 3 Counter overflow interrupt request 1 FF FF FF
6
0
Fig. DE-3 Interrupt interval determination operation example (at rising edge active)
41
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(When IIDCON 4 = “1”) Noise filter Sampling clock
INT2 pin
Acceptance of interrupt Counter sampling clock N 8-bit binary up counter value N Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 0 1 1 1 Remote control interrupt request 0 1 2 3 FE 4 0 4 4 Remote control interrupt request 1 1 1 Remote control interrupt request 0 1 1 1 Remote control interrupt request 0 1 1 1 0 FF FF Counter overflow interrupt request 0 FF
Fig. DE-4 Interrupt interval determination operation example (at both-sided edge active)
42
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ZERO CROSS DETECTION CIRCUIT
The zero cross detection circuit compares the voltage applied to P45/INT1/ZCR pin and VSS. The result can be read from the zero cross detection circuit input bit (bit 7) of the zero cross detection control register. It is set to “1” when the input voltage is higher than VSS and to “0” when it is lower than VSS. The input signal to P45/ INT1/ZCR pin can select to either pass through the zero cross detection comparator or not to do. When using 100 V AC as input signal, insert an external circuit between it and P4 5/INT 1 /ZCR pin. Set the input current limiting resistors used in the external circuit to a value which satisfies the absolute maximum rating of port P45.
VCC 100V AC R1 R2 P45/INT1 /ZCR
VSS
Fig. JE-1 External circuit example for zero cross detection
b7
b0
Zero cross detection control register (ZCRCON : address 003916) Zero cross detection ON/OFF selection bit 0 : Without passing through zero cross detection comparator 1 : Passing through zero cross detection comparator Not used (returns “0” when read) Noise filter sampling clock selection bits (INT1 ) b3 b2 0 0 : Not use noise filter 0 1 : f(XIN )/64 or f(X CIN )/64 1 0 : f(XIN )/128 or f(X CIN )/128 1 1 : f(XIN )/256 or f(X CIN )/256 One-sided/both-sided edge detection selection bit 0 : One-sided edge detection 1 : Both-sided edge detection Not used (return “0” when read) Zero cross detection circuit input bit (read only) 0 : Less than 0 V 1 : 0 V or more
Fig. JE-2 Structure of zero cross detection control register
P45/INT1 /ZCR Zero cross detection ON/OFF selection bit “0” “1” Rising/falling edge switch When not using the filter When using the filter INT1/ZCR interrupt request
Zero cross detection circuit input bit Zero cross detection comparator
Noise filter
One-sided/both-sided edge detection selection bit Noise filter sampling clock selection bit f(XCIN ) f(XIN )
1/256 1/28 1/64 Divider
Fig. JE-3 Block diagram of zero cross detection circuit
43
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOISE FILTER
The noise filter uses a sampling clock to remove the noise component digitally from the input signal of P4 5 /INT 1 /ZCR pin. The sampling clock can be selected from 8 µs, 16 µs, or 32 µ s (at f(XIN)= 8.38 MHz) and this is used to change the noise component to be removed. It is also possible to generate an internal trigger and INT1/ZCR interrupt request directly without passing through
the noise filter. When passing through the noise filter, either bothsided edge detection or one-sided edge detection can be selected as the interrupt request generating source. The zero cross detection control register is used for this selection. Furthermore, switch between rising edge and falling edge is performed with the bit 1 of the interrupt edge selection register (address 003A16).
Input signal from P45/INT1 /ZCR pin
D C R
Q
A
D C R
Q
B
S R
Q
C
D C R
Q
One-sided/both-sided edge detection selection bit (bit 4 of ZCRCON) “0” INT1 /ZCR “1” interrupt request
Sampling clock
RESET
Fig. JE-4 Noise filter circuit diagram
RESET Sampling clock P45/INT1/ZCR Input signal from P45/INT1 /ZCR pin A B C (one-sided edge) (both-sided edge) (Note 2) Switched with bit 4 of ZCRCON (Note 1) 0V
INT1 /ZCR interrupt request
Notes 1 2
: Ignored this because of treating this as noise : INT1/ZCR interrupt request occurs
Fig. JE-5 Timing of noise filter circuit
44
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 2.8 V and 5.5 V, and XIN oscillation is stable), reset is released. In order to give the X IN clock time to stabilize, internal operation does not begin until after about 4000 XIN clock cycles (256 cycles of f(XIN)/16) are completed. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order) and address FFFC16 (low-order). Make sure that the reset input voltage is 0.5 V or less for 2.8 V of VCC.
Poweron Power source voltage RESET VCC 0V Reset input voltage 0.2VCC 0V Note : Reset release voltage : V CC = 2.8 V (Note)
RESET
VCC Power source voltage detection circuit
Fig. VB-2 Example of reset circuit
XIN φ RESET Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH, ADL Reset address from vector table
Data SYNC about 4000 XIN clock cycles
?
?
?
?
ADL
ADH
Notes 1 : f(XIN ) and f( φ) are in the relationship : f(X IN ) = 8•f(φ) 2 : A question mark (?) indicates an undefined state that depends on the previous state.
Fig. VB-2 Reset sequence
45
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address (1) Port P0 (2) Port P1 (3) Port P2 (4) Port P2 direction register (5) Port P3 (6) Port P4 (7) Port P4 direction register (8) Port P5 (9) Port P5 direction register (10) Port P6 (11) Port P6 direction register (12) Port P7 (13) Port P7 direction register (14) Port P8 (15) Port P8 direction register (16) Port P9 (17) Port PA (18) Port PA direction register (19) Port PB (20) Port PB direction register (21) Serial I/O1 control register (22) Serial I/O automatic transfer control register (23) Serial I/O automatic transfer interval register (24) Serial I/O2 control register (25) Serial I/O3 control register (26) Timer 1 (27) Timer 2 (28) Timer 3 (29) Timer 4 (30) Timer 5 (001D16) • • • (001E16) • • • (002016) • • • (002116) • • • (002216) • • • (002316) • • • (002416) • • • (001C16) • • • (000016) • • • (000216) • • • (000416) • • • (000516) • • • (000616) • • • (000816) • • • (000916) • • • (000A16) • • • (000B16) • • • (000C16) • • • (000D16) • • • (000E16) • • • (000F16) • • • (001016) • • • (001116) • • • (001216) • • • (001416) • • • (001516) • • • (001616) • • • (001716) • • • (001916) • • • (001A16) • • •
Register contents 0016 0016 0016 0F16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (31) Timer 6 (32) Timer 12 mode register (33) Timer 34 mode register (34) Timer 56 mode register (35) D-A conversion register (36) AD/DA control register (37) Interrupt interval determination control register (38) Port P0 segment/digit switch register (39) Port P2 digit/port switching register (40) Port P8 segment/port switch register (41) Port PA segment/port switch (42) FLDC mode register 1 (43) FLDC mode register 2 (44) Zero cross detection control register (45) Interrupt edge selection register (46) CPU mode register (47) Interrupt request register 1 (48) Interrupt request register 2 0016 (49) Interrupt control register 1 (50) Interrupt control register 2 0016 0016 FF16 0116 FF16 FF16 FF16 (51) Processor status register (52) Program counter
Address (002516) • • • (002816) • • • (002916) • • • (002A16 ) • • • (002B16 ) • • • (002C16) • • • (003116) • • •
Register contents FF16 0016 0016 0016 0016 1016 0016
(003216) • • •
0016
(003316) • • •
0016
(003416) • • •
0016
(003516) • • • (003616) • • • (003716) • • • (003916) • • •
0016 0016 0016 0016
(003A16 ) • • •
0016
(003B16 ) • • • 0 1 0 0 1 0 0 0 (003C16) • • • (003D16) • • • (003E16 ) • • • (003F16) • • • 0016 0016 0016 0016
(PS) • • • ! ! ! ! ! 1 ! ! (PCH) • • • Contents of address FFFD16 (PCL ) • • • Contents of address FFFC16
Note : ! : Undefined The contents of all other registers and RAM are undefined at reset, so set their initial values.
Fig. VB-3 Internal status at reset
46
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3819 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after poweron, only the X IN oscillation circuit starts oscillation, and XCIN and XCOUT pins function as I/O ports.
Oscillation Control
Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1, and the output of timer 1 is connected to timer 2. The bits of the timer 12 mode register are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 1 underflows. When using an external resonator, it is necessary for oscillating to stabilize. Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
Frequency Control
Middle-speed mode The internal clock φ is the frequency of X IN divided by 8. After reset, this mode is selected. High-speed mode The internal clock φ is half the frequency of XIN. Low-speed mode The internal clock φ is half the frequency of XCIN.
Note : If you switch the mode between middle/high-speed and low-speed, stabilize both X IN a nd XCIN o scillations. The sufficient time is required for the X CIN oscillation to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3·f(XCIN).
Low-power dissipation mode When stopping the main clock XIN in the low-speed mode, the lowpower dissipation operation starts. To stop the main clock, set the bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. The low-power dissipation operation 200 µA or less (at f(XIN) = 32 kHz) can be realized by reducing the XCIN–XCOUT drivability. To reduce the XCIN–XCOUT drivability, clear the bit 3 of the CPU mode register to “0”. At reset or when executing the STP instruction, this bit is set to “1” and strong drivability is selected to help the oscillation to start.
XCIN
XCOUT Rf
XIN
XOUT
Rd CCOUT CIN COUT
CCIN
Fig. WA-1 Ceramic resonator external circuit
XCIN
XCOUT Open
XIN
XOUT Open
External oscillation circuit or pulse VCC VSS VCC VSS
External oscillation circuit
Fig. WA-2 External clock input circuit
47
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT “1” “0” Port XC switch bit (Note 3)
XIN
Internal system clock selection bit (Note 1, 3) Low-speed mode “1” 1/2 1/4 1/2 “0” Middle/ High-speed mode XOUT
Timer 1 count source selection bit (Note 2) “1” Timer 1 “0”
Main clock division ratio selection bit (Note 3) Middle-speed mode High-speed mode or Low-speed mode Main clock stop bit (Note 3) Timing φ (Internal clock)
Q
S R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag I Interrupt request Notes 1 : When selecting the low-speed mode, set the port X C switch bit to “1”. 2 : Refer to the structure of timer 12 mode register. 3 : Refer to the structure of CPU mode register (next page).
Fig. WA-3 Clock generating circuit block diagram
48
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode ( φ =1 MHz) CM 7 = 0 (8 MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (X IN oscillating) CM 4 = 0 (32 kHz stopped)
CM 6 “1” “0”
High-speed mode ( φ = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (X IN oscillating) CM4 = 0 (32 kHz stopped)
“0”
4 ” CM “0 ” 6 “1 CM “0” ” “1
CM 4
“1”
6
“0
”
High-speed mode ( φ = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (X IN oscillating) CM4 = 1 (32 kHz oscillating)
Middle-speed mode ( φ =1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (X IN oscillating) CM4 = 1 (32 kHz oscillating)
CM6 “1” “0”
“0”
CM 7
“1”
CM7 CM6 “1” “0” Low-speed mode ( φ = 16 kHz) CM7 = 1 (32 kHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (X IN oscillating) CM 4 = 1 (32 kHz oscillating) “1”
Low-speed mode ( φ =16 kHz) CM 7 = 1 (32 kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (X IN oscillating) CM 4 = 1 (32 kHz oscillating)
“0”
“1”
“1
”
CM
“1
”
CM4
“0
”
CM
4
“0”
b7
b0
CPU mode register (CPUM (CM) : address 003B 16)
CM 5
“1”
6
“1
”
“0
”
Low power dissipation mode ( φ =16 kHz) CM6 CM7 = 1 (32 kHz selected) “1” “0” CM6 = 1 (Middle-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32 kHz oscillating)
Low power dissipation mode ( φ =16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (X IN stopped) CM4 = 1 (32 kHz oscillating)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. Timer operates in the wait mode. 3 : When the stop mode is released in middle/high-speed mode, a delay of approximately 0.5 ms occurs automatically by timer 1. 4 : When the stop mode is released in low-speed mode, a delay of approximately 0.125 s occurs automatically by timer 1. 5 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the X CIN pin. φ indicates the internal clock.
Fig. WA-4 State transitions of system clock
“1”
“1
”
CM
6
“
0”
“1
”
CM
“1
”
CM5
CM
5
” “0
“0
”
CM
5
CM 4 : Port X C switch bit 0 : I/O port function 1 : X CIN -XCOUT oscillating function CM 5 : Main clock (X IN-X OUT) stop bit 0 : Oscillating 1 : Stopped CM 6 : Main clock division ratio selection bit 0 : f(X IN)/2 (high-speed mode) 1 : f(X IN)/8 (middle-speed mode) CM 7 : Internal system clock selection bit 0 : X IN -XOUT selected (middle/high-speed mode) 1 : X CIN -XCOUT selected (low-speed mode)
“0”
“0”
49
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
When using an external clock, input “H” to the external clock input pin and clear the serial I/O interrupt request bit before executing serial I/O transfer and serial I/O automatic transfer. When using the internal clock, set the synchronous clock to internal clock, then clear the serial I/O interrupt request bit before executing a serial I/O transfer and serial I/O automatic transfer.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500 kHz or more during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flag are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the XIN or XCIN frequency.
At the STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register are cleared. The XCOUT drivability selection bit (the CPU mode register) is set to “1” (high drive) in order to start oscillating.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: • the data transfer instruction (LDA, etc.) • the operation instruction when the index X mode flag (T) is “1” • the addressing mode which uses the value of a direction register as an index • the bit-test instruction (BBC or BBS, etc.) to a direction register • the read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
50
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
PROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter.
Package 100P6S-A 100D0
Name of Programming Adapter PCA4738F-100A PCA4738L-100A
Set the address of PROM programmer in the user ROM area. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after writing, the procedure shown in Figure XC-1 is recommended to verify programming.
Programming with PROM Programmer
Screening (Caution) (150°C for 40 hours)
Verification with PROM Programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours.
Fig. XC-1 Programming and testing of One Time PROM version
51
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VEE VI VI VI VI VI VO Parameter Power source voltage Pull-down power source voltage Input voltage P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, PB0–PB3 Input voltage P40, P45 Input voltage P80–P87, PA0–PA7 All voltages are based on VSS. Input voltage RESET, XIN Output transistors are cut off. Input voltage XCIN Output voltage P00–P07, P10–P17, P20–P23, P30–P37, P80–P87, P90–P97, PA0–PA7 Output voltage P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, PB0–PB3, XOUT, XCOUT Ta = 25°C Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 7.0 VCC –40 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 VCC –40 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 VCC –40 to VCC +0.3 Unit V V V V V V V V
VO Pd Topr Tstg
–0.3 to VCC +0.3 600 –10 to 85 –40 to 125
V mW °C °C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VSS VEE VREF AVSS VIA VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL Power source voltage Parameter High-speed mode Middle/Low-speed mode
(Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted) Min. 4.0 2.8 VCC–38 2.0 3.0 0 0 0.75VCC 0.4VCC 0.8VCC 0.8VCC 0.8VCC 0 0 0 0 0 VCC VCC VCC VCC VCC VCC 0.25VCC 0.16VCC 0.2VCC 0.2VCC 0.2VCC Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC VCC VCC Unit V V V V V V V V V V V V V V V V V V
Power source voltage Pull-down power source voltage Analog reference voltage (when using A-D converter) Analog reference voltage (when using D-A converter) Analog power source voltage Analog input voltage AN0–AN15 “H” input voltage P40–P47, P50–P57, P60–P67, P70–P77, PB0–PB3 “H” input voltage P24–P27 “H” input voltage P80–P87, PA0–PA7 “H” input voltage RESET “H” input voltage XIN, XCIN “L” input voltage P40–P47, P50–P57, P60–P67, P70–P77, PB0–PB3 “L” input voltage “L” input voltage “L” input voltage “L” input voltage P24–P27 P80–P87, PA0–PA7 RESET XIN, XCIN
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MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
(Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted) Limits Min. Typ. Max. –240 Unit
ΣIOH(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN)
“H” total peak output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87, P90–P97, (Note 1) PA6, PA7 “H” total peak output current P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, PA0–PA5, (Note 1) PB0–PB3 “L” total peak output current P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, (Note 1) PB0–PB3 “H” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P80–P87, P90–P97, (Note 1) PA6, PA7 “H” total average output current P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, PA0–PA5, (Note 1) PB0–PB3 “L” total average output current P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, (Note 1) PB0–PB3 “H” peak output current P00–P07, P10–P17, P20–P23, P30–P37, P80–P87, P90–P97, (Note 2) PA0–PA7 “H” peak output current P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, (Note 2) PB0–PB3 “L” peak output current P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, (Note 3) PB0–PB3 “H” average output current P00–P07, P10–P17, P20–P23, P30–P37, P80–P87, P90–P97, (Note 3) PA0–PA7 “H” average output current P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, (Note 3) PB0–PB3 “L” average output current P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, (Note 3) PB0–PB3 Clock input frequency for timers 2 and 4 (duty cycle 50%) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5)
mA
–60
mA
100
mA
–120
mA
–30
mA
50
mA
–40
mA
–10
mA
10
mA
–18
mA
–5.0
mA
5.0 250 8.4 50
mA kHz MHz kHz
32.768
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports.The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current in an average value measured over 100 ms. 4 : When the oscillation frequency has a 50% duty cycle. 5 : When using the microcomputer in low-speed operation mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
53
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Symbol Parameter
(Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted) Limits Test conditions Min. VCC–2.0 Typ. Max. Unit
VOH
VOH
VOL
“H” output voltage P00–P07, P10–P17, P20–P23, P30–P37, P80–P87, P90–P97, PA0–PA7 “H” output voltage P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, PB0–PB3 “L” output voltage P24–P27, P41–P44, P46, P47, P50–P57, P60–P67, P70–P77, PB0–PB3 Hysteresis INT0–INT4, SIN1, SIN2, SIN3, SCLK11, SCLK2, SCLK3, CS, CNTR0, CNTR1 Hysteresis RESET, XIN Hysteresis XCIN “H” input current P24–P27, P40–P47, P50–P57, P60–P67, P70–P77, PB0–PB3 “H” input current P80–P87, PA0–PA7 (Note) “H” input current RESET, X CIN “H” input current XIN “L” input current P24–P27, P40–P47, P50–P57, P60–P67, P70–P77, PB0–PB3 “L” input current P80–P87, PA0–PA7 (Note) “L” input current RESET, XCIN “L” input current XIN Output load current P00–P07, P10–P17, P20–P23, P30–P37, P90–P97 Output leakage current P00–P07, P10–P17, P20–P23, P30–P37, P80–P87, P90–P97, PA0–PA7 RAM hold voltage
IOH=–18 mA
V
IOH=–10 mA
VCC–2.0
V
IOL=10 mA When using a non-port function
2.0
V
VT+–VT– VT+–VT– VT+–VT– IH IH IH IH IL IL IL IL ILOAD
0.4 0.5 0.5
V V V 5.0 5.0 5.0 µA µA µA µA µA µA µA µA µA
VI=VCC VI=VCC VI=VCC VI=VCC VI=VSS VI=VSS VI=VSS VI=VSS VEE=VCC–36 V, VOL=VCC, Output transistors “off” VEE=VCC–38 V, VOL=VCC–38 V, Output transistors “off” When clock is stopped 2
4.0 –5.0 –5.0 –5.0 –4.0 150 500 900
ILEAK
–10
µA
VRAM
5.5
V
Note : Except when reading ports P8 or PA.
54
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol Parameter Test conditions • High-speed mode f(XIN) = 8.4 MHz f(XCIN) = 32 kHz Output transistors “off” • High-speed mode f(XIN) = 8.4 MHz (in WIT state) f(XCIN) = 32 kHz Output transistors “off” • Middle-speed mode f(XIN) = 8.4 MHz f(XCIN) = stopped Output transistors “off” • Middle-speed mode f(XIN) = 8.4 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” • Low-speed mode f(XIN) = stopped, f(XCIN) = 32 kHz Low-power dissipation mode set (CM3) = 0 Output transistors “off” • Low-speed mode f(XIN) = stopped f(XCIN) = 32 kHz (in WIT state) Low-power dissipation mode set (CM3) = 0 Output transistors “off” Increase at A-D converter operating f(XIN) = 8.4 MHz Increase at zero cross detection (P45 = VCC) All oscillation stopped Ta = 25°C (in STP state) Output transistors “off” Ta = 85°C 60 200 µA Min. Limits Typ. Max. Unit
7.5
15
mA
1
mA
3
mA
1
mA
ICC
Power source current
20
40
µA
0.6 1 0.1 1 10
mA mA µA
55
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ZERO CROSS DETECTION INPUT CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted) Symbol fZCR ∆VT Parameter Input frequency of zero cross detection Voltage error of zero cross detection distinction Test conditions Limits Min. –100 Typ. 50, 60 0 Max. 1000 100 Unit Hz mV
50 Hz or 60 Hz
1/fZCR
100V AC
P45 /INT1/ZCR clamp correction input waveform
5.7 V VT VI 0V – 0.7 V
Zero cross detection comparator output
Fig. ZA-1 Zero cross detection input characteristics
A-D CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, high-speed operation mode f(XIN) = 500 kHz to 8.4 MHz, unless otherwise noted) Symbol – – TCONV IVREF IIA RLADDER Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Reference power source input current Analog port input current Ladder resistor Test conditions Limits Min. Typ. ±1 49 50 150 0.5 35 Max. 8 ±2.5 50 200 5.0 Unit Bits LSB t c ( φ) µA µA kΩ
VCC = VREF = 5.12 V VREF = 5 V
D-A CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to VCC, Ta = –10 to 85°C, unless otherwise noted) Symbol – – Tsu RO IVREF Resolution Absolute accuracy VCC = 4.0 to 5.5 V VCC = 3.0 to 5.5 V 1 2.5 Parameter Test conditions Limits Min. Typ. Max. 8 1.0 2.5 3 4 3.2 Unit Bits % % µs kΩ mA
Setting time Output resistor Reference power source input current (Note)
Note : Exclude currents flowing through the A-D converter ladder resistor
56
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XcIN) tWH(XcIN) tWL(XcIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK–SIN) th(SCLK–SIN) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width Sub-clock input cycle time (XCIN input) Sub-clock input “H” pulse width Sub-clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0–INT4 input “H” pulse width INT0–INT4 input “L” pulse width Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input setup time Serial I/O input hold time Limits Min. 2.0 119 30 30 20 5.0 5.0 4.0 1.6 1.6 80 80 1.0 400 400 200 200 Typ. Max. Unit µs ns ns ns µs µs µs µs µs µs ns ns µs ns ns ns ns
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol tWH(SCLK) tWL(SCLK) td(SCLK–SOUT) tv(SCLK–SOUT) tr(SCLK) tf(SCLK) tr(Pch–strg) tf(Pch–weak) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output hold time Serial I/O clock output rising time Serial I/O clock output falling time High-breakdown-voltage P-channel opendrain output rising time (Note 1) High-breakdown-voltage P-channel opendrain output falling time (Note 2) Test conditions CL = 100 pF CL = 100 pF Limits Min. tc(SCLK) /2–160 tc(SCLK) /2–160 0.2tc(SCLK) 0 CL = 100 pF CL = 100 pF CL = 100 pF VEE = VCC –36 V CL = 100 pF VEE = VCC –36 V 55 1.8 40 40 Typ. Max. Unit ns ns ns ns ns ns ns µs
Notes 1 : When the bit 7 of the FLDC mode register 1 (address 003616) is at “0”. 2 : When the bit 7 of the FLDC mode register 1 (address 003616) is at “1”.
Serial clock output port
P56/SCLK3 , P52/SCLK2 , P66/SCLK11 CL
High-breakdown-voltage P-channel open-drain output port
P0, P1, P20 –P23, P3, P8, P9, PA CL
(Note) Note : Ports P8 and PA need external resistors.
VEE
Fig. ZA-2 Circuit for measuring output switching characteristics
57
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tC(CNTR)
tWH(CNTR) tWL(CNTR)
CNTR0 CNTR1
0.8VCC 0.2VCC
tWH(INT)
tWL(INT)
0.8VCC
INT0INT4
0.2VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN)
XIN
0.8VCC
0.2VCC
tC(XCIN) tWH(XCIN) tWL(XCIN)
XCIN
0.8VCC
0.2VCC
tC(SCLK)
t
f
tWL(SCLK)
0.2VCC
t
r
tWH(SCLK)
SCLK
0.8VCC
tsu(SIN-SCLK)
0.8VCC
th(SCLK-SIN)
SIN
0.2VCC
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
58
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
•
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•
© 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jan. 1998. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
3819 GROUP DATA SHEET
Revision Description Rev. date 980109
(1/1)
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