M38827FD-XXXHP

3882 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0089-0101 Rev.1.01 Nov 14, 2005 GENERAL DESCRIPTION The 3882 group is the 8-bit microcomputer based on the 740 family core technology. The 3882 group is designed for Keyboard Controller for the note book PC. FEATURES q Basic machine-language instructions ...................................... 71 q Minimum instruction execution time .................................. 0.5 µs (at 8 MHz oscillation frequency) q Memory size ROM ............................................................................. 20K bytes RAM ............................................................................ 1024 bytes q Programmable input/output ports ............................................ 72 q Software pull-up transistors ....................................................... 8 q Interrupts ................................................. 17 sources, 14 vectors q Timers ............................................................................. 8-bit ✕ 4 q Watchdog timer ............................................................ 16-bit ✕ 1 q LPC interface .............................................................. 2 channels q Serialized IRQ ................................................................ 3 factors q Clock generating circuit ..................................... Built-in 1 circuits (connect to external ceramic resonator) q Power source voltage ................................................ 3.0 to 3.6 V q Power dissipation In high-speed mode .......................................................... 20 mW (at 8 MHz oscillation frequency, at 3.3 V power source voltage) q Operating temperature range .................................... –20 to 85°C APPLICATION Note book PC PIN CONFIGURATION (TOP VIEW) 48 47 46 45 60 59 58 44 43 51 50 49 57 56 55 54 53 52 42 41 40 39 38 37 36 35 34 33 P32 P33 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P31 P30 P87/SERIRQ P86/LCLK P85/LRESET P84/LFRAME P83/LAD3 P82/LAD2 P81/LAD1 P80/LAD0 VCC NC NC P67 P66 P65 P64 P63 P62 P61 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M38827G5-XXXHP M38827G5HP 32 31 30 29 28 27 26 25 24 23 22 21 P16 P17 P20 P21 P22 P23 P24(LED0) P25(LED1) P26(LED2) P27(LED3) VSS XOUT XIN P40 P41 RESET CNVSS P42/INT0 P43/INT1 P44 13 14 15 16 17 12 11 Package type : PLQP0080KB-A (80P6Q-A) Fig. 1 Pin configuration Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 1 of 60 P60 P77 P76 P75/INT41 P74/INT31 P73/INT21 P72 P71 P70 P57 P56 P55/CNTR1 P54/CNTR0 P53/INT40 P52/INT30 P51/INT20 P50/INT5 P47/CLKRUN P46 P45 10 18 19 20 6 3 4 5 7 8 1 2 9 FUNCTIONAL BLOCK DIAGRAM (Package : PLQP0080KB-A) Reset input VSS VCC RESET 25 24 71 30 3882 Group Main-clock input XIN CNVSS Main-clock output XOUT Rev.1.01 Nov 14, 2005 REJ03B0089-0101 CPU Fig. 2 Functional block diagram A X Prescaler 12 (8) Prescaler X (8) 28 29 Clock generating circuit page 2 of 60 RAM ROM Y Timer 1 (8) Timer 2 (8) Timer X (8) Timer Y (8) S PC H Prescaler Y (8) PC L PS CNTR0 CNTR1 Watchdog timer Reset CLKRUN INT20, INT30, INT40, INT5 INT0, INT1 LPC interface INT21, INT31, INT41 Key-on wake-up P8(8) P6(8) P5(8) P7(8) P4(8) P3(8) P2(8) P1(8) P0(8) 63 64 65 66 67 68 69 70 23456789 72 73 74 75 76 77 78 79 80 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 26 27 55 56 57 58 59 60 61 62 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 NC NC I/O port P8 I/O port P6 I/O port P7 I/O port P5 I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0 3882 Group PIN DESCRIPTION Table 1 Pin description (1) Pin VCC, VSS CNVSS RESET XIN XOUT Name Power source CNVSS input Reset input Clock input Clock output Functions •Apply voltage of 3.3 V ±10 % to Vcc, and 0 V to Vss. •Connected to VSS. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator between the XIN and XOUT pins to set the oscillation frequency. •When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •8-bit I/O port. P00–P07 I/O port P0 •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure or N-channel open-drain output structure. •8-bit I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level. •CMOS 3-state output structure or N-channel open-drain output structure. •8-bit I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. P20–P27 I/O port P2 •CMOS compatible input level. •CMOS 3-state output structure. •P24 to P27 (4 bits) are enabled to output large current for LED drive. •8-bit I/O port. •I/O direction register allows each pin to be individually programmed as either input or output. P30–P37 I/O port P3 •CMOS compatible input level. •CMOS 3-state output structure. •These pins function as key-on wake-up . •These pins are enabled to control pull-up. •Key-on wake-up input pins Function except a port function P10–P17 I/O port P1 Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 3 of 60 3882 Group Table 2 Pin description (2) Pin P40 P41 P42/INT0 P43/INT1 P44 P45 P46 P47 /CLKRUN P50/INT5 P51/INT20 P52/INT30 P53/INT40 P54/CNTR0 P55/CNTR1 P56 P57 •8-bit I/O port with the same function as port P0 P60–P67 P70 P71 P72 P73/INT21 P74/INT31 P75/INT41 P76 P77 P80/LAD0 P81/LAD1 P82/LAD2 P83/LAD3 P84/LFRAME P85/LRESET P86/LCLK P87/SERIRQ I/O port P6 •CMOS compatible input level. •CMOS 3-state output structure. •8-bit CMOS I/O port with the same function as port P0 P70–P75 : CMOS compatible input level or TTL compatible input level I/O port P7 P76, P77 : CMOS compatible input level N-channel open-drain output structure •Each pin level of P7 0 to P75 can be read even in output port mode. •8-bit CMOS I/O port with the same function as port P0 •CMOS compatible input level. •CMOS 3-state output structure. I/O port P8 •LPC interface function pins •Interrupt input pins I/O port P4 Name Functions •8-bit I/O port with the same function as port P0 CMOS compatible input level P40, P41 : CMOS 3-state output structure P42-P47 : CMOS 3-state output structure or Nchannel open-drain output structure •Each pin level of P42 to P46 can be read even in output port mode. •8-bit I/O port with the same function as port P0 •CMOS compatible input level •CMOS 3-state output structure I/O port P5 •Timer X, timer Y function pins •Interrupt input pins •Serialized IRQ function pin •Interrupt input pins Function except a port function •Serialized IRQ function pin Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 4 of 60 3882 Group PART NUMBERING Product name M3882 7 G 5 -XXX HP Package type HP : PLQP0080KB-A ROM number Omitted in in shipped in blank version. ROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 9: 36864 bytes A: 40960 bytes B: 45056 bytes C: 49152 bytes D: 53248 bytes E: 57344 bytes 7 : 28672 bytes F: 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; user cannot use those bytes. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version F : Flash memory version G : QzROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 3 Part numbering Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 5 of 60 3882 Group GROUP EXPANSION Renesas plans to expand the 3882 group as follows. Packages PLQP0080KB-A ....................... 0.5 mm-pitch plastic molded LQFP Memory Type Support for QzROM version. Memory Size ROM size ........................................................................ 20 K bytes RAM size ....................................................................... 1024 bytes Memory Expansion ROM size (bytes) ROM external 60K 56K 48K 40K 32K 24K M38827G5 16K 8K 256 512 768 1024 1280 RAM size (bytes) 1536 1792 2048 Fig. 4 Memory expansion plan Table 3 Products plan list Product name M38827G5-XXXHP M38827G5HP Notes 1: This means a shipment of which User ROM has been programmed. 2: The user ROM area of a blank product is blank. As of Nov 2005 RAM size (bytes) 1024 Package 80P6Q-A Remarks QzROM version (Programmed shipment) (Note 1) QzROM version (blank) (Note 2) ROM size (bytes) ROM size for User in ( ) 20480(20350) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 6 of 60 3882 Group FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3882 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 5 740 Family CPU register structure Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 7 of 60 3882 Group On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 6 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 8 of 60 3882 Group [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 9 of 60 3882 Group [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. b7 b0 0 01 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Fix this bit to “0”. Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : Not available 1 1 : Not available Fig. 7 Structure of CPU mode register Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 10 of 60 3882 Group MEMORY RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special Function Register (SFR) Area The special function register area contains the control registers such as I/O ports, timers, serial I/O, etc. ROM Code Protect Address “0016 ” is written into ROM code protect address (other than the user ROM area) when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp..When “ 00 16 ” i s set to the ROM code protect address,the protect function is enabled,so that reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing,“0016 ” (protect enabled) or “FF16 ” (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of “0016" or “FF16 ” can be selected as ROM option setup (“MASK option ” written in the mask file converter) when ordering. ROM ROM is used for program code and data table storage. The first 128 bytes and the last 2 bytes of ROM are reserved for device testing code and the rest is user area. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. 000016 SFR area RAM area RAM size (bytes) Address XXXX16 004016 010016 RAM Zero page 1024 043F16 XXXX16 Not used 0FF016 0FFF16 SFR area YYYY16 Reserved ROM area (Note) (128 bytes) ZZZZ16 ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 20480 B00016 B08016 ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area (Note) Special page Notes: This area is reserved in the QzROM version. Fig. 8 Memory map diagram Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 11 of 60 3882 Group 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8)/Port P4 input register (P4I) Port P8 direction register (P8D)/Port P7 input register (P7I) 002016 Prescaler 12 (PRE12) 002116 Timer 1 (T1) 002216 Timer 2 (T2) 002316 Timer XY mode register (TM) 002416 002516 002616 002716 002816 Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Data bas buffer register 0 (DBB0) 002916 Data bas buffer status register 0 (DBBSTS0) 002A16 002B16 LPC control register (LPCCON) Data bas buffer register 1 (DBB1) 002C16 Data bas buffer status register 1 (DBBSTS1) 002D16 002E16 Port control register 1 (PCTL1) 002F16 Port control register 2 (PCTL2) 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Serialized IRQ control register (SERCON) Watchdog timer control register (WDTCON) Serialized IRQ request register (SERIRQ) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) 0FF016 LPC0 address register L (LPC0ADL) 0FF116 LPC0 address register H (LPC0ADH) 0FF216 LPC1 address register L (LPC1ADL) 0FF316 LPC1 address register H (LPC1ADH) 0FF816 Port P5 input register (P5I) 0FF916 Port control register 3 (PCTL3) Fig. 9 Memory map of special function register (SFR) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 12 of 60 3882 Group I/O PORTS All I/O pins are programmable as input or output. All I/O ports have direction registers which specify the data direction of each pin like input/output. One bit in a direction register corresponds to one pin. Each pin can be set to be input or output port. Writing “0” to the bit corresponding to the pin, that pin becomes an input mode. Writing “ 1 ” t o the bit, that pin becomes an output mode. When the data is read from the bit of the port register corresponding to the pin which is set to output, the value shows the port latch data, not the input level of the pin. When a pin set to input, the pin Table 6 I/O port function (1) Pin P00-P07 P10-P17 P20-P27 Name Port P0 Port P1 Port P2 CMOS compatible input level CMOS 3-state output Input/Output I/O Structure CMOS compatible input level CMOS 3-state output or N-channel opendrain output comes floating. In input port mode, writing the port register changes only the data of the port latch and the pin remains high impedance state. When the P8 function selection bit of the port control register 2 is set to “1”, reading from address 001016 reads the port P4 register, and reading from address 001116 reads the port P7 register. Especially, the input level of P42 to P46 pins and P70 to P75 pins can be read regardless of the data of the direction registers in this case. Non-Port Function Related SFRs Port control register 1 Ref.No. (1) (2) P30-P37 Port P3 Key-on wake up input Port control register 1 (3) P40 P41 P42/INT0 P43/INT1 P44 P45 P46 Port P4 (4) Input/output, individual bits CMOS compatible input level CMOS 3-state output or N-channel opendrain output Serialized IRQ function output External interrupt input Interrupt edge selection register Port control register 2 (5) Port control register 2 (6) P47/CLKRUN Serialized IRQ control register (7) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 13 of 60 3882 Group Table 7 I/O port function (2) Pin P50/INT5 P51/INT20 P52/INT30 P53/INT40 Port P5 P54/CNTR0 P55/CNTR1 P56 P57 P60– P67 P70 P71 P72 P73/INT21 P74/INT31 P75/INT41 P76 P77 P80/LAD0 P81/LAD1 P82/LAD2 P83/LAD3 P84/ LFRAME P85/ LRESET P86/LCLK P87/ SERIRQ Port P7 Input/output, individual bits Port P6 CMOS compatible input level CMOS 3-state output Name Input/Output I/O Format CMOS compatible input level CMOS 3-state output or N-channel opendrain output Non-Port Function Related SFRs Interrupt edge selection register Port control register 2 Port control register 3 Timer XY mode register Ref.No. External interrupt input (8) Timer X, timer Y function I/O (9) (10) (10) Port control register 2 CMOS compatible input level or TTL input level Pure N-channel open-drain output CMOS compatible input level Pure N-channel open-drain output (11) External interrupt input Interrupt edge selection register Port control register 2 (12) (13) (14) LPC interface function I/O Data bus buffer control register Port control register 2 (15) Port P8 CMOS compatible input level CMOS 3-state output Serialized IRQ function I/O (16) Notes1: For details usage of double-function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level of each pin should be either 0 V or VCC in STP mode. When an input level is at an intermediate voltage level, the ICC current will become large because of the input buffer gate. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 14 of 60 3882 Group (1) Ports P0, P1 P00–P03, P04–P07, P10–P13, P14–P17 output structure selection bits Direction register (2) Port P20–P27 Direction register Data bus Data bus Port latch Port latch (3) Ports P30–P37 P30–P33, P34–P37 pull-up control bit (4) Port P40, P41 Direction register Direction register Data bus Port latch Data bus Port latch Key-on wake-up input (5) Ports P42, P43 P4 output structure selection bit Direction register Data bus Port latch ✻1 Interrupt input ✻1. Reading the port P8 register (address 001016) is switched to port P4 pin input level by the P8 function selection bit of the port control register 2 (PCTL2). Fig. 10 Port block diagram (1) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 15 of 60 3882 Group (6) Ports P44 to P46 P4 output structure selection bit Direction register (7) Port P47 Serialized IRQ enable bit Direction register Data bus Port latch Data bus Port latch ✻1 CLKRUN output (8) Ports P50 to P53 P5i open drain selection bit Direction register (9) Ports P54, P55 Direction register Data bus Port latch Data bus Port latch Interrupt input Pulse output mode Timer output CNTR0, CNTR1 interrupt input (10) Ports P56, P57, P6 Direction register (11) Ports P70 to P72 Direction register Data bus Port latch Data bus Port latch ✻2 ✻1. Reading the port P8 register (address 001016) is switched to port P4 pin input level by the P8 function selection bit of the port control register 2 (PCTL2). ✻2. Reading the port P8 direction register is switched to port P7 pin input level by the P8 function selection bit of the port control register 2 (PCTL2). Fig. 11 Port block diagram (2) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 16 of 60 3882 Group (12) Ports P73 to P75 Direction register (13) Port P76, P77 Direction register Data bus Port latch Data bus Port latch ✻2 Interrupt input ✻2 (14) Ports P80 to P83 LPC enable bit Direction register (15) Ports P84 to P86 LPC enable bit Direction register Data bus Port latch Data bus Port latch LAD [3 : 0] LRESET LCLK LFRAME (16) Port P87 SIRQ enable bit Direction register Data bus Port latch IRQSER ✻2. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port control register 2 (PCTL2). Reading the port P8 direction register is switched to port P7 pin input level by the P8 function selection bit of the port control register 2 (PCTL2). Fig. 12 Port block diagram (3) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 17 of 60 3882 Group b7 b0 Port control register 1 (PCTL1: address 002E16) P00–P03 output structure selection bit 0: CMOS 1: N-channel open-drain P04–P07 output structure selection bit 0: CMOS 1: N-channel open-drain P10–P13 output structure selection bit 0: CMOS 1: N-channel open-drain P14–P17 output structure selection bit 0: CMOS 1: N-channel open-drain P30–P33 pull-up control bit 0: No pull-up 1: Pull-up P34–P37 pull-up control bit 0: No pull-up 1: Pull-up Not used (returns “0” when read) b7 b0 Port control register 2 (PCTL2: address 002F16) P45 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) P7 input level selection bit (P70-P75) 0: CMOS input level 1: TTL input level P4 output structure selection bit (P42, P43, P44, P46) 0: CMOS 1: N-channel open-drain P8 function selection bit 0: Port P8/Port P8 direction register 1: Port P4 input register/Port P7 input register INT2, INT3, INT4 interrupt switch bit 0: INT20, INT30, INT40 interrupt 1: INT21, INT31, INT41 interrupt Not used (returns “0” when read) Oscillation stabilizing time set after STP instruction released bit 0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12 1: No automatic set Not used (returns “0” when read) Fig. 13 Structure of port I/O related registers (1) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 18 of 60 3882 Group b7 b0 Port P5 input register (P5I: address 0FF816) P50 input level bit P51 input level bit P52 input level bit P53 input level bit These bits directly show the pin input levels. 0: “L” level input 1: “H” level input Not used (returns “0” when read) b7 b0 Port control register 3 (PCTL3: address 0FF916) P50 open drain selection bit P51 open drain selection bit P52 open drain selection bit P53 open drain selection bit 0: CMOS 1: N-channel open drain Not used (returns “0” when read) Fig. 14 Structure of port I/O related registers (2) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 19 of 60 3882 Group INTERRUPTS Interrupts occur by 14 sources among 17 sources: ten external, six internal, and one software. Interrupt Source Selection Any of the following interrupt sources can be selected by the interrupt source selection register (INTSEL). 1. INT0 or Input buffer full 2. INT1 or Output buffer empty 3. Timer 2 or INT5 4. CNTR0 or INT0 5. CNTR1 or INT1 Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt caused by the BRK instruction. An interrupt occurs when both the corresponding interrupt request bit and interrupt enable bit are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are serviced according to the priority. External Interrupt Pin Selection The external interrupt sources of INT2, INT3, and INT4 can be selected from either input pin from INT20, INT30, INT40 or input pin from INT21, INT31, INT41 by the INT2, INT3, INT4 interrupt switch bit (bit 4 of PCTL2). s Notes When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A 16); Timer XY mode register (address 002316) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection register (address 003916) •When setting input pin of external interrupts INT2, INT3 and INT4 Related register: INT2, INT3, INT4 interrupt switch bit of Port control register 2 (bit 4 of address 002F16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the corresponding interrupt enable bit to “0” (disabled). (2) Set the active edge selection bit or the interrupt source selec tion bit to “1”. (3) Set the corresponding interrupt request bit to “ 0 ” a fter 1 or more instructions have been executed. (4) Set the corresponding interrupt enable bit to “1” (enabled). Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table and stored into the program counter. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 20 of 60 3882 Group Table 8 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 2 Input buffer full (IBF) INT1 3 Output buffer empty (OBE) LRESET Timer X Timer Y Timer 1 Timer 2 INT5 CNTR0 9 INT0 CNTR1 10 INT1 INT2 INT3 INT4 Key-on wake-up BRK instruction 11 12 13 14 15 FFE916 FFE816 FFEB16 FFEA16 4 5 6 7 8 FFF916 FFF816 FFFB16 FFFA16 At input data bus buffer writing At detection of either rising or falling edge of INT1 input At output data bus buffer reading At falling edge of LRESET input At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow FFED16 FFEC16 At detection of either rising or falling edge of INT5 input At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of CNTR1 input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At falling of port P3 (at input) input logical level AND At BRK instruction execution External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (falling valid) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (falling valid) Non-maskable software interrupt STP release timer underflow External interrupt (active edge selectable) Priority 1 Vector Addresses (Note 1) Low High FFFC16 FFFD16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input Remarks Non-maskable External interrupt (active edge selectable) FFF716 FFF316 FFF116 FFEF16 FFF616 FFF216 FFF016 FFEE16 External interrupt FFE516 FFE316 FFE116 FFDF16 FFDD16 FFE416 FFE216 FFE016 FFDE16 FFDC16 Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset functions in the same way as an interrupt with the highest priority. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 21 of 60 3882 Group Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 15 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit INT5 active edge selection bit Not used (returns “0” when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0/INT0 interrupt request bit CNTR1/INT1 interrupt request bit Not used (returns “0” when read) INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit key-on wake-up interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 0 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0/INT0 interrupt enable bit CNTR1/INT1 interrupt enable bit Not used (returns “0” when read) INT2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit key-on wake-up interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0/input buffer full interrupt request bit INT1/output buffer empty interrupt request bit LRESET request bit Not used (returns “0” when read) Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2/INT5 interrupt request bit b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/input buffer full interrupt enable bit INT1/output buffer empty interrupt enable bit LRESET enable bit Not used (returns “0” when read) Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2/INT5 interrupt enable bit Fig. 16 Structure of interrupt-related registers (1) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 22 of 60 3882 Group b7 b0 Interrupt source selection register (INTSEL: address 003916) INT0/input buffer full interrupt source selection bit 0 : INT0 interrupt 1 : Input buffer full interrupt INT1/output buffer empty interrupt source selection bit 0 : INT1 interrupt 1 : Outpud buffer empty interrupt LRESET interrupt source selection bit 0 : Not used 1 : LRESET interrupt Not used (returns “0” when read) (Do not write “1” to this bit) Timer 2/INT5 interrupt source selection bit 0 : Timer 2 interrupt 1 : INT5 interrupt CNTR0/INT0 interrupt source selection bit 0 : CNTR0 interrupt 1 : INT0 interrupt CNTR1/INT1 interrupt source selection bit 0 : CNTR1 interrupt 1 : INT1 interrupt Key-on wake-up interrupt source selection bit 0 : Not used 1 : Key-on wake-up interrupt Fig. 17 Structure of interrupt-related registers (2) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 23 of 60 3882 Group Key Input Interrupt (Key-on Wake Up) A Key input interrupt request is generated by applying “L” level to any pin of port P3 that have been set to input mode. In other words, it is generated when the logical AND of all port P3 input goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P30–P33. Port PXx “L” level output Port control register 1 Bit 5 = “0” ✻ ✻✻ Port P37 direction register = “1” Port P37 latch Key input interrupt request P37 output Port P36 direction register = “1” Port P36 latch ✻ ✻✻ P36 output ✻ ✻✻ Port P35 direction register = “1” Port P35 latch P35 output ✻ ✻✻ Port P34 direction register = “1” Port P34 latch P34 output ✻ P33 input Port control register 1 Bit 4 = “1” ✻✻ Port P33 latch Port P33 direction register = “0” Port P3 input circuit ✻ ✻✻ Port P32 direction register = “0” Port P32 latch P32 input ✻ ✻✻ Port P31 direction register = “0” Port P31 latch P31 input ✻ ✻✻ Port P30 direction register = “0” Port P30 latch P30 input ✻ P-channel transistor for pull-up ✻✻ CMOS output buffer Fig. 18 Connection example when using key input interrupt and port P3 block diagram Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 24 of 60 3882 Group TIMERS The 3882 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down structure. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each select one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts f(XIN)/16. (2) Pulse Output Mode b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b5b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach “ 00 16” , the signal output from the CNTR 0 ( or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P54 ( or port P55) direction register to output mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts f(XIN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR 0 ( or CNTR 1 ) active edge selection bit is “ 1 ” , the timer counts while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer overflows. The count source for timer Y in the timer mode or the pulse output mode can be selected from f(XIN)/16 by the timer Y count source selection bit of the port control register 2 (bit 5 of PCTL2). Fig. 19 Structure of timer XY mode register Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 25 of 60 3882 Group Data bus Oscillator f(XIN) Divider 1/16 Prescaler X latch (8) Pulse width measurement Timer mode mode Pulse output mode Prescaler X (8) CNTR0 active edge selection bit “0” “1” Event counter mode Timer X count stop bit To CNTR0 interrupt request bit Q Q Timer X latch (8) Timer X (8) To timer X interrupt request bit P54/CNTR0 CNTR0 active edge selection “1” bit “0” Toggle flip-flop T R Timer X latch write pulse Pulse output mode Port P54 direction register Port P54 latch Pulse output mode Data bus Timer Y count source selection bit “0 ” Prescaler Y latch (8) Pulse width measureTimer mode ment mode Pulse output mode Prescaler Y (8) Oscillator f(XIN) Divider 1/16 Timer Y latch (8) Timer Y (8) P55/CNTR1 CNTR1 active edge selection bit “0” “1” To timer Y interrupt request bit Event counter mode Timer Y count stop bit To CNTR1 interrupt request bit Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode CNTR1 active edge selection “1” bit “0” Port P55 direction register Pulse output mode Port P55 latch Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Oscillator f(XIN) Divider 1/16 Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 20 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 26 of 60 3882 Group WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Bit 6 of Watchdog Timer Control Register When bit 6 of the watchdog timer control register is “0”, the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting (Note). When executing the WIT instruction, the watchdog timer does not stop. When bit 6 is “1”, execution of STP instruction causes an internal reset. When this bit is set to “1” once, it cannot be rewritten to “0” by program. Bit 6 is “0” at reset. The necessary time after writing to the watchdog timer control register to an underflow of the watchdog timer H is shown as follows. When bit 7 of the watchdog timer control register is “0”: 131.072 ms at XIN = 8 MHz frequency. When bit 7 of the watchdog timer control register is “1”: 512 µs at XIN = 8 MHz frequency. Note: The watchdog timer continues to count for waiting for a stop mode release time. Do not generate an underflow of the watchdog timer H during that time. Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register (address 001E16), each of watchdog timer H and L is set to “FF16”. Any instruction which generates a write signal such as the instructions of STA, LDM, CLB and others can be used to write. The data of bits 6 and 7 are only valid when writing to the watchdog timer control register. Each of watchdog timer is set to “FF16” regardless of the written data of bits 0 to 5. Operation of Watchdog Timer The watchdog timer stops at reset and starts to count down by writing to the watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer H. The reset is released after waiting for a reset release time and the program is processed from the reset vector address. Accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow of the watchdog timer H. If writing to the watchdog timer control register is not performed once, the watchdog timer does not function. “FF16” is set when watchdog timer control register is written to. Main clock division ratio selection bits (Note) XIN Watchdog timer L (8) 1/16 “00” “01” Data bus “FF16” is set when watchdog timer control register is written to. Watchdog timer H (8) “0” “1” Watchdog timer H count source selection bit STP instruction function select bit STP instruction Reset circuit Internal reset RESET Note: Any one of high-speed or middle-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 21 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction function select bit 0: Entering Stop mode by excution of STP instruction 1: Internal reset by excution of STP instruction Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 Fig. 22 Structure of Watchdog timer control register Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 27 of 60 3882 Group LPC INTERFACE LPC interface function is base on Low Pin Count (LPC) Interface Specification, Revision 1.0. The 3882 supports only I/O read cycle and I/O write cycle. There are two channels of bus buffers to the host. The functions of Input Data Bus Buffer, Output Data Bus Buffer and Data Bus Buffer Status Register are the same as that of the 8042, 3880 group, 3881 group,3886 group and 3885 group. It can be written in or read out from the host controller through LPC interface. LPC interface function block diagram is shown in Figure 23. Functional input or output pins of LPC interface are shared with Port 8 (P80 – P8 6 ). Setting the LPC interface enable bit (bit3 of LPCCON) to “1” enables LPC interface. Enabling channel i (i = 0, 1) of the data bus buffer is controlled by the data bus buffer i (i = 0, 1) enable bits (bit 4 or bit 5 of LPCCON). The slave addresses of the data bus buffer channel i (i = 0, 1) are definable by setting LPCi (i = 0, 1) address register H/L (LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH). The bit 2 value of LPCi address register L is not decoded. This bit returns “0” when the internal CPU read. The bit 2 of slave address is latched to XA2i flag when the host controller writes the data. The input buffer full (IBF) interrupt occurs when the host controller writes the data. The output buffer empty (OBE) interrupt is generated when the host controller reads out the data. The 3882 merges two input buffer full (IBF) interrupt requests and two output buffer empty (OBE) interrupt requests as shown in Figure 24. Table 9 Function explanation of the control pin in LPC interface Pin name Input/ Output Function P80/LAD0 P81/LAD1 P82/LAD2 P83/LAD3 P84/LFRAME P85/LRESET P86/LCLK I/O I/O I/O I/O I I I These pins communicate address, control and data information between the host and the data bus buffer of the 3882. Input the signal to indicate the start of new cycle and termination of abnormal communication cycles. Input the signal to reset the LPC interface function. Input the LPC synchronous clock signal. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 28 of 60 3882 Group P84/LFRAME P85/LRESET P86/LCLK Address register HH Address register HL Address register LH Input Data Comparator P80/LAD0 P81/LAD1 Input Control Circuit LPC Data Bus Address register LL RD/WR register Start register P82/LAD2 Input Data Bus Buffer [7:4] Input Data Bus Buffer [3:0] Output Data Bus Buffer [7:4] P83/LAD3 Output Data Bus Buffer [3:0] Data bus buffer status register U7i U6i U5i U4i XA2i U2i IBFi OBFi Output Control Circuit SYNC register TAR register Interrupt Generate Circuit Interrupt signal IBF, OBE 0 b6 b5 b4 b3 b2 b1 b0 LPC control register (LPCCON) Fig. 23 Block diagram of LPC interface function (1ch) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 29 of 60 Internal CPU Bus 3882 Group Input buffer full flag 0 IBF0 Input buffer full flag 1 IBF1 Rising edge detection circuit Rising edge detection circuit One-shot pulse generating circuit One-shot pulse generating circuit Input buffer full interrupt request signal IBF Output buffer full flag 0 OBF0 Output buffer full flag 1 OBF1 OBE0 Rising edge detection circuit Rising edge detection circuit One-shot pulse generating circuit One-shot pulse generating circuit Output buffer empty interrupt request signal OBE OBE1 IBF0 IBF1 IBF Interrupt request is set at this rising edge OBF0 (OBE0) OBF1 (OBE1) OBE Interrupt request is set at this rising edge Fig. 24 Interrupt request circuit of data bus buffer Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 30 of 60 3882 Group [LPC Control Register (LPCCON)] 002A16 • SYNC output select bit (SYNCSEL) “00”: OK “01”: LONG & OK “10”: Err “11”: LONG & Err • LPC interface software reset bit (LPCSR) “0”: Reset release (automatic) “1”: Reset • LPC interface enable bit (LPCBEN) “0”: P80–P86 works as port “1”: P80–P86 works as LPC interface • Data bus buffer 0 enable bit (DBBEN0) “0”: Data bus buffer 0 disable “1”: Data bus buffer 0 enable • Data bus buffer 1 enable bit (DBBEN1) “0”: Data bus buffer 1 disable “1”: Data bus buffer 1 enable Bits 0 and 1 of the LPC control register (LPCCON) specify the SYNC code output. Bit 2 of the LPC control register (LPCCON) enables the LPC interface to enter the reset state by software. When LPCSR is set to “1”, LPC interface is initialized in the same manner as the external “L” input to LRESET pin (See Figure 30). Writing “0” to LPCSR the reset state will be released after 1.5 cycle of φ a nd this bit is cleared to “0”. [Output Data Bus Buffer i (i = 0, 1) (DBBOUT0, DBBOUT1)] 002816, 002B16 Writing data to data bus buffer registers (DBB0 , DBB1) address from the internal CPU means writing to DBBOUTi (i = 0, 1). The data of DBBOUTi (i = 1, 0) is read out from the host controller when bit 2 of slave address (A2) is “0”. [LPCi address register H/L (LPC0ADL, LPC1ADL / LPC0ADH, LPC1ADH)] 0FF016 to 0FF316 The slave addresses of data bus buffer channel i(i=0,1) are definable by setting LPCi address registers H/L (LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH ). These registers can be set and cleared any time. When the internal CPU reads LPCi address register L, the bit 2 (A2) is fixed to “ 0 ” . The bit 2 of slave address (A2) is latched to XA2i flag when the host controller writes the data. The slave addresses, set in these registers, is used for comparing with the addresses from the host controller. [Data Bus Buffer Status Register i (i = 0, 1) (DBBSTS0, DBBSTS1)] 002916, 002C16 Bits 0, 1 and 3 are read-only bits and indicate the status of the data bus buffer. Bits 2, 4, 5, 6 and 7 are user definable flags which can be read and written by software. The data bus buffer status register can be read out by the host controller when bit 2 of the slave address (A2) is “1”. •Bit 0: Output buffer full flag i (OBFi) This bit is set to “1” when a data is written into the output data bus buffer i and cleared to “0” when the host controller reads out the data from the output data bus buffer i. •Bit 1: Input buffer full flag i (IBFi) This bit is set to “1” when a data is written into the input data bus buffer i by the host controller, and cleared to “0” when the data is read out from the input data bus buffer i by the internal CPU. •Bit 3: XA2 flag (XA2i) The bit 2 of slave address is latched while a data is written into the input data bus buffer i. [Input Data Bus Buffer i(i=0,1) (DBBIN0, DBBIN1)] 002816, 002B16 In I/O write cycle from the host controller, the data byte of the data phase is latched to DBBINi (i=0,1). The data of DBBINi can be read out form the data bus buffer registers (DBB0, DBB1) address in SFR area. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 31 of 60 3882 Group LPC control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol LPCCON Address 002A16 When reset 000000002 Bit symbol SYNCSEL Bit name SYNC output select bit Function 00:OK 01:Long & OK 10:Err 11:Long & Err RW LPCSR LPCEN DBBEN0 DBBEN1 LPC interface software reset bit 0 : Reset release(automatic) 1 : Reset LPC interface enable bit Data bus buffer 0 enable bit Data bus buffer 1 enable bit 0 : P80 to P86 as port 1 : LPC interface enable 0 : Data bus buffer 0 disable 1 : Data bus buffer 0 enable 0 : Data bus buffer 1 disable 1 : Data bus buffer 1 enable Cannot write to this bit. Returns "0"when read. Fig. 25 LPC control register Data bus buffer status register i (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DBBSTS0 DBBSTS1 Address 002916 002C16 When reset 000000002 000000002 Bit symbol OBFi IBFi U2i XA2i U4i U5i U6i U7i Bit name Output buffer full flag Input buffer full flag User definable flag XA2i flag Function 0 : Buffer empty 1 : Buffer full 0 : Buffer empty 1 : Buffer full This flag can be freely defined by user. This flag indicates the A2 status when IBFi flag is set. This flag can be freely defined by user. RW User definable flag Fig. 26 Data bus buffer control register Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 32 of 60 3882 Group LPCi address register L (i=0,1) b7 b6 b5 b4 b3 b2 b1 b0 (Note2) Address 0FF02 0FF22 When reset 000000002 000000002 Symbol LPC0ADL LPC1ADL Bit symbol LPCSAD0 LPCSAD1 LPCSAD2 LPCSAD3 LPCSAD4 LPCSAD5 LPCSAD6 LPCSAD7 Bit name Slave address bit 0 Slave address bit 1 Slave address bit 2 (Note 1) Slave address bit 3 Slave address bit 4 Slave address bit 5 Slave address bit 6 Slave address bit 7 RW Notes 1: Always returnes “0” when read , even if writing “1” to this bit. 2: Do not set the same 16-bit slave address to both channel 0 and channel 1. LPCi address register H (i=0,1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol LPC0ADH LPC1ADH Address 0FF12 0FF32 When reset 000000002 000000002 Bit symbol LPCSAD8 LPCSAD9 LPCSAD10 LPCSAD11 LPCSAD12 LPCSAD13 LPCSAD14 LPCSAD15 Bit name Slave address bit 8 Slave address bit 9 Slave address bit 10 Slave address bit 11 Slave address bit 12 Slave address bit 13 Slave address bit 14 Slave address bit 15 RW Fig. 27 LPC related registers Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 33 of 60 3882 Group Basic Operation of LPC Interface Set up steps for LPC interface is as below. •Set the LPC interface enable bit (bit3 of LPCCON) to “1”. •Choose which data bus buffer channel use. • Set the data bus buffer i enable bit (i = 0, 1) (bit 4 or 5 of LPCCON) to “1”. •Set the slave address to LPCi address register L and H (i = 0, 1) (LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH). (2) Example for I/O read cycle The I/O read cycle timing is shown in Figure 29. The standard transfer cycle number of I/O read cycle is 13. The data on LAD [3:0] is monitored at every rising edge of LCLK. The communication starts from the falling edge of LFRAME. •1st clock: The last clock when LFRAME is “Low”. The host sends “00002” on LAD [3:0] for communication start. •2nd clock: LFRAME is “High”. The host sends “000X2” on LAD [3:0] to inform the cycle type as I/O read. • From 3rd clock to 6th clock: In these four cycles , the host sends 16-bit slave address. The 3882 compares it with the LPCi address register H or L (i = 0, 1). 3rd clock: The slave address bit [15:12]. 4th clock: The slave address bit [11:8]. 5th clock: The slave address bit [7:4]. 6th clock: The slave address bit [3:0]. • 7thclock and 8thclock are used for turning the communication direction from the host→the peripheral to the peripheral→the host. 7th clock: The host outputs “11112” on LAD [3:0]. 8th clock: The LAD [3:0] is set to tri-state by the host to turn the communication direction. • 9th clock: The 3882 outputs “00002” (SYNC OK) to LAD [3:0] for acknowledgment. • 10th clock and 11th clock are used for one data byte transfer from the output data bus buffer i (DBBOUTi) or data bus buffer status register i (DBBSTSi). 10th clock: The 3882 sends the data bit [3:0]. 11th clock: The 3882 sends the data bit [7:4]. th clock: The 3882 outputs “11112” to LAD [3:0]. In this timing • 12 OBFi (bit 2 of DBBSTSi) is cleared to “0” and OBE interrupt signal is generated. • 13th clock: The LAD [3:0] is set to tri-state by the host to turn the communication direction. (1) Example of I/O write cycle The I/O write cycle timing is shown in Figure 28. The standard transfer cycle number of I/O write cycle is 13. The communication starts from the falling edge of LFRAME. The data on LAD [3:0] is monitored at every rising edge of LCLK. • 1st clock: The last clock when LFRAME is “Low”. The host send “00002” on LAD [3:0] for communication start. • 2 nd c lock: LFRAME is “ High ” . The host send “ 001X 2” o n LAD [3:0] to inform the cycle type as I/O write. • From 3rd clock to 6th clock : In these four cycles , the host sends 16-bit slave address. The 3882 compares it with the LPCi address register H and L (i = 0, 1). 3rd clock: The slave address bit [15:12]. 4th clock: The slave address bit [11:8]. 5th clock: The slave address bit [7:4]. 6th clock: The slave address bit [3:0]. • 7th clock and 8th clock are used for one data byte transfer. The data is written to the input data bus buffer (DBBINi, i = 0, 1) 7th clock: The host sends the data bit [3:0]. 8th clock: The host sends the data bit [7:4]. th clock and 10th clock are for turning the communication direc•9 tion from the host→the peripheral to the slave→the host. 9th clock: The host outputs “11112” on LAD [3:0]. 10th clock: The LAD [3:0] is set to tri-state by the host to turn the communication direction. • 11th clock: The 3882 outputs “00002” (SYNC OK) to LAD [3:0] for acknowledgment. • 12th clock: The 3882 outputs “11112” to LAD [3:0]. In this timing the address bit 2 is latched to XA2i (bit3 of DBBSTSi), IBFi (bit 1 of DBBSTSi) is set to “1” and IBF interrupt signal is generated. • 13th clock: The LAD [3:0] is set to tri-state by the host to turn the communication direction. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 34 of 60 3882 Group q Data write (I/O write cycle) START CYCTYPE + DIR ADDRESS DATA TAR SYNC TAR LCLK LFRAME (Note) LAD [3:0] Input data bus buffer i XA2i flag IBFi flag driven by the host driven by the 3882 q Command write (I/O write cycle) START CYCTYPE + DIR ADDRESS DATA TAR SYNC TAR LCLK LFRAME (Note) LAD [3:0] Input data bus buffer i XA2i flag IBFi flag driven by the 3882 driven by the host Note: LAD0 to LAD3 pins remain tri-state after transfer Fig. 28 Data and command write timing Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 35 of 60 3882 Group Data Read (I/O read cycle) START CYCTYPE + DIR ADDRESS TAR SYNC DATA TAR LCLK LFRAME (Note 1) LAD [3:0] Output data bus buffer i OBFi flag driven by the host driven by the 3882 Status Read (I/O read cycle) START CYCTYPE + DIR ADDRESS TAR SYNC DATA TAR LCLK LFRAME (Note 1) LAD [3:0] OBFi flag (Note 2) driven by the host driven by the the 3882 Notes: 1: LAD0 to LAD3 pins remain tri-state after transfer completion. 2: OBFi flag does not change. Fig. 29 Data and status read timing Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 36 of 60 3882 Group LPCSR write signal LPCSR bit (LPC interface software reset signal) 1.5 cycle of φ LRESET LPC interface reset signal CPU Data bus bit 2 LPCSR write signal CPU RESET D Q D Q CK R D Q CK R CK R φ CPU RESET Fig. 30 Reset timing and block Table 10 Reset conditions of LPC interface function Pin name / Internal register P80/LAD0 P81/LAD1 P82/LAD2 P83/LAD3 P84/LFRAME P85/LRESET P86/LCLK Input data bus buffer registeri Output data bus buffer registeri Uxi flag 7, 6, 5, 4, 2 XA2i flag IBFi flag OBFi flag LPCi address register LPCCON Input LRESET = “L” Tri-state Note Pin LPC bus interface function Input Keep same value before LRESET goes “L”. Internal register Initialization to “0”. Initialization to “0”. Initialization to “0”. Keep same value before LRESET goes “L”. There is possibility to generate IBF interrupt request. There is possibility to generate OBE interrupt request. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 37 of 60 3882 Group SERIALIZED INTERRUPT The serialized IRQ circuit communicates the interrupt status to the host controller based on the Serialized IRQ Support for PCI System, Version 6.0. Table 11 shows the summary of serialized interrupt of 3882. Table 11 Smmary of serialized IRQ function Item The factors of serialized IRQ Function The numbers of serialized IRQ factor that can output simultaneously are 3. • Channel 0 (IRQ1,IRQ2) ➀ Setting Software IRQi (i = 1, 12) request bit (bits 0, 1 of SERIRQ) to “1”. ➁ The “1” of OBF0 and Hardware IRQi ( i=1, 12) request bit (bits 3, 4 of SERCON) to “1”. • Channel 1 (IRQx ; user selectable) ➀ Setting the IRQx request bit (bit 7 of SERIRQ) to “1”. ➁ The “1” of OBF1 and Hardware IRQx request bit to “1”. • Channel 0 (IRQ1, IRQ12) ➀ Setting Software IRQ1 request bit (bit 0 of SERIRQ) to “1” or detecting “1” of OBF0 with “1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ1 Frame . ➁ Setting IRQ12 Software request bit (bit 1 of SERIRQ) to “1” or detecting “1” of OBF0 with “1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ12 Frame. • Channel 1 (IRQx ; user selectable) Setting IRQx frame select bit (bit 2-6 of SERIRQ) selects IRQ 1–15 frame or extend frame 0–10. Synchronized with LCLK (Max. 33 MHz). LPC clock restart enable bit (bit 1 of SERCON) enables restart owing to “L” output of CLKRUN with the interrupt when the LPC clock has stopped or slowed down. LPC clock stop inhibition bit (bit 2 of SERCON) enables the inhibition of clock stop control during the IRQSER cycle when the clock tends to stop or slow down. The number of frame Operation clock Clock restart Clock stop inhibition Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 38 of 60 3882 Group Internal data bus Serialized IRQ control register Serialized IRQ request register b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Clock stop inhibition enable and clock restart enable Serialized IRQ enable OBF0 – OBF1 Software Serialized IRQ request OBF interrupt control Serialized interrupt request control circuit IRQx frame number Serialized IRQ request Frame number SERIRQ Serialized interrupt control circuit Clock operation status and finish acknowledgement Clock restart request and start frame activate request Clock monitor control circuit CLKRUN# * LCLK LRESET# CPU clock φ * Open Drain Fig. 31 Block diagram of serialized interrupt Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 39 of 60 3882 Group Register Explanation The serialized IRQ function is configured and controlled by the serialized IRQ request register (SERIRQ) and the serialized IRQ control register (SERCON). Bit 3 : Hardware IRQ1 request bit (SEIR1) When this bit is “1”, OBF0 status is directly connected to the IRQ1 frame. Bit 4 : Hardware IRQ12 request bit (SEIR12 ) When this bit is “1”, OBF0 status is directly connected to IRQ12 frame. Bit 5 : Hardware IRQx request bit (SEIRx ) When this bit is “1”, OBF1 status is directly connected to the IRQx frame. Bit 6 : IRQ1/IRQ12 disable bit (SCH0EN ) This bit controls whether the serialized IRQ channel 0 transfers the IRQ1 and IRQ12 frame to the host or not. Bit 7 : IRQx output polarity bit (SCH1POL) This bit selects IRx frame output level. [Serialized IRQ control register (SERCON)] 001D16 Bit 0 : Serialized IRQ enable bit (SIRQEN ) This bit enables/disables the serialized IRQ interface. When this bit is “1”, use of serialized IRQ is enabled. Then P87 functions as IRQ/Data line (SERIRQ) and P47 functions as CLKRUN. Output structure of CLKRUN pin becomes N-channel open drain. Bit 1 : LPC clock restart enable bit (RUNEN ) Setting this bit to “ 1 ” e nables clock restart with “ L ” o utput of CLKRUN. Bit 2 : LPC clock stop inhibition bit (SUPEN ) Setting this bit to “1” makes CLKRUN output change to “L” for inhibiting the clock stop. Serialized IRQ control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol SERCON Address 001D16 When reset 000000002 Bit symbol SIRQEN RUNEN SUPEN SEIR1 SEIR12 SEIRx SCH0EN SCH1POL Bit name Serialized IRQ enable bit LPC clock restart enable bit LPC clock stop inhibition bit Hardware IRQ1 request bit Function 0 : Serialized IRQ disable 1 : Serialized IRQ enable 0 : Clock restart disable 1 : Clock restart enable 0 : Stop inhibition control disable 1 : Stop inhibition control enable 0 : No IRQ1 request 1 : OBF0 synchronized IRQ1 request R W Hardware IRQ12 request bit 0 : No IRQ12 request 1 : OBF0 synchronized IRQ12 request Hardware IRQx request bit IRQ1/IRQ12 disable bit IRQx output polarity bit 0 : No IRQx request 1 : OBF1 synchronized IRQx request 0 : IRQ1/IRQ12 output enable 1 : IRQ1/IRQ12 output disable 0 : -Request Hiz-Hiz-Hiz -No request L-H-Hiz 1 : -Request L-H-Hiz -No request Hiz-Hiz-Hiz Fig. 32 Configuration of serialized IRQ control register Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 40 of 60 3882 Group [Serialized IRQ request register (SERIRQ)] 001F16 The interrupt source is definable by this register. Bit 0 : Software IRQ1 request bit (IR1) SERIRQ line shows IR1 value at the sample phase of IRQ1 frame, when the SCH0EN is “1”. Bit 1 : Software IRQ12 request bit (IR12) SERIRQ line shows IR12 value at the sample phase of IRQ12 frame, when the SCH0EN is “1”. Bits 2-6 : IRQx frame select bits (ISi, i = 0–4) These bits select the active IRQ frame of serial IRQ channel 1. When these bit are “000002”, the serial IRQ channel 1 is disabled. Bit 7 : Software IRQx request bit (IRx) SERIRQ line shows IRx value at the sample phase of IRQx frame which is selected by bits 2 to 6 of SERIRQ. Output level is selectable by the IRQx output polarity bit (SCH1POL). Serialized IRQ request register b7 b6 b5 b4 b3 b2 b1 b0 Symbol SERIRQ Bit symbol IR1 IR12 IS0 Address 001F16 Bit name Software IRQ1 request bit Software IRQ12 request bit IRQx frame select bit When reset 000000002 Function 0: No IRQ1 request 1: IRQ1 request 0: No IRQ12 request 1: IRQ12 request b6b5b4b3b2 RW IS1 IS2 IS3 IS4 0 0 0 0 0 : Disable serial IRQ channel 1 0 0 0 0 1 : IRQ1 Frame 0 0 0 1 0 : IRQ2 Frame 0 0 0 1 1 : IRQ3 Frame 0 0 1 0 0 : IRQ4 Frame 0 0 1 0 1 : IRQ5 Frame 0 0 1 1 0 : IRQ6 Frame 0 0 1 1 1 : IRQ7 Frame 0 1 0 0 0 : IRQ8 Frame 0 1 0 0 1 : IRQ9 Frame 0 1 0 1 0 : IRQ10 Frame 0 1 0 1 1 : IRQ11 Frame 0 1 1 0 0 : IRQ12 Frame 0 1 1 0 1 : IRQ13 Frame 0 1 1 1 0 : IRQ14 Frame 0 1 1 1 1 : IRQ15 Frame 1 0 0 0 0 : Do not select 1 0 0 0 1 : Do not select 1 0 0 1 0 : Do not select 1 0 0 1 1 : Do not select 1 0 1 0 0 : Do not select 1 0 1 0 1 : Extend Frame 0 1 0 1 1 0 : Extend Frame 1 1 0 1 1 1 : Extend Frame 2 1 1 0 0 0 : Extend Frame 3 1 1 0 0 1 : Extend Frame 4 1 1 0 1 0 : Extend Frame 5 1 1 0 1 1 : Extend Frame 6 1 1 1 0 0 : Extend Frame 7 1 1 1 0 1 : Extend Frame 8 1 1 1 1 0 : Extend Frame 9 1 1 1 1 1 : Extend Frame 10 Software IRQx request bit 0: No IRQx request 1: IRQx request IRx Fig. 33 Structure of serialized IRQ request register Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 41 of 60 3882 Group Operation of Serialized IRQ A cycle operation of serialized IRQ starts with Start Frame and finishes with Stop Frame. There are two modes of operation : Continuous (Idle) mode and Quiet (Active) mode. The next operation mode is determined by monitoring the stop frame pulse width. qTiming of serialized IRQ cycle Figure 54 shows the timing diagram of serialized IRQ cycle. (1) Start Frame The Start Frame is detected when the SERIRQ line remains “L” in 4 to 8 clocks. (2) IRQ/Data Frame Each IRQ/Data Frame is three clocks. When the IRQi (i = 0, 1, x) request is “0”, then the SERIRQ line is driven to “L” during the Sample phase (1st clock) of the corresponding IRQ/Data frame, to “H” during the Recovery phase (2nd clock), to tri-state during the Turn-around phase (3rd clock). When the IRQi request is “1”, then the SERIRQ line is tri-state in all phases (3 clocks period). (3) Stop Frame The Stop Frame is detected when the SERIRQ line remains “L” in 2 or 3 clocks. The next operation mode is Quiet mode when the pulse width of “ L ” i s 2 clocks. The next operation mode is the Continuous mode when the pulse width is 3 clocks. Start frame Clock SERIRQ Driver source Host control IRQ0 frame IRQ1 frame IRQ15 frame IOCHK frame Stop frame To the next cycle IRQ1 device control IRQ15 device control Host control Fig. 34 Timing diagram of serialized IRQ cycle Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 42 of 60 3882 Group Operation Mode Figure 35 shows the timing of continuous mode; Figure 36 shows that of Quiet mode. (1) Continuous mode Serialized IRQ cycles starts in Continuous mode after CPU reset in the case of LRESET = “L” and the previous stop frame being 3 clocks. After receiving the start frame; the IRQ1 Frame, IRQ12 Frame or IRQx frame is asserted. Note : If the pulse width of “L” is less than 4 clocks, or 9 clocks or more; the start frame is not detected and the next start (the falling edge of SERIRQ) is waited. Start frame (Note) LCLK SERIRQ line Host SERIRQ output 3883 SERIRQ output Drive source Host IRQ0 frame IRQ1 frame IRQ2 frame IRQ3 frame 3882 Note: The start frame count is 4 clocks as exemple. Fig. 35 Timing diagram of Continuous mode (2) Quiet mode At clock stop, clock slow down or the pulse width of the last stop frame being 2 clocks, it is the Quiet mode. In this mode the 3882 drives the SERIRQ line to “ L ” i n the 1 st clock. After that the host drives the rest start frame (Note). The IRQ1 frame, IRQ12 frame or IRQx frame is asserted. Note: When the sum of pulse width of “L” driven by the 3882 in the 1 st c lock and driven by the host in the rest clocks is within 4 to 8-clock cycles, the start frame is detected. If the sum of pulse width of “L” is less than 4 clocks, or 9 clocks or more; the start frame is not detected and the next start (the falling edge of SERIRQ) is waited. Start frame (Note) LCLK SERIRQ line Host SERIRQ output 3883 SERIRQ output Drive source 3882 Host IRQ0 frame IRQ1 frame IRQ2 frame IRQ3 frame 3882 Note: The start frame count is 4 clocks as exemple Fig. 36 Timing diagram of Quiet mode Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 43 of 60 3882 Group Clock Restart/Stop Inhibition Request Asserting the CLKRUN signal can request the host to restart for clocks stopped or slowed down, or maintain the clock tending to stop or slow down. Figure 37 shows the timing diagram of clock restart request; Figure 38 shows an example of timing of clock stop inhibition request. (1) Clock restart operation In case the LPC clock restart enable bit (bit 1 of SERCON) is “1” and the CLKRUN (BUS) is “H”, when the serialized interrupt request occurs, the 3882 drives CLKRUN to “L” for requesting the PCI clock generator to restart the LCLK if the clock is slowed down or stopped. LCLK Bus CLKRUN Central Resource CLKRUN 3882 CLKRUN Bus SERIRQ Host SERIRQ 3882 SERIRQ Restart frame Start frame φ Interrupt request Internal restart request signal Fig. 37 Timing diagram of clock restart request (2) Clock stop inhibition request In case the LPC clock stop inhibition bit (bit 2 of SERCON) is “1” and the serialized interrupt request is held, if the LCLK tends to stop, the 3882 drives CLKRUN to “L” for requesting the PCI clock generator not to stop LCLK. LCLK Bus CLKRUN Central Resource CLKRUN 3882 CLKRUN Bus SERIRQ Interrupt request Internal inhibition request signal IRQSER cycle Inhibition request Fig. 38 Timing diagram of clock stop inhibition request Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 44 of 60 3882 Group RESET CIRCUIT ____________ To reset the microcomputer, RESET pin should be held at an “L” level for 16 X IN cycle or more. (When the power source voltage should be between 3.3V ± 0.3V and the oscillation should be ____________ stable.) Then the RESET pin set to “H”, the reset state is released. After the reset is completed, the program starts from the address contained in address FFFD 16 ( high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.6 V for VCC of 3.0 V. Poweron Power source voltage 0V Reset input voltage 0V (Note) RESET VCC 0.2VCC Note : Reset release voltage ; Vcc=3.0 V RESET VCC Power source voltage detection circuit Fig. 39 Reset circuit example XIN φ RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ). 2: The question marks (?) indicate an undefined data that depends on the previous state. Fig. 40 Reset sequence Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 45 of 60 3882 Group Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001D16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (38) Interrupt edge selection register (INTEDGE) (39) CPU mode register (CPUM) (40) Interrupt request register 1 (IREQ1) (41) Interrupt request register 2 (IREQ2) (42) Interrupt control register 1 (ICON1) (43) Interrupt control register 2 (ICON2) (44) LPC0 address register L (LPC0ADL) (45) LPC0 address register H (LPC0ADH) (46) LPC1 address register L (LPC1ADL) (47) LPC1 address register H (LPC1ADH) (48) Port P5 input register (P5I) (49) Port control register 3 (PCTL3) (50) Processor status register (51) Program counter Address Register contents 003A16 0016 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0FF016 0FF116 0FF216 0FF316 0FF816 0FF916 (PS) (PCH) (PCL) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X XXXX1 XX FFFD16 contents FFFC16 contents (10) Port P4 direction register (P4D) (11) Port P5 (P5) (12) Port P5 direction register (P5D) (13) Port P6 (P6) (14) Port P6 direction register (P6D) (15) Port P7 (P7) (16) Port P7 direction register (P7D) (17) Port P8 (P8) (18) Port P8 direction register (P8D) (19) Serialized IRQ control register (SERCON) (20) Watchdog timer control register (WDTCON) (21) Serialized IRQ request register (SERIRQ) (22) Prescaler 12 (PRE12) (23) Timer 1 (T1) (24) Timer 2 (T2) (25) Timer XY mode register (TM) (26) Prescaler X (PREX) (27) Timer X (TX) (28) Prescaler Y (PREY) (29) Timer Y (TY) (30) Data bus buffer register 0 (DBB0) (31) Data bus buffer status register 0 (DBBSTS0) 001E16 0 0 1 1 1 1 1 1 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 002816 X X X X X X X X 002916 002A16 0016 0016 (32) LPC control register (LPCCON) (33) Data bus buffer register 1 (DBB1) (34) Data bus buffer status register 1 (DBBSTS1) 002B16 X X X X X X X X 002C16 002E16 002F16 003916 0016 0016 0016 0016 (35) Port control register 1 (PCTL1) (36) Port control register 2 (PCTL2) (37) Interrupt source selection register (INTSEL) Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 41 Internal status at reset Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 46 of 60 3882 Group CLOCK GENERATING CIRCUIT The 3882 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT Use the circuit constants in accordance with the resonator manufacturer ’ s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) Immediately after power on, only the XIN oscillation circuit starts oscillating. XIN XOUT Rd (Note) Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected. CIN COUT (2) High-speed mode The internal clock φ is half the frequency of XIN. sNote If you switch the mode between middle/high-speed ,stabilize XIN oscillations. Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies to add a feedback resistor externally to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig. 42 Ceramic resonator circuit Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the oscillation stabilizing time set after STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. XIN divided by 16 is input to the prescaler 12 as count source, and the output of the prescaler 12 is connected to timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “ H ” ) until timer 1 underflows. The internal clock φ i s supplied for the first time, when timer 1 underflows. Therefore make sure not to set the timer 1 interrupt request bit to “1” before the STP instruction stops the oscillator. When the oscillator is restarted by reset, apply “ L ” l evel to the RESET pin until the oscillation is stable since a wait time will not be generated. XIN XOUT Open External oscillation circuit VCC VSS Fig. 43 External clock input circuit (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 47 of 60 3882 Group XIN (Note 3) XOUT 1/2 High-speed or middle-speed mode 1/4 1/2 Prescaler 12 FF16 Timer 1 Reset or 0116 STP instruction (Note 2) Main clock division ratio selection bits (Note1) Middle-speed mode High-speed Timing φ (internal clock) Q S R STP instruction WIT instruction SQ R QS R STP instruction Reset Interrupt disable flag l Interrupt request Notes 1: Either high-speed ,or middle-speed is selected by bits 7 and 6 of the CPU mode register. 2: f(XIN)/16 is supplied as the count source to the Prescaler 12 at reset. When exciting STP instruction, the count source does not change either f(XIN))/16 after releasing stop mode. Oscillation stabilizing time is not fixed “01FF16” when the bit 6 of PCTL2 is “1”. 3: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 44 System clock generating circuit block diagram (Single-chip mode) Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 48 of 60 3882 Group Reset Middle-speed mode (f(φ)=1 MHz) CM7=0 CM6=1 CM6 “1”←→“0” High-speed mode (f(φ)=4 MHz) CM7=0 CM6=0 b7 b6 CPU mode register (CPUM : address 003B16) CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 1 1 0 : φ = f(XIN)/2 ( High-speed mode) 1 : φ = f(XIN)/8 (Middle-speed mode) 0 : Not available 1 : Not available Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode. 5 : The example assumes that 8 MHz is being applied to the XIN pin . φ indicates the internal clock. Fig. 45 State transitions of system clock Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 49 of 60 3882 Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Instruction Execution Time The instruction execution time is obtained by multiplying the period of the internal clock φ b y the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The period of the internal clock φ is twice of the XIN period in highspeed mode. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Reserved Area, Reserved Bit Do not write any data to the reserved area in the SFR area and thespecial page. (Do not change the contents after reset.) CPU Mode Register Be sure to fix bit 3 of the CPU mode register (address 003B16) to “1”. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The instruction with the addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 50 of 60 3882 Group NOTES ON USAGE Termination of Unused Pins Be sure to perform the termination of unused pins. The shortest CNVSS/(VPP) (Note) Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recommended. Approx. 5kΩ VSS (Note) The shortest Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Note. Shows the microcomputer's pin. Fig. 46 Wiring for the CNVSS/(VPP) pin NOTES ON QzROM Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension : .msk) which is made by the mask file converter MM. Be sure to set the ROM option (“MASK option“ written in the mask file converter) setup when making the mask file by using the mask file converter MM. Product shipped in blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 %may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. The ROM option setup data in the mask file is “0016” for protect enabled or “FF16” for protect disabled. Therefore, the contents of the ROM code protect address (other than the user ROM area)of the QzROM product shipped after writing is “0016” or “FF16”. Note that the mask file which has nothing at the ROM option data or has the data other than “0016” and “FF16” can not be accepted. Overvoltage Take care that overvoltage is not applied. Overvoltage may cause the QzROM contents rewriting. Take care especially at turning on the power. QzROM Version Connect the CNV SS/(VPP) pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k Ω resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. •Reason The CNVSS/(VPP) pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the VPP pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily.If noise enters the CNVSS/(VPP) pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1.QzROM Writing Confirmation Form* 2.Mark Specification Form* 3.ROM data...........Mask file *For the QzROM writing confirmation form and the mark specification form, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 51 of 60 3882 Group ELECTRICAL CHARACTERISTICS Table 12 Absolute maximum ratings Symbol VCC VI Parameter Power source voltages Input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67, P80–P87, RESET, XIN,CNVSS Input voltage P70–P77 Output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67, P80–P87, XOUT Output voltage P70–P77 Power dissipation Operating temperature Storage temperature Conditions Ratings –0.3 to 4.6 Unit V –0.3 to VCC +0.3 All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. V VI VO VO Pd Topr Tstg –0.3 to 5.8 –0.3 to VCC +0.3 0.3 to 5.8 500 –20 to 85 –40 to 125 V V V mW °C °C Ta = 25°C Table 13 Recommended operating conditions (VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VSS VIH VIH VIH VIH VIL Power source voltage Power source voltage “H” input voltage “H” input voltage P00–P07, P10–P17, P20–P27, ____________ 7, P40–P47, P30–P3 P50–P57, P60–P67, P80–P87, RESET, CNVSS P70–P77 0.8VCC 0.8VCC 2.0 0.8VCC 0 Parameter Limits Min. 3.0 Typ. 3.3 0 VCC 5.5 5.5 VCC 0.2VCC Max. 3.6 Unit V V V V V V V “H” input voltage (when TTL input level is selected) P70–P75 “H” input voltage “L” input voltage XIN P00–P07, P10–P17, P20–P27, P30–P37,____________ 7, P40–P4 P50–P57, P60–P67, P70–P77, P80–P87, RESET, CNVSS VIL VIL “L” input voltage (when TTL input level is selected) P70–P75 “L” input voltage XIN 0 0 0.8 0.16VCC V V Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 52 of 60 3882 Group Table 14 Recommended operating conditions (VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current Parameter P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 P40–P47, P50–P57, P60–P67 P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 P24–P27 P40–P47,P50–P57, P60–P67, P70–P77 P00–P07, P10–P17, P20–P27, P30–P37, P80–P87 P40–P47,P50–P57, P60–P67 P00–P07, P10–P17, P20–P23, P30–P37, P80–P87 P24–P27 P40–P47,P50–P57, P60–P67, P70–P77 Min. Limits Typ. Max. –80 –80 80 80 80 –40 –40 40 40 40 Unit mA mA mA mA mA mA mA mA mA mA Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Table 15 Recommended operating conditions (VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) “H” peak output current “L” peak output current “L” peak output current “H” average output current “L” average output current “L” peak output current Parameter P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67, P80–P87 (Note 1) P00–P07, P10–P17, P20–P23, P30–P37, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 (Note 1) P24–P27 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P67, P80–P87 (Note 2) P00–P07, P10–P17, P20–P23, P30–P37, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 (Note 2) P24–P27 (Note 2) Min. Limits Typ. Max. –10 10 20 –5 5 15 8 Unit mA mA mA mA mA mA MHz Main clock input oscillation frequency (Note 3) Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 53 of 60 3882 Group Table 16 Electrical characteristics (VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter “H” output voltage P00–P07, P10–P17, P20–P27 P30–P37, P40–P47, P50–P57 P60–P67, P80–P87 (Note) “L” output voltage P00–P07, P10–P17, P20–P27 P30–P37, P40–P47, P50–P57 P60–P67, P70–P77, P80–P87 Hysteresis CNTR0, CNTR1, INT0, INT1 INT20–INT40, INT21–INT41, INT5 P30–P37, LRESET LFRAME, LCLK, SERIRQ “H” input current P00–P07, P10–P17, P20–P27 P30–P37, P40–P47, P50–P57 P60–P67, P70–P77, P80–P87 RESET, CNVSS “H” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P37, P40–P47, P50–P57 P60–P67, P70–P77, P80–P87 RESET,CNVSS “L” input current XIN “L” input current P30–P37 (at Pull-up) RAM hold voltage Test conditions Min. VCC–1.0 Typ. Max. Unit VOH IOH = –5 mA V IOL = 5 mA IOL = 1.6 mA 1.0 0.4 V V VOL VT+–VT– 0.4 V IIH VI = VCC (Pin floating. Pull-up transistors “off”) VI = VCC VI = VSS (Pin floating. Pull-up transistors “off”) VI = VSS VI = VSS When clock stopped –3 –50 3 5.0 µA µA IIH –5.0 IIL µA µA µA V IIL IIL VRAM –13 2.0 –100 3.6 Note: P00–P03 are measured when the P00–P03 output structure selection bit (bit 0 of PCTL1) is “0”. P04–P07 are measured when the P04–P07 output structure selection bit (bit 1 of PCTL1) is “0”. P10–P13 are measured when the P10–P13 output structure selection bit (bit 2 of PCTL1) is “0”. P14–P17 are measured when the P14–P17 output structure selection bit (bit 3 of PCTL1) is “0”. P42, P43, P44, and P46 are measured when the P4 output structure selection bit (bit 2 of PCTL2) is “0”. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 54 of 60 3882 Group Table 17 Electrical characteristics (VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions High-speed mode f(XIN) = 8 MHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN) = 8 MHz Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) Output transistors “off” Additional current when LPC I/F functions LCLK = 33 MHz All oscillation stopped (in STP state) Output transistors “off” Ta = 25 °C Ta = 85 °C Min. Typ. 1.5 Max. 5 Unit mA 0.5 2 mA 0.7 3 mA ICC Power source current 0.4 1.5 0.1 1.5 mA mA 1.0 10 µA µA Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 55 of 60 3882 Group Table 18 Timing requirements (VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) Parameter Reset input “L” pulse width Main clock input cycle time Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41 input “H” pulse width INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41 input “L” pulse width Limits Min. 16 125 50 50 200 80 80 80 80 Typ. Max. Unit tc(XIN) ns ns ns ns ns ns ns ns Table 19 Switching characteristics (VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tr (CMOS) tf (CMOS) Parameter CMOS output rising time (Note 1) CMOS output falling time (Note 1) Test conditions Fig. 46 Limits Min. Typ. 10 10 Max. 30 30 Unit ns ns Notes 1: The XOUT pin is excluded. Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 56 of 60 3882 Group Measurement output pin 50pF CMOS output Fig. 47 Circuit for measuring output switching characteristics Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 57 of 60 3882 Group Timing diagram tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 0.8VCC tWH(INT) tWL(INT) 0.2VCC INT0, INT1, INT5 INT20, INT30, INT40 INT21, INT31, INT41 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC Fig. 48 Timing diagram Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 58 of 60 3882 Group Table 20 Timing requirements and switching characteristics (VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tC(CLK) tWH(CLK) tWL(CLK) tsu(D-C) th(C-D) tV(C-D) toff(A-F) Parameter LCLK clock input cycle time LCLK clock input “H” pulse width LCLK clock input “L” pulse width input set up time LAD3 to LAD0, SERIRQ, CLKRUN, LFRAME input hold time LAD3 to LAD0, CLKRUN, LFRAME SERIRQ, LAD3 to LAD0, SERIRQ, CLKRUN valid delay time LAD3 to LAD0,SERIRQ,CLKRUN floating output delay time Standard Min. 30 11 11 13 7 0 2 2 Typ. Max. Unit ns ns ns ns ns 15 28 ns ns Timing diagrams of LPC Bus Interface and Serial Interrupt Output tC(CLK) tWH(CLK) tWL(CLK) LCLK VIH VIL tsu(D-C) th(C-D) LAD[3:0] SERIRQ, CLKRUN, LFRAME (Input) tv(C-D) LAD[3:0] SERIRQ, CLKRUN (Active output) toff(A-F) LAD[3:0] SERIRQ, CLKRUN (Floating output ) Fig. 49 Timing diagram of LPC Interface and Serialized IRQ Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 59 of 60 3882 Group PACKAGE OUTLINE JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 61 40 bp b1 c1 *2 HE E c Reference Dimension in Millimeters Symbol Terminal cross section 80 21 1 ZD Index mark 20 F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e bp A1 *3 x L L1 Detail F Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 10° 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 ZE A2 A Rev.1.01 Nov 14, 2005 REJ03B0089-0101 page 60 of 60 c REVISION HISTORY Rev. Date Page 1.00 Oct 29, 2004 1.01 Nov 14, 2005 – 1 1-2,5-6 3 5 6 11 14 16 27 47 48 50 51 First edition issued 3882 Group Data Sheet Description Summary 52 55 60 Power dissipation is revised. 1.5 mA → 20mW Package name of 80P6Q-A is revised. 80P6Q-A → PLQP0080KB-A Table 1 is partly revised. Fig.3 is partly revised. Table 3 is partly added. Note of Table 2 is added. ROM Code Protect Address is added. Table 7 is partly revised. Note 2 of Fig.11 is added. • WATCHDOG TIMER is revised. • Fig.21 and Fig.22 are partly revised. • CLOCK GENERATING CIRCUIT is partly revised. • Fig.42 is partly revised. Note 3 of Fig.44 is added. Reserved Area, Reserved Bit and CPU Mode Register are added. The following are added; -Termination of Unused Pins -Product shipped in blank -Overvoltage -QzROM Version -Fig.46 Wiring for the CNVSS/(VPP) pin -Notes On QzROM Writing Orders -Notes On ROM Code Protect -DATA REQUIRED FOR QzROM WRITING ORDERS Table 12 is partly revised. Table 17 is partly revised. PACKAGE OUTLINE of 80P6Q-A is revised. 1/1 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: 2-796-3115, Fax: 2-796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .4.0