M38C84MF

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 38C8 group is the 8-bit microcomputer based on the 740 family core technology. The 38C8 group has a LCD drive control circuit (bias control, time sharing control), a 10-bit A-D converter, and a Serial I/O as additional functions. The various microcomputers in the 38C8 group include variations of internal memory type and packaging. For details, refer to the section on part numbering. FEATURES q Basic machine-language instructions ....................................... 71 q The minimum instruction execution time ............................ 0.5 µs (at 8 MHz oscillation frequency) q Memory size ROM ............................................................................ 60 K bytes RAM ............................................................................ 2048 bytes q Programmable input/output ports ............................................. 35 q Software pull-up resistors .................................................................. Ports P0–P3, P41–P47 q Interrupts ................................................... 14 sources, 14 vectors (includes key input interrupt) q Timers ............................................................ 8-bit ✕ 3, 16-bit ✕ 2 q Serial I/O ........................ 8-bit ✕ 1 (UART or Clock-synchronized) q A-D converter (32 kHz operating available) ... 10-bit ✕ 8 channels q LCD drive control circuit Bias ................................................................................... 1/5, 1/7 Duty .............................................................................. 1/16, 1/32 Common output ............................................................... 16 or 32 Segment output ............................................................... 52 or 68 q Main clock generating circuit (RC oscillation selectable) ...................... (connect to external ceramic resonator or resistor) q Sub-clock generating circuit ............................... (connect to external quartz-crystal oscilaltor) q Power source voltage In high-speed mode .................................................... 4.0 to 5.5 V In middle-speed mode ................................................ 2.2 to 5.5 V In low-speed mode ..................................................... 2.2 to 5.5 V q Power dissipation In high-speed mode ........................................................... 30 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................. 60 µW (at 32 kHz oscillation frequency, at 3 V power source voltage, at WIT state, at voltage multiplier operating, LCD drive waveform generating state) q Operating temperature range ................................... – 20 to 85°C APPLICATIONS Dot-matrix-type LCD displays 1 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) 101 100 99 98 97 96 108 107 106 105 104 103 102 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7/COM23 SEG6/COM22 SEG5/COM21 SEG4/COM20 SEG3/COM19 SEG2/COM18 SEG1/COM17 SEG0/COM16 COM7 COM6 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60/COM31 SEG61/COM30 SEG62/COM29 SEG63/COM28 SEG64/COM27 SEG65/COM26 SEG66/COM25 SEG67/COM24 COM15 COM14 M38C89MF-XXXFP COM13 COM12 COM11 COM10 COM9 COM8 P30/AIN0 P31/AIN1 P32/AIN2 P33/AIN3 NC XIN NC VSS XOUT OSCSEL VCC NC XCIN XCOUT NC RESET P10/AIN4 P11/AIN5 P12/AIN6 P13/AIN7 P14 P15 P16 P17 P00 P01 P02 P03 P04 P05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Fig. 1 M38C89MF-XXXFP pin configuration 2 COM5 COM4 COM3 COM2 COM1 COM0 VL1 VL2 VL3 VL4 VL5 C3 C2 C1 VLIN VSS (NC) NC VSS P27 P26 P25 P24 P23 P22 P21 P20 P47/SRDY P46/SCLK P45/TXD P44/RXD P43/CNTR1/BEEPP42/CNTR0/BEEP+ P41/INT1/ADT P40/INT0 P07 P06 Package type : 144P6Q-A 33 34 35 36 CNTR0, CNTR1 Key-on wake-up P4 (7) INT0, INT1 Fig. 2 Functional block diagram FUNCTIONAL BLOCK DIAGRAM (Package: 144P6Q-A) Sub-clock input RC Sub-clock Clock Clock oscillation output input output select XIN 61 XOUT OSCSEL XCIN 58 57 54 XCOUT 53 Reset input RESET 51 VCC 56 VSS 59 VSS 18 Data bus Clock generating circuit CPU A X ROM RAM φ PCH Y S PCL PS Timer Timer X (16) Timer Y (16) Timer 1 (8) LCD RAM (240 byte) LCD controller Timer 2 (8) Timer 3 (8) COM0 COM1 COM2 3 COM3 2 COM4 1 COM5 144 COM6 143 COM7 142 SEG0/COM16 141 SEG1/COM17 140 SEG2/COM18 139 SEG3/COM19 138 SEG4/COM20 137 SEG5/COM21 136 SEG6/COM22 135 SEG7/COM23 134 SEG8 133 SEG9 132 SEG10 131 SEG11 130 SEG12 6 5 4 87 SEG55 86 SEG56 85 SEG57 84 SEG58 83 SEG59 82 SEG60/COM31 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O (8) A-D converter (10) P3 (4) P0 (8) P1 (8) P2 (8) 27 28 29 30 31 32 33 34 63 64 65 66 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 19 20 21 22 23 24 25 26 15 14 13 12 11 10 9 8 7 SEG61/COM30 SEG62/COM29 SEG63/COM28 78 SEG64/COM27 77 SEG65/COM26 76 SEG66/COM25 75 SEG67/COM24 74 COM15 73 COM14 72 COM13 71 COM12 70 COM11 69 COM10 68 COM9 67 COM8 81 80 79 MITSUBISHI MICROCOMPUTERS 38C8 Group VLIN I/O port P4 I/O port P3 I/O port P0 I/O port P1 I/O port P2 C1 C2 C3 VL1 VL2 VL3 VL4 VL5 3 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1 Pin description Pin VCC, VSS RESET XIN XOUT OSCSEL XCIN XCOUT VLIN VL1 – VL5 COM0 – COM15 SEG0/COM16– SEG7/COM23, SEG60COM31– SEG67/COM24 SEG8–SEG59 P00–P07 P14–P17 P10/AIN4– P13/AIN7 P20–P27 P30/AIN0 – P33/AIN3 P40/INT0 Name Power source Reset input Clock input Clock output RC oscillation select Sub-clock input Sub-clock output Power source input for LCD LCD power source Common output Segment output/ Common output Function except a port function • Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS. (at high-speed mode) • Reset input pin for active “L.” • Input and output pins for the main clock generating circuit. • Feedback resistor is built in between XIN pin and XOUT pin. • Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. • If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. • This pin determines the oscillation between XIN and XOUT. The oscillation method can be selected from either by an oscillator or by a resistor. • Input and output pins for sub-clock generating circuit. (Connect a quartz-crystal oscillator between the XCIN and XCOUT pins to set the oscillation frequency. The clock generated the externals cannot be input directly.) • Reference voltage input pin for LCD. • The input voltage to this pin is boosted threefold by voltage multiplier. • LCD drive power source pins. • LCD common output pins. • LCD segment/common output pins. Function Segment output I/O port P0 I/O port P1 • LCD segment output pins. • 8-bit I/O port. • CMOS compatible input level. • CMOS 3-state output structure. • A-D converter analog input pin • Key-on wake-up interrupt input pin • A-D converter analog input pin I/O port P2 I/O port P3 Input port P4 P41/INT1/ADT I/O port P4 P42/CNTR0/ BEEP+, P43/CNTR1/ BEEPP44/RxD, P45/TxD, P46/SCLK, P47/SRDY C1, Voltage multiplier C2, C3 VSS (NC), NC • 4-bit I/O port. • CMOS compatible input level. • CMOS 3-state output structure. • 1-bit input port. • CMOS compatible input level. • 7-bit I/O port. • CMOS compatible input level. • CMOS 3-state output structure. • I/O direction register allows each pin to be individually programmed as either input or output. • External interrupt pin • External interrupt pin • A-D trigger input pin •Timer function I/O pin • Serial I/O I/O pin • External capacitor connect pins for a voltage multiplier of LCD. • Non-function pins. • Leave the VSS (NC) pin open. 4 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M38C8 9 M F –XXX FP Package type FP: 144P6Q-A package ROM number Omitted in One Time PROM version. ROM/PROM size 1: 4096 bytes 9: 36864 bytes 2: 8192 bytes A: 40960 bytes 3: 12288 bytes B: 45056 bytes 4: 16384 bytes C: 49152 bytes 5: 20480 bytes D: 53248 bytes 6: 24576 bytes E: 57344 bytes 7: 28672 bytes F: 61440 bytes 8: 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas; they cannot be used. Memory type M: Mask ROM version E: One Time PROM version RAM size 0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes Fig. 3 Part numbering 5 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 38C8 group as follows. Packages 144P6Q-A ................................... 0.5 mm-pitch plastic molded QFP Memory Type Support for mask ROM and One Time PROM versions Memory Size ROM/PROM size ............................................................ 60 K bytes RAM size ........................................................................ 2048 bytes Memory Expansion Plan ROM size (bytes) 60K 56K 48K 40K 32K 28K 24K 20K 16K 12K 8K 4K M38C89MF/EF 192 256 384 512 640 768 896 1,024 1,536 2,048 RAM size (bytes) Fig. 4 Memory expansion plan Currently products are listed below. Table 2 List of products Product name M38C89MF-XXXFP M38C89EFFP (P) ROM size (bytes) ROM size for User in ( ) 61440 (61310) 61440 (61310) RAM size (bytes) 2048 2048 Package 144P6Q-A 144P6Q-A Remarks Mask ROM version One Time PROM version 6 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 38C8 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 A b7 X b7 Y b7 S b15 PCH b7 b7 PCL b0 Accumulator b0 Index register X b0 Index register Y b0 Stack pointer b0 Program counter b0 Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag NVTBD I ZC Fig. 5 740 Family CPU register structure 7 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER On-going Routine Interrupt request (Note) Execute JSR M (S) Push return address on stack (S) M (S) (S) (PCH) (S) – 1 (PCL) (S)– 1 M (S) (S) M (S) (S) M (S) (S) (PCH) (S) – 1 (PCL) (S) – 1 (PS) (S) – 1 Push contents of processor status register on stack Push return address on stack Subroutine Execute RTS POP return address from stack (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S) + 1 M (S) (S) + 1 M (S) (S) + 1 M (S) I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Note: Condition for acceptance of an interrupt Interrupt disable flag is “0” and Interrupt enable bit corresponding to each interrupt is “1” Fig. 6 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Accumulator Processor status register PHA PHP Pop instruction from stack PLA PLP 8 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. •Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. •Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. •Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. •Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. •Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. •Bit 5: Index X mode flag (T) When the T flag is “ 0 ” , arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. •Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. •Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register C flag Set instruction Clear instruction SEC CLC Z flag – – I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – 9 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16. b7 b0 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Sub-clock (XCIN–XCOUT) oscillating bit 0 : Stopped 1 : Oscillating Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Fig. 7 Structure of CPU mode register 10 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFDC16 FFFE16 FFFF16 Reserved ROM area Interrupt vector area Special page FF0016 ROM ZZZZ16 084016 Not used YYYY16 Reserved ROM area (128 bytes) Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 043016 RAM 013016 XXXX16 034016 LCD display RAM area✽ 000016 SFR area 004016 LCD display RAM area✽ Zero page ✽ The start address of the LCD display area can be switched either zero page (addresses 004016–012F16) or 3 page (addresses 034016 –042F16) by software. Immediately after reset released, 3 page is selected. Fig. 8 Memory map diagram 11 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 PULL register A (PULLA) 001716 PULL register B (PULLB) 001816 Transmit/Receive buffer register (TB/RB) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIOCON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 001E16 001F16 002016 Timer X (low-order) (TXL) 002116 Timer X (high-order) (TXH) 002216 Timer Y (low-order) (TYL) 002316 Timer Y (high-order) (TYH) 002416 Timer 1 (T1) 002516 Timer 2 (T2) 002616 Timer 3 (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 A-D control register (ADCON) 003216 A-D conversion register (low-order) (ADL) 003316 A-D conversion register (high-order) (ADH) 003416 003516 003616 003716 LCD control register 1 (LC1) 003816 LCD control register 2 (LC2) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) Fig. 9 Memory map of special function register (SFR) 12 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS [Direction Registers] The I/O ports P0–P3 and P41–P47 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. b7 b0 PULL register A (PULLA: address 001616) P00–P03 pull-up P04–P07 pull-up P10–P13 pull-up P14–P17 pull-up P20–P23 pull-up P24–P27 pull-up P30–P33 pull-up Not used (return “0” when read) b7 b0 PULL register B (PULLB: address 001716) Not used (return “0” when read) P41 pull-up P42 pull-up P43 pull-up P44 pull-up P45 pull-up P46 pull-up P47 pull-up 0: No pull-up 1: Pull-up Pull-up Control By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P4 except for port P40 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Note: The contents of PULL register A and PULL register B do not affect ports programmed as the output port. Fig. 10 Structure of PULL register A and PULL register B 13 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 5 List of I/O port function Pin P00–P07 P10/AIN4– P13/AIN7 P14–P17 P20–P27 Name Port P0 Port P1 Input/Output Input/Output, individual bits I/O format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS 3-state output Non-port function A-D converter input Related SFRs PULL register A PULL register A A-D control register PULL register A PULL register A Interrupt control register 2 PULL register A A-D control register PULL register B Interrupt edge select register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Serial I/O control register Serial I/O status register UART control register LCD mode register Ref. No. (1) (2) (1) (1) Port P2 Input/Output, individual bits Input/Output, individual bits Input Input/Output, individual bits P30/AIN0– P33/AIN3 P40/INT0 P41/INT1/ADT P42/CNTR0/ BEEP+ P43/CNTR1/ BEEPP44/RxD P45/TxD P46/SCLK P47/SRDY COM0–COM7, COM8–COM15 SEG0/COM16– SEG7/COM23, SEG60/COM31– SEG67/COM24 SEG8–SEG59 Port P3 Key input (key-on wake-up) interrupt input A-D converter input (2) Port P4 External interrupt input Timer X function I/O Timer Y function I/O Serial I/O funtion I/O (3) (1) (4) (5) (6) (7) (8) (9) Common Segment/ Common Output LCD common output LCD segment output LCD common ouput Segment LCD segment output 14 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0, P14–P17, P2, P41 Pull-up control (2) Ports P10–P13, P3 Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Key-on wake-up interrupt input INT1 interrupt input, ADT Except P0, P14–P17 A-D converter input Analog input pin selection bit (3) Port P40 Data bus INT0 interrupt input (4) Port P42 Pull-up control (5) Port P43 Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch Buzzer output mode Timer output CNTR0 interrupt input Buzzer output mode Timer output CNTR1 interrupt input Fig. 11 Port block diagram (1) 15 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (6) Port P44 (7) Port P45 Serial I/O enable bit Receive enalble bit Direction register Pull-up control P45/TxD P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Databus Port latch Pull-up control Data bus Port latch Serial I/O input Serial I/O output (8) Port P46 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch (9) Port P47 Pull-up control Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch Pull-up control Serial I/O clock output Serial I/O clock input Serial I/O ready output Fig. 12 Port block diagram (2) 16 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS Interrupts occur by fourteen sources: five external, eight internal, and one software. Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. sNotes on interrupts When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: A-D control regsiter (address 3116) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ➀Set the corresponding interrupt enable bit to “0” (disabled). ➁Set the interrupt edge select bit (active edge switch bit) or the interrupt source select bit to “1”. ➂Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the corresponding interrupt enable bit to “1” (enabled). Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. Table 6 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Low Reset (Note 2) 1 FFFD16 FFFC16 INT0 2 FFFB16 FFFA16 INT1 Serial I/O reception Serial I/O transmission Timer X Timer Y Timer 2 Timer 3 CNTR0 CNTR1 Timer 1 Key input (Keyon wake-up) A-D conversion BRK instruction 3 4 5 6 7 8 9 10 11 12 13 14 15 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE116 FFDF16 FFDD16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE016 FFDE16 FFDC16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 intput At detection of either rising or falling edge of INT1 input At completion of serial I/O data reception At completion of serial I/O transmission shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At falling of port P2 (at input) input logical level AND At completion of A-D conversion At BRK instruction execution Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O is selected Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (falling valid) Valid when A-D conversion interrupt is selected Non-maskable software interrupt Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 17 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 13 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (return “0” when read) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit Not used (returns “0” when read) Key input interrupt request bit A-D conversion interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) Key input interrupt enable bit A-D conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Fig. 14 Structure of interrupt-related registers 18 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt (Key-on Wake-Up) A key input interrupt request is generated by applying “L” level to any pin of port P2 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 15, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P23. Port PXx “L” level output PULL register A Bit 5 = “1” Port P27 direction register = “1” ✽ ✽✽ Key input interrupt request Port P27 latch P27 output Port P26 direction register = “1” ✽ ✽✽ Port P26 latch P26 output ✽ Port P25 direction register = “1” ✽✽ Port P25 latch P25 output Port P24 direction register = “1” ✽ ✽✽ Port P24 latch P24 output PULL register A Bit 4 = “1” ✽ ✽✽ Port P23 direction register = “0” Port P23 latch Port P2 Input reading circuit P23 input Port P22 direction register = “0” ✽ ✽✽ P22 input Port P22 latch Port P21 direction register = “0” ✽ ✽✽ P21 input Port P21 latch Port P20 direction register = “0” ✽ ✽✽ P20 input Port P20 latch ✽ P-channel transistor ✽✽ CMOS output buffer for pull-up Fig. 15 Connection example when using key input interrupt and port P2 block diagram 19 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 38C8 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the highorder byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Data bus f(XIN)/16 (f(XCIN)/16 in low-speed mode✽) f(XIN) “00”,“11” f(XCIN) “01” Timer X count source “1” selection bit Timer X stop control bit Timer X write control bit Timer X operating CNTR0 active mode bits edge switch bit “0 ” Timer X operating mode bits P42/CNTR0/BEEP+ “0 ” “1 ” Pulse width measurement mode “00”,“01”,“11” “10” Timer X (low) latch (8) Timer X (low) (8) Timer X (high) latch (8) Timer X (high) (8) Timer X interrupt request CNTR0 active edge switch bit Buzzer output mode CNTR0 interrupt request “0 ” Q S T Q Timer Y operating mode bits P42 direction register P42 latch Buzzer output mode “1 ” “00”,“01”,“10” Pulse width HL continuously measurement mode CNTR1 interrupt request Rising edge detection Falling edge detection f(XIN)/16 (f(XCIN)/16 in low-speed mode✽) Timer Y stop control bit Period measurement mode “11” CNTR1 active edge switch bit “00”,“01”,“11” “10” Timer Y operating mode bits Timer Y (low) latch (8) Timer Y (low) (8) Timer Y (low) high (8) Timer Y (high) (8) Timer Y interrupt request P43/CNTR1/BEEP- “0 ” “1 ” P43 direction register P43 latch BEEP- valid bit f(XIN)/16 (f(XCIN)/16 in low-speed mode✽) Timer 1 count source selection bit “0” Timer 2 count source selection bit Timer 2 write control bit Timer 1 interrupt request Timer 1 latch (8) Timer 1 (8) “0 ” “1 ” Timer 2 latch (8) Timer 2 (8) Timer 2 interrupt request f(XCIN)/32 “1 ” f(XIN)/16 (f(XCIN)/16 in low-speed mode✽) “0 ” f(XCIN)/32 “1 ” Timer 3 latch (8) Timer 3 (8) Timer 3 interrupt request Timer 3 count source selection bit ✽ Internal clock φ = XCIN divided by 2 in low-speed mode Fig. 16 Timer block diagram 20 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write by setting the timer X mode register. b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only BEEP- valid bit 0 : Invalid 1 : Valid Not used Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Buzzer output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in buzzer output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for interrupt 1 : Count at falling edge in event counter mode Start from “L” output in buzzer output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for interrupt Timer X stop control bit 0 : Count start 1 : Count stop (1) Timer Mode When the timer X count source selection bit is “0”, the timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). When it is “1”, the timer counts f(XIN). (2) Buzzer Output Mode When the timer X count source selection bit is “0”, the timer counts f(XCIN). When it is “1”, the timer counts f(XIN). Each time the timer underflows, a signal output from the BEEP+ pin is inverted. When the BEEP- valid bit is “1”, the opposite phase of BEEP+ signal is output from the BEEP- pin. When using the BEEP+ pin and the BEEP- pin, set ports shared with these pins to output. (3) Event Counter Mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR0 pin to input. (4) Pulse Width Measurement Mode When the timer X count source selection bit is “0”, the count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). When it is “1”, the count source is f(XIN). If CNTR 0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the port shared with the CNTR0 pin to input. qTimer X write control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Fig. 17 Structure of timer X mode register sNotes on CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. 21 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. b7 b0 Timer Y mode register (TYM : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 in low-speed mode✽) 1 : f(XIN) Not used (return “0” when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNT R1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Interrupt falling edge active 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Interrupt rising edge active Timer Y stop control bit 0 : Count start 1 : Count stop (1) Timer Mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period Measurement Mode CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the abovementioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR1 pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR1 pin input signal is found by CNTR1 interrupt. When using a timer in this mode, set the port shared with the CNTR1 pin to input. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the port shared with the CNTR1 pin to input. ✽ Internal clock φ in low-speed mode is XCIN divided by 2. When the timer X operating mode bits are “00” or “11”, the timer X count source is f(XCIN)/16. When the timer X operating mode bits are “01”, the timer X count source is f(XCIN). Fig. 18 Structure of timer Y mode register (4) Pulse Width HL Continuously Measurement Mode CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the port shared with the CNTR1 pin to input. sNotes on CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 22 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by the timer 123 mode register. The timer latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. qTimer 2 write control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. b7 b0 Timer 123 mode register (T123M :address 002916) Not used Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode*) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XCIN)/32 Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode*) 1 : f(XCIN)/32 Not used (return “0” when read) * Internal clock φ is XCIN/2 in the low-speed mode. sNotes on timer 1 to timer 3 When the count source of timer 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 19 Structure of timer 123 mode register 23 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer registers. Data bus Address 001816 Receive buffer register Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P44/RXD Receive shift register Shift clock P46/SCLK Serial I/O clock selection bit Frequency division ratio 1/(n+1) Baud rate generator BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 P47/SRDY F/F Falling-edge detector 1/4 Address 001C16 Clock control circuit Shift clock P45/TXD Transmit shift register Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Address 001916 Address 001816 Data bus Serial I/O status register Fig. 20 Block diagram of clock synchronous serial I/O Transmit/receive shift clock (1/2 to 1/2048 of internal clock, or an external clock) Serial output TXD Serial input RXD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY Write signal to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 21 Operation of clock synchronous serial I/O function 24 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer register, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register OE Character length selection bit STdetector 7 bits Receive shift register 8 bits Serial I/O control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P44/RXD PE FE SP detector Clock control circuit UART control register Address 001B16 Serial I/O clock selection bit P46/SCLK BRG count source selection bit f(XIN) (f(XCIN) in lowspeed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 P45/TXD Character length selection bit Transmit buffer register Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Transmit shift register Address 001816 Data bus Fig. 22 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 TBE=0 TBE=1 D1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 ✽Generated TSC=1✽ SP at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=1 Serial input RXD ST D0 D1 SP ST D0 RBF=0 RBF=1 SP D1 Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the T BE or TSC flag becomes “1” by the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 23 Operation of UART serial I/O function 25 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Buffer/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. sNotes on serial I/O When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. ➀Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁Set the transmit enable bit to “1”. ➂Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the serial I/O transmit interrupt enable bit to “1” (enabled). [Serial I/O Status Register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE. Writing “0” to the serial I/O enable bit (SIOE) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O Control Register (SIOCON)] 001A16 The serial I/O control register contains eight control bits for the serial I/O function. [UART Control Register (UARTCON)] 001B16 This is a 5 bit register containing four control bits, which are valid when UART is selected and set the data format of an data receiver/ transfer, and one control bit, which is always valid and sets the output structure of the P45/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 26 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Serial I/O status register (SIOSTS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: OE U PE U FE =0 1: OE U PE U FE =1 Not used (returns “1” when read) b7 b0 Serial I/O control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin. 1: P47 pin operates as SRDY output pin. Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P44–P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P44–P47 operate as serial I/O pins) b7 b0 UART control regi ster (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return “1” when read) Fig. 24 Structure of serial I/O control registers 27 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003216, 003316 The A-D conversion registers are read-only registers that contain the result of an A-D conversion. During A-D conversion, do not read these registers. Resistor ladder The resistor ladder outputs the comparison voltage by dividing the voltage between VDD and VSS by resistance. Channel Selector The channel selector selects one of the ports P33/AIN3–P30/AIN0 and ports P10/AIN4–P13/AIN7, and inputs it to the comparator. [A-D Control Register (ADCON)] 003116 The A-D control register controls the A-D conversion process. Bits 0 to 2 are analog input pin selection bits. Bit 3 is an A-D conversion completion bit and “0” during A-D conversion, then changes to “1” when the A-D conversion is completed. Writing “0” to this bit starts the A-D conversion. When bit 5, which is the A-D external trigger valid bit, is set to “1”, A-D conversion is started even by a rising edge or falling edge of an ADT input. b7 b0 A-D control register (ADCON : address 003116) Analog input pin selection bits 0 0 0 : P30/AIN0 0 0 1 : P31/AIN1 0 1 0 : P32/AIN2 0 1 1 : P33/AIN3 1 0 0 : P10/AIN4 1 0 1 : P11/AIN5 1 1 0 : P12/AIN6 1 1 1 : P13/AIN7 A-D conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (return “0” when read) A-D external trigger valid bit 0 : A-D external trigger invalid 1 : A-D external trigger valid Not used (return “0” when read) Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Because the comparator consists of a capacitor coupling, a deficient conversion speed may cause lack of electric charge and make the conversion accuracy worse. When A-D conversion is performed, set f(XIN) to at least 500 kHz. When both bit 5 and bit 4 of the CPU mode register are set to “1”, A-D conversion is performed by using the built-in self-oscillation circuit. •8-bit read (Read only address 003216.) b7 A-D conversion register (low-order) (ADL: Address 003216) b0 b9 b8 b7 b6 b5 b4 b3 b2 •10-bit read (Read address 003316 first.) b7 A-D conversion register (high-order) (ADH: Address 003316) b7 A-D conversion register (low-order) (ADL: Address 003216) b0 b9 b8 b0 Trigger Start When using the A-D external trigger, set the port shared with the ADT pin to input. The polarity of INT1 interrupt edge also applies to the A-D external trigger. When the INT1 interrupt edge polarity is switched after an external trigger is validated, an A-D conversion may be started. b7 b6 b5 b4 b3 b2 b1 b0 Note: High-order 6 bits of address 003316 becomes “0” at reading. Fig. 25 Structure of A-D control register Data bus b7 A-D control register P41/INT1/ADT 3 P30/AIN0 P31/AIN1 P32/AIN2 P33/AIN3 P10/AIN4 P11/AIN5 P12/AIN6 P13/AIN7 b0 A-D control circuit Channel selector ( H) A-D interrupt request (L) Comparater A-D conversion register A-D conversion register 10 Resistor ladder VSS Fig. 26 A-D converter block diagram VCC 28 Data bus LCD mode register (address 003916) L M7 L M6 L M5 L M4 L M3 L M2 L M1 L M0 LCD CONTROLLER/DRIVER LCD control register 1 (address 003716) LC17 LC16 LC15 LC14 LC13 LC12 LC11 LC10 The 38C8 group has the built-in Liquid Crystal Display (LCD) controller/driver consisting of the following. q240-byte LCD display RAM q52 or 68 segment driver q 16 or 32 common driver q LCD clock generator q Timing controller Fig. 27 Block diagram of LCD controller/driver LCD control register 2 (address 003816) LC27 LC26 LC25 LC24 LC23 LC22 LC21 LC20 008316, 00C716 or 038316, 03C716 Bit 14 15 01 78 14 15 LCD display RAM 004016, 008416 or 034016, 038416 Bit 78 004116, 008516 or 034116, 038516 “0” 008216, 00C616 or 038216, 03C616 Bit Bit 01 78 14 15 0 1 78 14 15 01 LCD clock generator “1” f(XIN)/1024 f(XCIN)/16 LCDCK Bit selector Timing controller Bit selector Bit selector Bit selector Segment driver Bias controller Voltage multiplier Segment driver Segment driver Segment driver Common driver Common/Segment driver 11 84 SEG58 SEG59 VL4 VL2 C3 9 10 VL3 8 VL1 7 134 133 83 VL5 13 15 12 C2 14 VLIN C1 6 5 COM0 COM1 74 142 141 73 COM15 COM16/ COM17/ COM31/ SEG60 SEG1 SEG0 MITSUBISHI MICROCOMPUTERS SEG8 SEG9 38C8 Group q Bias controller q Voltage multiplier q LCD mode register q LCD control registers 1, 2 A maximum of 68 segment output pins and 32 common output pins can be used for control of external LCD display. SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 29 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Controller/Driver Function The controller/driver performs the bias control and the time sharing control by the LCD control registers 1, 2 (LC1, LC2), and the LCD mode register (LM). The data of corresponding LCDRAM is output from the segment pins according to the output timing of the common pins. The 38C8 group has the voltage multiplier only for LCD in addition to LCD controller/driver . Table 7 Maximum number of display pixels at each duty ratio Duty ratio 16 32 Maximum number of display pixel 16 ✕ 68 dots (5 ✕ 7 dots + cursor 2 lines) 32 ✕ 52 dots (5 ✕ 7 dots + cursor 4 lines) [LCD mode register (LM)] 003916 The LCD mode register is used for setting the LCD controller/driver according to the LCD panel used. Note: When executing the STP instruction while operating LCD, execute the STP instruction after prohibiting LCD (set “0” to bit 3 of the LCD mode regsiter). [LCD control register 1 (LC1)] 003716 The LCD control register 1 controls the voltage multiplier and built-in resistance. [LCD control register 2 (LC2)] 003816 The LCD control register 2 is write-only. Setting “1” to bit 5 makes built-in resistance low resistance, and can raise drivability of the segment pins and the common pins. b7 b0 LCD control register 1 (LC1: address 003716) Not used (Do not write “1” to these bits.) Drivability selection bit 1 0 : Normal (Drivability selection bit 2 valid) 1 : Restraint (Note 1) Not used (Do not write “1” to this bit.) Voltage multiplier enable bit 0 : Voltage multiplier stop 1 : Voltage multiplier operating b7 b0 LCD mode register (LM: address 003916) Duty ratio selsection bit✽ 1 : 32 duty (use COM0–COM31) 0 : 16 duty (use COM0–COM15) Not used (Do not write “0” to this bit.) LCD display RAM address selection bit 0 : 3 page 1 : 0 page LCD enable bit 0 : LCD OFF 1 : LCD ON LCD drive timing selection bit 0 : A type 1 : B type LCDCK division ratio selection bits b6 b5 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note 3) 0 : f(XIN)/1024 1 : f(XCIN)/16 Note 1: Consumption current can be reduced by restraint of drivability. But an irregular display might be caused according to the panel or the display pattern. b7 b0 LCD control register 2 (LC2: address 003816) Not used (Do not write “1” to these bits.) Drivability selection bit 2 0 : Normal 1 : Reinforcing (Note 2) Not used (Do not write “1” to these bits.) Note 3: LCDCK is a clock for a LCD timing controller. Internal clock φ is XCIN divided by 2 in the low-speed mode. ✽ When selecting 32 duty, functions of pins 135 to 142 become COM16 to COM23, and functions of pins 75 to 82 become COM24 to COM31. Note 2: The drive of a more large-scale LCD panel becomes easy by setting “1” to this bit. But consumption current is increased at LCD drive. When the drivability selection bit 1 is “1”, this function is invaid. Fig. 28 Structure of LCD control register 30 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bias Control In the LCD power source pins (VL1–VL5), 1/7 bias is automatically generated in 32 duty ratio and 1/5 bias is done in 16 duty ratio as well. Be sure to connect the capacitor for smoothness to these pins. When requiring 1/5 bias in 32 duty ratio, use an external resistor to generate a necessary level. In this case the drivability selection bit 1 of LCD control register 1 must be “1”. Voltage Multiplier When the voltage multiplier is operated after a reference voltage for boosting is applied to LCD power supply VLIN, a voltage that is approximately three times as large as that of VLIN pin occurs at the VL5 pin. Operate the voltage multiplier after applying a reference voltage for boosting to VLIN. The voltage multiplier multiplies a VLIN voltage by charge/discharge of capacitors between C1 and C2 pins and to C3 pin. Accordingly, if a large LCD panel is driven or a vias value is changed owing to an external resistor, a level from VL5 pin might be not a requested level. To prevent this, we recommend use of an external power source which can supply stabilized power. Additionally, when using the voltage multiplier, set a higher resistor value (the sum of R1 to R5) as possible (100 kΩ or more recommended). Table 8 Bias control and applied voltage to VL1–VL5 Bias value VL5 = VLCD VL4 = 6/7 VLCD VL3 = 5/7 VLCD VL2 = 2/7 VLCD VL1 = 1/7 VLCD VL5 = VLCD VL4 = 4/5 VLCD VL3 = 3/5 VLCD VL2 = 2/5 VLCD VL1 = 1/5 VLCD Voltage value 1/7 bias in 32 duty ratio 1/5 bias in 16 duty ratio Note: VLCD is a value which can be supplied to the LCD panel. Set value which is less than maximum ratings to VLCD. RT VL5 VL4 VL3 VL2 VL1 C3 C2 C1 VLIN 1.3 to 2.33 V RT VL5 VL4 VL3 VL2 VL1 C3 C2 C1 VLIN •At 1/5 bias R1=R2=R3=R4=R5 •At 1/7 bias R1=R2=R4=R5 R3=3•R1 R1 R2 R3 R4 R5 VL5 VL4 VL3 VL2 VL1 C3 C2 C1 VLIN 1/5, 1/7 bias When using voltage multiplier circuit Fig. 29 Example of circuit at each bias 1/5, 1/7 bias When not using voltage multiplier circuit (1) 1/5, 1/7 bias When not using voltage multiplier circuit (2) 31 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Common Pin and Duty Ratio Control The common pins (COM0–COM31) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bit (bit 0 of the LCD mode register). Table 9 Duty ratio control and common pins used Duty ratio 16 32 Duty ratio selection bit 0 1 Common pins used COM0–COM15 (Note) COM0–COM31 LCD Display RAM When LCD display RAM address selection bit is “0”, the area of addresses 034016 to 042F16 is the designated RAM for the LCD display. When the bit is “1”, the area of addresses 004016 to 012F16 is the designated RAM for it. When “1”s are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation; f(LCDCK) = (frequency of count source for LCDCK) (divider division ratio for LCD) f(LCDCK) (duty ratio) Note: The SEG0/COM16–SEG7/COM23 pins are used as the SEG0–SEG7. The SEG67/COM24–SEG60/COM31 pins are used as the SEG67–SEG60. Frame frequency = SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 000000001000101110111110 000000001101100100001000 000000001010100100001000 000000001000100100001000 000000001000100100001000 000000001000100100001000 000000001000101110001000 000000000000000000000000 010001011111001110001110 011011000010010001010001 010101000100010001010000 010001000010001110010000 010001000001010001010000 010001010001010001010001 010001001110001110001110 000000000000000000000000 0010001011111001 0011011000010010 0010101000100010 0010001000010001 0010001000001010 0010001010001010 0010001001110001 0000000000000000 0000000000100010 0000000000100010 0000000000010100 0000001110001000 0000000000010100 0000000000100010 0000000000100010 0000000000000000 LCD display map When selecting 3 page 0340 0341 0342 0343 0344 0345 0346 0347 0348 0349 034A 034B 034C 034D 034E 034F 0350 0351 0352 0353 0354 0355 0356 0357 036C 036D 036E 036F 0370 0371 0372 0378 0374 0375 0376 0377 0378 0379 037A 037B 037C 037D 037E 037F 0380 0381 0382 0383 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 00EC 00ED 00EE 00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079 007A 007B 007C 007D 007E 007F 0080 0081 0082 0083 0420 0421 0422 0423 0424 0425 0426 0427 0428 0429 042A 042B 042C 042D 042E 042F 03EC 03ED 03EE 03EF 03F0 03F1 03F2 03F3 03F4 03F5 03F6 03F7 03F8 03F9 03FA 03FB 03B0 03B1 03B2 03B3 03B4 03B5 03B6 03B7 03B8 03B9 03BA 03BB 03BC 03BD 03BE 03BF 03C0 03C1 03C2 03C3 03C4 03C5 03C6 03C7 Fig. 30 LCD display RAM map 32 00FC 00FD 00FE 00FF 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 010A 010B 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 0084 0085 0086 0087 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 03FC 03FD 03FE 03FF 0400 0401 0402 0403 0404 0405 0406 0407 0408 0409 040A 040B 03C8 03C9 03CA 03CB 03CC 03CD 03CE 03CF 03D0 03D1 03D2 03D3 03D4 03D5 03D6 03D7 0384 0385 0386 0387 0388 0389 038A 038B 038C 038D 038E 038F 0390 0391 0392 0393 0394 0395 0396 0397 0398 0399 039A 039B When selecting 0 page SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 LSB 010001010001001000000000 010000010001001000000000 001110011111001000000000 000001010001001000000000 010001010001001000000000 001110010001011100000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 LSB 100000100000100000100010 100000100000100000100010 111100111100111100111100 100000100000100000100000 100000100000100000100000 111110100000100000100000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB 1 0 0 1 0 0 0 1 0 1 1 1 1 1 0 0 LSB 0101101101000000 0101010101000000 1101000101111000 0101000101000000 0101000101000000 1001000101000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 LSB 1000001000100000 1000001000100000 1111001111000000 1000001000000000 1000001000000000 1000001000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCDCK 1 frame (16 clocks) VL5 VL4 COM23 VL3 VL2 VL1 VSS VL5 VL4 COM22 VL3 VL2 VL1 VSS VL5 VL4 SEG0 VL3 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 SEG0 – COM23 VSS VL1 VL2 VL3 VL4 VL5 ON VL5 VL4 VL3 VL2 VL1 SEG0 – COM22 VSS VL1 VL2 VL3 VL4 VL5 OFF OFF OFF ON OFF 1 frame (16 clocks) Fig. 31 LCD drive waveform (16 duty ratio, 1/5 bias, A type) 33 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCDCK 1 frame (32 clocks) VL5 VL4 VL3 VL2 VL1 VSS VL5 VL4 VL3 COM30 VL2 VL1 VSS VL5 VL4 VL3 SEG0 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 ON OFF ON OFF ON OFF 1 frame (32 clocks) COM31 SEG0 – COM31 VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 SEG0 – COM30 OFF OFF OFF Fig. 32 LCD drive waveform (32 duty ratio, 1/7 bias, B type) 34 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between VCC (min.) and 5.5 V, and the quartz-crystal oscillator should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.2Vcc when a power source voltage passes VCC (min.). Poweron Power source voltage 0V Reset input voltage 0V RESET VCC 0.2VCC RESET VCC Power source voltage detection circuit Fig. 33 Reset circuit example XIN φ RESET Internal reset Reset address from vector table Address Data ? ? ? ? FFFC ADL FFFD ADH, ADL ADH SYNC XIN : about 8200 cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 34 Reset sequence 35 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Port P4 direction register (6) PULL register A (7) PULL register B (8) Serial I/O status register (9) Serial I/O control register (10) UART control register (11) Timer X (low-order) (12) Timer X (high-order) (13) Timer Y (low-order) (14) Timer Y (high-order) (15) Timer 1 (16) Timer 2 (17) Timer 3 (18) Timer X mode register (19) Timer Y mode register (20) Timer 123 mode register 000116 000316 000516 000716 000916 001616 001716 001916 001A16 001B16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 Register contents 0016 0016 0016 0016 0016 0016 0016 8016 0016 E016 FF16 FF16 FF16 FF16 FF16 0116 FF16 0016 0016 0016 (21) A-D control register (22) A-D conversion register (low-order) (23) A-D conversion register (high-order) (24) LCD control register 1 (25) LCD control register 2 (26) LCD mode register Address 003116 003216 003316 003716 003816 003916 Register contents 0816 XX16 XX16 0016 0016 0316 0016 4C16 0016 0016 0016 0016 (27) Interrupt edge selection register 003A16 (28) CPU mode register (29) Interrupt request register 1 (30) Interrupt request register 2 (31) Interrupt control register 1 (32) Interrupt control register 2 (33) Processor status register (34) Program counter 003B16 003C16 003D16 003E16 003F16 (PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕ (PCH) (PCL) Contents of address FFFD16 Contents of address FFFC16 Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined Fig. 35 Internal status at reset 36 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 38C8 group has two built-in oscillation circuits: main clock XINXOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). RC oscillation is available for XIN-XOUT. Immediately after reset is released, the XIN-XOUT oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high impedance state. Oscillation Control (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116.” Either XIN divided by 16 or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits except bit 4 of the timer 123 mode register are cleared to “0.” Set the interrupt enable bits of timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Main Clock An oscillation circuit by a resonator can be formed by setting the OSCSEL pin is set to “L” level and connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists onchip. To supply a clock signal externally, make the XOUT pin open in the “L” level state of the OSCSEL pin, and supply the clock from the XIN pin. The RC oscillation circuit can be formed by setting the OSCSEL pin to “H” level and connecting a resistor between the XIN pin and the XOUT pin. At this time, the feed-back resistor is cut off. The frequency of the RC oscillation changes owing to a parasitic capacitance or the wiring length etc. of the printed circuit board. Do not use the RC oscillation in the usage which the frequency accuracy of the main clock is needed. (2) Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Sub-clock Connect a resonator between XCIN and XCOUT. An external feedback resistor is needed between XCIN and XCOUT since a feed-back resistor does not exist on-chip. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external resonator to oscillate. XCIN Rf XCOUT OSCSEL XIN XOUT Rd Rosc Frequency Control (1) Middle-speed Mode The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected. CCIN (2) High-speed Mode The internal clock φ is the frequency of XIN divided by 2. Fig. 36 RC oscillation circuit (3) Low-speed Mode The internal clock φ is the frequency of XCIN divided by 2. A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. sNotes on clock generating circuit If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN). XCIN XCOUT OSCSEL XIN XOUT Rf CCIN Rd CCOUT CI N COUT Fig. 37 Resonator circuit 37 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT XIN XOUT Internal system clock selection bit (Note) Timer 1 count source selection bit “1” Timer 1 “0” Timer 2 count source selection bit “0” Timer 2 “1” Low-speed mode “1” 1/2 “0” Middle-/High-speed mode 1/4 1/2 Main clock division ratio selection bit Middle-speed mode “1” “0” High-speed mode or Low-speed mode Timing φ (Internal clock) Main clock stop bit Q S R WIT instruction S Q Q S STP instruction R R STP instruction Reset Interrupt disable flag I Interrupt request Note: When selecting the XC oscillation, set the sub-clock (XCIN –XCOUT) oscillating bit to “1”. Fig. 38 Clock generating circuit block diagram 38 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Middle-speed mode (f(φ) = 0.5 MHz) CM7 = 0 (4 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (4 MHz oscillating) CM4 = 0 (32 kHz stoped) CM6 “1” High-speed mode (f(φ) = 2 MHz) “0” CM7 = 0 (4 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (4 MHz oscillating) CM4 = 0 (32 kHz stoped) C” M0 “ “0” “0 ” C “1 M4 C” M “0 ” CM4 “1” CM4 6 “1 ” Middle-speed mode (f(φ) = 0 .5 MHz) CM6 “1” “0” High-sp eed mode (f(φ) = 2 MHz) CM7 = 0 (4 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (4 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 = 0 (4 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (4 MHz oscillating) CM4 = 1 (32 kHz oscillating) “0” CM7 “1” Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (4 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “1” Low-speed mode (f(φ) =16 kHz) “0” CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (4 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM7 “1” “0” “1” “0” 4 C M1” “ 6 ” “1 ” “0 C” M “0 6 C” M1 “ b7 b4 CPU mode register (CPUM : address 003B16) “0” “0” L ow-speed mode (f(φ) =16 kHz) CM6 “1” “0” Low-speed mode (f(φ) =16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (4 MHz stopped) CM4 = 1 (32 kHz oscillating) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (4 MHz stopped) CM4 = 1 (32 kHz oscillating) CM4 : Sub-clock (XCIN –XCOUT) oscillating bit 0: Stopped 1: Oscillating CM5 : Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) 5 C “1 M5 C” “1 M6 ” “0 ” “0 ” CM5 “1” Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : T he all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3 : T imer and LCD operate in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode. 7 : T he example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock. Fig. 39 State transitions of system clock CM5 “1” ” “1 ” “0 39 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. A-D Converter The comparator is constructed linked to a capacitor. When the conversion speed is not enough, the conversion accuracy might be ruined by the disappearance of the charge. When A-D conversion is performed, set f(XIN) to at least 500 kHz. When the following operations are performed, the A-D conversion operation cannot be guaranteed. •When the CPU mode register is operated during A-D conversion operation, •When the A-D control register is operated during A-D conversion operation, •When STP or WIT instruction is executed during A-D conversion operation. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. LCD Control Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). When using the voltage multiplier, apply prescribed voltage to the VLIN pin in the state in which the LCD enable bit is “0”, and set the voltage multiplier enable bit to “1”. Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the TxD pin after transmission is completed. 40 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON USE Countermeasures Against Noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). q Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise XIN XOUT VSS N.G. Fig. 41 Wiring for clock I/O pins XIN XOUT VSS O.K. Noise Reset circuit VSS N.G. RESET VSS (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Reset circuit VSS RESET VSS VCC VCC O.K. Fig. 40 Wiring for the RESET pin ➁ Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. VSS VSS N.G. O.K. Fig. 42 Bypass capacitor across the VSS line and the VCC line 41 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful especially when range of voltage or/and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines (4) Analog input The analog input pin is connected to the capacitor of a comparator. Accordingly, sufficient accuracy may not be obtained by the charge/ discharge current at the time of A-D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A-D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A-D conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evaluation for each product of every after confirming product specification. (6) Wiring to VPP pin of One Time PROM version Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series. Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM version, the microcomputer operates correctly. q Reason The VPP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the built-in PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. Microcomputer Mutual inductance M Large current GND ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 44 Wiring for the VPP pin of One Time PROM About 5kΩ P40/VPP Source signal XIN XOUT VSS VSS N.G. Do not cross CNTR XIN XOUT VSS Fig. 43 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently 42 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form✽ 2. Mark Specification Form✽ 3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. ✽For the mask ROM confirmation and the mark specifications, refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.maec.co.jp/indexe.htm). ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter (PCA7447FP). Table 10 Programming adapter Package 144P6Q-A Name of Programming Adapter PCA7447FP The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 45 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 45 Programming and testing of One Time PROM version 43 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 11 Absolute maximum ratings Symbol VCC VI VI VI VI VI VO VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47 Input voltage C1, C2 Input voltage RESET, XIN, XCIN Input voltage VLIN Input voltage Output voltage VL1, VL2, VL3, VL4, VL5 P00–P07, P10–P17, P20–P27, P30–P33, P41–P47 Output voltage C1, C2, C3 Output voltage COM0–COM31, SEG0–SEG67 Output voltage XOUT, XCOUT Power dissipation Operating temperature Storage temperature Conditions All voltages are based on Vss. Output transistors are cut off. When voltage multiplier is not operated. VL1≤VL2≤VL3≤VL4≤VL5 Ratings –0.3 to 7.0 –0.3 to VCC+0.3 –0.3 to 7.0 –0.3 to VCC+0.3 –0.3 to 7.0 –0.3 to 7.0 –0.3 to VCC+0.3 –0.3 to 7.0 –0.3 to VL5+0.3 –0.3 to VCC+0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V V V V mW °C °C Ta = 25°C Table 12 Recommended operating conditions (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Limits Symbol Parameter Min. Typ. VCC Power source High-speed mode f(XIN) ≤ 8 MHz 4.0 5.0 voltage Middle-speed mode f(XIN) ≤ 8 MHz 2.7 5.0 Middle-speed mode (mask ROM version) f(XIN) ≤ 4 MHz 2.2 5.0 Middle-speed mode (One Time PROM version) f(XIN) ≤ 4 MHz 2.5 5.0 Low-speed mode (mask ROM version) 2.2 5.0 Low-speed mode (One Time PROM version) 2.5 5.0 VSS Power source voltage 0 VLIN Power source voltage VLIN VL5 Power source voltage VL5 VIA Analog input voltage AIN0–AIN7 VSS VIH “H” input voltage P00–P07, P10–P17, P45, P47 0.7VCC VIH “H” input voltage P20–P27, P30–P33, P40–P43, P44, P46 0.8VCC VIH “H” input voltage RESET 0.8VCC VIH “H” input voltage XIN 0.8VCC VIL “L” input voltage P00–P07, P10–P17, P45, P47 VSS VIL “L” input voltage P20–P27, P30–P33, P40–P43, P44, P46 VSS VIL “L” input voltage RESET VSS VIL “L” input voltage XIN VSS ΣIOH(peak) “H” total peak output current All ports (Note 1) ΣIOL(peak) “L” total peak output current All ports (Note 1) ΣIOH(avg) “H” total average output current All ports (Note 2) ΣIOL(avg) “L” total average output current All ports (Note 2) IOH(peak) “H” peak output current All ports (Note 3) IOL(peak) “L” peak output current All ports (Note 3) IOH(avg) “H” average output current All ports (Note 4) IOL(avg) “L” average output current All ports (Note 4) ROSC Oscillation resistor at selecting RC oscillation 5 8.2 Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. 2: The total average output current is the average value measured over 100 ms flowing through all the applicable ports. 3: The peak output current is the peak current flowing in each port. 4: The average output current is an average value measured over 100 ms. Max. 5.5 5.5 5.5 5.5 5.5 5.5 2.33 7.0 VCC VCC VCC VCC VCC 0.3VCC 0.2VCC 0.2VCC 0.2VCC –60.0 60.0 –30.0 30.0 –5.0 10.0 –2.5 5.0 10 Unit V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA kΩ 44 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 13 Recommended operating conditions (mask ROM version) (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol f(CNTR0) f(CNTR1) f(XIN) Parameter Timer X, timer Y input frequency (duty cycle 50%) Main clock input oscillation frequency (Note 1) High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (2.2 V ≤ VCC < 4.0 V) Middle-speed mode (2.7 V ≤ VCC ≤ 5.5 V) Middle-speed mode (2.2 V ≤ VCC < 2.7 V) 32.768 Conditions Min. Limits Typ. Max. f(XIN)/2 8.0 2.9✕VCC–3.6 8.0 8✕(VCC–1.7) 50 Unit Hz MHz MHz MHz MHz kHz f(XCIN) Sub-clock input oscillation frequency (Notes 1, 2) Notes 1: When the oscillation frequency has a duty cycle of 50 %. 2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Table 14 Recommended operating conditions (PROM version) (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol f(CNTR0) f(CNTR1) f(XIN) Parameter Timer X, timer Y input frequency (duty cycle 50%) Main clock input oscillation frequency (Note 1) High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (2.5 V ≤ VCC < 4.0 V) Middle-speed mode (2.7 V ≤ VCC ≤ 5.5 V) Middle-speed mode (2.5 V ≤ VCC < 2.7 V) 32.768 Conditions Min. Limits Typ. Max. f(XIN)/2 8.0 4✕VCC–8 8.0 20✕(VCC–2.3) 50 Unit Hz MHz MHz MHz MHz kHz f(XCIN) Sub-clock input oscillation frequency (Notes 1, 2) Notes 1: When the oscillation frequency has a duty cycle of 50 %. 2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 45 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 15 Electrical characteristics (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P30–P33 Test conditions IOH = –5.0 mA VCC = 5.0 V IOH = –1.5 mA VCC = 5.0 V IOH = –1.25 mA VCC = 2.2 V IOH = –5.0 mA VCC = 5.0 V IOH = –1.5 mA VCC = 5.0 V IOH = –1.25 mA VCC = 2.2 V IOL = 5.0 mA VCC = 5.0 V IOL = 1.5 mA VCC = 5.0 V IOL = 1.25 mA VCC = 2.2 V IOL = 5.0 mA VCC = 5.0 V IOL = 1.5 mA VCC = 5.0 V IOL = 1.25 mA VCC = 2.2 V Min. VCC–2.0 VCC–0.5 VCC–1.0 VCC–2.0 VCC–0.5 VCC–1.0 2.0 0.5 1.0 2.0 0.5 1.0 0.5 0.5 0.5 5.0 5.0 4.0 VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” VCC = 2.2 V, VI = VSS Pull-ups “on” VI = VSS VI = VSS –5.0 –60.0 –5.0 –120.0 –20.0 –240.0 –40.0 –5.0 –4.0 Limits Typ. Max. Unit V V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA VOH “H” output voltage P20–P27, P41–P47 VOL “L” output voltage P00–P07, P10–P17, P30–P33 VOL “L” output voltage P20–P27, P41–P47 VT+–VTVT+–VTVT+–VTIIH IIH IIH IIL Hysteresis INT0, INT1, ADT, CNTR0, CNTR1, P20–P27 Hysteresis SCLK, RxD Hysteresis RESET “H” input current All ports “H” input current RESET “H” input current XIN “L” input current All ports IIL IIL “L” input current RESET “L” input current XIN 46 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 16 Electrical characteristics (Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VRAM ICC Parameter RAM hold voltage Power source current Test conditions When clock is stopped High-speed mode, Vcc = 5.0 V f(XIN) = 8.0 MHz f(XCIN) = 32.768 kHz Middle-speed mode, Vcc = 5.0 V f(XIN) = 8.0 MHz f(XCIN) = 32.768 kHz Middle-speed mode, Vcc = 3.0 V f(XIN) = 8.0 MHz f(XCIN) = 32.768 kHz Low-speed mode, VCC = 3.0 V, f(XIN) = stopped f(XCIN) = 32.768 kHz High-/Middle-speed mode, VCC = 5.0 V, f(XIN) = 8.0 MHz (in WIT state) f(XCIN) = 32.768 kHz High-/Middle-speed mode, Vcc = 3.0 V f(XIN) = 8.0 MHz (in WIT state) f(XCIN) = 32.768 kHz Low-speed mode, VCC = 3.0 V, f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) All oscillation stopped Ta = 25 °C, Output transistors “off” (in STP state) All oscillation stopped Ta = 85 °C, Output transistors “off” (in STP state) Current increase at A-D converter operated, f(XIN) = 8.0 MHz VL5 = 6.0 V, Ta = 25 °C ROSC = 8.2 kΩ Min. 2.0 Limits Typ. 5.0 5.5 Max. 5.5 11.0 Unit V mA 3.0 6.0 mA 1.0 2.0 mA 20.0 40.0 µA 0.9 1.8 mA 0.3 0.6 mA 4.5 9.0 µA µA µA 0.1 1.0 10.0 IAD IL5 FROSC A-D converter current dissipation VL5 input current (Note) RC oscillation frequency 0.8 3 2.5 1.6 6 3.5 mA µA MHz 1.5 Note: When normal drivability (drivability selection bit 1 = “0”, drivability selection bit 2 = “0”) is selected. 47 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 17 A-D converter characteristics (Vcc = 2.2 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, f(XIN) ≤ 4 MHz, in middle-speed/high-speed mode) Symbol — — tconv IIA Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Analog port input current Test conditions Min. Limits Typ. Max. 10 ±4 ±6 34 5.0 Unit Bits LSB LSB µs µA VCC = 2.7–5.5 V VCC = 2.5–2.7 V (Ta = –10 to 50 °C) f(XIN) = 4 MHz (Note) 30.5 0.5 Note: When main clock is selected as system clock. Table 18 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input setup time Serial I/O input hold time Min. 2 125 45 40 250 105 105 80 80 800 370 370 220 100 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns (Note) (Note) (Note) Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Table 19 Timing requirements 2 (mask ROM version) (Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Vcc = 2.7 to 4.0 V Main clock input cycle time (XIN input) Vcc = 2.2 to 2.7 V Main clock input “H” pulse width Vcc = 2.7 to 4.0 V Main clock input “H” pulse width Vcc = 2.2 to 2.7 V Main clock input “L” pulse width Vcc = 2.7 to 4.0 V Main clock input “L” pulse width Vcc = 2.2 to 2.7 V CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input setup time Serial I/O input hold time Limits Min. 2 125 250 45 100 40 100 2/f(XIN) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Typ. Max. Unit µs ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. 48 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 20 Timing requirements 2 (One Time PROM version) (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol tw(RESET) tc(XIN) twH(XIN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK) twH(SCLK) twL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input “L” pulse width Main clock input cycle time (XIN input) Vcc = 2.7 to 4.0 V Main clock input cycle time (XIN input) Vcc = 2.5 to 2.7 V Main clock input “H” pulse width Vcc = 2.7 to 4.0 V Main clock input “H” pulse width Vcc = 2.5 to 2.7 V Main clock input “L” pulse width Vcc = 2.7 to 4.0 V Main clock input “L” pulse width Vcc = 2.5 to 2.7 V CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input “H” pulse width (Note) Serial I/O clock input “L” pulse width (Note) Serial I/O input setup time Serial I/O input hold time Limits Min. 2 125 250 45 100 40 100 2/f(XIN) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Typ. Max. Unit µs ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. 49 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 21 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(SCLK) twL(SCLK) td(SCLK-TxD) tV(SCLK-TxD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time CMOS output falling time Limits Min. tc(SCLK)/2–30 tc(SCLK)/2–30 (Note 1) (Note 1) –30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns 140 (Note 2) (Note 2) 10 10 Notes 1: When the P45/TxD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: The XOUT and XCOUT pins are excluded. Table 22 Switching characteristics 2 (Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(SCLK) twL(SCLK) td(SCLK-TxD) tV(SCLK-TxD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time CMOS output falling time Limits Min. tC(SCLK)/2–50 tC(SCLK)/2–50 (Note 1) (Note 1) –30 50 50 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns 350 (Note 2) (Note 2) 20 20 Notes 1: When the P45/TxD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: The XOUT and XCOUT pins are excluded. 1 kΩ Measurement output pin 100 pF Measurement output pin 100 pF CMOS output N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 001B16) is “1”. (N-channel opendrain output mode) Fig. 46 Circuit for measuring output switching characteristics 50 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 0.8VCC tWH(INT) tWL(INT) 0.2VCC INT0, INT1 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(SCLK) tf tWL(SCLK) 0.2VCC tsu(RXD-SCLK) tr 0.8VCC tWH(SCLK) SCLK th(SCLK-RXD) R XD td(SCLK-TXD) 0.8VCC 0.2VCC tv(SCLK-TXD) T XD Fig. 47 Timing diagram 51 MITSUBISHI MICROCOMPUTERS 38C8 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE 144P6Q-A MMP JEDEC Code – HD Weight(g) 1.23 Lead Material Cu Alloy Plastic 144pin 20✕20mm body LQFP MD e EIAJ Package Code LQFP144-P-2020-0.50 144 109 1 108 b2 D l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 36 73 37 72 A F L1 e x y b2 I2 MD ME y b x M L Detail F Lp Dimension in Millimeters Min Nom Max – – 1.7 0.125 0.2 0.05 – – 1.4 0.17 0.22 0.27 0.105 0.125 0.175 19.9 20.0 20.1 19.9 20.0 20.1 0.5 – – 21.8 22.0 22.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 0.1 – – 0° 8° – 0.225 – – 0.95 – – 20.4 – – – – 20.4 HE E A2 A1 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 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Specifications subject to change without notice. c A3 ME REVISION HISTORY Rev. 1.0 1.1 Date Page 01/18/01 03/21/01 2 3 4 14 17 26 33 34 37 37 40 41 42 42 1.2 10/15/01 3 15 16 41 42 43 43 43 43 43 46 46 47 3 14 17 18 28 28 28 40 All pages 1 3 4 6 8 9 10 11 14 First Edition 38C8 GROUP DATA SHEET Description Summary Figure 1 is partly revised. Figure 2 is partly revised. Pin name into Table 1 is partly revised. Pin name into Table 5 is partly revised. Explanations of “Interrupt Operation” are partly eliminated. Address of [Baud Rate Generator (BRG)] is revised. Figure name of Figure 31 is partly revised. Figure name of Figure 32 is partly revised. Explanations of “CLOCK GENERATING CIRCUIT” are partly revised. Explanations of “(1) Middle-speed Mode” of “Frequency Control” are partly revised. “At STP Instruction Release” is eliminated. Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised. Pin name of VIA into Table 11 is revised. Limits of VIH, VIL of P40, P43 are revised. Figure 2 is partly revised. Figure 11 is partly revised. Figure 12 is partly revised. Table 10 is added. Vcc parameter into Table 12 is partly eliminated. Unit of f(CNTR0), f(CNTR1) into Table 13 is revised. Limits of f(XIN) in high-speed mode (2.2 V ≤ Vcc < 4.0 V) into Table 13 is revised. f(XIN) in middle-speed mode (2.2 V ≤ Vcc < 2.7 V) into Table 13 is added. Unit of f(CNTR0), f(CNTR1) into Table 14 is revised. f(XIN) in middle-speed mode (2.5 V ≤ Vcc < 2.7 V) into Table 14 is added. Limits of tc(XIN), tWH(XIN), tWL(XIN) into Table 19 are added. Limits and unit of tc(CNTR) into Table 19 are revised. Table 20 is added. Figure 2 is partly revised. Table 5 is partly revised. Explanations of “sNotes on interrupts” are partly revised. Figure 14 is partly revised. Explanations of “[A-D Control Register (ADCON)]” are partly revised. Explanations of “Comparator and Control Circuit” are partly revised. Figure 25 is partly revised. Explanations of “A-D Converter” of “NOTES ON PROGRAMMING” are partly revised. Preliminary Notice in the header is eliminated. Interrupts of “[FEATURES]” are corrected. Figure 2 is partly revised. Pin COM0–COM15 in Table 1 is revised. Figure 4 is partly revised. Note in Figure 4 is partly revised. Explanations of bit 3 are added. Bit 4 name in Figure 7 is revised. Remarks in Figure 7 are partly revised. Table 5 is partly revised. 1.3 12/05/01 1.4 06/25/02 (1/2) REVISION HISTORY Rev. 1.4 Date Page 06/25/02 15 17 19 20 20 21 25 30 31 31 32 35 37 38 39 40 41, 42 44 46 47 15 38C8 GROUP DATA SHEET Description Summary (1) in Figure 11 is partly revised. Some source numbers in “[INTERRUPTS]” are corrected. Figure 15 is partly revised. The mode name (buzzer output mode) in Figure 16 is corrected.The mode name of bit 6 in Figure 17 is corrected. Explanations of “[(2) Buzzer Output Mode]” are partly added. f(XCIN) in Figure 22 is added. Explanations of “[LC2]” are partly revised. Explanations of “[Bias Control]” and “[Voltage Multiplier]” are partly revised. Table 8 is partly revised. Explanations of “[LCD Display RAM]” is partly revised. Note in Figure 33 is eliminated. Explanations of “[(1) Stop Mode]” is partly revised. Note in Figure 38 is partly revised. Bit 4 name in Figure 39 is revised. Explanations of “[A-D Converter]” is partly revised. “[NOTES ON USE]” is added. Table 12 is partly revised. Table 15 is partly revised. Table 16 is partly revised. (3), (4) and (5) in Figure 11 are partly revised. 1.5 10/23/02 (2/2)