MC-10105F1-821-FNA-M1-A

Datasheet R19DS0069EJ0107 Rev.1.07 Jul 30th, 2018 TPS-1 Single Chip Interface Solution for PROFINET IO Devices DESCRIPTION The TPS-1 is a single-chip PROFINET interface component integrating a CPU, a 2-port switch supporting latest PROFINET specifications, the Ethernet PHYs and peripheral modules to interface to the application layer of any application building a PROFINET IO device. The internal structure is designed to fulfill the requirements of the IRT protocol. The integrated components realize the complete interface functionality. TPS-1 rounds off the basic technology range of PROFINET specifically for compact devices, and complies with PROFINET specification 2.3. Detailed functions are described in the following user’s manual. Be sure to read this manual when you design your systems. TPS-1 User’s Manual: Hardware (R19UH0081ED) FEATURES • Applications  Industrial Drives  Compact and modular Remote I/Os • Product features  Integrated PROFINET IO CPU  Compliant with Conformance Class C  2 Ethernet ports, 100 Mbps, full duplex  2 integrated PHYs with an auto negotiation, auto crossover  Integrated IRT switch, 8 priority levels  Support RJ45 or fiber optic interfaces  Fiber optic diagnosis via I2C interface per port  IRT bridge-delay < 3 μs  Hardware support for PROFINET protocols including PTCP and LLDP  Versatile host interface for serial or parallel connection of external CPUs or local inputs/outputs  Small package(15 x 15 mm),1mm ball pitch • Application interface The TPS-1 provides 48 General Purpose I/O (GPIO) pins that you can individually configure according to your specific application requirements.  48 GPIO for digital I/Os  8- or 16-bit parallel host interface  Serial host interface (SPI Slave)  5GPIO for internal signals (e.g. LEDs)  Serial Flash interface The TPS-1 interfaces to an application CPU via the internal shared memory either through the fast SPI slave interface or through the 8- or 16-bit parallel port. ORDERING INFORMATION Part No. MC-10105F1-821-FNA-M1-A Application TPS-1 PROFINET IO Device Package FPBGA 196 Pins 15 x 15 mm The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with our sales representative for availability and additional information. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 1 of 40 TPS-1 INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM The block diagram shows the internal structure and main components of the TPS-1. The additional serial boot Flash component, the oscillator and the physical adaptation for the Ethernet interfaces are not listed. JTAG / Debug RAM ARM Core BootROM Host Interface Parallel Interface 8 / 16 Bit SPI Slave PROFINET IO Core IRT Switch Time Sync PHY 1 LAN signals (I2C-bus, link and Activity), Test Sync MDI Link1, Act1, Link2, Act2 Test Sync R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 48 GPIO I/O Interface Protocol Handling Host Interface / Parallel - Serial MUX PROFINET IO CPU Shared Memory Serial Flash (SPI Slave) Status Info LEDs Control Signals Clock Signals T1 to T6 PHY 2 MDI Clock Unit Power Supply Switching Regulator 25 MHz 3.3 V 1.5 V 1.0 V page 2 of 40 TPS-1 PIN IDENTIFICATION PIN IDENTIFICATION SPI Master for Boot Flash ROM CS_FLASH_OUT : FW Flash: Receive Data – MISO SPI3_STXD_OUT : FW Flash: Send Data – MOSI : FO Transmitter enable (active high) : FW Flash: Chip Select SPI3_SCLK_OUT : FW Flash: CLOCK SPI3_SRXD_IN P(2:1)_FX_EN_OUT Oscillator XCLK1 :Connection external oscillator (1) In, 25 MHz XCLK2 :Connection external oscillator (2) Out, 25 MHz JTAG – Interface Synchronisation signals TM(1:0) : Test Input (1:0) TRSTN : Test Reset TMS : Test Mode Select TDO : Test Data Output LED signals device status PROFINET IO TCK : Test Clock LED_BF_OUT : Control LED „Bus Failure“ TDI : Test Data Input LED_SF_OUT : Control LED „System Fail“ TEST_SYNC : Clock signal for certification T(6:1) : Clock signals(6:1) (isochronous mode, IRT) LED_READY_OUT : Control LED „Device Ready“ Reset / Test LED_MT_OUT RESETN : TPS-1 Reset (Global Reset) ATP : Test pin for production test (n.c.) EXTRES : External reference resistor TMC(2:1) : Test Mode Control(2:1) (production test) : Control LED „Maintenance“ PHY Port 1 and 2 I2C_(2:1)_D_INOUT SCLK_(2:1)_INOUT LINK_PHY(2:1) : FO I2C-Bus “Data” 2 :FO I C-Bus “Clock” : Ethernet LINK indication (up or down) ACT_PHY(2:1) : Activity Ethernet P(2:1)_TX_P : Ethernet Transmit Data (positive) P(2:1)_TX_N : Ethernet Transmit Data (negative) P(2:1)_RX_P : Ethernet Receive Data (positive) P(2:1)_RX_N : Ethernet Receive Data (negative) P(2:1)_SD_P : FO Signal Detect (positive) P(2:1)_SD_N : FO Signal Detect (negative) P(2:1)_RD_P : FO Receive Data (positive) P(2:1)_RD_N : FO Receive Data (negative) P(2:1)_TD_OUT_P : FO Transmit Data (negative) P(2:1)_TD_OUT_N : FO Transmit Data (positive) R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 TEST_(2:1)_IN : Test Pin (2:1) for HW test of TPS-1 TESTDOUT(7:5) : Test Data Output (7:5) (High Speed Signals for PHY) Host interface WD_IN : Watchdog input (from the Host) WD_OUT : Watchdog output (to the Host) INT_OUT : Interrupt output (to the Host) Boot interface (serial) UART6_TX : Boot UART “Transmit Data“ UART6_RX : Boot UART “Receive Data“ BOOT_1 : Forced Boot page 3 of 40 TPS-1 PIN IDENTIFICATION Test signals for switching regulator Configurable GPIOs TEST(3:1) GPIO_(47:0) : Test Pin switching regulator (in combination with another test pins) :GPIO pins Alternate use of the GPIOs PHY supply voltages VDD33ESD : Analog test supply, 3.3 V VDDQ_PECL_B(2:1) : PECL buffer power supply 3.3 V (Port(2:1)) P(2:1)VDDARXTX : Analog Rx/Tx power supply 1.5 V – Port (2:1) LBU_WR_EN_IN : Write Enable LBU_READ_EN_IN : Read Enable LBU_CS_IN : Chip Select LBU_BE_(2:1)_IN : Byte Selection (1:low,2:high) LBU_READY_OUT : Ready Signal TPS-1 VDDACB : Analog central power supply 3.3 V LBU_DATA(15:0) : Data Bits VSSAPLLCB : Analog central GND LBU_A(13:0)_IN : Address Bits VDDAPLL : Analog central power supply 1.5 V LBU_SEG(1:0)_IN : Segment select (2:1) HOST_RESET_IN : Reset Host SPI Interface Pins for core PLL power supply HOST_SFRN_IN : Start new SPI Transfer PLL_AGND : PLL analog GND (core PLL) HOST_SRXD_IN : SPI receive data PLL_AVDD : PLL analog 1.0 V (core PLL) HOST_SCLK_IN : SPI Clock HOST_STXD_OUT : SPI transmit data Pins for switching regulator HOST_SHDR_OUT : Header recognized BVDD LOCAL_SCLK_OUT : SPI Clock LOCAL_SFRM_OUT : SPI chip select LOCAL_SRXD_IN : SPI receive data LOCAL_STXD_OUT : SPI transmit data BGND : Supply voltage for the switching regulator (3.3 V supply for the switching transistor) : GND for switching regulator (please place bypass capacitor between analog power supply and GND). AVDD_REG : Analog VDD for regulator (3.3 V supply),smoothed voltage to feed the internal POR. AGND_REG : Analog GND switching regulator LX : 1.5 V output of the internal switching regulator FB : Feedback (regulator) R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 4 of 40 TPS-1 PIN CONFIGURATION PIN CONFIGURATION 196-PIN PLASTIC BGA(15x15) R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 5 of 40 TPS-1 Pin PIN CONFIGURATION Designation Pin Designation Pin Designation Pin Designation A1 GND D8 TESTDOUT5 H1 LX L8 TESTDOUT7 A2 A3 VDD15 GPIO_7 D9 D10 TESTDOUT6 ACT_PHY1 H2 H3 VDD33 TEST1 L9 L10 PLL_AGND PLL_AVDD A4 A5 GPIO_4 P1_FX_EN_OUT D11 D12 T6 AGND H4 H5 GPIO_26 GPIO_25 L11 L12 SCLK_2_INOUT AGND A6 A7 P1_TD_OUT_N VDD15 D13 D14 AGND P1VDDARXT X H6 H7 GND GND L13 L14 AGND P2VDDARXTX A8 A9 P1_SD_N P1_RD_N E1 E2 TEST3 GPIO_16 H8 H9 GND GND M1 M2 GPIO_36 GPIO_35 A10 A11 ACT_PHY2 WD_IN E3 E4 GPIO_17 GPIO_18 H10 H11 GND T2 M3 M4 GPIO_37 GPIO_42 A12 A13 RESETN VDD15 E5 E6 GPIO_19 VDD10 H12 H13 ATP EXTRES M5 M6 GPIO_45 GPIO_46 A14 B1 GND VDD33 E7 E8 VDD10 VDD10 H14 J1 VDDACB BVDD M7 M8 GPIO_47 VDDQ_PECL_B2 B2 B3 GPIO_9 GPIO_8 E9 E10 VDD10 TMC1 J2 J3 GND GPIO_28 M9 M10 VDD15 GND B4 B5 GPIO_5 GPIO_1 E11 E12 T5 VDD33ESD J4 J5 GPIO_27 TCK M11 M12 I2C_2_D_INOUT CS_FLASH_OUT B6 B7 P1_TD_OUT_P GND E13 E14 P1_RX_P P1_RX_N J6 J7 GND GND M13 M14 SPI3_SRXD_IN SPI3_STXD_OUT B8 B9 P1_SD_P P1_RD_P F1 F2 FB AVDD_REG J8 J9 GND GND N1 N2 VDD33 GPIO_40 B10 B11 LED_MT_OUT LED_SF_OUT F3 F4 GPIO_22 GPIO_21 J10 J11 TM1 T1 N3 N4 GPIO_39 GPIO_41 B12 B13 WD_OUT LED_BF_OUT F5 F6 GPIO_20 VDD33 J12 J13 GND P2_TX_P N5 N6 GPIO_44 P2_TD_OUT_P B14 C1 VDD33 GPIO_12 F7 F8 GND GND J14 K1 P2_TX_N VDD15 N7 N8 GND P2_SD_P C2 C3 GPIO_13 GPIO_6 F9 F10 GND VDD33 K2 K3 GPIO_31 GPIO_29 N9 N10 P2_RD_P GND C4 C5 GPIO_3 GPIO_2 F11 F12 T4 VDD15 K4 K5 GPIO_30 TRSTN N11 N12 XCLK1 TEST_SYNC C6 C7 SCLK_1_INOUT VDD33 F13 F14 P1_TX_P P1_TX_N K6 K7 VDD10 VDD10 N13 N14 SPI3_SCLK_OUT VDD33 C8 C9 VDDQ_PECL_B1 I2C_1_D_INOUT G1 G2 BGND AGND_REG K8 K9 VDD10 VDD10 P1 P2 GND VDD15 C10 C11 LED_READY_OUT LINK_PHY2 G3 G4 TEST2 GPIO_24 K10 K11 TMC2 INT_OUT P3 P4 GPIO_38 GPIO_43 C12 C13 LINK_PHY1 UART6_RX G5 G6 GPIO_23 GND K12 K13 VDD15 P2_RX_P P5 P6 P2_FX_EN_OUT P2_TD_OUT_N C14 D1 UART6_TX GPIO_15 G7 G8 GND GND K14 L1 P2_RX_N GPIO_34 P7 P8 VDD33 P2_SD_N D2 D3 GPIO_14 GPIO_10 G9 G10 GND GND L2 L3 GPIO_32 GPIO_33 P9 P10 P2_RD_N VDD33 D4 D5 GPIO_11 GPIO_0 G11 G12 T3 GND L4 L5 TM0 TDI P11 P12 XCLK2 BOOT_1 D6 D7 TEST_1_IN TEST_2_IN G13 G14 VSSAPLLCB VDDAPLL L6 L7 TMS TDO P13 P14 VDD15 GND R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 6 of 40 TPS-1 Table of Contents Table of Contents 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 3. 4. Pin Functions .................................................................................................................... 10 List of Pin Functions ......................................................................................................... 10 1.1.1. Host Interface –Parallel Interface ........................................................................ 10 1.1.2. Host Interface –SPI slave Interface ...................................................................... 10 1.1.3. PROFINET IO Switch ......................................................................................... 11 1.1.4. Integrated peripherals........................................................................................... 12 Pin Characteristics ............................................................................................................ 17 Electrical Specifications .................................................................................................... 21 Absolute Maximum Ratings ............................................................................................. 21 Operating Conditions ........................................................................................................ 22 Thermal Characteristics .................................................................................................... 23 AC Characteristics ............................................................................................................ 24 2.4.1. Clock Timing ....................................................................................................... 24 2.4.2. I/O timing specification ....................................................................................... 25 2.4.2.1. JTAG interface timing ......................................................................................... 26 2.4.2.2. Parallel host interface timing diagrams ............................................................... 27 2.4.2.2.1. Host read from TPS-1 with separate read/write line ......................................... 27 2.4.2.2.2. Host write to TPS-1 with separate read/write line............................................. 28 2.4.2.2.3. Host read from TPS-1 with common read/write line ........................................ 29 2.4.2.2.4. Host write to TPS-1 with common read/write line ............................................ 30 2.4.2.3 SPI Slave Timing ................................................................................................ 31 2.4.3. I2C-Bus timing definition ................................................................................... 32 2.4.3.1. PHY DC Specifications(100 BASE-TX) ............................................................ 33 2.4.3.2. PHY AC Specifications (100BASE-TX) ............................................................ 34 2.4.4. Power-up sequence .............................................................................................. 35 2.4.5. Reset timing ......................................................................................................... 36 Package Drawing .............................................................................................................. 37 Recommended Soldering Conditions ................................................................................ 38 R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 7 of 40 TPS-1 List of Figures List of Figures Figure 2-1: Figure 2-2: Figure 2-3: Figure 2-4: Figure 2-5: Figure 2-6: Figure 2-7: Figure 2-8: Figure 2-9: Figure 2-10: Figure 2-11: Figure 2-12: Figure 2-13: Figure 3-1: Clock Waveforms ................................................................................................... 24 Input setup and hold waveforms ............................................................................ 25 Output delay waveforms ........................................................................................ 25 Host read with separate read/write line .................................................................. 27 Host write with separate read/write line ................................................................. 28 Host read with common read/write line ................................................................. 29 Host write with common read/write line ................................................................ 30 SPI Slave Timing.................................................................................................... 30 I2C-Bus timing definition ...................................................................................... 31 PHY DC Specification ........................................................................................... 32 PHY AC Specification ........................................................................................... 33 Power-Up Sequence Timing Diagram.................................................................... 34 Reset Timing Diagram ........................................................................................... 35 196-ball FPBGA Package Drawing........................................................................ 36 R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 8 of 40 TPS-1 List of Tables List of Tables Table 1-1: Table 1-2: Table1-3: Table 1-4: Table 1-5: Table1-6: Table 1-7: Table 1-8: Table 1-9: Table 1-10: Table 1-11: Table 1-12: Table 1-13: Table 1-14: Table 1-15: Table 1-16: Table 2-1: Table 2-2: Table 2-3: Table 2-4: Table 2-5: Table 2-6: Table 2-7: Table 2-8: Table 2-9: Table 2-10: Table 2-11: Table 2-12: Table 2-13: Table 2-14: Table 2-15: Table 2-16: Table 2-17: Table 2-18: Table 4-1: Parallel host interface ............................................................................................. 10 SPI host interface ................................................................................................... 10 Status signals of the ETHERNET interface (Port 1/Port2) .................................... 11 Signal lines 100Base-TX interface (Port 1/Port2) .................................................. 11 Signal lines 100Base-FX interface (Port 1/Port2) .................................................. 11 Additional TPS-1 pins ............................................................................................ 11 Boot Flash SPI Master Interface ............................................................................ 12 General Purpose I/O pin functions ......................................................................... 13 Status LEDs PROFINET IO................................................................................... 14 I2C interface lines .................................................................................................. 14 Boot UART lines .................................................................................................... 14 Interrupt signals ..................................................................................................... 14 Watchdog signals ................................................................................................... 15 JTAG interface pin definition................................................................................. 15 Supply Voltage Circuitry ....................................................................................... 16 Signal characteristics .............................................................................................. 17 Absolute Maximum Ratings ................................................................................... 21 Recommended Operating Conditions (supply voltages) ........................................ 22 Recommended Operating Conditions (input / output level) ................................... 22 TPS-1 power consumption overview ..................................................................... 22 Thermal Characteristics of the Package ................................................................. 23 Clock AC Characteristics (using a crystal) ............................................................ 24 Clock AC Characteristics (using an external oscillator)......................................... 23 Timing JTAG interface .......................................................................................... 26 Host read with separate read/write line .................................................................. 27 Host write with separate read/write line ................................................................. 28 Host read with common read/write line ................................................................. 29 Host write with common read/write line ................................................................ 30 SPI Slave Timing ................................................................................................... 30 Characteristics of the SCL and SDA lines ............................................................. 31 PHY DC Specification ........................................................................................... 32 PHY AC Timing .................................................................................................... 33 Signals for Power-Up ............................................................................................. 34 Signals for Reset Timing ........................................................................................ 35 Recommended soldering conditions....................................................................... 37 R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 9 of 40 TPS-1 1. Pin Functions 1. 1.1. Pin Functions List of Pin Functions 1.1.1. Host Interface –Parallel Interface Table 1-1: Parallel host interface Pin Name LBU_WR_EN_IN I/O I Function Write Control Remarks Active low (Intel mode) Alternate Function GPIO_0 0:write; 1:read (Motorola mode) LBU_READ_EN_IN I Read Control LBU_CS_IN I Chip Select GPIO_2 LBU_BE_1_IN LBU_BE_2_IN I I Byte Select 1 Byte Select 2 GPIO_3 GPIO_4 LBU_READY_OUT LBU_DATA(15:0) O I/O Ready Signal data line 0 – 15 LBU_A(13:0)_IN LBU_SEG0_IN I I Address lines 0 - 13 Low Bit of the segment select LBU_SEG1_IN I High Bit of the segment select 1.1.2. Active low (Intel mode) No function (Motorola mode) Polarity configurable GPIO_1 GPIO_5 GPIO_(21:6) Page selection GPIO_(35:22) GPIO_36 Page selection GPIO_37 Host Interface –SPI slave Interface Table 1-2: SPI host interface Pin Name I/O Function Remarks Alternate Function HOST_RESET_IN I Serial Reset The SPI Slave interface can be reset by using this signal. (signal is active high) GPIO_38 HOST_SFRN_IN I Serial Frame GPIO_39 HOST_SRXD_IN I Serial Data Input The start of a new SPI transfer is signaled. MOSI (Master out Slave in) HOST_SCLK_IN I Serial Clock Input GPIO_41 HOST_STXD_OUT O Serial Data Output Serial Clock driven by the SPI Master MISO (Master in Slave out) HOST_SHDR_OUT O Serial Header Information header information available GPIO_43 R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 GPIO_40 GPIO_42 page 10 of 40 TPS-1 1.1.3. 1. Pin Functions PROFINET IO Switch Table 1-3: Status signals of the ETHERNET interface (Port 1/Port2) Pin Name I/O Function Remarks LINK_PHY(2:1) O LINK ETHERNET Active high ACT_PHY(2:1) O Activity ETHERNET Active high Table 1-4: Signal lines 100Base-TX interface (Port 1/Port2) Pin Name I/O Function Remarks P(2:1)_TX_P O Transmit data+ e.g. RJ45 P(2:1)_TX_N P(2:1)_RX_P O I Transmit dataReceive data+ e.g. RJ45 e.g. RJ45 P(2:1)_RX_N I Receive data- e.g. RJ45 Table 1-5: Signal lines 100Base-FX interface (Port 1/Port2) Pin Name I/O Function Remarks I2C_(2:1)_D_INOUT I/O I2 C SCLK_(2:1)_INOUT P(2:1)_SD_P O I I2C clock line Signal detect (differential, +) e.g. SC-RJ e.g. SC-RJ P(2:1)_SD_N P(2:1)_RD_N I I Signal detect (differential, -) Receive signal (differential, -) e.g. SC-RJ e.g. SC-RJ P(2:1)_RD_P P(2:1)_FX_EN_OUT I O Receive signal (differential, +) Transmitter enable (transceiver output) e.g. SC-RJ e.g. SC-RJ P(2:1)_TD_OUT_P P(2:1)_TD_OUT_N O O Transmit signal (differential, +) Transmit signal (differential, -) e.g. SC-RJ e.g. SC-RJ data line e.g. SC-RJ Table 1-6: Additional TPS-1 pins Pin Name I/O Function Remarks ATP AI/O (analog I/O) Analog Test: This signal is used for the manufacturing process. Pin is left open. EXTRES AI/O (analog I/O) Reference resistor: Connect via a resistor 12.4 kΩ / 1% to GND. This external resistor should be placed as close as possible to the chip. It must be terminated to analog GND. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 11 of 40 TPS-1 1.1.4. 1. Pin Functions Integrated peripherals Table 1-7: Boot Flash SPI Master Interface Pin Name I/O Function CS_FLASH_OUT O SPI-Master-Interface Firmware Flash: Chip Select (TPS-1) – active low SPI3_SCLK_OUT O SPI-Master-Interface Firmware Flash: CLOCK (TPS-1) SPI3_SRXD_IN I SPI3_STXD_OUT O SPI-Master-Interface Firmware Flash: Receive Data (TPS-1) – MISO SPI- Master-Interface Firmware Flash: Send Data (TPS-1) – MOSI R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 12 of 40 TPS-1 1. Pin Functions Table 1-8: General Purpose I/O pin functions Pin Name I/O Function Alternate Function GPIO_0 I/O General purpose digital I/O signal / Write Enable LBU_WR_EN_IN GPIO_1 GPIO_2 I/O I/O General purpose digital I/O signal / Read Enable General purpose digital I/O signal / Chip Select LBU_READ_EN_IN LBU_CS_IN GPIO_3 GPIO_4 I/O I/O General purpose digital I/O signal / Byte Selection (low) General purpose digital I/O signal / Byte Selection (high) LBU_BE_1_IN LBU_BE_2_IN GPIO_5 GPIO_6 I/O I/O General purpose digital I/O signal / Ready Signal TPS-1 Note2 General purpose digital I/O signal / Data Bit LBU_READY_OUT LBU_DATA0 GPIO_7 GPIO_8 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA1 LBU_DATA2 GPIO_9 GPIO_10 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA3 LBU_DATA4 GPIO_11 GPIO_12 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA5 LBU_DATA6 GPIO_13 GPIO_14 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA7 LBU_DATA8 GPIO_15 GPIO_16 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA9 LBU_DATA10 GPIO_17 GPIO_18 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA11 LBU_DATA12 GPIO_19 GPIO_20 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Data Bit LBU_DATA13 LBU_DATA14 GPIO_21 GPIO_22 I/O I/O General purpose digital I/O signal / Data Bit General purpose digital I/O signal / Address Bit LBU_DATA15 LBU_A0_IN GPIO_23 GPIO_24 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Address Bit LBU_A1_IN LBU_A2_IN GPIO_25 GPIO_26 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Address Bit LBU_A3_IN LBU_A4_IN GPIO_27 GPIO_28 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Address Bit LBU_A5_IN LBU_A6_IN GPIO_29 GPIO_30 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Address Bit LBU_A7_IN LBU_A8_IN GPIO_31 GPIO_32 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Address Bit LBU_A9_IN LBU_A10_IN GPIO_33 GPIO_34 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Address Bit LBU_A11_IN LBU_A12_IN GPIO_35 GPIO_36 I/O I/O General purpose digital I/O signal / Address Bit General purpose digital I/O signal / Segment select 1 LBU_A13_IN LBU_SEG0_IN GPIO_37 GPIO_38 I/O I/O General purpose digital I/O signal / Segment select 2 General purpose digital I/O signal / Reset Host SPI Interface LBU_SEG1_IN HOST_RESET_IN GPIO_39 GPIO_40 I/O I/O General purpose digital I/O signal / Start new SPI Transfer General purpose digital I/O signal / SPI receive data HOST_SFRN_IN HOST_SRXD_IN GPIO_41 GPIO_42 I/O I/O General purpose digital I/O signal / SPI Clock General purpose digital I/O signal / SPI transmit data HOST_SCLK_IN HOST_STXD_OUT GPIO_43 GPIO_44 I/O I/O General purpose digital I/O signal / Header recognized General purpose digital I/O signal / SPI Clock HOST_SHDR_OUT LOCAL_SCLK_OUT GPIO_45 GPIO_46 I/O I/O General purpose digital I/O signal / Start new SPI transfer General purpose digital I/O signal / SPI receive data LOCAL_SFRM_OUT LOCAL_SRXD_IN GPIO_47 I/O General purpose digital I/O signal / SPI transmit data LOCAL_STXD_OUT Notes: 1. You can only use one interface exclusively. It is not allowed to use e.g. the parallel and serial host interface at the same time. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 13 of 40 TPS-1 1. Pin Functions Notes: 2 The signal “LBU_READY_OUT” is designed to connect only to a single microcontroller. If you want to connect additional devices, you must add circuitry to realize the high-impedance state. 3. If the CPU does not have a READY input for connection to LBU_READY_OUT, customers can choose a wait time of 260 ns during each transfer cycle. 4. As soon as the signal HOST_SFRN_IN is set to “1”, no more data is received on the RxD interface. Setting the signal is not allowed during an ongoing transfer. Table 1-9: Status LEDs PROFINET IO Pin Name(LED) LED_BF_OUT LED_SF_OUT LED_MT_OUT LED_READY_OUT Color red red yellow green I/O State O Function Bus Communication (active low): ON Flashing No link status available. Link status ok; no communication link to a PROFINET IOController. OFF The PROFINET IO-Controller has an active communication link to this PROFINET IO-Device. O ON System Fail (active low): PROFINET diagnostic exists. OFF No PROFINET diagnostic. O Maintenance required / demanded (active low) ON PROFINET diagnostic alarm with maintenance state required or demanded. OFF No diagnostic alarm with maintenance state required or demanded pending. O OFF Flashing ON Device Ready (active low): TPS-1 has not started correctly. TPS-1 is waiting for the synchronization of the Host CPU (firmware start is complete). TPS-1 has started correctly. Table 1-10: I2C interface lines Pin Name I2C_(2:1)_D_INOUT SCLK_(2:1)_INOUT I/O I/O O Function Fiber Optic Port(2:1) I2C-Bus “Data” Fiber Optic Port(2:1) I2C-Bus “Clock” Table 1-11: Boot UART lines Pin Name I/O Function UART6_TX UART6_RX O I Boot UART “Transmit data” Boot UART “Receive data” BOOT_1 I Forced Boot Value 0x0 0x1 R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Function BROM: Boot from Boot Flash is enabled (normal operating mode). UART: Boot via UART is enabled. page 14 of 40 TPS-1 1. Pin Functions Table 1-12: Interrupt signals Pin Name INT_OUT I/O Function Interrupt output (to the Host) O Remark Interrupt to host can be generated by a configurable set of internal TPS-1 events (active high). Table 1-13: Watchdog signals Pin Name I/O Function WD_IN I Watchdog Input (from the Host) WD_OUT O Watchdog Output (to the Host) Remark This signal triggers the TPS-1 watchdog that monitors the Host CPU. A rising edge of this signal restarts the watchdog counter (active high). This signal is set when a watchdog trigger of the TPS-1 occurs (active low). Table 1-14: JTAG interface pin definition Pin Name I/O Function Remark TRSTN I Test Reset JTAG Reset. Input: Reset signal of the target port. External pull-down (4.7KΩ to GND) TMS I Test Mode Select TDO O Test Data Output JTAG interface is activated from the debug unit. pull-up (4.7KΩ to VDD) can be left open TCK I Test Clock JTAG clock signal to the TPS-1. It is recommended that this pin is set to a defined state on the target board. External pull-up (4.7KΩ to VDD) TDI I Test Data Input External pull-up(4.7KΩ to VDD) R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 15 of 40 TPS-1 1. Pin Functions Table 1-15: Supply Voltage Circuitry Pin Name Function P(2:1)VDDARXTX Analog port RX/TX power supply, 1.5 V (PHY port 2:1) VDDAPLL VDDACB Analog central power supply, 1.5 V (PHY) Analog central power supply, 3.3 V (PHY) VDD33ESD VSSAPLLCB Analog test power supply, 3.3 V (PHY) Analog central GND (PHY) VDDQ_PECL_B(2:1) PLL_AGND PECL buffer power supply 3.3 V (port 1 and port 2) Analog Ground for the internal CPU clock generation PLL_AVDD GND Power supply for the internal CPU clock generation (1.0V) Digital GND AGND VDD33 Analog Ground for PHYs Voltage Supply 3.3 V (external) VDD15 Voltage Supply 1.5 V from Switching Regulator or external Voltage Supply 1.0 V (external) VDD10 AGND_REG AVDD_REG Analog Ground for switching regulator. Supply voltage for regulator(3.3V supply), smoothed voltage to feed the internal POR. BGND GND for switching regulator BVDD Supply voltage for the switching regulator (3.3V) R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Supply Voltage Generation Must be generated from VDD15 via a filter. Must be generated from VDD33 via a filter. Must be generated from GND Core/IO via a filter or connected to GND Core/IO at the far end from TPS-1. Please place bypass capacitor between analog power supply and GND For the switching transistor page 16 of 40 TPS-1 1.2. 1. Pin Functions Pin Characteristics Table 1-16: Signal characteristics Pin Name I/O Output type Input type Pull up / down internal Pull up / down external Drive capability Capacity load (pF) IOH IOL SPI-Master for Flash ROM CS_FLASH_OUT SPI3_SCLK_OUT O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA SPI3_SRXD_IN SPI3_STXD_OUT I O Schmitt - 3.3V CMOS 3.3V CMOS - 30 6 mA 6 mA Synchronization signals TEST_SYNC O - 3.3V CMOS - 30 6 mA 6 mA T1 T2 O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA T3 T4 O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA T5 T6 O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA LED signals for PROFINET IO status LED_BF_OUT O - 3.3V CMOS - 30 6 mA 6 mA LED_SF_OUT LED_READY_OUT O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA LED_MT_OUT PHY Port 1 O - 3.3V CMOS 30 6 mA 6 mA I2C_1_D_INOUT SCLK_1_INOUT I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA LINK_PHY1 ACT_PHY1 O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA P1_TX_P P1_TX_N O O - Analog Analog - - - - P1_RX_P P1_RX_N I I - Analog Analog - - - - P1_SD_P P1_SD_N I I PECL PECL - - - - - P1_RD_P P1_RD_N I I PECL PECL - - - - - P1_TD_OUT_P P1_TD_OUT_N O O - 3.3V CMOS 3.3V CMOS - - 12 mA 12 mA 12 mA 12 mA P1_FX_EN_OUT PHY Port 2 O - 3.3V CMOS - 30 12 mA 12 mA I2C_2_D_INOUT SCLK_2_INOUT I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA LINK_PHY2 ACT_PHY2 O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA P2_TX_P P2_TX_N O O - Analog Analog - - - - P2_RX_P P2_RX_N I I - Analog Analog - - - - P2_SD_P P2_SD_N I I PECL PECL - - - - - P2_RD_P P2_RD_N I I PECL PECL - - - - - P2_TD_OUT_P O - 3.3V CMOS - - 12 mA 12 mA R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 17 of 40 TPS-1 Pin Name 1. Pin Functions I/O Output type Input type Pull up / down Pull up / down internal external Drive capability Capacity load (pF) IOH IOL P2_TD_OUT_N O - 3.3V CMOS - - 12 mA 12 mA P2_FX_EN_OUT Oscillator O - 3.3V CMOS - 30 12 mA 12 mA XCLK1 XCLK2 I O Osc. in - - 25 6 mA 6 mA JTAG – Interface TM0 I Schmitt Pull-down 1 kΩ - - - TM1 I Schmitt - - - - TRSTN I Schmitt 3.3V CMOS - Pull-down 1 kΩ Pull-down 4.7 kΩ - - - TMS I Schmitt 3.3V CMOS - - - - TDO O - 3.3V CMOS - Pull-up 4.7 kΩ - 30 6 mA 6 mA TCK I Schmitt 3.3V CMOS - - - - TDI I Schmitt 3.3V CMOS Pull-up 4.7 kΩ Pull-up 4.7 kΩ - - - Reset / Test RESETN I Schmitt 3.3V CMOS - - - - ATP EXTRES IO IO Analog - - - - - TMC1 I 3.3V CMOS pull-down - - - - - - - - - - - - Osc. Out Pull-up 50 kΩ (50 kΩ) TMC2 I TEST_1_IN I 3.3V CMOS pull-down (l 50 kΩ) Schmitt 3.3V CMOS pull-down (50 kΩ) TEST_2_IN I Schmitt 3.3V CMOS pull-down ( 50 kΩ) TESTDOUT5 O 3.3V CMOS - - 12 mA 12 mA TESTDOUT6 TESTDOUT7 O O 3.3V CMOS 3.3V CMOS - - 12 mA 12 mA 12 mA 12 mA Host interface WD_IN I Schmitt 3.3V CMOS - - - - WD_OUT INT_OUT O O - 3.3V CMOS 3.3V CMOS - 30 30 6 mA 6 mA 6 mA 6 mA Boot interface (serial) UART6_TX O - 3.3V CMOS - 30 6 mA 6 mA UART6_RX BOOT_1 Schmitt Schmitt 3.3V CMOS - pull-down - 6 mA - 6 mA - I I (50 kΩ) Test signals – switching regulator TEST1 TEST2 I I - - - see note 1 see note 1 - - - TEST3 Power Supplies I - - - see note 1 - - - GND VDD33 - - - - - - - R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 18 of 40 TPS-1 Pin Name 1. Pin Functions I/O Output type Input type Pull up / down Pull up / down internal external Drive capability Capacity load (pF) IOH IOL VDD15 - - - - - - - VDD10 VDD33ESD - - - - - - - VDDAPLL VDDACB - - - - - - - VDDQ_PECL_B1 VDDQ_PECL_B2 I I - - - - - - P1VDDARXTX P2VDDARXTX I I - - - - - - VSSAPLLCB LX O - - - - - - FB (1.5V analog) AVDD_REG I I - - - - - - BGND AGND_REG - - - - - - - BVDD PLL_AGND I - - - - - - PLL_AVDD GPIOs I - - - - - - GPIO_00 GPIO_01 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6mA 6mA GPIO_02 GPIO_03 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6mA 6mA GPIO_04 GPIO_05 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 50 6 mA 9 mA 6mA 9 mA GPIO_06 GPIO_07 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_08 GPIO_09 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_10 GPIO_11 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_12 GPIO_13 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_14 GPIO_15 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_16 GPIO_17 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_18 GPIO_19 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_20 GPIO_21 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 50 50 9 mA 9 mA 9 mA 9 mA GPIO_22 GPIO_23 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_24 GPIO_25 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_26 GPIO_27 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_28 GPIO_29 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 19 of 40 TPS-1 Pin Name 1. Pin Functions I/O Input type Output type Pull up / down Pull up / down internal external Capacity load (pF) Drive capability IOH IOL GPIO_30 I/O Schmitt 3.3V CMOS - see note 2 30 6 mA 6 mA GPIO_31 GPIO_32 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_33 GPIO_34 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_35 GPIO_36 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_37 GPIO_38 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_39 GPIO_40 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_41 GPIO_42 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_43 GPIO_44 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_45 GPIO_46 I/O I/O Schmitt Schmitt 3.3V CMOS 3.3V CMOS - see note 2 see note 2 30 30 6 mA 6 mA 6 mA 6 mA GPIO_47 I/O Schmitt 3.3V CMOS - see note 2 30 6 mA 6 mA Note 1: These pins (TEST(3:1)) must not be left open. For the required connection please consult the TPS-1 User Manual. Note 2: The GPIO pins GPIO_00 to GPIO_47 can be configured as diagnosis input lines (local IO mode). The GPIO pins are configured into groups of 8 bit. Unused diagnosis inputs must have a pull-down or pull-up resistor (depending on customer’s design). A missing termination can cause undefined diagnosis. Note 3: Generally unused GPIO pins should be pulled up (10 kΩ to VDD33). From PROFINET stack version V1.4 onwards all unused GPIOs should be left open, because the stack will configure them to outputs. This does not apply to pins handled in note 2. Abbreviations: I O I/O Input Output Input/Output R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 20 of 40 TPS-1 2. Electrical Specifications 2. Electrical Specifications 2.1. Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply for core VDD10 -0.5 to +1.4 V Power supply for IO Power supply for PHYs VDD33 VDD15 -0.5 to +4.6 -0.5 to +2.0 V V Analog power supply for PLL Analog central 3.3V supply for PHYs PLL_AVDD VDDACB -0.5 to +1.4 -0.5 to +4.6 V V Analog central 1.5V supply for PHYs Analog Rx/Tx port power supply VDDAPLL P(2:1)VDDARXTX -0.5 to +2.0 -0.5 to +2.0 V V PECL buffer power supply PHY 1 PECL buffer power supply PHY 2 VDDQ_PECL_B1 VDDQ_PECL_B2 -0.5 to +4.6 -0.5 to +4.6 V V Analog test supply Input voltage VDD33ESD VI -0.5 to +4.6 -0.5 to +4.6 V V Operating temperature TJ -40 to + 125 0C Storage temperature TSTG -65 to + 150 0C 3.3V CMOS VI < VDD + 0.5V Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 21 of 40 TPS-1 2.2. 2. Electrical Specifications Operating Conditions Table 2-2: Recommended Operating Conditions (supply voltages) Parameter Symbol MIN. TYP. MAX. Unit Power supply for core (digital) VDD10 0.9 1.0 1.1 V Power supply for IO (digital) Power supply for PHYs (digital) VDD33 VDD15 3.0 1.35 3.3 1.5 3.6 1.65 V V Analog power supply for PHYs Analog central 3.3V supply for PHYs AVDD_REG VDDACB 3.0 3.0 3.3 3.3 3.6 3.6 V V Analog central 1.5V supply for PHYs PECL buffer power supply PHY 1 VDDAPLL 1.35 1.5 1.65 V VDDQ_PECL_B1 3.0 3.3 3.6 V PECL buffer power supply PHY 2 Analog test supply VDDQ_PECL_B2 VDD33ESD 3.0 3.0 3.3 3.3 3.6 3.6 V V Analog power supply for PLL Ambient temperature PLL_AVDD TA 0.9 -40 1.0 1.1 +85 V 0C Table 2-3: Recommended Operating Conditions (input / output level) Parameter Output voltage high 3.3V CMOS Symbol VOH Test Conditions MIN. IOH= 0 mA nominal output current Output voltage low 3.3V CMOS VOL Input voltage high 3.3V CMOS 3.3V PECL VIH Input voltage low 3.3V CMOS 3.3V PECL VIL Positive trigger voltage Negative trigger voltage 3.3V buffer Hysteresis voltage TYP. MAX. VDD33 – 0.1V 2.4 IOL= 0 mA nominal output current Unit V V 0.1 0.4 V V 2 -0.880 VDD33 1.165 V V 0 -1.474 0.8 -1.880 V V VP 1.2 2.4 V 3.3V buffer VN 0.6 1.8 V 3.3V buffer VH 0.3 1.5 V Difference to VDDQ_PECL_B(2:1) Difference to VDDQ_PECL_B(2:1) Table 2-4: TPS-1 power consumption overview Parameter Power consumption MIN. TYP. MAX. Unit 1.0 V 300 mW 1.5V 3.3V 240 363 mW mW 903 mW Total: 800 Note Note: The power consumption of the TPS-1 is approx. 800mW (average). R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 22 of 40 TPS-1 2.3. 2. Electrical Specifications Thermal Characteristics Table 2-5: Thermal Characteristics of the Package Airflow (m/s) Parameter Symbol Unit 0 0.2 1 2 Thermal resistance junction to ambient Note1 Θja 21.99 20.91 18.86 17.80 K/W Thermal resistance junction to top center of the package surface Note1 Thermal resistance junction to case Note2 Ψjt 0.12 0.17 0.31 0.37 K/W Note Θjc 7.38 K/W 1. The parameters are valid, if no heat sink is used and PCB with 4 layers and massive ground and power planes. 2. The parameter is valid, if a heat sink is used. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 23 of 40 TPS-1 2. Electrical Specifications 2.4. AC Characteristics 2.4.1. Clock Timing Table 2-6: Clock AC Characteristics (using a crystal) Parameter Symbol MIN. TYP. MAX. Unit fC - 25 - MHz Oscillator clock frequency (XCLK1, Pin N11) XCLK2, Pin P11) Note 1 Frequency tolerance EXTAL clock cycle time EXTAL clock rising time Note 2 EXTAL clock falling time Note 2 Input capacity (incl. package), XCLK1, N11 Output capacity (incl. package), XCLK2, P11 High level input voltage Low level input voltage JTAG clock frequency Notes: ftol -50 ppm - + 50 ppm TEXcyc tEXr 0 40 - 4 ns ns tEXf CIN 0 - 4.2 4 - ns pF COUT VIH 3 2.0 4 - 5 pF V VIL - - - 0.8 20 V MHz 1. See TPS-1 User’s Manual: Hardware () for recommended XTAL 2. Input voltage rising from 10% to 90% or falling from 90% to 10% of its nominal value. T tEXf tEXr tEXH tEXL TEXcyc Figure 2-1: Clock Waveforms Table 2-7: Clock AC Characteristics (using an external oscillator) Symbol MIN. TYP. MAX. Unit External clock source frequency Parameter fIN - 25 - MHz Frequency tolerance Note 1 XCLK1 high level voltage ftol VIH -50 ppm 2 3.3 + 50 ppm VDDACB V XCLK1 low level voltage XCLK1 rise or fall time VIL tRFC 0 0 1 0.8 4 V ns XCLK1 high or low time Note 2 XCLK1 jitter tolerance tW tJIT 16 - 20 20 24 - pF ps (RMS) DuCy 40 50 60 % XCLK1 duty cycle Notes: 1. The specified frequency tolerance must be maintained over all lifetime and temperature. 2. tW was calculated at fIN(TYP)=25 MHz, e.g. tw(MIN) = 10 * (DuCy(MIN) / fIN(TYP)) R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 24 of 40 TPS-1 2.4.2. 2. Electrical Specifications I/O timing specification Figure 2-2: Figure 2-3: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Input setup and hold waveforms Output delay waveforms page 25 of 40 TPS-1 2. Electrical Specifications 2.4.2.1. JTAG interface timing Table 2-8: Timing JTAG interface Input Signal Setup time (TIS min.) Output Hold time (TIH min.) Valid delay (TOV max.) Unit Hold time (TOH min.) Clock TRSTN 8 0 ns TCK TMS 8 0 ns TCK TDI 8 0 TCK - - TDO Note Notes ns TCK - - - - Note 2 10 2 ns TCK Note 1 1: Minimum hold time is measured with 10 pF load and maximum valid Delay is measured with 30 pF load. 2: For TCK a maximum speed of 20 MHz is allowed. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 26 of 40 TPS-1 2. Electrical Specifications 2.4.2.2. Parallel host interface timing diagrams 2.4.2.2.1. Host read from TPS-1 with separate read/write line (LBU_READY_OUT active low) TA = - 40 to +85OC; VDD15 = 1.35 V ~ 1.65 V; VDD33 = 3.0 V ~ 3.6 V Table 2-9: Host read with separate read/write line Symbol Condition MIN. MAX. Unit Chip select asserted to read pulse asserted delay Address valid to read pulse asserted setup time Parameter tCSRS tARS - 0 0 - ns ns Read pulse asserted to ready enabled delay Read pulse asserted to data enable delay tRRE tRDE - 5 5 12 12 ns ns Ready asserted to data valid delay Read pulse deasserted to chip select deasserted delay tRTD tRCSH - 0 5 - ns ns Address valid to read pulse deasserted hold time Data valid/enable to read pulse deasserted hold time tRHA tRDH - 0 0 12 ns ns Read recovery time tRR - 25 - ns LBU_CS_N tCSRS tRCSH LBU_RD_EN_N tRR tARS LBU_A(13:0)_IN LBU_SEG(1:0)_IN LBU_BE_(2:1)_IN tRAH tRRE LBU_READY_OUT tRDE tRTD tRDH LBU_DATA(15:0) Figure 2-4: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Host read with separate read/write line page 27 of 40 TPS-1 2.4.2.2.2. 2. Electrical Specifications Host write to TPS-1 with separate read/write line (LBU_READY_OUT active low) TA = - 40 to +85OC; VDD15 = 1.35 V ~ 1.65 V; VDD33 = 3.0 V ~ 3.6 V Table 2-10: Host write with separate read/write line Parameter Symbol Condition MIN. MAX. Unit Chip select asserted to write pulse asserted delay tCSWS - 0 - ns Address valid to write pulse asserted setup time Write pulse asserted to ready enabled delay tAWS tWRE - 0 5 12 ns ns Write pulse asserted to data valid delay Write pulse deasserted to chip select deasserted delay tWDV - - 40 ns tWCSH - 0 - ns Address hold time after write strobe deasserted Ready asserted to write pulse deasserted delay tWAH tRTW - 0 0 - ns ns Data hold time after write pulse deasserted Write recovery time tWDH tWR - 0 25 - ns ns LBU_CS_N tCSWS tWCSH LBU_WD_EN_N tWR tAWS LBU_A(13:0)_IN LBU_SEG(1:0)_IN LBU_BE_(2:1)_IN tRTW tWAH tWRE LBU_READY_OUT tWDV tWDH LBU_DATA(15:0) Figure 2-5: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Host write with separate read/write line page 28 of 40 TPS-1 2.4.2.2.3. 2. Electrical Specifications Host read from TPS-1 with common read/write line (LBU_READY_OUT active low) TA = - 40 to +85OC; VDD15 = 1.35 V ~ 1.65 V; VDD33 = 3.0 V ~ 3.6 V Table 2-11: Host read with common read/write line Parameter Symbol Condition MIN. MAX. Unit Write signal deasserted to chip select asserted setup time tWCS - 2 - ns Address valid to chip select asserted setup time Chip select asserted to ready enabled delay tACS tCRE - 0 5 12 ns ns Chip select asserted to data enable delay Ready asserted to data valid delay tCDE tRTD - 5 - 12 5 ns ns tCWH - 0 - ns tCAH - 0 - ns tCDH tRR - 0 25 12 - ns ns Write signal inactive to chip select deasserted hold time Chip select deasserted to address invalid hold time Chip select deasserted to data invalid hold time Read recovery time LBU_CS_N tWCS tRR LBU_WR_EN_N tCWH tACS LBU_A(13:0)_IN LBU_SEG(1:0)_IN LBU_BE_(2:1)_IN tCAH tCRE LBU_READY_OUT tCDE tRTD tCDH LBU_DATA(15:0) Figure 2-6: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Host read with common read/write line page 29 of 40 TPS-1 2.4.2.2.4. 2. Electrical Specifications Host write to TPS-1 with common read/write line (LBU_READY_OUT active low) TA = - 40 to +85OC; VDD15 = 1.35 V ~ 1.65 V; VDD33 = 3.0 V ~ 3.6 V Table 2-12: Host write with common read/write line Parameter Symbol Condition MIN. MAX. Unit Write signal deasserted to chip select asserted setup time tWCS - 2 - ns Address valid to chip select asserted setup time Chip select asserted to ready enabled delay tACS tCRE - 0 5 12 ns ns Chip select asserted to data valid delay Write signal deasserted to chip select deasserted hold time tCDV - - 40 ns tCWH - 0 - ns Address hold time after chip select deasserted Ready asserted to chip select deasserted delay tCAH tRTC - 0 0 - ns ns Chip select deasserted to data invalid hold time Read recovery time tCDH tWR - 0 25 - ns ns LBU_CS_N tWR tWCS LBU_WR_EN_N tCWH tACS LBU_A(13:0)_IN LBU_SEG(1:0)_IN LBU_BE_(2:1)_IN tCRE tRTC tCAH LBU_READY_OUT tCDV tCDH LBU_DATA(15:0) Figure 2-7: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Host write with common read/write line page 30 of 40 TPS-1 2. Electrical Specifications 2.4.2.3 SPI Slave Timing TA = - 40 to +85OC; VDD15 = 1.35 V ~ 1.65 V; VDD33 = 3.0 V ~ 3.6 V Table 2-13: SPI Slave Timing Parameter Symbol Condition Min. Max. Unit SPI clock tcl - 40 - ns Setup time tsu - 13 - ns Hold time th - 13 - ns tcl HOST_SCLK_IN tsu th HOST_RESET_IN HOST_SRXD_IN tsu th HOST_STXD_OUT HOST_SHDR_OUT Figure 2-8: SPI Slave Timing R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 31 of 40 TPS-1 2.4.3. 2. Electrical Specifications I2C-Bus timing definition TA = - 40 to +85OC; VDD15 = 1.35 V ~ 1.65 V; VDD33 = 3.0 V ~ 3.6 V Table 2-14: Characteristics of the SCL and SDA lines Standard-Mode Parameter Fast-Mode Symbol Max. Min. Max. fSCL 0 100 0 400 kHz tBUF 4.7 - 1.3 - µs tHD;STA 4.0 - 0.6 - µs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - µs µs tSU;DAT 4.7 - 0.6 - µs tHD;DAT 0(1) - 0(1) 0.9 µs 100(2) SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) Start condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for repeated START condition Data hold time Unit Min. Data set-up time Rise time of both SDA and SCL signals tSU;STA tR 250 - 1000 20+0.1Cb 300 ns ns Fall time of both SDA and SCL signals Capacitive load for each bus line tf Cb - 300 400 20+0.1Cb - 300 400 ns pF Notes: 1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 2. A fast-mode device can be used in a Standard-bus system, but the requirement tSU;STA must be met. I2C_x_D_INOUT tBUF tLOW tF tR tHD;STA SCLK_x_INOUT tHD;DAT tHD;STA Figure 2-9: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 tHIGH tSU;DAT tSU;STA I2C-Bus timing definition page 32 of 40 TPS-1 2. Electrical Specifications 2.4.3.1. PHY DC Specifications (100 BASE-TX) TA = -40 to +85 OC, AVDD33 = 3.0 to 3.6V, AVDD15 = 1.35 to 1.65V, DVDD = 1.35 to 1.65V Table 2-15: PHY DC Specification Parameter TX Output, High Level Differential Signal, TXP/TXN TX Output, Low Level Differential Signal, TXP/TXN TX Output, Mid. Level Differential Signal, TXP/TXN TX Output, Overshoot Differential Signal, TXP/TXN Symbol Min. VOUTH Typ. Max. Unit 0.95 1.05 V VOUTL -0.95 -1.05 V VOUTM -0.05 +0.05 V V0VS 0 5 % These specifications are complying with ANSI/IEEE 802.3 Std. VOUTTH(Max) VOUTTH(Min) VOUTM(Max) 0V VOUTM(Min) VOUTL(Max) VOUTL(Min) Figure 2-10: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 PHY DC Specification page 33 of 40 TPS-1 2. Electrical Specifications 2.4.3.2. PHY AC Specifications (100BASE-TX) TA = -40 to +85 OC, AVDD33 = 3.0 to 3.6V, AVDD15 = 1.35 to 1.65V, DVDD = 1.35 to 1.65V Table 2-16: PHY AC Timing Parameter Rise time and fall time, TXP/TXN Symbol Min. tr , tf 3 Duty cycle distortion, TXP/TXN Transmit Jitter, TXP/TXN Typ. Max. Unit 5 ns 0.5 1.4 ns ns These specifications are complying with ANSI/IEEE 802.3 Std. 0V tr tf Figure 2-11: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 tf tr PHY AC Specification page 34 of 40 TPS-1 2.4.4. 2. Electrical Specifications Power-up sequence For operation the TPS-1 needs three supply voltages. These are 3.3V, 1.5V and 1.0V, whereby the 1.5V power supply can be generated internally by a switch regulator. It is also possible to feed this power supply from an external circuitry. Table 2-17: Signals for Power-Up Signal TPS-1 Description VDD Power Supply (all voltages) RESET_N XCLK_1 External Reset Quartz connection (input) Remark active low VDD RESET_N min. 35us XCLK1 Unstable Figure 2-12: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 min. 2us Power-Up Sequence Timing Diagram page 35 of 40 TPS-1 2.4.5. 2. Electrical Specifications Reset timing Table 2-18: Signals for Reset Timing Signal TPS-1 Description Remark XCLK1 Quartz connection (input) External Signal CLK_ARM RESET_N Clock for the ARM CPU External Reset Internal Signal External Signal (active low) POR_OUT PLL_LOCK Power On Reset Clocks are synchronous to XCLK1 Internal Signal (supply voltages stable) Internal Signal The start-up time of the oscillator cannot be defined by the semiconductor vendor, because the timing heavily depends on the external components (external resonator crystal). Check the TPS-1 User’s Manual: Hardware (R19UH0081ED) for details. XCLK1 (25 MHz) 30 us 1.0V supply active 1.5V supply active RESET_N 3.3V supply stable CLK_ARM (100 MHz) (internal) 500 us POR_OUT (internal) PLL_LOCK (internal) Figure 2-13: R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 Reset Timing Diagram page 36 of 40 TPS-1 3. 3. Package Drawing Package Drawing Figure 3-1: 196-ball FPBGA Package Drawing Package: Package Ball Pitch Dimensions FPBGA 196 Pins 1.0 mm Pitch 15 mm * 15 mm R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 37 of 40 TPS-1 4. 4. Recommended Soldering Conditions Recommended Soldering Conditions Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to the information document. Renesas Semiconductor Package Mount Manual, (Rev.5.0, Feb 2015) (R50ZZ0003EJ0500) The applied standard is “IR60-107-3”. Table 4-1: Recommended soldering conditions Condition Symbol IR60 Soldering Conditions Package peak temperature: 2600C, Time: 60 seconds max. (at 2200C or higher). -107 -3 Exposure limit: 7 daysNote (after that, prebake at 1250C for 20 to 72 hours). Count: Three times or less. Note: After opening the dry pack, store it at 250C or less and 65% RH or less for the allowable storage period. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 38 of 40 TPS-1 Instructions for the use of product In this section, the precautions are described for over whole of CMOS device. Please refer to this manual about individual precaution. When there is a mention unlike the text of this manual, a mention of the text takes first priority 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. - The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. - The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. - The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. - When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. R19DS0069EJ0107 Rev. 1.07 Jul 30th, 2018 page 39 of 40 TPS-1 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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