DATASHEET
MK1575-01
CLOCK RECOVERY PLL
Description
Pre-Configured Input/Output
Frequency Combinations:
The MK1575-01 is a clock recovery Phase-Locked Loop
(PLL) designed for clock synthesis and synchronization in
cost sensitive applications. The device is optimized to
accept a low-frequency reference clock to generate a
high-frequency data or graphics pixel clock. External loop
filter components allow tailoring of loop frequency response
characteristics. For low jitter / phase noise requirements
refer to the MK2069 products.
Telecom T/E Clock Modes (rising edge aligned):
Features
• Long-term output jitter 1), calculate the value of CP based
on a CS value that would be used for a damping factor of 1.
This will minimize baseband peaking and loop instability that
can lead to output jitter.
To prevent jitter on the output clocks due to modulation of
the PLL by the input reference frequency, the following
general rule should be observed:
PLL Bandwidth
CP also helps to damp VCO input voltage modulation
caused by the charge pump correction pulses. A CP value
that is too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme cases
where input jitter is high, charge pump current is high, and
CP is too small, the VCO input voltage can hit the supply or
ground rail resulting in non-linear loop response.
f Phase Detector
≤-------------------------------20
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. For video applications, a low
damping factor (0.7 to 1.0) is generally desired for fast
genlocking. For telecom applications, a higher damping
IDT™ CLOCK RECOVERY PLL
= C B + 300 pF
The best way to set the value of CP is to use the External
Loop Filter Solver located on the IDT web site.
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MK1575-01
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MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Loop Filter Capacitor Type
choosing capacitor types. Performance differences are best
determined through experimentation.
Clock Jitter and input-to-output skew performance of the
MK1575-01 can be affected by loop filter capacitor type.
Cost vs. performance trade-offs can be made when
Recommended capacitors can be found at
http://www.icst.com/products/telecom/
Example Loop Filter Component Values for Pre-Configured Frequency
Combinations Listed on Page 1.
Addr
Output
Frequency
N Factor
(MHz)
Input
Frequency
RS
CS
CB
24704
15 kΩ
1 µF
2.2 nF
CLK1 CLK2
000
8 kHz
000
001
Loop
Loop Passband
BW
Damp Peaking
(-3dB)
363 Hz
2.5
0.19 dB
Notes
3.088
1.544
1
8 kHz
3.088
1.544
24704
6.8 kΩ
10 µF
4.7 nF
199 Hz
4.46
0.06 dB
2
8 kHz
16.384 2.048
32768
18 kΩ
1 µF
2.2 nF
425 Hz
3.24
0.12 dB
1
001
8 kHz
16.384 2.048
32768
8.2 kΩ
10 µF
4.7 nF
181 Hz
4.67
0.05 dB
2
010
8 kHz
34.368 17.184
34368
18 kΩ
1 µF
2.2 nF
405 Hz
3.16
0.13 dB
1
010
8 kHz
34.368 17.184
34368
8.2 kΩ
10 µF
4.7 nF
173 Hz
4.56
0.06 dB
2
011
8 kHz
44.736 22.368
22368
12 kΩ
1 µF
1 nF
390 Hz
2.62
0.17 dB
1
011
8 kHz
44.736 22.368
22368
6.8 kΩ
10 µF
4.7 nF
219 Hz
4.69
0.05 dB
2
100
15.625 kHz
54
27
13824
10 kΩ 0.068 µF 3.3 nF
758 Hz
0.72
2.16 dB
3
101
15.734 kHz
54
27
13728
10 kΩ 0.068 µF 3.3 nF
760 Hz
0.73
2.15 dB
3
110
15.625 kHz
35.468 17.734
18160
10 kΩ 0.068 µF 3.3 nF
760 Hz
0.73
2.15 dB
3
111
15.734 kHz
28.636 14.318
14560
10 kΩ 0.068 µF 4.7 nF
721 Hz
0.7
2.42 dB
3
Notes:
1) This loop filter selection is optimized for cost and component size. It provides stable clock outputs and moderate
input reference jitter attenuation. This configuration could be used when producing an internal system clock, one which
will not be used as a data transmit clock when locked to a recovered data clock.
2) This loop filter selection is optimized for low pass-band peaking. This configuration should be used when generating
data transmit clock that is locked to a recovered data clock. This will ensure that the data clock conforms with Belcore
GR-1244-CORE wander transfer specifications.
3) A loop bandwidth of 700 Hz and damping factor of 0.7 is typical for video genlock applications. This combination
assures minimal Hsync frequency modulation of the pixel clock yet genlocking.
4) Example vendors and part numbers for above capacitor selections:
0.15 µF
Panasonic ECP-U1C154MA5 (SMT film type, 1206 size, available from DigiKey)
IDT™ CLOCK RECOVERY PLL
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MK1575-01
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MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
0.68 µF
Panasonic ECP-U1C684MA5 (SMT film type, 1206 size, available from DigiKey)
10 µF
MuRata GRM42-2X5R106K10
10 nF
Panasonic ECH-U1C103JB5 (SMT film type, 805 size, available from DigiKey)
33 nF
Panasonic ECH-U1C333JB5 (SMT film type, 1206 size, available from DigiKey)
Input-to-Output Skew Induced by Loop Filter
Leakage
Avoiding PLL Lockup
Leakage across the loop filter, due to PCB contamination or
poor quality loop filter capacitors, can increase
input-to-output clock skew error. Concern regarding
input-to-output skew error is usually limited to “zero delay”
configurations, where CLK1 or CLK2 is directly connected to
FBIN. In sever cases of loop filter leakage, however, output
clock jitter can also be increased.
In some applications, the MK1575-01 VCO can “lock up” at
it’s maximum operating frequency. To avoid this problem
observe the following rules:
1) Do not open the clock feedback path with the MK1575-01
enabled. If the MK1575-01 is enabled and does not get a
feedback clock into pin FBIN, the output frequency will be
forced to the maximum value by the PLL.
The capacitors CS and CP in the external loop filter maintain
the VCO frequency control voltage between charge pump
pulses, which by design coincide with phase detector
events. VCO frequency or phase adjustments are made by
these charge pump pulses, pumping current into (or out of)
the external loop filter capacitors to adjust the VCO control
voltage as needed. Like the capacitors, the CHGP pin (pin
8) is a high-impedance PLL node; the charge pump is a
current source, which is high impedance by definition, and
the VCO input is also high impedance.
If an external divider is in the feedback path and it has a
delay before becoming active, hold the OE pin high until the
divider is ready to work. This could occur, for example, if the
divider is implemented in a FPGA.
Holding OE high powers down the MK1575-01 and dumps
the charge off the loop filter.
2) If an external divider is used in the feedback path, use a
circuit that can operate well beyond the intended output
clock frequency.
During normal (locked) operation, in the event of current
leakage in the loop filter, the charge pump will need to
deliver equal and opposite charge in the form of longer
charge pump pulses. The increased length of the charge
pump pulse will be translated directly to increased
input-to-output clock skew. This can also result in higher
output jitter due to higher reference clock feedthrough
(where the reference clock is fREFIN), depending on the loop
filter attenuation characterisitcs.
Power Supply Considerations
As with any integrated clock device, the MK1575-01 has a
special set of power supply requirements:
• The feed from the system power supply must be filtered
for noise that can cause output clock jitter. Power supply
noise sources include the system switching power supply
or other system components. The noise can interfere with
device PLL components such as the VCO or phase
detector.
The Input-to-Output skew parameters in the DC Electrical
Specifications assume minimal loop filter leakage.
Additional skew due to loop filter leakage may be calculated
as follows:
• Each VDD pin must be decoupled individually to prevent
I Leakage
Leakage Induced I/O Skew (sec) = -------------------------------I CP × F REFIN
power supply noise generated by one device circuit block
from interfering with another circuit block.
• Clock noise from device VDD pins must not get onto the
PCB power plane or system EMI problems may result.
IDT™ CLOCK RECOVERY PLL
7
MK1575-01
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MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
1) Each 0.01µF power supply decoupling capacitor should
be mounted as close to the VDD pin as possible. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite chip and bulk decoupling from the device is less
critical.
This above set of requirements is served by the circuit
illustrated in the Optimum Power Supply Connection, below.
The main features of this circuit are as follows:
• Only one connection is made to the PCB power plane.
• The capacitors and ferrite chip (or ferrite bead) on the
common device supply form a lowpass ‘pi’ filter that
remove noise from the power supply as well as clock
noise back toward the supply. The bulk capacitor should
be a tantalum type, 1 µF minimum. The other capacitors
should be ceramic type.
2) The loop filter components (RZ, CS and CB) must also be
placed close to the CHGP and VIN pins. CB should be
closest to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces short
and away from active signal traces. Use of vias should be
avoided.
• The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
3) To minimize EMI the 33Ω series termination resistor, if
needed, should be placed close to the clock output.
• The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as
possible. There should be no vias between the
decoupling capacitor and the supply pin.
4) Because each input selection pin includes an internal
pull-up device, those inputs requiring a logic high state (“1”)
can be left unconnected. The pins requiring a logic low state
(“0”) can be grounded.
Optimum Power Supply Connection
Connection Via to 3.3V
Power Plane
0.01 F
0.01 F
10Ω
1 nF
BULK
0.1 F
Ferrite
Chip
Loss of Reference Clock
If a loss occurs on the REFIN clock, the output frequency
will decrease at a rate of
VDDA
Pin
df
4250
=
dt
C x VS
VDDD
Pin
Hz/s
where:
C = C1 + C2
VS = value of VS divider (from the table on page 3)
If the input is held low, the output will stop high or low, or
might toggle at several Hz.
Series Termination Resistor
Low Frequency Operation
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to reduce
EMI. To series terminate a 50Ω trace, which is a commonly
used PCB trace impedance, place a 33Ω resistor in series
with the clock line as close to the clock output pin as
possible. The nominal impedance of the clock output is 20Ω.
The output frequency can be extended below 1.5 MHz by
adding a divider in the output path. In this configuration, it is
desirable to take the feedback signal from CLK1 rather than
the output of the divider. However, if zero delay operation is
required, the feedback signal must come from the divider
output.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following printed circuit board layout
recommendations should be observed.
IDT™ CLOCK RECOVERY PLL
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MK1575-01
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MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
700
600
500
MHz
400
300
200
100
0
0
0.5
1
1.5
2
2.5
3
3.5
Vin
MK1575-01 Typical VCO Transfer Curve
IDT™ CLOCK RECOVERY PLL
9
MK1575-01
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MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1575-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (industrial version)
-40 to +85° C
Ambient Operating Temperature (commercial version)
0 to +70° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
Recommended Operation Conditions
Parameter
Min.
Max.
Units
-40
+85
°C
Ambient Operating Temperature (commercial version)
0
+70
°C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.45
V
Ambient Operating Temperature (industrial version)
Typ.
+3.3
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
3.15
3.3
3.45
V
Operating Voltage
VDD
Supply Current
IDD
Clock outputs
unloaded, VDD = 3.3
V
10
mA
Supply Current in Power Down
IDD
OE = VDD
100
µA
12.5
µA
Charge Pump Current
ICP
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIH = VDD
Input Low Current
IIL
VIL = 0
Input Capacitance, except X1
CIN
Output High Voltage (CMOS
Level)
VOH
IDT™ CLOCK RECOVERY PLL
2
V
0.8
V
-10
+10
µA
-10
+10
µA
7
IOH = -4 mA
10
pF
VDD-0.4
V
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
Parameter
CLOCK SYNTHESIZER
Symbol
Output High Voltage
VOH
Output Low Voltage
VOL
Short Circuit Current
IOS
Nominal Output Impedance
Conditions
Min.
Typ.
Max.
Units
IOH = -8 mA
CLK1, CLK2
2.0
V
IOH = -4 mA
FCLK
2.0
V
IOL = 8 mA
CLK1, CLK2
0.4
V
IOL = 4 mA
FCLK
0.4
V
CLK1, CLK2
±43
mA
FCLK
±18
mA
20
Ω
ZOUT
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Input Clock Frequency
(into pins REFIN or FBIN)
fREF
Conditions
fVCO
fCLK
Output Rise Time
tOR
0.8 to 2.0 V
Output Fall Time
tOF
2.0 to 0.8 V
Output Clock Duty Cycle
tDC
At VDD/2
tJ
Long Term Timing Jitter, pk-pk
tJLT
VCO Gain
KO
IDT™ CLOCK RECOVERY PLL
Typ.
96
Internal VCO Frequency
Output Frequency
Jitter, Absolute Peak-to-peak
Min.
45
Units
20
MHz
320
MHz
80
MHz
.6
1.1
ns
.6
1.1
ns
50
55
%
Single cycle
measurement;
Deviation from mean
150
10 µS trigger delay
1.7
340
11
Max.
ps
3.0
ns
MHz/V
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
16
Millimeters
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
IN D EX
AR EA
1
2
D
A
2
A
Min
Inches
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
1
c
-C e
b
S E A TIN G
P LA N E
L
aaa C
IDT™ CLOCK RECOVERY PLL
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MK1575-01
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MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
Marking Diagram (commercial)
16
Marking Diagram (industrial)
9
16
1575-01G
######
YYWW
1
157501GI
######
YYWW
8
1
Marking Diagram (Pb free, industrial)
16
8
Marking Diagram (Pb free, commercial)
16
16
9
15751GIL
######
YYWW
1
9
9
157501GL
######
YYWW
8
11
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
3. “L” designates Pb (lead) free package.
4. “I” designates industrial temperature grade.
5. Bottom marking: (origin). Origin = country of origin of not USA.
Ordering Information
Part / Order Number
MK1575-01G*
MK1575-01GTR*
MK1575-01GLF
MK1575-01GLFTR
MK1575-01GI*
MK1575-01GITR*
MK1575-01GILF
MK1575-01GILFTR
Marking
Shipping Packaging
Package
Temperature
see Marking
Diagrams above
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
0 to + 70° C
0 to + 70° C
0 to + 70° C
0 to + 70° C
-40 to + 85° C
-40 to + 85° C
-40 to + 85° C
-40 to + 85° C
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ CLOCK RECOVERY PLL
13
MK1575-01
REV N 121809
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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Printed in USA