MK1581-01GILF

DATASHEET MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR Description Features The MK1581-01 provides synchronization and timing control for T1 and E1 based network access or multitrunk telecommunication systems. The device accepts an 8 kHz frame clock input and uses an on-chip VCXO to produce a synchronized low phase noise clock output. • Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. Through selection of external loop filter components values, the device can be tailored to meet the system’s clock jitter attenuation requirements. Low-pass jitter attenuation characteristics in the Hz range are possible. • • • • • • • • clock from an 8kHz frame clock input Configurable jitter attenuation characteristics, excellent for use as a Stratum source de-jitter circuit VCXO-based clock generation ensures very low jitter and phase noise generation Output clock is phase and frequency locked to the input reference clock +115ppm minimum crystal frequency pullability range, using recommended crystal Industrial temperature range Low power CMOS technology 16 pin TSSOP package Single 3.3 V power supply Block Diagram RSET ISET Pullable Crystal X1 VDD VDD X2 3 Phase Detector Output Divider VCXO 8kHz_IN CLK Charge Pump Feedback Divider SEL CHGP RS CS IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR VIN GND 5 CP 1 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Pin Assignment Output Clock Selection Table VDD 1 16 X1 VDD 2 15 X2 VDD 3 14 8kHz_IN VIN 4 13 SEL GND 5 12 CLK GND 6 11 GND GND 7 10 GND CHGP 8 9 ISET Input Clock SEL Output Clock (MHz) Crystal Used (MHz) 8 kHz 0 1.544 24.704 8 kHz 1 2.048 24.576 16 pin 4.40 mil body, 0.65 mm pitch TSSOP Pin Descriptions Pin Number Pin Name Pin Type 1 VDD Power Power Supply. Connect to +3.3 V. 2 VDD Power Power Supply. Connect to +3.3 V. 3 VDD Power Power Supply. Connect to +3.3 V. 4 VIN Input VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop filter as shown in this data sheet. 5 GND Power Connect to ground. 6 GND Power Connect to ground. 7 GND Power Connect to ground. 8 CHGP Output Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. 9 ISET – 10 GND Power Connect to ground. 11 GND Power Connect to ground. 12 CLK Output Clock Output. 13 SEL Input Output Frequency Selection. Determines output frequency as per table above. Internal pull-up. 14 8kHz_IN Input 8 kHz reference clock input. 15 X2 – Crystal Output. Connect this pin to the specified crystal. 16 X1 – Crystal Input. Connect this pin to the specified crystal. Pin Description Charge pump current setting node, connection for setting resistor. IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 2 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Functional Description The frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. The MK1581-01 incorporates variable load capacitors on-chip which “pull”, or change, the frequency of the crystal. The crystals specified for use with the MK1581-01 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. To achieve this, the layout should use short traces between the MK1581-01 and the crystal. The MK1581-01 is a clock generator IC that generates a T1 or E1 reference clock directly from an internal VCXO circuit that works in conjunction with an external quartz crystal. The VCXO output frequency and phase is controlled by an internal PLL (Phase Locked Loop) circuit, enabling the device to perform clock regeneration from an 8 kHz input reference clock. A complete description of the recommended crystal parameters is in application note MAN05. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal, the MK1581-01 is able to generate a low jitter, low phase-noise output clock. The low bandwidth capability of the PLL circuit serves to provide input clock jitter attenuation and enables stable operation with the low frequency input reference clock. A list of approved crystals is located on the IDT web site (www.idt.com). PLL Loop Filter Components A phased-locked loop (PLL) is a control system that keeps the VCO frequency and phase locked with the input reference clock. Like all control systems, analog PLL circuits use a loop filter to establish operating stability. The MK1581-01 uses external loop filter components for the following reasons: The internal VCXO circuit requires an external pullable crystal for operation. External loop filter components enable a PLL configuration with low loop bandwidth. 1) Larger loop filter capacitor values can be used, allowing a lower loop bandwidth. This enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking is desired. Application Information Output Frequency Configuration The MK1581-01 is configured to generate either a 1.544 MHz T1 clock or a 2.048 MHz E1 clock from an 8 kHz input clock. Please refer to the Output Clock Selection Table on Page 2. Input bit SEL is set according to this table, as is the external crystal frequency. Please refer to the Quartz Crystal section on this page regarding external crystal requirements. 2) The loop filter values can be user selected to optimize loop response characteristics for a given application. Referencing the External Component Schematic on this page, the external loop filter is made up of components RS, CS and CP. RSET establishes PLL charge pump current and therefore influences loop filter characteristics. Quartz Crystal It is important that the correct type of quartz crystal is used with the MK1581-01. Failure to do so may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. Design aid tools for configuring the loop filter can be found at www.idt.com, including on-line and PC-based calculators. The MK1581-01 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the PCB Layout Recommendations section must be followed. IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 3 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER External Component Schematic Refer to Crystal Tuning section CL VDD VDD VDD VIN GND RS GND GND CS CHGP CP CL Pullable Crystal 1 2 3 4 5 6 7 8 X1 X2 8kHz_IN SEL CLK GND GND ISET 16 15 14 13 12 11 10 9 RSET Recommended Loop Filter Values Vs. Output Frequency Selection Crystal SEL Output Freq Multiplier (N) RSET RS CS CP Loop Bandwidth (-3dB point) Damping Factor 0 1.544 MHz 3088 120 kΩ 1.0 MΩ 0.1 µF 4.7 nF 18 Hz 1.4 1 2.048 MHz 3072 120 kΩ 1.0 MΩ 0.1 µF 4.7 nF 19 Hz 1.4 IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 4 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER A “normalized” PLL loop bandwidth may be calculated as follows: Charge Pump Current Table R S × I CP × 575 NBW = ----------------------------------------N RSET 1.4 MΩ 680 kΩ 540 kΩ 120 kΩ The “normalized” bandwidth (NBW) equation above does not take into account the effects of damping factor or the second pole. NBW is approximately equal to the actual -3dB bandwidth of the loop when the damping factor is about 5 and C2 is very small. In most applications, NBW is about 75% of the actual -3dB bandwidth. However, NBW does provide a useful approximation of filter performance. Charge Pump Current (ICP) 10 µA 20 µA 25 µA 100 µA Special considerations must be made in choosing loop components CS and CP. Series Termination Resistor The loop damping factor is calculated as follows: Damping Factor = R S × Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. (The optional series termination resistor is not shown in the External Component Schematic.) 625 × I CP × C S ------------------------------------------N Where: Decoupling Capacitors As with any high performance mixed-signal IC, the MK1581-01 must be isolated from system power supply noise to perform optimally. RS = Value of resistor in loop filter (Ohms) ICP = Charge pump current (amps) (refer to Charge Pump Current Table, below) N = Crystal multiplier shown in the above table CS = Value of capacitor CS in loop filter (Farads) Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK1581-01 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. As a general rule, the following relationship should be maintained between components CS and CP in the loop filter: C CP = -----S20 IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 5 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Recommended Power Supply Connection for Optimal Device Performance from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead B ulk D ecoupling C apacitor (such as 1 F Tantalum ) 0.01 V D D P in 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. V D D P in F D ecoupling C apacitors 4) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK1581-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. In most cases the load capacitors will not be required. They should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. If the need for the load capacitors is later determined, the values will fall within the 1-4 pF range. The need for, and value of, these trim capacitors can only be determined at prototype evaluation. Refer to MAN05 for the centering capacitor selection procedure. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 6 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Recommended PCB Layout For m inim um output clock jitter, device V D D connections should be m ade to com m on bulk decoupling device (see text). For m inim um output clock jitter, rem ove ground and pow er plane w ithin this entire area. A lso route all other traces aw ay from this area. G G G 1 16 2 15 3 14 4 G 5 13 G 6 12 G 7 8 G 11 G 10 G 9 Legend: G G = G round C onnection Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1581-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 7 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +85 °C +3.45 V -40 Power Supply Voltage (measured in respect to GND) +3.15 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Operating Voltage VDD Supply Current IDD Input High Voltage, SEL VIH Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V 10 15 mA Clock outputs unloaded, VDD = 3.3 V 2 V Input Low Voltage, SEL VIL Input High Voltage, 8kHz_IN VIH Input Low Voltage, 8kHz_IN VIL Input High Current IIH VIH = VDD Input Low Current IIL VIL = 0 Input Capacitance, except X1 CIN Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -8 mA 2.4 V Output Low Voltage VOL IOL = 8 mA Short Circuit Current IOS VIN, VCXO Control Voltage VXC Nominal Output Impedance ZOUT IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 0.8 V V VDD/2+1 VDD/2-1 V -10 +10 µA -10 +10 µA 7 pF 0.4 V ±50 0 mA VDD 20 8 MK1581-01 V Ω REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol VCXO Crystal Pull Range fXP VCXO Crystal Nominal Frequency fX Input Jitter Tolerance tji Input pulse width (1) Output Frequency Error Conditions Using Recommended Crystal Min. Typ. Max. Units -115 +115 ppm 24.704 24.576 MHz 0.4 UI 0 ppm 60 % In reference to input clock period tpi 10 ns FOUT ICLK = 0 ppm error 0 Output Duty Cycle (% high time) tOD Measured at VDD/2, CL=15 pF 40 Output Rise Time tOR 0.8 to 2.0V, CL=15 pF 1.5 ns Output Fall Time tOF 2.0 to 0.8V, CL=15 pF 1.5 ns Skew, Input to Output Clock tIO Note 2 Cycle Jitter (short term jitter) tja Peak to Peak 0 150 ps p-p Note 1: Minimum high or low time of input clock. Note 2: The input to output clock skew is not controlled nor predictable and will change between power up cycles. Because it is dependent on the phase relationship between the output and feedback divider states following power up, the input to output clock skew will remain stable during a given power up cycle. If controlled input to output skew is desired for this output clock frequency please refer to the MK2049 or MK2069 products. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR Symbol Conditions Min. Typ. Max. Units θJA Still air 78 ° C/W θJA 1 m/s air flow 70 ° C/W θJA 3 m/s air flow 68 ° C/W 37 ° C/W θJC 9 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c -C e b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK1581-01GILF 15810GIL Tubes 16-pin TSSOP -40 to +85° C MK1581-01GILFTR 15810GIL Tape and Reel 16-pin TSSOP -40 to +85° C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 10 MK1581-01 REV F 051310 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Innovate with IDT and accelerate your future networks. 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