MK1704ALF

DATASHEET MK1704A LOW EMI CLOCK GENERATOR Description Features The MK1704A is an upgraded version of the MK1704 and is recommended for all new designs. It offers more reduction in the frequency amplitude peaks and will support frequencies up to 140 MHz. • • • • • The MK1704A generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock or other clocks for flat panel graphics controllers. The MK1704A uses IDT’s proprietary mixture of analog and digital Phase Locked Loop (PLL) technology to synthesize the frequency. It also uses IDT’s patented technique to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. 8 pin SOIC package Pb (lead) free package Provides a spread spectrum output clock Supports leading flat panel controllers Accepts a clock input, provides same frequency dithered output • Optimized for higher resolutions that require up to 140 MHz, as well as 40 MHz (SVGA) and 65 MHz (XVGA) clocks • Peak reduction by 7 dB - 14 dB typical on 3rd - 19th odd harmonics • • • • IDT offers many other clocks for computers and computer peripherals. Consult IDT when you need to remove crystals and oscillators from your board. Low EMI feature can be disabled Operating voltage of 3.3V or 5V Advanced, low power CMOS process See the MK1714-01 for a multiplier with low EMI which can operate from a crystal Block Diagram VDD S1:0 2 PLL Clock Synthesis and Spread Spectrum Circuitry Low EMI Enable Input CLK Input Buffer GND IDT™ LOW EMI CLOCK GENERATOR 1 MK1704A REV G 051310 MK1704A LOW EMI CLOCK GENERATOR SSCG Pin Assignment Output Clock Selection Table ICLK 1 8 NC VDD 2 7 S0 GND 3 6 S1 CLK 4 5 LEE Input Input Input S1 S0 Min. Nom. Max. Mult. 0 0 60 135 140 0 1 1 0 60 80 30 40 1 1 40 65 Freq. spread vs. CLK x1 +0.5, -1.5% 120 x1 +0.5, -1.5% 60 x1 Down 2.5% 100 x1 +0.5, -1.5% 8 pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 ICLK XI Pin Description Connect to a clock input as shown in table above. 2 VDD Power Connect to +3.3V or +5V. 3 GND Power Connect to ground. 4 CLK Output Clock output equal to input frequency. 5 LEE Input Low EMI enable. Turns on the spread spectrum when high. Internal pull-up. 6 S1 Input Frequency select 1 input. Selects input/output clock range per table above. Internal pull-up. 7 S0 Input Frequency select 0 input. Selects input/output clock range per table above. Internal pull-up. 8 NC - No connect. Do not connect anything to this pin. External Components Series Termination Resistor the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3. PCB Layout Recommendations 3) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal 1) The 0.01µF decoupling capacitor should be mounted on IDT™ LOW EMI CLOCK GENERATOR 2 MK1704A REV G 051310 MK1704A LOW EMI CLOCK GENERATOR SSCG layers. Other signal traces should be routed away from the MK1704A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Powerup Considerations example, a “power good” signal. Another solution is to leave LEE unconnected to anything but a 0.01 µF capacitor to ground. The pullup resistor on LEE will charge the capacitor and provide approximately a one millisecond delay until spread spectrum is enabled. To insure proper operation of the spread spectrum generation circuit, some precautions must be taken in the implementation of the MK1704A. 1) An input signal should not be applied to ICLK until VDD is stable. This requirement can easily be met by operating the MK1704A and the ICLK source from the same power supply. 3) If the input frequency is changed during operation, disable spread spectrum until the input clock stabilizes at the new frequency. LEE should be disabled for 10 µs minimum. 2) LEE should not be enabled (taken high) until after the power supplies and input clock are stable. This requirement can be met by direct control of LEE by system logic; for Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1704A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 175° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) IDT™ LOW EMI CLOCK GENERATOR 3 Typ. Max. Units 0 +70 °C +3.0 +5.5 V MK1704A REV G 051310 MK1704A LOW EMI CLOCK GENERATOR SSCG DC Electrical Characteristics Unless stated otherwise, VDD = 5V, Ambient Temperature 0 to +70° C Parameter Symbol Operating Voltage VDD Supply Current IDD Conditions Min. Typ. Max. Units 5.5 V 3.0 No load, 3.3V 10 mA No load, 5V 15 mA VDD/2 V Input High Voltage VIH Clock input Input Low Voltage VIL Clock input Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -25 mA 2.4 V Output Low Voltage VOL IOL = 25 mA Input Capacitance CIN S0 pin Nominal Output Impedance ZOUT Internal Pull-up Resistor RPU (VDD/2)+1 VDD/2 LEE pin only (VDD/2)-1 0.4 V V 7 pF 20 Ω 500 kΩ AC Electrical Characteristics Unless stated otherwise, VDD = 5V, Ambient Temperature 0 to +70° C Parameter Symbol Input Frequency Input Clock Duty Cycle Conditions Min. Typ. Max. Units S1=0, S0=0 60 135 140 MHz S1-0, S0=1 60 80 120 MHz S1=1, S0=0 30 40 60 MHz S1=1, S0=1 40 65 100 MHz Time above VDD/2 20 80 % Output Rise Time tOR 0.8 to 2.0V, Note 1 1.5 ns Output Fall Time tOF 2.0 to 0.8V, Note 1 1.5 ns 60 % Output Clock Duty Cycle Time above 1.5V Output Clock Frequency Variation from Mean EMI Peak Frequency Reduction 3rd - 19th odd harmonics 40 50 1-2.5 % 10-16 dB Note 1: Measured with 15pF load IDT™ LOW EMI CLOCK GENERATOR 4 MK1704A REV G 051310 MK1704A LOW EMI CLOCK GENERATOR SSCG Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Units θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W 40 ° C/W θJC Marking Diagram (Pb free) 8 5 µCLOCK MK1704AL YYWW 1 4 Notes: 1. YYWW is the last two digits of the year and week the part was assembled. 2. “L” denotes Pb (lead) free package 3. Bottom Markings: ###### = lot number (origin) = country of origin if not USA IDT™ LOW EMI CLOCK GENERATOR 5 MK1704A REV G 051310 MK1704A LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number MK1704ALF MK1704ALFTR Marking Shipping Packaging Package Temperature see page 5 Tubes Tape and Reel 8 pin SOIC 8 pin SOIC 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ LOW EMI CLOCK GENERATOR 6 MK1704A REV G 051310 MK1704A LOW EMI CLOCK GENERATOR SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 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