MK1707SLFTR

DATASHEET MK1707 LOW EMI CLOCK GENERATOR Description Features The MK1707 generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for flat panel graphics controllers. The device uses IDT’s proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. • • • • • • • The MK1707 offers both centered and down spread from a high speed clock input. Refer to the MK1714-01/02 for a crystal input and the widest selection of input frequencies and multipliers. Packaged in 8-pin SOIC Pb-free package Industrial temperature range available Provides a spread spectrum output clock Supports ATI’s flat panel controllers Guaranteed to +85° C operation Accepts a clock input, provides same frequency dithered output • Good for all VGA modes from 80 to 167 MHz • Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics IDT offers many other clocks for computers and computer peripherals. Consult us when you need to remove crystals and oscillators from your board. • • • • Low EMI feature can be disabled Includes Power-down Operating voltage of 3.3 V or 5 V Advanced, low-power CMOS process Block Diagram VDD S1:0 2 Spread Direction PLL Clock Synthesis and Spread Spectrum Circuitry Low EMI Enable ICLK Clock Out Input Buffer GND IDT® LOW EMI CLOCK GENERATOR 1 MK1707 REV L 072312 MK1707 LOW EMI CLOCK GENERATOR SSCG Pin Assignment Spread Direction and Percentage Select Table ICLK 1 8 SD VDD 2 7 S1 GND 3 6 S0 CLK 4 5 LEE SD Pin 8 S1 Pin 7 S0 Pin 6 Spread Direction Spread Percentage (%) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 M M M 1 1 1 0 0 0 M M M 1 1 1 0 M 1 0 M 1 0 M 1 0 M 1 0 M 1 0 M 1 Down Down Down Down Center Down Down Center Down Center Down Power Down Center Center Center Center Center Center Test Center Power Down 0.6 0.8 1.25 +0.5, -1.5 2 +0.5, -2.5 +0.5, -3 5 ±0.35 ±0.5 ±0.7 ±0.8 ±1.1 ±1.4 Test ±2.5 - 8 pin (150 mil) SOIC 0 = connect to GND M = unconnected (floating) 1 = connect directly to VDD Pin Descriptions Pin Number Pin Name Pin Type 1 ICLK Input Connect to graphics input clock. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 CLK Output Spread spectrum clock output per table above. 5 LEE Input Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor. 6 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal mid-level. 7 S1 Input Function select 1input. Selects spread amount and direction per table above. Internal mid-level. 8 SD Input Spread direction select input. Selects the direction of spread per table above. Internal pull-up resistor. IDT® LOW EMI CLOCK GENERATOR Pin Description 2 MK1707 REV L 072312 MK1707 LOW EMI CLOCK GENERATOR SSCG External Components Powerup Considerations The MK1707 requires a minimum number of external components for proper operation. To insure proper operation of the spread spectrum generation circuit, some precautions must be taken while utilizing the MK1707. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. 1. An input signal should not be applied to ICLK until VDD is stable (within 10% of its final value). This requirement can easily be met by operating the MK1707 and then ICLK source from the same power supply. 2. LEE should not be enabled (taken high) until after the power supplies and input clock are stable. This requirement can be met by direct control of LEE by system logic - for example, a “power good” signal. Another solution is to leave LEE unconnected to anything but a 0.01μF capacitor to ground. The internal pullup resistor on LEE will charge the capacitor and provide approximately a 700μs delay until spread spectrum is enabled. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Tri-level Select Pin Operation 3. If the input frequency is changed during operation, disable spread spectrum until the input clock stabilizes at the new frequency. The S1, S0 select pins are tri-level, meaning they have three separate states to make the selections shown in the table on page 2. To select the M (mid) level, the connection to these pins must be eliminated by either floating them originally, or tri-stating the GPIO pins which drive the select pins. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1707. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT® LOW EMI CLOCK GENERATOR 3 MK1707 REV L 072312 MK1707 LOW EMI CLOCK GENERATOR SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1707. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature, Commercial 0 to +85° C Ambient Operating Temperature, Industrial -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. Max. Units 0 +85 °C +3.135 +5.5 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Parameter Symbol Conditions Min. Typ. 3.135 Max. Units 5.5 V Operating Voltage VDD Supply Current IDD No load, at 3.3 V 20 mA IDD No load, at 5 V 31 mA IDDPD S0=S1=SD=1 60 μA VDD/2 V Input High Voltage VIH ICLK Input Low Voltage VIL ICLK Input High Voltage VIH S1, S0 Input High Voltage VIH other inputs Input Low Voltage VIL S0, S1, SD, LEE pins Output High Voltage VOH CMOS, IOH = -4 mA Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = -12 mA Input Capacitance CIN S0, S1, SD, LEE pins IDT® LOW EMI CLOCK GENERATOR (VDD/2) + 1 VDD/2 (VDD/2) - 1 VDD-0.5 V 2.5 V 0.5 V VDD-0.4 V 2.4 V 0.4 4 V 5 V pF MK1707 REV L 072312 MK1707 LOW EMI CLOCK GENERATOR SSCG AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Parameter Symbol Conditions Input/Output Clock Frequency Min. Typ. Max. Units 80 167 MHz 80 % 60 % Input Clock Duty Cycle Time above VDD/2 20 Output Clock Duty Cycle Time above 1.5 V 40 50 Output Rise Time tOR 0.8 to 2.0 V 1.5 ns Output Fall Time tOF 2.0 to 0.8 V 1.5 ns Modulation Frequency EMI Peak Frequency Reduction 19 3rd - 19th odd harmonics 41 7 to 14 kHz dB Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT® LOW EMI CLOCK GENERATOR Symbol Conditions Min. Typ. Max. Units θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W 40 ° C/W θJC 5 MK1707 REV L 072312 MK1707 LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK1707SLF MK1707SLFTR MK1707SILF MK1707SILFTR MK1707SL MK1707SL MK1707IL MK1707IL Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +85° C 0 to +85° C -40 to +85° C -40 to +85° C Note: “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® LOW EMI CLOCK GENERATOR 6 MK1707 REV L 072312 MK1707 LOW EMI CLOCK GENERATOR SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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