MK1709AGLFTR

DATASHEET MK1709 LOW EMI CLOCK GENERATOR Description Features The MK1709 generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for flat panel graphics controllers. The device uses IDT’s proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. • Packaged in 8-pin SOIC (MK1709S) and in 8-pin TSSOP (MK1709AG) • • • • • The MK1709 offers centered spread from a high speed clock input. Refer to the MK1714-01/02 for a crystal input and the widest selection of input frequencies and multipliers. Pb-free package Provides a spread spectrum output clock Supports flat panel controllers Guaranteed to +85° C operation Accepts a clock input, provides same frequency dithered output • Good for all VGA modes from 40 to 167 MHz • Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics IDT offers many other clocks for computers and computer peripherals. Consult us when you need to remove crystals and oscillators from your board. • • • • Low EMI feature can be disabled Includes power-down Operating voltage of 3.3 V Advanced, low-power CMOS process Block Diagram VDD S0 S1 PLL Clock Synthesis and Spread Spectrum Circuitry S2 Low EMI Enable ICLK Clock Out Input Buffer GND IDT™ LOW EMI CLOCK GENERATOR 1 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG Pin Assignment Spread Percentage and Direction Select Table ICLK 1 8 S2 VDD 2 7 S1 GND 3 6 S0 CLK 4 5 LEE 8-pin SOIC (MK1709S) GND 1 8 VDD CLK 2 7 ICLK LEE 3 6 S2 S0 4 5 S1 8-pin TSSOP (MK1709AG) Frequency Spread Range Percentage (%) S2 Pin 8 (1709S) Pin 6 (1709AG) S1 Pin 7 (1709S) Pin 5 (1709AG) S0 Pin 6 (1709S) Pin 4 (1709AG) 0 0 0 0 0 M 40-50 40-50 ±0.9 ±0.7 0 0 1 40-50 (MK1709S) 25-50 (MK1709AG) ±0.8 0 M 0 40-50 (MK1709S) 25-50 (MK1709AG) ±0.6 0 M M 40-50 ±1.1 0 M 1 50 -100 ±0.6 0 1 0 50 -100 ±0.7 0 1 M 50 -100 ±0.8 0 1 1 Power Down — 1 1 0 0 0 M 50 -100 50 -100 ±0.9 ±1.1 1 0 1 100-165 ±0.7 1 M 0 100-165 ±0.6 1 M M 100-165 ±1.1 1 M 1 100-165 ±1.35 1 1 0 100-165 ±0.8 1 1 M 100-165 ±0.9 1 1 1 Power Down — 0 = connect to GND M = unconnected (floating) has internal Pull up resistor to VDD and is considered as a 1 state 1 = connect directly to VDD IDT™ LOW EMI CLOCK GENERATOR 2 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG Pin Descriptions (MK1709S) Pin Number Pin Name Pin Type Pin Description 1 ICLK Input Connect to graphics input clock. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 CLK Output Spread spectrum clock output per table above. 5 LEE Input Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor. 6 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal mid-level. 7 S1 Input Function select 1 input. Selects spread amount and direction per table above. Internal mid-level. 8 S2 Input Function select 2 input. Selects spread amount and direction per table above. Pin Descriptions (MK1709AG) Pin Number Pin Name Pin Type 1 GND Power Connect to ground. 2 CLK Output Spread spectrum clock output per table above. 3 LEE Input Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor. 4 S0 Input Function select 0 input. Selects spread amount and direction per table above. Internal mid-level. 5 S1 Input Function select 1 input. Selects spread amount and direction per table above. Internal mid-level. 6 S2 Input Function select 2 input. Selects spread amount and direction per table above. 7 ICLK Input Connect to graphics input clock. 8 VDD Power Connect to +3.3 V. IDT™ LOW EMI CLOCK GENERATOR Pin Description 3 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG External Components The MK1709 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3 for the MK1709S, or pins 1 and 8 for the MK1709AG. Place the capacitor as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Select Pin Operation The S1, S0 select pins are 2-level, meaning they have three separate states to make the selections shown in the table on page 2. PCB layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) Place a 33Ω series termination resistor (if needed) close to the clock output to minimize EMI. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1709. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT™ LOW EMI CLOCK GENERATOR 4 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1709. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Typical values are at 25° C. Item Rating Supply Voltage, VDD (referenced to GND) 5V All Inputs and Outputs (referenced to GND) -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +85° C Storage Temperature -65 to +150° C Soldering Temperature (maximum of 10 seconds) 260° C Recommended Operation Conditions Parameter Min. Max. Units 0 +85 °C +3.135 +3.6 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Parameter Symbol Conditions Min. Typ. 3.135 Max. Units 3.465 V Operating Voltage VDD Supply Current (MK1709S) IDD No load, at 3.3 V 20 mA Supply Current (MK1709AG) IDD No load, 50M 13 µA IDD No load, 150M 23 Input High Voltage (ICLK) VIH (VDD/2)+1 Input High Voltage (S1, S0) VIH VDD-0.5 V Input High Voltage (other inputs) VIH 2 V Input Low Voltage (ICLK) VIL Input Low Voltage VIL Output High Voltage (CMOS) VOH IOH = -4mA Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Input Capacitance CIN S0, S1, S2, LEE pins IDT™ LOW EMI CLOCK GENERATOR VDD/2 VDD/2 V (VDD/2)-1 V 0.5 V VDD-0.4 V 2.4 V 0.4 5 7 V pF MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG AC Electrical Characteristics (MK1709S) Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Parameter Symbol Conditions Input/Output Clock Frequency Min. Typ. Max. Units 40 167 MHz 80 % 60 % Input Clock Duty Cycle Time above VDD/2 20 Output Clock Duty Cycle Time above 1.5 V 40 50 Output Clock Rise Time tOR 0.8 to 2.0V 1.5 ns Output Clock Fall Time tOF 2.0 to 0.8V 1.5 ns 7 to 14 dB EMI Peak Frequency Reduction 3rd - 19th odd harmonics AC Electrical Characteristics (MK1709AG) Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +85° C Parameter Symbol Conditions Input/Output Clock Frequency Min. Typ. Max. Units 25 165 MHz 80 % 55 % Input Clock Duty Cycle Time above VDD/2 20 Output Clock Duty Cycle Time above 1.5 V, 40 MHz - 100 MHz 40 50 Time above 1.5 V, 100 MHz - 150 MHz 45 % Time above 1.5 V, >150 MHz 35 % Output Clock Rise Time tOR 0.8 to 2.0V 1.5 ns Output Clock Fall Time tOF 2.0 to 0.8V 1.5 ns EMI Peak Frequency Reduction 3rd - 19th odd harmonics 7 to 14 dB Spread Spectrum Modulation Rate For 40 to 50 MHz selections, modulation rate = input frequency/1028; for 50 to 100 MHz selections, modulation rate = input frequency/2056; for 100 to 165 MHz selections, modulation rate = input frequency/4112. IDT™ LOW EMI CLOCK GENERATOR 6 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG Marking Diagram 8 Marking for TSSOP package 5 8 1 YYWW 1709AL MK1709SL ###### YYWW 1 4 5 Bottom marking: Lot number and country of origin 4 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E A A1 B C D E e H h L α H INDEX AREA 1 2 D A Min Inches Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Min Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) IDT™ LOW EMI CLOCK GENERATOR C 7 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG Package Outline and Package Dimensions (8-pin TSSOP, 173 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 3.90 3.10 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.114 0.122 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° 0.004 A A 1 c -C e b S E A TIN G P LA N E L C aaa Ordering Information Part / Order Number MK1709SLF MK1709SLFTR MK1709AGLF MK1709AGLFTR Marking Shipping Packaging Package (see page 7) Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin TSSOP 8-pin TSSOP Temperature 0 to +85° 0 to +85° 0 to +85° 0 to +85° C C C C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ LOW EMI CLOCK GENERATOR 8 MK1709 REV M 051310 MK1709 LOW EMI CLOCK GENERATOR SSCG Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.