MK2069-04GILFTR

DATASHEET MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Description Features The MK2069-04 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that features a PLL (Phase-Locked Loop) input reference divider and feedback divider that have a wide numeric range selectable by the user. This enables a complex PLL multiplication ratio that can be used for translation between clock frequency standards. • Input clock frequency 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. Loop Filter Response Software CP also dampens VCXO input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where Online tools to calculate loop filter response can be found at www.idt.com/?app=calculators&source=support_menu. Graph of Charge Pump Current vs. Value of RSET (external resistor) ICP, Amps 1E-3 100E-6 10E-6 100E+3 1E+6 RSET, ohms Charge Pump Current, Example Settings from Above Graph RSET 5 MΩ 3 MΩ 2 MΩ 1 MΩ 480 kΩ Charge Pump Current (ICP) 25 μA 42 μA 65 μA 125 μA 255 μA 400 kΩ 300 μA Recommended Range of Operation 10E+6 µA to 300 µA. Below 25 µA, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from IDT, increasing charge pump current (ICP) increases both bandwidth and damping factor. Setting Charge Pump Current The recommended range for the charge pump current is 25 IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 7 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER VCXO Gain (KO) vs. XTAL Frequency V C X O G a in (K O ), H z p e r V o lt 6000 5000 4000 3000 2000 1000 10 15 20 25 30 C ry s ta l F re q u e n c y , M H z Setting the RPV, RV, FV and SV Divider Values in the VCXO PLL to maintain the same PLL frequency multiplication ratio. However, the phase detector frequency, FPD, also needs to be considered. FPD is equal to the input frequency divided by the value of the RPV x RV. FPD should be typically at least 20x the loop bandwidth to prevent loop modulation (phase noise) by the phase detector frequency. The phase detector jitter tolerance limit (use 0.4UI) and input phase noise frequency aliasing should be considerations as well. As shown in the loop bandwidth and damping factor equations on page 6, or by using the filter response software available from IDT, increasing FV or SV decreases both bandwidth and damping factor. Many applications require that SV = 1. In these cases, one way to decrease loop bandwidth is to increase the value of FV, which is accompanied by an increase in the value of RPV and/or RV Example Loop Filter Component Value FV Div CS CP Xtal Freq (MHz) SV Div VCLK (MHz) 8 kHz 19.44 1 19.44 2430 1 MΩ 560 kΩ 4.7 nF 22 Hz 8 kHz 19.44 1 19.44 2430 1 MΩ 560 kΩ 0.1 μF 4.7 nF 27 Hz 8 kHz 22.368 1 22.368 2796 1 MΩ 680 kΩ 1 μF 19.44 MHz 19.44 1 19.44 1 μF 128 RSET RS Phase Detector Frequency 1 MΩ 27 kΩ 1 μF Loop Loop BW Damp. (-3dB) Passband Peaking Note 4.0 0.15dB at 1Hz 1 1.4 1.2dB at 6Hz 2 4.7 nF 20 Hz 4.5 0.12dB at 1Hz 3 47 nF 0.85 1.8dB at 8Hz 4 25 Hz Notes: 1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander transfer requirements ( 50 pF (to avoid excessive error due to stray capacitance, which can be as much as 10 pF including Cin of LDC) Power Supply Considerations As with any integrated clock device, the MK2069-04 has a special set of power supply requirements: Lock Detector Application example: • The feed from the system power supply must be filtered for noise that can cause output clock jitter. Power supply noise sources include the system switching power supply or other system components. The noise can interfere with device PLL components such as the VCO or phase detector. The desired maximum allowable loop phase error for a generated 19.44 MHz clock is 100UI which is 5.1 μs. Solution: 5.1 μs = (0.001 μF) x (8.5 kΩ) • Each VDD pin must be decoupled individually to prevent power supply noise generated by one device circuit block from interfering with another circuit block. Under ideal conditions, where the VCXO is phase- locked to a low-jitter reference input, loop phase error is typically maintained to within a few nanoseconds. • Clock noise from device VDD pins must not get onto the PCB power plane or system EMI problems may result. This above set of requirements is served by the circuit illustrated in the Recommended Power Supply Connection (next page). The main features of this circuit are as follows: Lock Detection Circuit Diagram • Only one connection is made to the PCB power plane. • The capacitors and ferrite chip (or ferrite bead) on the L o c k D e te ctio n C irc u it FV D iv id e r O u tp u t Lock Q u a lific a tio n C o u n te r (8 u p , 1 d o w n ) common device supply form a lowpass ‘pi’ filter that remove noise from the power supply as well as clock noise back toward the supply. The bulk capacitor should be a tantalum type, 1 μF minimum. The other capacitors should be ceramic type. LD RESET VCXO Phase D e te c to r E rro r O u tp u t • The power supply traces to the individual VDD pins should fan out at the common supply filter to reduce interaction between the device circuit blocks. OEL LDR • The decoupling capacitors at the VDD pins should be LDC In p u t T h res h o ld se t to V D D /2 ceramic type and should be as close to the VDD pin as possible. There should be no via’s between the decoupling capacitor and the supply pin. RLD CLD If the lock detection circuit is not used, the LDR output may remain unconnected, however the LDC input should be tied high or low. If the PCB was designed to accommodate the IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 10 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER 0.01 µF 0.01 µF 1 nF BULK 0.1 µF Ferrite Chip 0.01 µF Connection Via to 3.3V Power Plane 0.01 µF Recommended Power Supply Connection Recommended Crystal Parameters: Crystal parameters can be found in application note MAN05 on www.idt.com. Approved crystals can be found at www.idt.com (search “crystal”). VDD Pin Crystal Tuning Load Capacitors The crystal traces should include pads for small capacitors from X1 and X2 to ground, shown as CL in the External VCXO PLL Components diagram on page 6. These capacitors are used to center the total load capacitor adjustment range imposed on the crystal. The load adjustment range includes stray PCB capacitance that varies with board layout. Because the typical telecom reference frequency is accurate to less than 32 ppm, the MK2069-04 may operate properly without these adjustment capacitors. However, IDT recommends that these capacitors be included to minimize the effects of variation in individual crystals, including those induced by temperature and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout, using the procedure described in MAN05. VDD Pin VDD Pin VDD Pin Series Termination Resistor PCB Layout Recommendations Output clock PCB traces over 1 inch should use series termination to maintain clock signal integrity and to reduce EMI. To series terminate a 50Ω trace, which is a commonly used PCB trace impedance, place a 33Ω resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please refer to the Recommended PCB Layout drawing on the following page. 1) Each 0.01µF decoupling capacitor (CD) should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite chip and bulk decoupling from the device is less critical. Quartz Crystal The MK2069-04 operates by phase-locking the VCXO circuit to the input signal at the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2069-04 incorporates variable load capacitors on-chip which “pull” or change the frequency of the crystal. The crystals specified for use with the MK2069-04 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. To achieve this, the layout should use short traces between the MK2069-04 and the crystal. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 3) The external crystal should be mounted as close the device as possible, on the component side of the board. This will keep the crystal PCB traces short which will minimize parasitic load capacitance on the crystal and as well as noise pickup. The crystal traces should be spaced away from each other and should use minimum trace width. 11 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER 4) Add a ground trace around the crystal circuit to shield from other active traces on the component layer. There should be no signal traces near the crystal or the traces. Also refer to the Optional Crystal Shielding section that follows. 4) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. The external crystal is particularly sensitive to other system clock sources that are at or near the crystal frequency since it will try to lock to the interfering clock source. The crystal should be keep away from these clock sources. 5) All components should be on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor may be mounted on the back). Other signal traces should be routed away from the MK2069-04. This includes signal traces on PCB traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. 6) Because each input selection pin includes an internal pull-up device, those inputs requiring a logic high state (“1”) can be left unconnected. The pins requiring a logic low state (“0”) can be grounded. Optional Crystal Shielding The crystal and connection traces to pins X1 and X2 are sensitive to noise pickup. In applications that especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-04 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. 1) The metal layer underneath the crystal section should be the ground layer. Remove all other layers that are above. This ground layer will help shield the crystal circuit from other system noise sources. As an alternative, all layers underneath the crystal can be removed, however this is not recommended if there are adjacent PCBs that can induce noise into the unshielded crystal circuit. 2) Cut a channel in the PCB ground plane around the crystal area as shown. This will eliminate high frequency ground currents that can couple into to crystal circuit. 3) Add a through-hole for the optional third lead offered by the crystal manufacturer (case ground). The requirement for this third lead can be made at prototype evaluation. The crystal is less sensitive to system noise interference when the case is grounded. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 12 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER Recommended PCB Layout Diagram SUPPLY SOURCE TO DEVICE (SUCH AS VIA TO SUPPLY PLANE) OPTIONAL CRYSTAL SHIELDING V SHIELD TRACE (TOP LAYER) CUT CHANNEL IN GROUND PLANE CE 603 G FC A G CL 603 G CL 603 CD 603 XTAL 53 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 G CD 603 CP 805 G 42 G G RSET 603 41 40 39 G 19 20 RS 603 38 37 21 22 36 35 23 24 34 33 25 26 32 31 27 28 G CD 603 G G RT 603 43 16 17 18 G 44 MK2069 15 G 55 54 5 14 G G 4 13 CS 1206 G 56 G 2 3 G G CBB 603 1 G G G CBD A CD 603 THRU HOLE FOR 3RD LEAD (XTAL CASE GROUND) RT 603 RLD 603 CLD 603 G 30 29 Components are identified by function (top line) and by typical package type (bottom line) which may vary. CP = External loop capacitor CP (film type) RS = External loop resistor RS RSET = Resistor RSET used to determine charge pump current RT = Series termination resistor for clock output, typical value 33 Ω RLD* = External resistor for lock detector circuit CLD* = External capacitor for lock detector circuit Legend: G = Via to PCB Ground plane V = Via to PCB Power Plane CE = EMI suppression cap, typical value 0.1 μF (ceramic) FC = Ferrite chip CBD = Bulk decoupling capacitor for chip power supply, 1 μF minimum (tantalum) CBB = Bulk bypass cap for chip power supply, typical value 1000 nF (ceramic) CD = Decoupling capacitor for VDD pin (ceramic) CL = Optional load capacitor for crystal tuning (do not stuff) CS = External loop capacitor CS (film type) IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR *Note: If output LD is not used, RLD and CLD may be omitted. See text on page 10. 13 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER Circuit Troubleshooting leakage. Refer to item 1.5 above. 1) IF TCLK or VCLK does not lock to ICLK 2.3) VCLK and TCLK jitter can also be caused by poor power supply decoupling. Ensure a bulk decoupling capacitor is in place. First check VCLK to ICLK. It is best to display and trigger the scope with RCLK, especially if a non-integer VCXO PLL multiplication ratio is used. 2.4) Ensure that the VCXO PLL loop bandwidth is sufficiently low. It should be at least 1/20th of the phase detector frequency. If VCLK is not locked to ICLK: 1.1) Ensure the proper ICLK input is selected. 2.5) Ensure that the VCXO PLL loop damping is sufficient. If should be at least 0.7, preferably 1.0 or higher. 1.2) Check RPV, RV, SV, FV Divider settings 1.3) Ensure ICLK is within lock range (within about 100 ppm of the nominal input frequency, limited by pull range of the external crystal). If in doubt, tweak the ICLK frequency up and down to see if VCLK locks. 2.6) Ensure that the 2nd pole in the VCXO PLL loop filter is set sufficiently. In general, CP should be equal to CS/20. If CP is too high, passband peaking will occur and loop instability may occur. If CP is set too low, excessive VCXO modulation by the charge correction pulses may occur. 1.4) Ensure ICLK jitter is not excessive. If ICLK jitter is excessive device may not lock. Also see item 2.1 below. 3) If There is Excessive Input to Output Skew 3.1) TCLK should track VCLK. The rising edge of TCLK should be within a few nanoseconds of VCLK. 1.5) Clean the PCB. The VCXO PLL loop filter is very sensitive to board leakage, especially when the VCXO PLL phase detector frequency is in the low kHz. If organic solder flux is used (most common today) scrub the PCB board with detergent and water and then blow and bake dry. Inorganic solder flux (Rosen core) requires solvent. See also section 3 below. 3.1) VCLK should track RCLK. The rising edge of VCLK should be within 5-10 nsec of RCLK (VCLK leads). 3.3) The biggest cause of input to output skew is VCXO PLL loop filter leakage. Skew is best observed by comparing ICLK to RCLK. When no leakage is present the rising edge of RCLK should lag the rising edge of ICLK by about 10 μsec. Loop filter leakage can greatly increase this lag time or cause the loop to not lock. Refer to item 1.5, above. 2) If There is Excessive Jitter on VCLK or TCLK 2.1) The problem may be an unstable input reference clock. An unstable ICLK will not appear to jitter when ICLK is used as the oscilloscope trigger source. In this condition, VCLK and TCLK may appear to be unstable since the jitter from ICLK (the trigger source) has been removed by the trigger circuit of the scope. 3.4) Another way to view the loop filter leakage is to observe LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. 2.2) The instability may be caused by VCXO PLL loop filter IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 14 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-04. These ratings, which are standard values for IDT industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured in respect to GND) IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Typ. 15 +3.15 +3.3 Max. Units +85 °C +3.45 V MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V 20 30 mA Operating Voltage VDD Supply Current IDD Input High Voltage, RPV1:0, RV11:0, FV11:0, SV1:0, FT2:0, ST1:0 VIH 2 VDD + 0.4 V Input Low Voltage, RPV1:0, RV11:0, FV11:0, SV1:0, FT2:0, ST1:0 VIL -0.4 0.8 V Input Pull-Up Resistor (Note 1) RPU Input High Voltage, CLR VIH VDD/2+1 VDD + 0.4 V Input High Voltage, ICLK (Note 2) VIH VDD/2+1 5.5 V Input Low Voltage, ICLK, CLR VIL -0.4 VDD/2-1 V Input High Current (Note 1) IIH VIH = VDD -10 +10 μA Input Low Current (Note 1) IIL VIL = 0 -10 +10 μA Input Capacitance, except X1 CIN Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 Output High Voltage VOH IOH = -8 mA 2.4 Output Low Voltage VOL IOL = 4 mA Output Short Circuit Current, TCLK IOS ±50 mA Output Short Circuit Current, VCLK, RCLK and LD IOS ±20 mA VIN, VCXO Control Voltage VXC All clock outputs loaded with 15 pF, VCLK = 19.44 MHz, TCLK = 155.52 MHz 200 kΩ 7 pF V V 0.4 0 VDD V V Note 1: All logic select inputs (RPV1:0, RV11:0, FV11:0, SV1:0, FT2:0, ST1:0, CLR) have an internal pull-up resistor. Note 2: ICLK can safely be brought to VIH max prior to the application of VDD, providing utility in hot-plug line card applications. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 16 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units Crystal Frequency Range (Note 1) fXTAL Using recommended crystal 13.5 27 MHz VCXO Crystal Pull Range fXP Using recommended crystal ±115 ±150 ppm VCXO Crystal Free-Run Frequency (Note 2) fXF Input reference = 0 Hz -300 -150 ppm Input Clock Frequency when RPV Divider = 8 (Note 3) fI 0.008 170 MHz Input Clock Frequency when RPV Divider = 1 (Note 3, 4) fI 0.002 160 MHz Input Clock Pulse Width tID VCXO PLL Phase Detector Frequency (Note 3) fPD VCXO PLL Phase Detector Jitter Tolerance tJT Translator PLL VCO Frequency fV Positive or Negative Pulse 10 nsec 0.001 1 UI = phase detector period 27 0.4 40 MHz UI 320 MHz Timing Jitter, Filtered 500 Hz-1.3 MHz (OC-3) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 95 ps Timing Jitter, Filtered 65 kHz-5 MHz (OC-3) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 85 ps Timing Jitter, Filtered 1 kHz-5 MHz (OC-12) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 105 ps Timing Jitter, Filtered 250 kHz-5 MHz (OC-12) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 80 ps Output Duty Cycle (% high time), VCLK when SV Divider = 1 tOD Measured at VDD/2, CL=15 pF 40 50 60 % Output Duty Cycle (% high time), VCLK when SV Divider > 1, TCLK tOD Measured at VDD/2, CL=15 pF 44 50 65 % Output High Time, RCLK (Note 5) tOH Measured at VDD/2, CL=15 pF IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 17 0.5 VCLK Period MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Parameter Symbol VCXO AND SYNTHESIZER Conditions Min. Typ. Max. Units Output Rise Time, VCLK and RCLK tOR 0.8 to 2.0 V, CL=15 pF 1.5 2 ns Output Fall Time, VCLK and RCLK tOF 2.0 to 0.8 V, CL=15 pF 1.5 2 ns Output Rise Time, TCLK tOR 0.8 to 2.0 V, CL=15 pF 0.75 1 ns Output Fall Time, TCLK tOF 2.0 to 0.8 V, CL=15 pF 0.75 1 ns Skew, ICLK to VCLK (Note 6) tIV Rising edges, CL=15 pF -5 2.5 +10 ns Skew, ICLK to RCLK (Note 6) tIV Rising edges, CL=15 pF +5 10 +20 ns Skew, ICLK to TCLK (Note 6) tVT Rising edges, CL=15 pF -5 1.5 +10 ns Nominal Output Impedance ZOUT Ω 20 Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may result in increased output phase noise. Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the attempt of the PLL to lock to 0 Hz. Note 3: The minimum practical phase detector frequency is 1 kHz. Through proper loop filter design lower input frequencies may be possible. Input frequencies as low as 400 Hz have been tested. Note 4: A higher input clock frequency can be used when RPV divider = 8. Note 5: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period. Note 6: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the external VCXO PLL loop filter. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 18 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER Package Outline and Package Dimensions (56-pin TSSOP 6.10 mm (240 mil) body, 0.50 mm. (20 mil) pitch) Package dimensions are kept current with JEDEC Publication No. 95 56 Millimeters Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Inches* Max Min -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 13.90 14.10 8.10 BASIC 6.00 6.20 0.50 Basic 0.45 0.75 0° 8° -0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.011 0.0035 0.008 0.547 0.555 0.319 BASIC 0.236 0.244 0.020 Basic 0.018 0.030 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A A 1 c -C e b S E A T IN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK2069-04GILF MK2069-04GILF Tubes 56-pin TSSOP -40 to +85° C MK2069-04GILFTR MK2069-04GILF Tape and Reel 56-pin TSSOP -40 to +85° C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instrument. IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 19 MK2069-04 REV J 051310 MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR VCXO AND SYNTHESIZER Innovate with IDT and accelerate your future networks. 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