DATASHEET
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
Description
Features
The MK2302-01 is a high performance Zero Delay Buffer
(ZDB) which integrates IDT’s proprietary analog/digital
Phase Locked Loop (PLL) techniques. The chip is part of
IDT’s ClockBlocksTM family and was designed as a
performance upgrade to meet today’s higher speed and
lower voltage requirements. The zero delay feature means
that the rising edge of the input clock aligns with the rising
edges of both output clocks, giving the appearance of no
delay through the device. There are two outputs on the chip,
one being a low-skew divide by two of the other output.
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The MK2302-01 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
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8-pin SOIC package
Available in Pb (lead) free package
Low input to output skew of 250 ps max
Absolute jitter ± 500 ps
Propagation Delay ± 350 ps
Ability to choose between different multipliers from 0.5X
to 16X
Output clock frequency up to 168 MHz at 3.3 V
Can recover degraded input clock duty cycle
Output clock duty cycle of 45/55
Full CMOS clock swings with 25mA drive capability at
TTL levels
Advanced, low power CMOS process
Operating voltage of 3.3 V or 5 V
Industrial temperature version available
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
IC L K
S 1 :0
F B IN
d ivid e
by N
P h a se
D e te cto r,
C h a rg e
Pum p,
and Loop
F ilte r
VCO
C LK1
/2
C LK2
E xte rn a l fe e d b a ck ca n co m e fro m C L K 1 o r C L K 2 (se e ta b le o n p a g e 2 )
IDT™ MULTIPLIER AND ZERO DELAY BUFFER
1
MK2302-01
REV F 122109
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Pin Assignment
FBIN
1
8
CLK2
ICLK
2
7
VDD
GND
3
6
CLK1
S0
4
5
S1
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table 1
(Multiplies Input clock by shown amount)
FBIN
S1
S0
CLK1
CLK2
CLK1
0
0
2 X ICLK
ICLK
CLK1
0
1
4 X ICLK
2 X ICLK
CLK1
1
0
ICLK
ICLK/2
CLK1
1
1
8 X ICLK
4 X ICLK
CLK2
0
0
4 X ICLK
2 X ICLK
CLK2
0
1
8 X ICLK
4 X ICLK
CLK2
1
0
2 X ICLK
ICLK
CLK2
1
1
16 X ICLK
8 XICLK
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
FBIN
ICLK
GND
S0
S1
CLK1
VDD
CLK2
Pin
Type
Input
Input
Power
Input
Input
Output
Power
Output
IDT™ MULTIPLIER AND ZERO DELAY BUFFER
Pin Description
Feedback clock input.
Reference clock input.
Connect to ground.
Select 0 for output clock per decoding table above. Pull-up.
Select 1 for output clock per decoding table above. Pull up.
Clock output per table above.
Connect to +3.3 V or +5.0 V.
Clock output per table above. Low skew divide by two of pin 6 clock.
2
MK2302-01
REV F 122109
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
External Components
The MK2302-01 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the part to minimize lead inductance. No external power supply filtering is required for this
device. A 33Ω series terminating resistor can be used next to each output pin.
Using CLK1 as the feedback will always result in synchronized rising edges between ICLK and CLK1. However, the
CLK2 could be a falling edge compared with ICLK. IDT recommends using CLK2 feedback whenever possible. This
will synchronize the rising edges of all three clocks.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2302-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-55 to 125° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Power Dissipation
0.5 W
Recommended Operation Conditions
Parameter
Min.
Max.
Units
0
+70
°C
Ambient Operating Temperature (industrial)
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+4.5
+5.0
+5.5
V
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
Ambient Operating Temperature (commercial)
IDT™ MULTIPLIER AND ZERO DELAY BUFFER
3
Typ.
MK2302-01
REV F 122109
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
DC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Symbol Conditions
Min.
Typ.
3.15
Max.
Units
3.45
V
Operating Voltage
VDD
Operating Current
IDD
Input High Voltage
VIH
ICLK, FBIN
Input Low Voltage
VIL
ICLK, FBIN
Input High Voltage
VIH
S0, S1
Input Low Voltage
(mid-level)
VIM
S0, S1
Input Low Voltage
VIL
S0, S1
Output High Voltage
(CMOS High)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
S0, S1
20
ma
2
V
0.8
V
VDD-0.5
V
VDD/2
V
0.5
V
0.4
V
±70
mA
5
pF
VDD = 5 V ±10%, Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Symbol Conditions
Typ.
4.5
Max.
Units
5.5
V
Operating Voltage
VDD
Operating Current
IDD
Input High Voltage
VIH
ICLK, FBIN
Input Low Voltage
VIL
ICLK, FBIN
Input High Voltage
VIH
S0, S1
Input Low Voltage
(mid-level)
VIM
S0, S1
Input Low Voltage
VIL
S0, S1
Output High Voltage (CMOS
High)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
S0, S1
IDT™ MULTIPLIER AND ZERO DELAY BUFFER
5V
Min.
30
ma
2
V
0.8
VDD-0.5
V
VDD/2
V
0.5
4
V
0.4
V
V
±100
mA
5
pF
MK2302-01
REV F 122109
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
AC Electrical Characteristics
VDD = 3.3 V or 5 V ±5%, Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Symbol
Conditions
Input Frequency, ICLK
FBIN from CLK/2
Output Clock Frequency
CLK1
Min.
Typ.
Max. Units
See table on page 2
10
Output to Output Skew
100
168
MHz
175
ps
200
ps
Input to Output Jitter
40 - 150 MHz
Input Skew
ICLK to FBIN,
CLK>30 MHz, Note 1
-300
300
ps
ICLK to FBIN,
CLK
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