Low Voltage PLL Clock Driver
MPC93R51
DATASHEET
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for
high performance clock distribution systems. With output frequencies of up to
240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal
solution for the most demanding clock tree designs. The device offers 9 low skew
clock outputs, each is configurable to support the clocking needs of the various
high-performance microprocessors including the PowerQuicc II integrated
communication microprocessor. The devices employ a fully differential PLL
design to minimize cycle-to-cycle and long-term jitter.
Features
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9 Outputs LVCMOS PLL Clock Generator
25–240 MHz Output Frequency Range
Fully Integrated PLL
Compatible to Various Microprocessors Such as PowerQuicc II
Supports Networking, Telecommunications and Computer Applications
Configurable Outputs: Divide-by-2, 4 and 8 of VCO Frequency
LVPECL and LVCMOS Compatible Inputs
External Feedback Enables Zero-Delay Configurations
Output Enable/Disable and Static Test Mode (PLL Enable/Disable)
Low Skew Characteristics: Maximum 150 ps Output-to-Output
Cycle-to-Cycle Jitter Max. 22 ps RMS
32-Lead LQFP Package
32-Lead Pb-Free Package Available
Ambient Temperature Range 0°C to +70°C
Pin and Function Compatible With the MPC951
For functional replacement use 8T49N285
MPC93R51
LOW VOLTAGE 3.3 V
PLL CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of
the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase
locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external
loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the
MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm2 32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
MPC93R51 REVISION 4 MARCH 14, 2016
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©2016 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
PCLK
PCLK
TCLK
(Pullup)
(Pulldown)
REF_SEL
(Pulldown)
EXT_FB
(Pulldown)
0
0
2
Ref
1
1
PLL
0
4
D
Q
QA
D
Q
QB
1
8
FB
0
200 – 480 MHz
1
PLL_EN
(Pullup)
QC0
0
FSELA
FSELB
(Pulldown)
FSELC
(Pulldown)
FSELD
(Pulldown)
D
Q
QC1
1
(Pulldown)
QD0
QD1
0
D
Q
QD2
1
QD3
QD4
OE
(Pulldown)
The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see Applications Information for details.
QC0
VCCO
QC1
GND
QD0
VCCO
QD1
GND
Figure 1. MPC93R51 Logic Diagram
24
23
22
21
20
19
18
17
GND
25
16
QD2
QB
26
15
VCCO
VCCO
27
14
QD3
QA
28
13
GND
GND
29
12
QD4
TCLK
30
11
VCCO
PLL_EN
31
10
OE
REF_SEL
32
MPC93R51
FSELA
FSELB
6
7
8
PCLK
EXT_FB
5
GND
4
FSELD
3
FSELC
2
VCCA
9
1
PCLK
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
MPC93R51 REVISION 4 MARCH 14, 2016
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©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Table 1. Pin Description
Number
Name
Type
Description
PCLK, PCLK
Input
LVPECL
Differential clock reference
Low voltage positive ECL input
TCLK
Input
LVCMOS
Single ended reference clock signal or test clock
EXT_FB
Input
LVCMOS
Feedback signal input, connect to a QA, QB, QC, QD output
REF_SEL
Input
LVCMOS
Selects input reference clock
FSELA
Input
LVCMOS
Output A divider selection
FSELB
Input
LVCMOS
Output B divider selection
FSELC
Input
LVCMOS
Outputs C divider selection
FSELD
Input
LVCMOS
Outputs D divider selection
OE
Input
LVCMOS
Output enable/disable
QA
Output
LVCMOS
Bank A clock output
QB
Output
LVCMOS
Bank B clock output
QC0, QC1
Output
LVCMOS
Bank C clock outputs
QD0 – QD4
Output
LVCMOS
Bank D clock outputs
VCCA
Supply
VCC
Positive power supply for the PLL
VCC
Supply
VCC
Positive power supply for I/O and core
GND
Supply
Ground
Negative power supply
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
Selects PCLK as reference clock
Selects TCLK as reference clock
PLL_EN
1
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
PLL enabled. The VCO output is routed to the
output dividers
OE
0
Outputs enabled
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
FSELA
0
QA = VCO 2
QA = VCO 4
FSELB
0
QB = VCO 4
QB = VCO 8
FSELC
0
QC = VCO 4
QC = VCO 8
FSELD
0
QD = VCO 4
QD = VCO 8
Table 3. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
4.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VCC+0.3
V
DC Input Current
20
mA
DC Output Current
50
mA
150
°C
VOUT
IIN
IOUT
TS
Storage Temperature
MPC93R51 REVISION 4 MARCH 14, 2016
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©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Table 4. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VCC 2
VTT
Output Termination Voltage
MM
ESD (Machine Model)
200
V
HBM
ESD (Human Body Model)
2000
V
LU
Latch-Up
200
mA
CPD
Power Dissipation Capacitance
CIN
Condition
V
10
pF
Per output
4.0
pF
Inputs
Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0° to 70°C)
Symbol
Characteristics
Min
VIH
Input High Voltage
VIL
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
250
Common Mode Range
PCLK, PCLK
1.0
VCMR(1)
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
IIN
Typ
2.0
Max
Unit
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
mV
LVPECL
V
LVPECL
V
IOH = –24 mA(2)
V
V
IOL = 24 mA
IOL = 12 mA
VCC–0.6
2.4
0.55
0.30
14 –17
Input Leakage Current
Condition
150
A
VIN = VCC or GND
ICCA
Maximum PLL Supply Current
3.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
7.0
10
mA
All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. The MPC93R51 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
MPC93R51 REVISION 4 MARCH 14, 2016
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©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0° to 70°C)(1)
Symbol
fref
Characteristics
Input Frequency(2)
Min
4 feedback
8 feedback
Static test mode
Typ
Max
Unit
50
25
0
120
60
300
MHz
MHz
MHz
200
480
MHz
100
50
25
240
120
60
MHz
MHz
MHz
25
75
%
Condition
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
fVCO
VCO Frequency
fMAX
Maximum Output Frequency(2)
frefDC
Reference Input Duty Cycle
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
Common Mode Range
PCLK, PCLK
1.2
VCC–0.9
V
LVPECL
1.0
ns
0.8 to 2.0 V
+150
+325
ps
ps
PLL locked
PLL locked
150
ps
55
52.5
51.75
%
%
%
1.0
ns
VCMR
tr, tf
(3)
(4)
t()
tsk(o)
2 output
4 output
8 output
TCLK Input Rise/Fall Time
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
-50
+25
Output-to-Output Skew
DC
Output Duty Cycle
tr, tf
Output Rise/Fall Time
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, ZH
Output Enable Time
6.0
ns
BW
PLL closed loop bandwidth
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
50
50
0.1
4 feedback
8 feedback
3.0 – 9.5
1.2 – 2.1
0.55 to 2.4 V
MHz
MHz
–3 db point of
PLL transfer characteristic
tJIT(CC)
Cycle-to-cycle jitter
4 feedback
Single Output Frequency Configuration
10
22
ps
RMS value
tJIT(PER)
Period Jitter
4 feedback
Single Output Frequency Configuration
8.0
15
ps
RMS value
ps
RMS value
tJIT()
I/O Phase Jitter
tLOCK
Maximum PLL Lock Time
4.0 – 17
1.0
ms
1. AC characteristics apply for parallel output termination of 50 to VTT.
2. The PLL will be unstable with a divide by 2 feedback ratio
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf
are within the specified range.
MPC93R51 REVISION 4 MARCH 14, 2016
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©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
APPLICATIONS INFORMATION
Programming the MPC93R51
The MPC93R51 clock driver outputs can be configured
into several divider modes. In addition, the external feedback
of the device allows for flexibility in establishing various input
to output frequency relationships. The output divider of the
four output groups allows the user to configure the outputs
into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
Table 7 illustrates the various output configurations. The
table describes the outputs using the input clock frequency
CLK as a reference.
The output division settings establish the output
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to
240 MHz while the VCO frequency range is specified from
200 MHz to 480 MHz and should not be exceeded for stable
operation.
Table 7. Output Frequency Relationship(1) for an Example Configuration
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC
QD
0
0
0
0
2 * CLK
CLK
CLK
CLK
0
0
0
1
2 * CLK
CLK
CLK
CLK 2
0
0
1
0
4 * CLK
2 * CLK
CLK
2* CLK
0
0
1
1
4 * CLK
2 * CLK
CLK
CLK
0
1
0
0
2 * CLK
CLK 2
CLK
CLK
0
1
0
1
2 * CLK
CLK 2
CLK
CLK 2
0
1
1
0
4 * CLK
CLK
CLK
2 * CLK
0
1
1
1
4 * CLK
CLK
CLK
CLK
1
0
0
0
CLK
CLK
CLK
CLK
1
0
0
1
CLK
CLK
CLK
CLK 2
1
0
1
0
2 * CLK
2 * CLK
CLK
2 * CLK
1
0
1
1
2 * CLK
2 * CLK
CLK
CLK
1
1
0
0
CLK
CLK 2
CLK
CLK
1
1
0
1
CLK
CLK 2
CLK
CLK 2
1
1
1
0
2 * CLK
CLK
CLK
2 * CLK
1
1
1
1
2 * CLK
CLK
CLK
CLK
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Using the MPC93R51 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC93R51. For these applications the MPC93R51 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC93R51 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC93R51 PLL
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge and virtually eliminates the propagation delay through
the device.
The remaining insertion delay (skew error) of the
MPC93R51 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
MPC93R51 REVISION 4 MARCH 14, 2016
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©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Table 8. Confidence Factor CF
fref = 100 MHz
QA
QB
TCLK
1
REF_SEL
1
1
0
0
0
PLL_EN
FSELA
FSELB
FSELC
FSELD
2 x 100 MHz
QC0
QC1
2 x 100 MHz
QD0
QD1
QD2
QD3
4 x 100 MHz
100 MHz (Feedback)
Figure 3. MPC93R51 Zero-Delay Configuration
(Feedback of QD4)
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
tSK(PP) = [-251ps...351ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC = 3.3 V (17 ps
RMS). I/O jitter is frequency dependent with a maximum at
the lowest VCO frequency (200 MHz for the MPC93R51).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 5 can be used to derive a smaller
I/O jitter number at the specific VCO frequency, resulting in
tighter timing limits in zero-delay mode and for part-to-part
skew tSK(PP).
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() · CF
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter.
Max. I/O Jitter versus frequency
TCLKCommon
tPD,LINE(FB)
—t(
30
tJIT() [ps] ms
25
tJIT()
Any QDevice 1
+tSK(O)
QFBDevice2
10
75
225
250
275
300
325
350
375
400
VCO frequency [MHz]
Figure 5. Max. I/O Jitter (RMS) Versus Frequency
for VCC = 3.3 V
+tSK(O)
Power Supply Filtering
The MPC93R51 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Noise on the VCCA (PLL) power supply impacts the device
characteristics, for instance, I/O jitter. The MPC93R51
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCCA) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
tSK(PP)
Figure 4. MPC93R51 Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter, a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Table 8. Confidence Factor CF
Probability of clock edge within the distribution
MPC93R51 REVISION 4 MARCH 14, 2016
15
0
tJIT()
Max. skew
20
5
+t()
CF
2
tSK(PP) = [-50ps...150ps] + [-150ps...150ps] +
[(17ps · –3)...(17ps ·3)] + tPD, LINE(FB)
Calculation of Part-to-Part Skew
The MPC93R51 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC93R51 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
Any QDevice 2
0.68268948
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –251 ps to 351 ps relative to TCLK (VCC = 3.3 V and
fVCO = 400 MHz):
QD4
Ext_FB
MPC93R51
QFBDevice 1
1
7
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93R51.
Figure 6 illustrates a typical power supply filter scheme.
The MPC93R51 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor RF. From the data sheet, the ICCA current (the current
sourced through the VCCA pin) is typically 3 mA (5 mA
maximum), assuming that a minimum of 3.0 V must be
maintained on the VCCA pin. The resistor RF shown in
Figure 6 must have a resistance of 5-15 to meet the
voltage drop criteria.
MPC93R51 REVISION 4 MARCH 14, 2016
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©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
VCC
LOW VOLTAGE PLL CLOCK DRIVER
RF
MPC93R51
OUTPUT
BUFFER
VCCA
22 pF
0.1 F
MPC93R51
IN
VCC
14
RS = 36
ZO = 50
RS = 36
ZO = 50
RS = 36
ZO = 50
OutA
0.1 F
MPC93R51
OUTPUT
BUFFER
OutB0
Figure 6. VCCA Power Supply Filter
IN
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
OutB1
Figure 7. Single versus Dual Transmission Lines
The waveform plots in Figure 8 show the simulation results
of an output driving a single line versus two lines. In both
cases, the drive capability of the MPC93R51 output buffer is
more than sufficient to drive 50 transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93R51. The output
waveform in Figure 8 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36 series
resistor, plus the output impedance, does not match the
parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
Driving Transmission Lines
The MPC93R51 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R51 clock driver. For the series
terminated case, however, there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 7 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93R51 clock
driver is effectively doubled due to its capability to drive
multiple lines.
MPC93R51 REVISION 4 MARCH 14, 2016
14
VL = VS (Z0 (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 (25 (18+17+25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
9
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 9 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
3.0
VOLTAGE (V)
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
MPC93R51
OUTPUT
BUFFER
1.0
RS = 22
ZO = 50
RS = 22
ZO = 50
14
0.5
0
2
4
6
8
TIME (ns)
10
12
14
14+ 22 || 22 = 50 || 50
25 = 25
Figure 9. Optimized Dual Line Termination
Figure 8. Single versus Dual Waveforms
MPC93R51 DUT
Pulse
Generator
Z = 50
ZO = 50
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 10. CLK MPC93R51 AC Test Reference for VCC = 3.3 V
Differential Pulse
Generator
Z = 50
ZO = 50
MPC93R51 DUT
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 11. PCLK MPC9R351 AC Test Reference
MPC93R51 REVISION 4 MARCH 14, 2016
10
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
PCLK
VCC
VCMR
VCMR
PCLK
VCC 2
TCLK
GND
VCC
VCC 2
Ext_FB
VCC
VCC 2
Ext_FB
GND
GND
t()
t()
Figure 12. Propagation Delay (tPD, Static Phase
Offset) Test Reference
Figure 13. Propagation Delay (tPD) Test Reference
VCC
VCC
VCC 2
VCC 2
GND
GND
tP
VCC
VCC 2
T0
GND
DC = tP/T0 x 100%
tSK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
Figure 14. Output Duty Cycle (DC)
Figure 15. Output-to-Output Skew tSK(O)
TN
TN+1
TJIT(CC) = |TN–TN+1|
T0
TJIT(PER) = |TN–1/f0|
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
Figure 16. Cycle-to-Cycle Jitter
Figure 17. Period Jitter
TCLK
(PCLK)
VCC=3.3 V
Ext_FB
2.4
TJIT() = |T0–T1mean|
0.55
tF
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
Figure 18. I/O Jitter
MPC93R51 REVISION 4 MARCH 14, 2016
tR
Figure 19. Transition Time Test Reference
11
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
4
1
NRND – Not Recommend for New Designs
12/20/12
4
1
Removed replacement part from features list.
1/31/13
4
1
Product Discontinuation Notice - Last time buy expires September 7, 2016.
PDN N-16-02
3/14/16
MPC93R51 REVISION 4 MARCH 14, 2016
12
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
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