3.3 V 1:8 LVCMOS PLL Clock Generator
MPC9653A
NRND
NRND – Not Recommend for New Designs
DATASHEET
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 125 MHz and output skews less than 150 ps the
device meets the needs of the most demanding clock applications.
MPC9653A
Features
•
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1:8 PLL based low-voltage clock generator
Supports zero-delay operation
3.3 V power supply
Generates clock signals up to 125 MHz
PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
Maximum output skew of 150 ps
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32-lead LQFP packaging
32-lead Pb-free Package Available
Ambient temperature range 0C to +70C
Pin and function compatible to the MPC953 and MPC9653
NRND – Not Recommend for New Designs
LOW VOLTAGE
3.3 V LVCMOS 1:8
PLL CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
The MPC9653A utilizes PLL technology to frequency lock its outputs onto an
input reference clock. Normal operation of the MPC9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the
reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The
two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine
the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653A is running
at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a low power PLL mode in the high
frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25 MHz.
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use
as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes
the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close
the phase locked loop, enabling the PLL to recover to normal operation.
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission
lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an
effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.
MPC9653A REVISION 4 JANUARY 8, 2013
1
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
VCC
Q0
225 k
PCLK
PCLK
&
Ref
VCO
0
0
1
0
1
2
1
4
1
Q2
Q3
PLL1
200-500 MHz
VCC
Q1
Q4
25 k
Q5
FB_IN
VCC
FB
Q6
325 k
Q7
PLL_EN
QFB
VCO_SEL
BYPASS
MR/OE
25 k
Note 1. PLL will lock @ 145 MHz
Q1
VCC
Q2
GND
Q3
VCC
Q4
GND
Figure 1. MPC9653A Logic Diagram
24
23
22
21
20
19
18
17
GND
25
16
Q5
Q0
26
15
VCC
VCC
27
14
Q6
QFB
28
13
GND
GND
29
12
Q7
PLL_EN
30
11
VCC
BYPASS
31
10
MR/OE
VCO_SEL
32
9
PCLK
FB_IN
NC
NC
5
6
7
8
PCLK
4
GND
3
NC
2
NC
1
VCC_PLL
MPC9653A
Figure 2. MPC9653A 32-Lead Package Pinout (Top View)
MPC9653A REVISION 4 JANUARY 8, 2013
2
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
Table 1. Pin Configuration
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
PECL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
VCO_SEL
Input
LVCMOS
Operating frequency range select
BYPASS
Input
LVCMOS
PLL and output divider bypass select
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
Q0–7
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
Clock output for PLL feedback, connect to FB_IN
GND
Supply
Ground
Negative power supply (GND)
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for
the analog power supply pin VCC_PLL. Refer to APPLICATIONS INFORMATION for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply
for correct operation
Table 2. Function Table
Control
Default
0
1
output(1)
PLL_EN
1
Test mode with PLL bypassed. The reference clock (PCLK) Selects the VCO
is substituted for the internal VCO output. MPC9653A is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9653A is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not
applicable.
Selects the output dividers.
VCO_SEL
1
VCO 1 (High frequency range). fREF = fQ0–7 = 4 fVCO
VCO 2 (Low output range). fREF = fQ0–7 = 8 fVCO
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset the PLL feedback loop is open.
The VCO is tied to its lowest frequency. The length of the
reset pulse should be greater than one reference clock
cycle (PCLK).
1. PLL operation requires BYPASS = 1 and PLL_EN = 1.
MPC9653A REVISION 4 JANUARY 8, 2013
3
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VCC 2
Condition
VTT
Output Termination Voltage
V
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch-Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
4.0
pF
Inputs
Table 4. Absolute Maximum Ratings(1)
Symbol
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.9
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
DC Output Voltage
–0.3
VCC + 0.3
V
DC Input Current
20
mA
DC Output Current
50
mA
125
C
VOUT
IIN
IOUT
TS
Characteristics
Storage Temperature
–65
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)
Symbol
Characteristics
VIH
Input high voltage
VIL
Input low voltage
VPP
VCMR
(1)
(PCLK)
300
Common Mode Range
(PCLK)
1.0
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output impedance
Input Current
Typ
2.0
Peak-to-peak input voltage
VOH
IIN
Min
Maximum PLL Supply Current
ICCQ(4)
Maximum Quiescent Supply Current
Unit
V
LVCMOS
0.8
V
LVCMOS
mV
LVPECL
V
LVPECL
V
IOH = –24 mA(2)
V
V
IOL = 24 mA
IOL = 12 mA
VCC – 0.6
2.4
0.55
0.30
5.0
Condition
14 – 17
(3)
ICC_PLL
Max
VCC + 0.3
200
A
VIN = VCC or GND
10
mA
VCC_PLL Pin
10
mA
All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. The MPC9653A is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. The
MPC9653A meets the VOH and VOL specification of the MPC953 (VOH > VCC -0.6 V at IOH = -20 mA and VOL > 0.6 V at IOL = 20 mA).
3. Inputs have pull-down or pull-up resistors affecting the input current.
4. OE/MR = 1 (outputs in high-impedance state).
MPC9653A REVISION 4 JANUARY 8, 2013
4
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)(1)
Symbol
fREF
fVCO
fVCOlock
Characteristics
Min
feedback(2)
4
8 feedback(3)
Input reference frequency in PLL bypass mode(4)
Input Reference Frequency
PLL Mode, External Feedback
VCO Operating Frequency
VCO Lock Frequency
Range(5), (6)
Range(7)
Typ
Max
Unit
50
25
125
62.5
MHz
MHz
0
200
MHz
200
500
MHz
145
500
MHz
4
8 feedback(3)
50
25
125
62.5
MHz
MHz
PLL locked
PLL locked
mV
LVPECL
V
LVPECL
Output Frequency
VPP
Peak-to-Peak Input Voltage
PCLK
450
1000
Common Mode Range
PCLK
1.2
VCC – 0.75
VCMR
tPW, MIN
Input Reference Pulse Width(9)
2
ns
t()
Propagation Delay (static phase offset)(10)
PCLK to FB_IN
–75
125
ps
tPD
Propagation Delay
PLL and divider bypass (BYPASS = 0), PCLK to Q0–7
PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0–7
1.2
3.0
3.3
7.0
ns
ns
Output-to-Output Skew(11)
150
ps
tsk(PP)
Device-to-Device Skew in PLL and Divider Bypass(12)
1.5
ns
BYPASS = 0
55
%
PLL locked
1.0
ns
0.55 to 2.4 V
Output Duty Cycle
45
tR, tF
Output Rise/Fall Time
0.1
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, LZ
Output Enable Time
6.0
ns
tJIT(CC)
Cycle-to-Cycle jitter
100
ps
tJIT(PER)
Period Jitter
100
ps
tJIT()
BW
tLOCK
9.
10.
11.
12.
13.
14.
PLL locked
tsk(O)
DC
1.
2.
3.
4.
5.
6.
7.
8.
PLL locked
PLL locked
feedback(2)
fMAX
(8)
Condition
(13)
I/O Phase Jitter
PLL closed loop bandwidth(14)
PLL mode, external feedback
RMS (1)
4 feedback(2)
8 feedback(3)
Maximum PLL Lock Time
50
25
ps
0.8 – 4
0.5 – 1.3
MHz
MHz
10
ms
AC characteristics apply for parallel output termination of 50 to VTT.
4 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
8 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0.
In bypass mode, the MPC9653A divides the input reference clock.
The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO FB.
fVCO is frequency range where AC parameters are guaranteed.
fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN.
For example, at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
Valid for fREF = 50 MHz and FB = 8 (VCO_SEL = 1). For other reference frequencies: t() [ps] = 50 ps (1 (120 fREF)).
Refer to the Application Information section for part-to-part skew calculation in PLL zero-delay mode.
For a specified temperature and voltage, includes output skew.
I/O phase jitter is reference frequency dependent. Refer to APPLICATIONS INFORMATION section for details.
–3 dB point of PLL transfer characteristics.
MPC9653A REVISION 4 JANUARY 8, 2013
5
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
Programming the MPC9653A
The MPC9653A supports output clock frequencies from 25
to 125 MHz. Two different feedback divider configurations
can be used to achieve the desired frequency operation
range. The feedback divider (VCO_SEL) should be used to
situate the VCO in the frequency lock range between 200 and
500 MHz for stable and optimal operation. Two operating
frequency ranges are supported: 25 to 62.5 MHz and 50 to
125 MHz. Table 7 illustrates the configurations supported by
the MPC9653A. PLL zero-delay is supported if BYPASS = 1,
PLL_EN = 1 and the input frequency is within the specified
PLL reference frequency range.
Table 7. MPC9653A Configurations (QFB connected to FB_IN)
Frequency
BYPASS
PLL_EN
VCO_SEL
Operation
0
X
X
Test mode: PLL and divider bypass
1
0
0
Test mode: PLL bypass
1
0
1
Test mode: PLL bypass
1
1
0
1
1
1
Ratio
Output Range (fQ0–7)
VCO
fQ0–7 = fREF
0 – 200 MHz
n/a
fQ0–7 = fREF 4
0 – 50 MHz
n/a
fQ0–7 = fREF 8
0 – 25 MHz
n/a
PLL mode (high frequency range)
fQ0–7 = fREF
50 to 125 MHz
fVCO = fREF 4
PLL mode (low frequency range)
fQ0–7 = fREF
25 to 62.5 MHz
fVCO = fREF 8
Power Supply Filtering
The MPC9653A is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCCA_PLL power supply impacts the
device characteristics, for instance I/O jitter. The MPC9653A
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCCA_PLL) of the device. The
purpose of this design technique is to isolate the high
switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simple but effective form of isolation is a power supply
filter on the VCC_PLL pin for the MPC9653A. Figure 3
illustrates a typical power supply filter scheme. The
MPC9653A frequency and phase stability is most susceptible
to noise with spectral content in the 100 kHz to 20 MHz
range. Therefore, the filter should be designed to target this
range. The key parameter that needs to be met in the final
filter design is the DC voltage drop across the series filter
resistor RF. From the data sheet the ICCA current (the current
sourced through the VCC_PLL pin) is typically 5 mA (10 mA
maximum), assuming that a minimum of 2.985 V must be
maintained on the VCC_PLL pin.
RF = 5–15
VCC
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3, the filter cut-off frequency is around
4 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9653A has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9653A in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9653A. Designs using the MPC9653A as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9653A clock driver allows for its use as a zero-delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or longterm jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
CF = 22 F
RF
VCC_PLL
CF
10 nF
MPC9653A
VCC
33...100 nF
Figure 3. VCC_PLL Power Supply Filter
MPC9653A REVISION 4 JANUARY 8, 2013
6
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
Calculation of Part-to-Part Skew
The MPC9653A zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9653As are connected together, the maximum overall
timing uncertainty from the common PCLK input to any output
is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –197 ps to 297 ps (at 125 MHz reference frequency)
relative to PCLK:
tSK(PP) = [-17ps...117ps] + [-150ps...150ps] +
[(10ps @ -3)...(10ps @ 3)] + tPD, LINE(FB)
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
PCLKCommon
Due to the frequency dependence of the I/O jitter,
Figure 5, can be used for a more precise timing performance
analysis.
tPD,LINE(FB)
30
3I/O Jitter [ps] RMS
—t(ý)
QFBDevice 1
tSK(PP) = [-197ps...297ps] + tPD, LINE(FB)
tJIT()
Any QDevice 1
+tSK(O)
Any QDevice 2
FB = 4
Figure 4. MPC9653A Maximum Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Table 8. Confidence Factor CF
Probability of clock edge within the distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
45
55
65
75
85 95 105 115 125
Reference Frequency [MHz]
Driving Transmission Lines
The MPC9653A clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50 resistance to VCC 2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9653A clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 5, illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC9653A clock
driver is effectively doubled due to its capability to drive
multiple lines.
tSK(PP)
CF
35
Figure 5. Maximum I/O Jitter versus Frequency
+tSK(O)
MPC9653A REVISION 4 JANUARY 8, 2013
FB = 8
25
tJIT()
Max. skew
10
0
+t()
QFBDevice2
20
7
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
3.0
MPC9653A
Output
Buffer
In
RS = 36
14
OutA
tD = 3.8956
2.5
ZO = 50
OutB
tD = 3.9386
OutA
MPC9653A
Output
Buffer
In
RS = 36
Voltage (V)
2.0
ZO = 50
OutB0
In
1.5
1.0
14
RS = 36
ZO = 50
0.5
OutB1
0
2
Figure 6. Single versus Dual Transmission Lines
8
Time (ns)
10
12
14
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 8, should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC9653A
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
VS (Z0 (RS + R0 + Z0))
50 || 50
36 || 36
14
3.0 (25 (18 + 14 + 25)
1.31 V
14 + 22 || 22 = 50 || 50
25 = 25
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Differential
Pulse Generator
Z = 50
6
Figure 7. Single versus Dual Waveforms
The waveform plots in Figure 7 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9653A output
buffer is more than sufficient to drive 50 transmission lines
on the incident edge. Note from the delay measurements in
the simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9653A. The output
waveform in Figure 7 shows a step in the waveform, this step
is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36 series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL =
Z0 =
RS =
R0 =
VL =
=
4
Figure 8. Optimized Dual Line Termination
MPC9653A DUT
ZO = 50
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 9. MPC9653A AC Test Reference
MPC9653A REVISION 4 JANUARY 8, 2013
8
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
VCC
VCC 2
PCLK
GND
VCC
VCC 2
VPP = 0.8 V
PCLK
VCMR =
VCC –1.3 V
FB_IN
VCC
VCC 2
GND
tSK(O)
GND
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
t(PD)
Figure 11. Propagation delay (t(PD), static phase
offset) Test Reference
Figure 10. Output-to-Output Skew tSK(O)
VCC
VCC 2
PCLK
PCLK
GND
tP
Ext_FB
T0
DC = tP/T0 x 100%
TJIT() = |T0–T1mean|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t0 for a controlled edge with respect to a T0
mean in a random sample of cycles
Figure 13. I/O Jitter
Figure 12. Output Duty Cycle (DC)
TN
TN+1
TJIT(CC) = |TN–TN+1|
TJIT(PER) = |TN–1/f0|
T0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
Figure 14. Cycle-to-Cycle Jitter
Figure 15. Period Jitter
VCC = 3.3 V
2.4
0.55
tF
tR
Figure 16. Output Transition Time Test
Reference
MPC9653A REVISION 4 JANUARY 8, 2013
9
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
PACKAGE DIMENSIONS
4X
0.20 H
6
A-B D
D1
PIN 1 INDEX
3
e/2
D1/2
32
A, B, D
25
1
E1/2 A
F
B
6 E1
E
4
F
DETAIL G
8
17
9
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
4
D
4X
A-B D
H
SEATING
PLANE
DETAIL G
D
D/2
0.20 C
E/2
28X
e
32X
C
0.1 C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
b
8X
(θ1˚)
0.20
R R2
A2
5
8
C A-B D
SECTION F-F
R R1
A
M
0.25
GAUGE PLANE
A1
(S)
L
(L1)
θ˚
DETAIL AD
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
q
q1
R1
R2
S
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0˚
7˚
12 REF
0.08
0.20
0.08
--0.20 REF
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC9653A REVISION 4 JANUARY 8, 2013
10
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
Revision History Sheet
Rev
4
Table
Page
1
Description of Change
Date
NRND – Not Recommend for New Designs
1/8/13
MPC9653A REVISION 4 JANUARY 8, 2013
11
©2013 Integrated Device Technology, Inc.
MPC9653A Data Sheet
3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR
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