MPC97H74AE

3.3 V 1:14 LVCMOS PLL Clock Generator MPC97H74 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 The MPC97H74 is a 3.3 V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications. DATASHEET MPC97H74 Features • • • • • • • • • • • • • • 1:14 PLL based low-voltage clock generator 3.3 V power supply Internal power-on reset Generates clock signals up to 125 MHz Maximum output skew of 175 ps Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Drives up to 28 clock lines Ambient temperature range -40°C to +85°C Pin and function compatible to the MPC974 52-lead Pb-free Package For drop in replacement part use 87974 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 848D-03 The MPC97H74 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC97H74 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H74 features frequency programmability between the three output bank outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC97H74 has an internal power-on reset. The MPC97H74 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. MPC97H74 REVISION 5 MARCH 16, 2016 1 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Bank A All input resistors have a value of 25 k VCC CCLK0 0 CCLK1 VCO Ref 1 CCLK_SEL 0 2 0 1 4 1 QA0 QA1 CLK Stop  2,  4  2, 4 PLL QA2 QA3  4, 6 QA4 4, 6,  8, 12 Bank B VCC QB0 QB1 CLK Stop FB FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QB2 QB3 QB4 2 Bank C CLK Stop VCC QC0 QC1 QC2 QC3 CLK_STOP POWER-ON RESET VCC QFB MR/OE NC VCC QFB GND FB_IN QB4 VCC QB3 GND QB2 VCC QB1 GND Figure 1. MPC97H74 Logic Diagram QB0 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 VCC VCC 41 25 QA0 NC 42 24 GND GND 43 23 QA1 QC3 44 22 VCC VCC 45 21 QA2 QC2 46 20 FSEL_FB1 GND 47 19 GND QC1 48 18 QA3 VCC 49 17 VCC QC0 50 16 QA4 GND 51 15 GND VCO_SEL 52 14 FSEL_FB0 CLK_STOP FSEL_B FSEL_C PLL_EN 8 9 10 11 12 13 VCC_PLL GND 7 NC 6 VCC 5 CCLK1 4 CCLK0 3 FSEL_A 2 CCLK_SEL 1 MR/OE MPC97H74 Figure 2. MPC97H74 52-Lead Package Pinout (Top View) MPC97H74 REVISION 5 MARCH 16, 2016 2 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configuration Pin I/O Type Function CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock FB_IN Input LVCMOS PLL feedback signal input, connect to QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL enable/PLL bypass mode select MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset CLK_STOP Input LVCMOS Output enable/clock stop (logic low state) FSEL_A Input LVCMOS Frequency divider select for bank A outputs FSEL_B Input LVCMOS Frequency divider select for bank B outputs FSEL_C Input LVCMOS Frequency divider select for bank C outputs FSEL_FB[1:0] Input LVCMOS Frequency divider select for the QFB output QA[4:0] Output LVCMOS Clock outputs (bank A) QB[4:0] Output LVCMOS Clock outputs (bank B) QC[3:0] Output LVCMOS Clock outputs (bank C) QFB Output LVCMOS PLL feedback output. Connect to FB_IN. GND Supply Ground Negative power supply VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2. Function Table (MPC97H74 Configuration Controls) Control Default 0 1 CCLK_SEL 0 Selects CCLK0 as PLL reference signal input Selects CCKL1 as PLL reference signal input VCO_SEL 0 Selects VCO  2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Selects VCO  4. The VCO frequency is scaled by a factor of 4 (low input frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is Normal operation mode with PLL enabled. substituted for the internal VCO output. MPC97H74 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. CLK_STOP 1 QA, QB an QC outputs disabled in logic low state. QFB is not Outputs enabled (active) affected by CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse to be distorted. MR/OE 1 Outputs disabled (high-impedance state) and reset of the device. Outputs enabled (active) During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC97H74 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios. Refer to Table 3 and Table 4 for the device frequency configuration. Table 3. Function Table (Output Dividers Bank A, B, and C) VCO_SEL FSEL_A QA[4:0] VCO_SEL FSEL_B QB[4:0] VCO_SEL FSEL_C 0 0 VCO  4 0 0 VCO  4 0 0 VCO  8 0 1 VCO  8 0 1 VCO  8 0 1 VCO  12 1 0 VCO  8 1 0 VCO  8 1 0 VCO  16 1 1 VCO  16 1 1 VCO  16 1 1 VCO  24 MPC97H74 REVISION 5 MARCH 16, 2016 3 QC[3:0] ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 4. Function Table (QFB) VCO_SEL FSEL_B1 FSEL_B0 QFB 0 0 0 VCO  8 0 0 1 VCO  16 0 1 0 VCO  12 0 1 1 VCO  24 1 0 0 VCO  16 1 0 1 VCO  32 1 1 0 VCO  24 1 1 1 VCO  48 Table 5. General Specifications Symbol Characteristics Min Typ Max Unit VCC  2 VTT Output Termination Voltage MM ESD protection (Machine Model) 200 V HBM ESD protection (Human Body Model) 2000 V 200 Condition V LU Latch-Up Immunity CPD Power Dissipation Capacitance 12 mA pF Per output CIN Input Capacitance 4.0 pF Inputs Table 6. Absolute Maximum Ratings(1) Symbol Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V DC Input Current 20 mA DC Output Current 50 mA 125 C VOUT IIN IOUT TS Characteristics Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 7. DC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to +85°C) Symbol Characteristics Min Typ Max Unit Condition VCC_PLL PLL Supply Voltage 3.02 VCC V LVCMOS VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VOH Output High Voltage V IOH = –24 mA(1) VOL Output Low Voltage V V IOL = 24 mA IOL = 12 mA ZOUT Output Impedance IIN ICC_PLL ICCQ Input 2.4 0.55 0.30  8 – 11 Current(2) Maximum PLL Supply Current 5.0 Maximum Quiescent Supply Current 200 A VIN = VCC or GND 7.5 mA VCC_PLL Pin 8.0 mA All VCC Pins 1. The MPC97H74 is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines. 2. Inputs have pull-down or pull-up resistors affecting the input current. MPC97H74 REVISION 5 MARCH 16, 2016 4 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 8. PLL Frequency Ranges (VCC = 3.3 V ± 5%) Symbol TA = -40°C to +85°C Characteristics fVCO VCO Frequency Lock Range(1) fREF Input Reference Frequency Range 8 feedback 12 feedback 16 feedback 24 feedback 32 feedback 48 feedback Input Reference Frequency Range in PLL Bypass Mode(2) fMAX Output Frequency Range 4 output 8 output 12 output 16 output 24 output TA = 0°C to +70°C Unit Condition Min Max Min Max 210 450 200 500 MHz 26.250 17.500 13.125 8.750 6.5625 4.375 56.250 37.500 28.125 18.750 14.0625 9.375 25.0 16.6 12.5 8.33 6.25 4.16 62.50 41.60 31.25 20.83 15.625 10.41 MHz MHz MHz MHz MHz MHz PLL locked 0 250 0 250 MHz PLL bypass 52.500 26.250 17.500 13.125 8.750 112.500 56.250 37.500 28.125 18.750 50.00 25.00 16.60 12.50 8.33 125.0 62.50 41.60 31.25 20.83 MHz MHz MHz MHz MHz PLL locked 1. The input reference frequency must match the VCO frequency lock range divided by the total feedback divider ratio (FB): fREF = fVCO(M  VCO_SEL). 2. In bypass mode, the MPC97H74 divides the input reference clock. Table 9. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40°C to +85°C)(1) Symbol tPW,MIN tR, tF t() tSK(O) DC Characteristics Min Input Reference Pulse Width(2) Typ Propagation Delay (static phase offset)(3) CCLKx to FB_IN (FB = 8 and fREF = 50 MHz) –250 within QA bank within QB bank within QC bank any output Output Duty Cycle 47 0.1 Unit 50 1.0 ns 0.8 to 2.0 V +100 ps PLL locked 100 125 100 175 ps ps ps ps 53 % tR, tF Output Rise/Fall Time 1.0 ns tPLZ, HZ Output Disable Time 10 ns tPZL Output Enable Time 10 ns Cycle-to-cycle Jitter(5) 90 ps 90 ps 15 49 18 22 26 34 ps ps ps ps ps ps tJIT(CC) tJIT(PER) tJIT() BW tLOCK Period Jitter (4) I/O Phase Jitter RMS (1 )(6) FB = 8 FB = 12 FB = 16 FB = 24 FB =  32 FB = 48 PLL Closed Loop Bandwidth(7) FB = 8 FB = 12 FB = 16 FB = 24 FB = 32 FB = 48 0.50 - 1.80 0.30 - 1.00 0.25 - 0.70 0.17 - 0.40 0.12 - 0.30 0.07 - 0.20 Maximum PLL Lock Time Condition ns CCLKx Input Rise/Fall Time Output-to-output Skew(4) Max 2.0 0.55 to 2.4 V MHz MHz MHZ MHz MHz MHz 10 ms 1. AC characteristics apply for parallel output termination of 50  to VTT. 2. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN  fREF  100% and DCREF,MAX = 100% – DCREF, MIN. E.g. at fREF = 62.5 MHz the input duty cycle range is 12.5% < DC < 87.5%. 3. Static phase offset depends on the reference frequency: t() = +50 ps  (1 (120  fREF)) for any reference frequency. 4. Refer to Application section for part-to-part skew calculation. 5. Valid for all outputs at the same fequency. 6. I/O jitter for fVCO = 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for confidence factors other than 1 . 7. –3 dB point of PLL transfer characteristics. MPC97H74 REVISION 5 MARCH 16, 2016 5 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR APPLICATIONS INFORMATION MPC97H74 Configurations Configuring the MPC97H74 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: The PLL post-divider VCO_SEL is either a divide-by-two or a divide-by-four and can be used to situate the VCO into the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and the output divider: fQA[4:0] = fVCO  (VCO_SEL  NA) fQB[4:0] = fVCO  (VCO_SEL  NB) fQC[3:0] = fVCO  (VCO_SEL  NC) fOUT = fREF  M  N fREF VCO_SEL PLL fOUT N M Table 10. MPC97H74 Dividers where fREF is the reference frequency of the selected input clock source (CCLKO or CCLK1), M is the PLL feedback divider and N is a output divider. M is configured by the FSEL_FB[0:1] and N is individually configured for each output bank by the FSEL_A, FSEL_B and FSEL_C inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 500 MHz (210 to 450 MHz for industrial temperature range) in order to achieve stable PLL operation: fVCO,MIN  (fREF  VCO_SEL  M)  fVCO,MAX Divider Function VCO_SEL Values M PLL feedback FSEL_FB[0:1] 2 8, 12, 16, 24 4 16, 24, 32, 48 NA Bank A Output Divider FSEL_A 2 4, 8 4 8, 16 NB Bank B Output Divider FSEL_B 2 4, 8 4 8, 16 NC Bank C Output Divider FSEL_C 2 8, 12 4 16, 24 Table 10 shows the various PLL feedback and output dividers. The output dividers for the three output banks allow the user to configure the outputs into 1:1, 2:1, 3:2, and 3:2:1 frequency ratios. Figure 3 and Figure 4 display example configurations for the MPC97H74: fREF = 20.83 MHz CCLK0 CCLK1 0 CCLK_SEL QA[4:0] 125 MHz 0 VCO_SEL FB_IN QB[4:0] 62.5 MHz QC[3:0] 62.5 MHz 0 1 0 11 FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] fREF = 25 MHz CCLK0 CCLK1 0 CCLK_SEL QA[4:0] 100 MHz 0 VCO_SEL FB_IN QB[4:0] 50 MHz QC[3:0] 33.3 MHz 0 1 1 01 QFB FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QFB MPC97H74 MPC97H74 20.83 MHz (Feedback) 25 MHz (Feedback) MPC97H74 example configuration (feedback of QFB = 25 MHz, VCO_SEL =2, M = 8, NA = 2, NB = 4, NC = 6, fVCO = 400 MHz). MPC97H74 example configuration (feedback of QFB = 20.83 MHz, VCO_SEL = 2, M = 12, NA = 2, NB = 4, NC = 4, fVCO = 500 MHz). TA = 0°C to 70°C Frequency Range Min Max Frequency Range TA = 0°C to +70°C TA = -40°C to +85°C Input 8.33 MHz 20.83 MHz Input 12.50 - 31.25 MHz 13.125 - 28.125 MHz QA outputs 50 MHz 125 MHz QA outputs 50.00 - 125.0 MHz 52.50 - 112.5 MHz QB outputs 25 MHz 62.5 MHz QB outputs 25.00 - 62.50 MHz 26.25 - 56.25 MHz QC outputs 25 MHz 62.5 MHz QC outputs 16.67 - 41.67 MHz 17.50 - 37.50 MHz Figure 3. Example Configuration MPC97H74 REVISION 5 MARCH 16, 2016 Figure 4. Example Configuration 6 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Using the MPC97H74 in Zero-Delay Applications Nested clock trees are typical applications for the MPC97H74. Designs using the MPC97H74 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback of the MPC97H74 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Table 11. Confidence Factor CF CF Probability of Clock Edge Within The Distribution  1 0.68268948  2 0.95449988  3 0.99730007  4 0.99993663  5 0.99999943  6 0.99999999 Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 6. MPC97H74 I/O Jitter and Figure 7. MPC97H74 I/O Jitter to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation a I/O jitter confidence factor of 99.7 percent ( 3 ) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of –470 ps to +320 ps relative to CCLK (PLL feedback = 8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 15 ps rms max., static phase offset t() = –250 ps to +100 ps): Calculation of Part-to-Part Skew The MPC97H74 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC97H74 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()  CF tSK(PP) = [–250 ps...+100 ps] + [–175 ps...175 ps] + [(15 ps  –3)...(15 ps  3)] + tPD, LINE(FB) This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: tSK(PP) = [–470 ps...+320 ps] + tPD, LINE(FB) Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB QFBDevice 1 100 tPD, LINE(FB) —t() tjit() [ps] RMS CCLKCommon tJIT() Any QDevice 1 250 300 350 400 VCO Frequency (MHz) 450 500 Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB tSK(O) tjit() [ps] RMS tSK(PP) Figure 5. MPC97H74 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a rms value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 11. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. MPC97H74 REVISION 5 MARCH 16, 2016 FB = 8 Figure 6. MPC97H74 I/O Jitter tJIT() Max. Skew FB =  16 40 0 200 +t() Any QDevice 2 FB = 32 60 20 tSK(O) QFBDevice2 80 160 140 FB12 120 100 FB48 80 60 FB24 40 20 0 200 250 300 350 400 VCO Frequency (MHz) 450 500 Figure 7. MPC97H74 I/O Jitter 7 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Driving Transmission Lines The MPC97H74 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20  the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50  resistance to VCC divided by 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC97H74 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8. Single versus Dual Transmission Lines illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC97H74 clock driver is effectively doubled due to its capability to drive multiple lines. combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = VS ( Z0  (RS + R0 + Z0)) 50  || 50  40  || 40  10  3.0 ( 25  (20 + 10 + 25) 1.36 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.7 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 Voltage (V) In 1.5 1.0 0.5 MPC97H74 Output Buffer IN 10  0 RS = 40  2 ZO = 50  4 6 8 10 12 14 Time (ns) OutA Figure 9. Single versus Dual Waveforms MPC97H74 Output Buffer IN RS = 40  ZO = 50  RS = 40  ZO = 50  Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10. Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutB0 10  OutB1 Figure 8. Single versus Dual Transmission Lines MPC97H74 Output Buffer The waveform plots in Figure 9. Single versus Dual Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC97H74 output buffer is more than sufficient to drive 50  transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC97H74. The output waveform in Figure 9. Single versus Dual Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 40  series resistor plus the output impedance does not match the parallel MPC97H74 REVISION 5 MARCH 16, 2016 RS = 30  ZO = 50  RS = 30  ZO = 50  10  10  + 30  || 30  = 50  || 50  25  = 25  Figure 10. Optimized Dual Line Termination 8 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Power Supply Filtering The MPC97H74 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC97H74 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC97H74. Figure 11. VCC_PLL Power Supply Filter illustrates a typical power supply filter scheme. The MPC97H74 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 5 mA (7.5 mA maximum), assuming that a minimum of 3.02 V (VCC_PLL, minimum) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 11. VCC_PLL Power Supply Filter must have a resistance of 5 – 15  to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 11. VCC_PLL Power Supply Filter, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. CF = 22 F RF = 5–15 VCC RF VCC_PLL CF 10 nF MPC97H74 VCC 33...100 nF Figure 11. VCC_PLL Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC97H74 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. MPC97H74 DUT Pulse Generator Z = 50  Z = 50  Z = 50  RT = 50  RT = 50  VTT VTT Figure 12. CCLK MPC97H74 AC Test Reference MPC97H74 REVISION 5 MARCH 16, 2016 9 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR VCC VCC 2 VCC GND VCC 2 CCLKx VCC VCC 2 GND GND VCC VCC 2 FB_IN tSK(O) GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t() Figure 13. Output-to-Output Skew tSK(O) Figure 14. Propagation Delay (t(), Static Phase Offset) Test Reference VCC VCC 2 CCLKx GND tP FB_IN t0 DC = tP/t0 x 100% tJIT(ý) = |t0 – t1mean| The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 16. I/O Jitter Figure 15. Output Duty Cycle (DC) tN tN+1 tJIT(CC) = |tN – tN + 1| tJIT(PER) = |tN – (1  f0)| t0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle-to-Cycle Jitter Figure 18. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 19. Output Transition Time Test Reference MPC97H74 REVISION 5 MARCH 16, 2016 10 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR PACKAGE DIMENSIONS 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 40 1 CL 39 AB G 3X VIEW Y -L- -M- AB B B1 13 V VIEW Y BASE METAL F PLATING V1 27 14 J 26 U -N- A1 D 0.13 (0.005) M T L-M S N S S1 SECTION AB-AB A ROTATED 90˚ CLOCKWISE S 4X θ2 C 0.10 (0.004) T - 4X θ3 TING NE VIEW AA 0.05 (0.002) S W 2X R θ1 R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA CASE 848D-03 ISSUE D 52-LEAD LQFP PACKAGE MPC97H74 REVISION 5 MARCH 16, 2016 11 NOTES: 1. CONTROLLING DIMENSIONS: MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSTION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Revision History Sheet Rev 5 5 Table Page Description of Change Date 1 NRND – Not Recommend for New Designs 1/9/13 1 Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02 3/16/16 MPC97H74 REVISION 5 MARCH 16, 2016 12 ©2016 Integrated Device Technology, Inc. MPC97H74 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support clocks@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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