Audio, Power Management
and Control
P95020
Preliminary Datasheet
KEY FEATURES
OVERVIEW
The P95020 is designed to provide maximum flexibility to
system designers by providing full customization and
programmability. It is the first of a new generation of
standardized
application-specific
controllers
that
incorporates a general purpose microcontroller, a high
fidelity audio CODEC including headphone outputs and a
2.5W Class D audio amplifier, full power management
functionality, a touch screen controller and a real time
clock all of which are required by portable consumer
devices such as cellular phone handsets, portable gaming
devices, digital media players, portable navigational
devices, etc.
The general purpose microcontroller controls the device
power-on/power-off sequencing and can also be used for
general system housekeeping.
The P95020 includes two I²C Interfaces, a master for
communicating with an external EEPROM and a slave for
communicating with the host.
The high fidelity audio CODEC along with headphone
outputs and the 2.5 watt Class D audio speaker amplifier
comprise a total audio solution for portable applications.
The switch-mode EnergyPath™ Battery Charger operates
with its own high efficiency buck regulator to transmit the
2.5 watts available from a USB port to the system with
minimal wasted power. It can also handle up to 2A from a
wall charger.
Its power management features along with switch-mode
converters and LDOs should be sufficient to provide power
for even the most complex hand-held devices.
The integrated touch screen controller allows adding touch
screen capability to devices at significantly reduced cost.
It also includes IDT‟s high quality, low power real time
clock.
APPLICATIONS
Master Controller during Power Up & Power-Down
• Initialization and power sequencing
Dynamic Power Management via I²C bus interface
Up to 10 General Purpose I/Os available
General house keeping for P95020 and other devices
Audio Features
4 Channel CODEC with 24-bit resolution and internal
registers for status and control
Integrated 2.5 Watt Mono Class D Amplifier
with Filterless Operation.
Stereo cap-less headphone driver
Differential Analog Audio Line Inputs
Dual Mode Microphone Inputs (Analog or DMIC)
Battery Charging Circuit
Autonomous Li-Ion/Li-Poly charger up to 1.5A
• Automatic Load Prioritization
• Advanced Battery Safety features
High efficiency switch-mode *EnergyPath™ controller
USB or Wall-mounted Charging
• Programmable Current Limit
• Automatic end-of-charge control
Internal 180 m ideal diode with external
ideal diode controller
Power Management Features
All Converters:
• Power up/down sequence field reprogrammable with
external EEPROM
• Dynamic voltage scaling
• Host or I2C output enable / disable
Buck DC-DC PWM converters with PFM mode
• Two at 500mA, 0.75V to 3.7V
• One at 1000mA, 0.75V to 3.7V
Boost DC-DC converters
• One at 1.5 A peak on inductor, 4.05V to 5.0V
• One LED supply with 2 W total output power
Two programmable current sinks, @ 25mA each
Voltage limited to rating of external FET & diode
Linear Regulators
• Three LDOs at 150mA, 0.75V to 3.7V
• Four LDOs at 50mA, 0.7V to 3.7V
• One always-on LDO at 10mA, 3.3 or 3.0V
ADC and Touch Screen Controller
Smart Phones
Portable Gaming Device
Digital Media Players
Portable Navigational Devices
Revision 0.7.10
Quick Turn Customization
Embedded Microcontroller
4-wire touch screen interface
One direct battery measurement channel
One direct VSYS measurement channel
One direct charge current measurement channel
On-Chip temperature measurement
Four auxiliary analog input channels (shared with GPIO
pins)
Touch pressure measurement
Sample rate: 62.5k SPS
12 bit resolution, DNL: -1~+2 LSB, INL: +-2
On-chip 2.5V reference
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©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
BLOCK DIAGRAM
Thermal Sensor
Power-On-Reset
SW_DET
I2C Slave I/F
To
External Processor
Audio Codec
Bus Arbitrator
Pin MUX
Real Time Clock
10 GPIOs
1.5K Byte
Program
RAM
Micro
Controller
4K Byte
Code Space
ROM
ADC
Touch Screen
Controller
Interrupt
Controller
WatchDog
LED_BOOST
LED Backlight P/S
with 2 Current Sinks
Hot Swap
Switches
Headphone Amp
&
CLASS_D Amp
Interrupt Manager
PLL
&
Clock Synthesizer
Battery
Charger
I2C Master
Interface
To external
EEPROM
LDO_150_2 (150mA)
LDO_150_1 (150mA)
LDO_150_0 (150mA)
LDO_050_3 (50mA)
LDO_050_2 (50mA)
LDO_050_1 (50mA)
LDO_050_0 (50mA)
LDO_LP (10mA)
BUCK1000 (1000 mA DC-DC)
BUCK500_1 (500mA DC-DC)
BUCK500_0 (500mA DC-DC)
BOOST5 (5V DC-DC)
Figure 1 – P95020 Block Diagram.
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P95020 / Preliminary Datasheet
TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................................................. 1
APPLICATIONS ...................................................................................................................................................................... 1
KEY FEATURES ..................................................................................................................................................................... 1
BLOCK DIAGRAM .................................................................................................................................................................. 2
PIN ASSIGNMENTS ............................................................................................................................................................... 7
PIN FUNCTIONS BY PIN NUMBER ....................................................................................................................................... 9
I/O LEVELS BY TYPE ........................................................................................................................................................... 14
ABSOLUTE MAXIMUM RATINGS........................................................................................................................................ 15
RECOMMENDED OPERATING CONDITIONS ................................................................................................................... 16
DIGITAL INTERFACES - DC ELECTRICAL CHARACTERISTICS ..................................................................................... 16
I2C MASTER - ELECTRICAL CHARACTERISTICS ............................................................................................................ 16
I2C SLAVE - ELECTRICAL CHARACTERISTICS ............................................................................................................... 16
I2S - ELECTRICAL CHARACTERISTICS ............................................................................................................................ 16
GPIO - ELECTRICAL CHARACTERISTICS ......................................................................................................................... 16
AUDIO POWER CONSUMPTION ........................................................................................................................................ 17
1.0
OVERVIEW .............................................................................................................................................................. 18
1.1 FUNCTIONAL MODES ............................................................................................................................................ 19
1.2 REGISTER MAP ...................................................................................................................................................... 20
1.3 BYTE ORDERING AND OFFSET ........................................................................................................................... 21
1.4 REGISTER ACCESS TYPES .................................................................................................................................. 21
1.5 RESERVED BIT FIELDS ......................................................................................................................................... 21
2.0
AUDIO MODULE ..................................................................................................................................................... 22
2.1 AUDIO - PIN DEFINITIONS ..................................................................................................................................... 22
2.2 AUDIO - SECTION OVERVIEW .............................................................................................................................. 23
2.3 AUDIO - ANALOG PERFORMANCE CHARACTERISTICS ................................................................................... 23
2.4 AUDIO - MICROPHONE INPUT PORT ................................................................................................................... 24
2.5 AUDIO - ANALOG LINE INPUT ............................................................................................................................... 27
2.6 AUDIO - DAC, ADC ................................................................................................................................................. 27
2.7 AUDIO - AUTOMATIC GAIN CONTROL ................................................................................................................. 28
2.8 AUDIO - ANALOG MIXER BLOCK .......................................................................................................................... 28
2.9 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE ....................................................................................... 29
2.10
AUDIO - REFERENCE VOLTAGE GENERATOR, BUFFER, & FILTERING CAPS .......................................... 31
2.11
AUDIO - ANALOG AND CLASS D OUTPUT BLOCK ......................................................................................... 31
2.12
AUDIO - CLASS-D BTL AMPLIFIER ................................................................................................................... 32
2.13
AUDIO CLASS_D - REGISTERS ........................................................................................................................ 32
2.14
AUDIO CLASS_D - EQUALIZER COEFFICIENT & PRESCALER RAM (EQRAM) ........................................... 39
2.15
AUDIO – AUDIO CONTROL REGISTERS ......................................................................................................... 40
3.0
CHARGER MODULE ............................................................................................................................................... 52
3.1 CHARGER - OVERVIEW ......................................................................................................................................... 52
3.2 CHARGER – SUB-BLOCKS .................................................................................................................................... 52
3.3 CHARGER – DC ELECTRICAL CHARACTERISTICS ........................................................................................... 53
3.4 CHARGER – TYPICAL PERFORMANCE CHARACTERISTICS ............................................................................ 54
3.5 CHARGER - REGISTER ADDRESSES .................................................................................................................. 55
3.6 CHARGER - PRE-REGULATOR ............................................................................................................................. 58
3.7 IDEAL DIODE FROM VBAT TO VSYS ......................................................................................................................... 59
3.8 CHARGER - CHARGER/DISCHARGER ................................................................................................................. 60
3.9 CHARGER - THERMAL MONITORING .................................................................................................................. 60
3.10
CHARGER - POWER ON RESET....................................................................................................................... 60
4.0
CLOCK GENERATOR MODULE ............................................................................................................................ 61
4.1 CKGEN - PIN DEFINITIONS ................................................................................................................................... 61
4.2 CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS ................................................................ 62
4.3 CKGEN - PLL CONTROL ........................................................................................................................................ 63
4.4 CKGEN – OSCILLATOR CIRCUIT .......................................................................................................................... 63
4.5 CKGEN - CKGEN POWER SOURCE ..................................................................................................................... 63
4.6 CKGEN – CLOCK ACCURACY ............................................................................................................................... 63
4.7 CKGEN – CLOCK GENERATOR REGISTERS ...................................................................................................... 64
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P95020 / Preliminary Datasheet
5.0
5.1
5.2
5.3
5.4
5.5
5.6
6.0
6.1
6.2
7.0
8.0
8.1
8.2
8.3
8.4
8.5
8.6
9.0
9.1
9.2
9.3
9.4
9.5
9.6
9.7
10.0
10.1
10.2
10.3
10.4
10.5
11.0
11.1
11.2
11.3
11.4
11.5
11.6
12.0
12.1
12.2
12.3
12.4
13.0
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14.0
14.1
14.2
14.3
14.4
15.0
15.1
15.2
15.3
RTC MODULE ......................................................................................................................................................... 66
RTC - GENERAL DESCRIPTION ............................................................................................................................ 66
RTC - TIMEKEEPER REGISTERS ......................................................................................................................... 67
RTC - DATE REGISTERS ....................................................................................................................................... 67
RTC - ALARM REGISTERS .................................................................................................................................... 68
RTC - INTERRUPT REGISTERS ............................................................................................................................ 69
RTC RESERVED REGISTERS ............................................................................................................................... 70
GENERAL PURPOSE TIMERS ............................................................................................................................... 71
GENERAL PURPOSE TIMERS – GENERAL DESCRIPTION................................................................................ 71
GENERAL PURPOSE TIMERS – REGISTERS ...................................................................................................... 71
DC_DC MODULE .................................................................................................................................................... 74
2MHz, 500mA & 1000mA SYNCHRONOUS BUCK REGULATORS ...................................................................... 75
BUCK1000 & BUCK500 - PIN DEFINITIONS.......................................................................................................... 76
BUCK1000 & BUCK500 - ELECTRICAL CHARACTERISTICS .............................................................................. 76
BUCK CONVERTERS – TYPICAL PERFORMANCE CHARACTERISTICS .......................................................... 77
BUCK1000 & BUCK500 - REGISTER ADDRESSES .............................................................................................. 79
BUCK1000 & BUCK500 - ENABLING & DISABLING ............................................................................................. 80
BUCK1000 & BUCK500 - APPLICATIONS INFORMATION ................................................................................... 81
HIGH EFFICIENCY 10 LED BOOST CONVERTER AND SINKS ........................................................................... 83
LED_BOOST - ELECTRICAL CHARACTERISTICS ............................................................................................... 84
LED_BOOST – TYPICAL PERFORMANCE CHARACTERISTICS ........................................................................ 84
LED_BOOST - REGISTER SETTINGS ................................................................................................................... 85
LED_BOOST - ENABLING & DISABLING .............................................................................................................. 86
LED_BOOST – Over-Voltage Protection ................................................................................................................. 87
LED_BOOST – Over-Current Limiter ....................................................................................................................... 87
LED_BOOST - APPLICATIONS INFORMATION .................................................................................................... 87
BOOST5 – 1.5A, SYNCHRONOUS PWM BOOST CONVERTER ......................................................................... 89
BOOST5 - ELECTRICAL CHARACTERISTICS.................................................................................................. 90
BOOST5 - REGISTER SETTINGS...................................................................................................................... 90
BOOST5 - ENABLING & DISABLING ................................................................................................................. 91
OUTPUT DIODE .................................................................................................................................................. 92
BOOST5 - APPLICATIONS INFORMATION ...................................................................................................... 92
CLASS_D BTL POWER OUTPUT STAGE ............................................................................................................. 93
CLASS_D - ELECTRICAL CHARACTERISTICS ................................................................................................ 93
CLASS_D – TYPICAL PERFORMANCE CHARACTERISTICS ......................................................................... 94
CLASS_D – REGISTER SETTINGS ................................................................................................................... 94
CLASS_D - AUDIO INTERFACE AND DECODE ............................................................................................... 95
CLASS_D - SHORT CIRCUIT PROTECTION CIRCUITRY ............................................................................... 95
CLASS_D - APPLICATIONS INFORMATION ..................................................................................................... 95
TSC MODULE - ADC AND TOUCH SCREEN CONTROLLER .............................................................................. 96
ADC AND TOUCH SCREEN CONTROLLER ELECTRICAL CHARACTERISTICS .......................................... 97
ADC AND TOUCH SCREEN CONTROLLER PIN DEFINITIONS ...................................................................... 97
ADC AND TOUCH SCREEN CONTROLLER OPERATION ............................................................................... 97
ADC AND TOUCH SCREEN CONTROLLER REGISTERS ............................................................................. 100
PCON MODULE – POWER CONTROLLER AND GENERAL PURPOSE I/O ..................................................... 107
GPIO PIN DEFINITIONS ................................................................................................................................... 107
POWER STATES .............................................................................................................................................. 107
POWER SEQUENCING BY EMBEDDED MICROCONTROLLER ................................................................... 107
POWER ON RESET OUTPUT (POR_OUT) ..................................................................................................... 108
POWER SWITCH DETECTOR (SW_DET) ....................................................................................................... 108
GPIO GENERAL DESCRIPTION ...................................................................................................................... 108
PCON REGISTERS ........................................................................................................................................... 108
HOTSWAP MODULE ............................................................................................................................................. 113
HOT SWAP (LOAD SWITCHES) – ELECTRICAL CHARACTERISTICS ......................................................... 113
HOTSWAP – TYPICAL PERFORMANCE CHARACTERISTICS ..................................................................... 114
HOTSWAP – PIN DEFINITIONS ....................................................................................................................... 115
PCON REGISTER - HOTSWAP CONFIGURATION ........................................................................................ 115
I2C_I2S MODULE .................................................................................................................................................. 116
I2C_I2S - PIN DEFINITIONS ............................................................................................................................. 116
I²C SLAVE.......................................................................................................................................................... 116
INTERRUPT DISPATCHER .............................................................................................................................. 117
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15.4
ACCESS ARBITER ........................................................................................................................................... 117
15.5
DIGITAL AUDIO DATA SERIAL INTERFACE .................................................................................................. 117
15.6
I2C_I2S – INTERFACE TIMING ........................................................................................................................ 118
15.7
GLOBAL REGISTER SETTINGS (I²C-page 0) ................................................................................................. 120
15.8
ACCM REGISTERS .......................................................................................................................................... 123
16.0
LDO MODULE ....................................................................................................................................................... 124
16.1
LDO - PIN DEFINITIONS .................................................................................................................................. 125
16.2
LDO - LDO_150 & LDO_050 ELECTRICAL CHARACTERISTICS .................................................................. 125
16.3
LDO – TYPICAL PERFORMANCE CHARACTERISTICS ................................................................................ 126
16.4
LDO - LDO_LP - ELECTRICAL CHARACTERISTICS ...................................................................................... 127
16.5
LDO - LIST OF ALL LDOS ................................................................................................................................ 127
16.6
LDO – REGISTER SETTINGS .......................................................................................................................... 127
17.0
EMBUP – EMBEDDED MICROCONTROLLER SUBSYSTEM & I/O.................................................................... 131
17.1
OVERVIEW ........................................................................................................................................................ 131
17.2
FUNCTIONAL DESCRIPTION .......................................................................................................................... 131
17.3
ON-CHIP RAM & ROM ...................................................................................................................................... 131
17.4
I²C SLAVE INTERFACE .................................................................................................................................... 131
17.5
PERIPHERALS .................................................................................................................................................. 132
17.6
INTERRUPT CONTROLLER ............................................................................................................................. 132
18.0
APPLICATIONS INFORMATION ........................................................................................................................... 133
18.1
EXTERNAL COMPONENTS ............................................................................................................................. 133
18.2
DIGITAL LOGIC DECOUPLING CAPACITORS ............................................................................................... 133
18.3
CLASS_D CONSIDERATIONS ......................................................................................................................... 133
18.4
SERIES TERMINATION RESISTORS .............................................................................................................. 133
18.5
I²C EXTERNAL RESISTOR CONNECTION ..................................................................................................... 133
18.6
CRYSTAL LOAD CAPACITORS ....................................................................................................................... 133
18.7
PCB LAYOUT CONSIDERATIONS................................................................................................................... 133
18.8
POWER DISSIPATION AND THERMAL REQUIREMENTS ............................................................................ 133
18.9
TYPICAL BLOCK PERFORMANCE CHARACTERISTICS GRAPHS .............................................................. 133
18.10 APPLICATIONS REFERENCE DESIGN(S) ...................................................................................................... 134
19.0
SOLDERING PROFILE.......................................................................................................................................... 134
20.0
PACKAGE OUTLINE DRAWING ........................................................................................................................... 134
20.1
LLG124 PACKAGE OUTLINE ........................................................................................................................... 134
20.2
NQG132 PACKAGE OUTLINE (Exposed Die Paddle Size D2 = E2 = 5.5 mm) ............................................... 135
21.0
ORDERING INFORMATION.................................................................................................................................. 135
TABLE OF FIGURES
Figure 1 – P95020 Block Diagram. ......................................................................................................................................... 2
Figure 2 – P95020 Pinout Diagram (LLG124) ........................................................................................................................ 7
Figure 3 – P95020 Pinout (NGQ132) ..................................................................................................................................... 8
Figure 4 – Overall System Functional Diagram. ................................................................................................................... 18
Figure 5 – Audio Block Diagram ........................................................................................................................................... 22
Figure 6 –Stereo Digital Microphone (Mode 3) ..................................................................................................................... 26
Figure 7 –Stereo Digital Microphone (Mode 1 & 2)............................................................................................................... 27
Figure 8 – Automatic Gain Control ........................................................................................................................................ 28
Figure 9 – Charger Block Diagram ....................................................................................................................................... 52
Figure 10 – Pre-Regulator Efficiency vs Load Current VBUS = 5.0V, VSYS = 3.7V............................................................ 54
Figure 11– Pre-Regulator Load Regulation VBUS = 5.0V, VSYS = 3.7V ............................................................................ 55
Figure 12 – Battery Charge Current vs Temperature ........................................................................................................... 55
Figure 13 – VSYS Regulation Curve (Tracking VBAT ) ............................................................................................................. 59
Figure 14 – Clock Generator Block Diagram ........................................................................................................................ 61
Figure 15 DC_DC Block Diagram ......................................................................................................................................... 74
Figure 16 – BUCK500 / BUCK1000 Block Diagram ............................................................................................................. 76
Figure 17 – BUCK500 DC-DC Regulator Efficiency vs Load Current PWM Mode .............................................................. 78
Figure 18 – BUCK1000 DC-DC Regulator Efficiency vs Load Current PWM Mode ............................................................ 78
Figure 19 – BUCK500 DC-DC Regulator Efficiency vs Load Current PFM Mode ................................................................ 79
Figure 20 – BUCK500 or BUCK 1000 Applications Diagram ............................................................................................... 81
Figure 21 – White LED Boost & Sink Driver Block Diagram ................................................................................................. 83
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P95020 / Preliminary Datasheet
Figure 22 – LED Boost Efficiency vs Load Current (two srings of 10 LEDs) ........................................................................ 84
Figure 23 – LED Boost Efficiency vs VIN (two srings of 10 LEDs) ....................................................................................... 85
Figure 24 – LED_BOOST Application Schematic ................................................................................................................. 87
Figure 25 – BOOST5 Block Diagram .................................................................................................................................... 89
Figure 26 – BOOST5 Applications Diagram ......................................................................................................................... 92
Figure 27 – Clss D BTL Efficiency vs Outpout Power (4 ohm speaker) ............................................................................... 94
Figure 28 – ADC & Touchscreen Controller Block Diagram ................................................................................................. 96
Figure 29 – Hotswap Block Diagram .................................................................................................................................. 113
Figure 30 – Hotswap #1 ON Resistance vs Temperature .................................................................................................. 114
Figure 31 – Hotswap #2 ON Resistance vs Temperature .................................................................................................. 114
2
Figure 32 – I C Read / Write Operation .............................................................................................................................. 117
Figure 33 – LDO_050 / LDO_150 Block Diagram ............................................................................................................... 124
Figure 34 – LDO_050_n 50mA LDO Load Regulation ....................................................................................................... 126
Figure 35 – LDO_150_n 150mA LDO Load Regulation ..................................................................................................... 126
Figure 36 - Top level Interrupt routing ................................................................................................................................. 132
Figure 37 – Power Derating Curve (Typical) ....................................................................................................................... 133
LIST OF TABLES
Table 1 – LLG124 Pin Functions by Pin Number (See Figure 2) ........................................................................................... 9
Table 2 - NQG132 Pin Functions by Pin Number (see Figure 3) ......................................................................................... 11
Table 3 – Register Address Global Mapping ........................................................................................................................ 20
Table 4 - Valid Digital Mic Configurations ............................................................................................................................. 25
Table 5 - MCLK Rate selection: MCLK_DIV2: MCLK_RATE .............................................................................................. 29
Table 6 – MCLK/Sample Rate .............................................................................................................................................. 30
Table 7 - EQRAM Addresses ................................................................................................................................................ 39
Table 8 – Register 0xA090 (0x90) Current Limit (I_LIM) Settings Bits [2:0] ........................................................................ 56
Table 9 – Register 0xA091, (0x91) Charging Maximum Voltage (CHG_VOL) Settings, Bits [5:4] ..................................... 56
Table 10 – Register 0xA091, (0x91) Charging Current Limit via Sense Resistor (CHG_CUR) Settings, Bits [3:0] ........... 56
Table 11 – Register 0xA092 (0x92) Charging Termination Time (CHG_TERM) Settings Bits [1:0] .................................... 56
Table 12 – Register 0xA093 (0x93) Battery Recovery Charge Current Control Settings Bits [7:5] ...................................... 57
Table 13 – Register 0xA093, (0x93) Battery Good Voltage Threshold Settings, Bits [4:3] .................................................. 57
Table 14 – Register 0xA095, (0x95) Current Charger Mode Settings, Bits [4:3] .................................................................. 57
Table 15 - Crystal Specifications........................................................................................................................................... 63
Table 16 - Alarm mask bits ................................................................................................................................................... 66
Table 17 – DC-DC Block Registers (Including the CLASS_D BTL Power Bridge) ............................................................... 74
Table 18 – BUCK500_0, BUCK500_1 and BUCK1000 Register Addresses ....................................................................... 79
Table 19 – Output Voltage Register Settings, Bits [6:0] ....................................................................................................... 79
Table 20 – Control Register Cycle by Cycle Current Limit (I_LIM) Settings for Bits [3:2] [Note ] ......................................... 80
Table 21 – Interoperability of enabling/disabling methods vs. loading default values. ......................................................... 80
Table 22 – Register 0xA086 (0x86) IOUT Current Settings for Bits [4:0], Half Scale and Full Scale ................................... 85
Table 23 – Interoperability of enabling/disabling methods vs. loading default values. ......................................................... 86
Table 24 – Register 0xA088 Output Voltage Bit Setting [4:0] ............................................................................................... 90
Table 25 – Register 0xA089 (0x89) Peak Current Limit (I_LIM) Settings Bits [3:2] .............................................................. 91
Table 26 – Interoperability of enabling/disabling methods vs. loading default values. ......................................................... 91
Table 27 – Peak Short Circuit Detect Level Settings for Bits [3:2]........................................................................................ 94
Table 28 – I2C Interface Timing .......................................................................................................................................... 118
Table 29 – I2S Interface Timing .......................................................................................................................................... 119
Table 30 - Interrupt Source Mapping .................................................................................................................................. 122
Table 31 – Control Register Current Limit (I_LIM) Settings for Bits [1:0]............................................................................ 128
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P95020 / Preliminary Datasheet
PIN ASSIGNMENTS
LED_BOOST_SINK1
094
095
097
096
099
098
101
100
103
102
105
104
107
106
109
108
111
113
115
117
119
GPIO3/LED2
GPIO2/LED1
GPIO1/SW_OUT
SW_DET
POR_OUT
DGND
GND_BAT/ADCGND
CHRG_VNTC
CHRG_NTC
CHRG_GATE
CHRG_ICHRG
CHRG_CLSEN
CHRG_BAT2
CHRG_BAT1
CHRG_SYSVCC2
CHRG_SYSVCC1
CHRG_INPUT2
CHRG_INPUT1
CHRG_SW2
CHRG_SW1
CHRG_GND2
CHRG_GND1
HSCTRL2
HSO2
HSPWR
HSO1
HSCTRL1
PSCREF
LED_BOOST_SINK2
123
121
GPIO4/CHRG_ILIM
003
091
005
089
007
087
009
085
011
083
013
081
004
DC_DC
093
LED_BOOST_GND
092
064
LED_BOOST_GATE
LED_BOOST_ISENSE
LED_BOOST_VIN
LED_BOOST_VSENSE
BUCK500_0_IN
BUCK500_0_OUT
BUCK500_0_GND
BUCK500_0_FDBK
BUCK500_1_IN
BUCK500_1_OUT
BUCK500_1_GND
BUCK500_1_FDBK
BUCK1000_GND
BUCK1000_OUT
BUCK1000_IN
BUCK1000_FDBK
BOOST5_GND
BOOST5_SW1
BOOST5_OUT
BOOST5_SW2
CLASS_D+
PVDD
PGND
CLASS_D
CLASS_DGND
I2CM_SDA
I2CM_SCL
I2CS_SDA
I2CS_SCL
063
I2S_SDIN1
090
006
088
008
086
010
084
012
082
014
080
015
016
017
018
P95020
079
(TOP VIEW)
077
078
076
019
075
021
073
023
071
025
069
027
067
029
065
020
074
022
072
024
070
026
068
062
I2S_SDOUT1
060
061
CKGEN
059
058
057
056
055
054
053
052
051
050
049
048
047
046
045
044
043
042
041
040
039
038
037
033
LDO_IN2
LDO_050_2
LDO_050_1
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
32KHZ_OUT2
CKGEN_GND
32KHZ_CLKIN/XTALIN
XTALOUT/32KHZ_OUT1
VDD_CKGEN18
HXTALOUT/TCXO_IN
VDD_CKGEN33
HXTALIN/TCXO_OUT1
TCXO_OUT2
SYS_CLK
CKGEN_GND
USB_CLK
VDDIO_CK
EX-ROM
DGND
I2S_BCLK2
I2S_WS2
I2S_SDOUT2
I2S_SDIN2
I2S_BCLK1
I2S_WS1
035
032
036
066
034
028
LDO_050_3
LDO
110
031
112
LDO_LP
114
030
116
002
118
GPIO6/ADC1
GPIO7/ADC3
GPIO8/ADC2
GPIO9/ADC0/MCLK_IN
GPIO10
MIC_RMIC_R+/DMICDAT2
MICBIAS_R/DMICSEL
MICBIAS_L/DMICCLK
MIC_L+/DMICDAT1
MIC_LAFILT2
AFILT1
AGND_MIC
LISLP
LISLM
AUDIO
LISRP
LISRM
LLO_L
LLO_R
AVREF
VDD_AUDIO33
ADC_REF
HP_R
HP_L
AGND
VIRT_GND
LDO_GND
LDO_IN3
120
001
122
GPIO5/INT_OUT
HOT
SWAP
CHARGER
124
GPIO_TSC
I2C_I2S
Figure 2 – P95020 Pinout Diagram (LLG124)
NOTES:
1. All the Buck Converter inputs (BUCK500_0_IN, BUCK500_1_IN, BUCK1000_IN) must be connected to
CHRG_SYSVCC1 and CHRG_SYSVCC2.
2. LLG124 package is available upon request.
Revision 0.7.10
7
©2010 Integrated Device Technology, Inc.
LED_BOOST_SINK1
A55
B46
A56
A57
A58
B47
A59
B48
A60
B49
A61
B50
A62
B51
A63
B52
A64
B53
A65
B54
A66
B55
A67
B56
A68
A69
NC
GPIO2/LED1
GPIO3/LED2
GPIO1/SW_OUT
SW_DET
POR_OUT
DGND
GND_BAT/ADCGND
CHRG_VNTC
CHRG_NTC
CHRG_GATE
CHRG_ICHRG
CHRG_CLSEN
CHRG_BAT2
CHRG_BAT1
CHRG_SYSVCC2
CHRG_SYSVCC1
CHRG_INPUT2
CHRG_INPUT1
CHRG_SW2
CHRG_SW1
CHRG_GND2
CHRG_GND1
HSCTRL2
HSO2
HSPWR
HSO1
HSCTRL1
LED_BOOST_SINK2
PSCREF
NC
A71
A70
GPIO4/CHRG_ILIM
B1
B45
B2
B44
B3
B43
B4
B42
B5
B41
B6
B40
B7
B39
A3
A54
LED_BOOST_GND
A53
A38
NC
LED_BOOST_GATE
LED_BOOST_ISENSE
LED_BOOST_VIN
LED_BOOST_VSENSE
BUCK500_0_IN
BUCK500_0_OUT
BUCK500_0_GND
BUCK500_0_FDBK
BUCK500_1_IN
BUCK500_1_OUT
BUCK500_1_GND
BUCK500_1_FDBK
BUCK1000_GND
BUCK1000_OUT
BUCK1000_IN
BUCK1000_FDBK
BOOST5_GND
BOOST5_SW1
BOOST5_OUT
BOOST5_SW2
CLASS_D+
PVDD
PGND
CLASS_DGND
I2CM_SDA
I2CM_SCL
I2CS_SDA
I2CS_SCL
I2S_SDIN1
A37
I2S_SDOUT1
A52
A4
A51
A5
A50
A6
A49
A7
A48
A8
A47
P95020
A9
B8
A10
A46
B38
A45
(TOP VIEW)
B9
B37
A11
A44
B10
B36
B11
B35
B12
B34
B13
B33
B14
B32
B15
B31
A12
A43
A13
A42
A14
A41
A15
A40
A16
A39
A36
NC
A34
B30
B29
A33
B28
A32
B27
A31
B26
A30
B25
A29
B24
A28
B23
A27
B22
A26
B21
A25
B20
A24
B19
A23
B18
A22
B17
A21
A35
NC
LDO_050_3
A20
A18
LDO_050_2
LDO_IN2
LDO_050_1
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
32KHZ_OUT2
CKGEN_GND
32KHZ_CLKIN/XTALIN
XTALOUT/32KHZ_OUT1
VDD_CKGEN18
HXTALOUT/TCXO_IN
VDD_CKGEN33
HXTALIN/TCXOOUT1
TCXO_OUT2
SYS_CLK
CKGEN_GND
USB_CLK
VDDIO_CK
EX_ROM
DGND
I2S_BCLK2
I2S_WS2
I2S_SDIN2
I2S_SDOUT2
I2S_WS1
I2S_BCLK1
NC
B16
A17
A19
LDO_LP
B57
A2
B58
NC
GPIO7/ADC3
GPIO6/ADC1
GPIO8/ADC2
GPIO9/ADC0
GPIO10
MIC_RMIC_R+/DMICDAT2
MICBIAS_R/DMICSEL
MICBIAS_L/DMICCLK
MIC_L+/DMICDAT1
MIC_LAFILT2
AFILT1
AGND_MIC
LISLP
LISLM
LISRP
LISRM
LLO_L
AVREF
LLO_R
ADC_REF
VDD_AUDIO33
HP_L
HP_R
VIRT_GND
AGND
LDO_IN3
LDO_GND
NC
B59
A1
B60
GPIO5/INT_OUT
A72
P95020 / Preliminary Datasheet
Figure 3 – P95020 Pinout (NGQ132)
NOTES:
All the Buck Converter inputs (BUCK500_0_IN, BUCK500_1_IN, BUCK1000_IN) must be connected to
CHRG_SYSVCC1 and CHRG_SYSVCC2.
Revision 0.7.10
8
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
PIN FUNCTIONS BY PIN NUMBER
Table 1 – LLG124 Pin Functions by Pin Number (See Figure 2)
MODULE
GPIO_TSC
(See Pins
117-124
also)
PIN #
PIN NAME
1
GPIO5/INT_OUT
2
GPIO6/ADC1
DESCRIPTION
GPIO 5: General Purpose I/O # 5
INT_OUT : Interrupt Output
GPIO 6: General Purpose I/O # 6
ADC1 : Auxiliary Input Channel 2 / X- pin to 4-wire resistive touch-screen
I/O TYPE
GPIO
GPIO
GPIO 7: General Purpose I/O # 7
3
GPIO7/ADC3
4
GPIO8/ADC2
ADC3 : Auxiliary Input Channel 4 / Y- pin to 4-wire resistive touch-screen
GPIO
GPIO 8: General Purpose I/O # 8
ADC2 : Auxiliary Input Channel 3 / Y+ pin to 4-wire resistive touch-screen
GPIO
GPIO 9: General Purpose I/O # 9
ADC0 : Auxiliary Input Channel 1 / X+ pin to 4-wire resistive touch-screen
AUDIO
LDO
CKGEN
Revision 0.7.10
5
GPIO9/ADC0/MCLK_IN
MCLK_IN : Master Clock Input
GPIO
6
7
GPIO10
MIC_R-
8
MIC_R+/DMICDAT2
9
MICBIAS_R/DMICSEL
10
MICBIAS_L/DMICCLK
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
MIC_L+/DMICDAT1
MIC_LAFILT2
AFILT1
AGND_MIC
LISLP
LISLM
LISRP
LISRM
LLO_L
LLO_R
AVREF
VDD_AUDIO33
ADC_REF
HP_R
HP_L
AGND
VIRT_GND
LDO_GND
GPIO
A-I
A-I
D-I
A-O
D-O
A-O
D-O
A-I
D-I
A-I
A-I
A-I
GND
A-I
A-I
A-I
A-I
A-O
A-O
A-O
A-O
A-I
A-O
A-O
GND
A-O
GND
30
LDO_IN3
31
32
33
34
35
LDO_LP
LDO_050_3
LDO_IN2
LDO_050_2
LDO_050_1
36
37
38
39
40
41
42
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
32KHZ_OUT2
CKGEN_GND
43
32KHZ_CLKIN/XTALIN
GPIO 10: General Purpose I/O # 10
MIC_R-: Analog Microphone Differential Stereo Right Inverting Input
MIC_R+: Analog Microphone Differential Stereo Right Non-Inverting Input
DMICDAT2: Digital Microphone 2 Data Input
MICBIAS : Microphone Right Bias
DMICSEL : Digital Microphone Select (Common to both inputs)
MICBIAS : Microphone Left Bias
DMICCLK : Digital Microphone Clock (Common to both inputs)
MIC_L+ : Analog Microphone Differential Stereo Left Non-Inverting Input
DMICDAT1 : Digital Microphone 1 Data Input
MIC_L- : Analog Microphone Differential Stereo Left Inverting Input
Microphone ADC Anti-Aliasing Filter Capacitor #2
Microphone ADC Anti-Aliasing Filter Capacitor #1
Microphone Ground (Analog Ground)
Line Input Stereo Left Non-Inverting
Line Input Stereo Left Inverting
Line Input Stereo Right Non-Inverting
Line Input Stereo Right Inverting
Line Level Output, Left
Line Level Output, Right
Analog Reference
Filter Capacitor for Internal 3.3V AUDIO LDO
ADC Reference Bypass Capacitor
Right Headphone Output
Left Headphone Output
Line Out Ground (Analog Ground)
Virtual Ground for Cap-Less Output
LDO Ground
Input Voltage to LDOs for AUDIO Power (VDD_AUDIO33 &
VDD_AUDIO18)
Always on Low Power LDO Output
(Voltage Programmable to 3.0 V or 3.3 V)
50mA LDO Output #3 (Voltage Range: 0.75-3.7 V)
Input Voltage to LDO_050_0, LDO_050_1, LDO_050_2 & LDO_050_3
50mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
50mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
50mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Note: This LDO also serves as the internal power source for I2S1, I2S2 and
I2CS. The external function of this pin is not affected but the voltage
register setting for this LDO will also govern the I/O level for I2S1, I2S2 and
I2CS.
150mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
Input Voltage to LDO_150_0, LDO_150_1, & LDO_050_2
150mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
150mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Buffered 32.768kHz Output #2
PLL Analog Ground
32KHZ_CLKIN: External 32.768kHz Clock Input;
XTALIN : Input Pin when used with an external crystal
9
AP-I
AP-O
AP-O
AP-I
AP-O
AP-O
AP-O
AP-O
AP-I
AP-O
AP-O
D-O
GND
A-I
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
MODULE
I2C_I2S
CLASS_D
DC_DC
HOTSWAP
Revision 0.7.10
PIN #
PIN NAME
44
45
XTALOUT/32KHZ_OUT1
VDD_CKGEN18
46
47
HXTALOUT/TCXO_IN
VDD_CKGEN33
48
HXTALIN/TCXO_OUT1
49
50
51
52
53
TCXO_OUT2
SYS_CLK
CKGEN_GND
USB_CLK
VDDIO_CK
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
EX_ROM
DGND
I2S_BCLK2
I2S_WS2
I2S_SDOUT2
I2S_SDIN2
I2S_BCLK1
I2S_WS1
I2S_SDOUT1
I2S_SDIN1
I2CS_SCL
I2CS_SDA
I2CM_SCL
I2CM_SDA
GND
CLASS_DPGND
PVDD
CLASS_D+
73
74
BOOST5_SW2
BOOST5_OUT
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
BOOST5_SW1
BOOST5_GND
BUCK1000_FDBK
BUCK1000_IN
BUCK1000_OUT
BUCK1000_GND
BUCK500_1_FDBK
BUCK500_1_GND
BUCK500_1_OUT
BUCK500_1_IN
BUCK500_0_FDBK
BUCK500_0_GND
BUCK500_0_OUT
BUCK500_0_IN
LED_BOOST_VSENSE
LED_BOOST_VIN
LED_BOOST_ISENSE
LED_BOOST_GATE
LED_BOOST_GND
LED_BOOST_SINK1
LED_BOOST_SINK2
PSCREF
HSCTRL1
HSO1
HSPWR
HSO2
HSCTRL2
DESCRIPTION
XTALOUT: Output Pin when used with an external crystal
32KHZ_OUT1: when XTALIN is connected to a 32kHz input this pin can be
a 32kHz Output when CKGEN_PLL_STATUS register, 32KOUT1_EN (bit
4) is set to 1.
Filter Capacitor for Internal 1.8V CKGEN LDO
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz crystal oscillator output
TCXO_IN: External 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Clock Input
Filter Capacitor for Internal 3.3V CKGEN LDO
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz, or 26 MHz crystal oscillator input
TCXO_OUT1: Buffered HXTALOUT/TCXO_IN Clock Output #1, 32.7638
KHz Output, 24 MHz PLL Output
Buffered HXTALOUT/TXCO_IN Clock Output #2, 12 MHz PLL Output,
24MHz PLL Output
12MHz Output or Buffered Output of TCXO_IN
PLL Analog Ground
24 MHz or 48 MHz Output
Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V)
ROM Select. EX_ROM = 1, read contents of external ROM. EX_ROM = 0,
read contents of internal ROM into internal shadow memory.
Digital Ground
I²S Bit Clock Channel 2
I²S Word Select (Left/Right) Channel 2
I²S Serial Data OUT Channel 2
I²S Serial Data IN Channel 2
I²S Bit Clock Channel 1
I²S Word Select (Left/Right) Channel 1
I²S Serial Data OUT Channel 1
I²S Serial Data IN Channel 1
I²C Slave clock
I²C Slave data
I²C Master clock
I²C Master data
GND : Ground
Class-D Inverting Output
Ground for Class D BTL Power Stage
Input Power for CLASS_D BTL Power Stage
Class-D Non-Inverting Output
BOOST5 Converter Power Switch
Internally connected to pin 075 (BOOST_SW1)
BOOST5 Converter Output
BOOST5 Converter Power Switch
Internally connected to pin 073 (BOOST_SW2)
Ground for BOOST5 Power Supply
BUCK2 Converter #2 -Feedback
BUCK2 Converter #2 - Input
BUCK2 Converter Output #2 – 1000mA
Ground for BUCK2 Converter #2
BUCK1 Converter #1 – Feedback
Ground for BUCK1 Converter #1
BUCK1 Converter Output #1 - 500mA
BUCK1 Converter #1 Input
BUCK0 Converter #0 feedback
Ground for BUCK0 Converter #0
BUCK0 Converter Output #0 - 500mA
BUCK0 Converter #0 Input
LED_BOOST Converter Output Voltage Sense Input to PWM Controller
LED_BOOST Converter GATE BIAS Supply
LED_BOOST Converter Output Current Sense Input to PWM Controller
LED_BOOST Converter GATE Drive to Power FET
Ground for LED_BOOST
LED_BOOST Converter Current Sink for LED String #1
LED_BOOST Converter Current Sink for LED String #2
Power Supply Current Reference
Hot Swap Control Input 1
Hot Swap Output 1
Hot Swap Switches Power Input
Hot Swap Output 2
Hot Swap Control Input 2
10
I/O TYPE
A-O
A-IO
TCXO-D-I
A-IO
TCXO-D-O
TCXO-D-O
D-O
GND
D-O
AP-I
D-I
GND
D-I
D-I
D-O
D-I
D-I
D-I
D-O
D-I
I2C-I/O
I2C-O
I2C-O
I2C-I/O
GND
A-O
GND
A-I
A-O
AP-O
AP-O
AP-O
AP-I
AP-I
AP-I
AP-O
GND
AP-I
GND
AP-O
AP-I
AP-I
GND
AP-O
AP-I
AP-I
AP-I
AP-I
AP-I
AP-I
AP-I
AP-I
AP-O
D-I
A-O
AP-I
A-O
D-I
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
MODULE
PIN #
102
PIN NAME
CHRG_GND1
103
104
CHRG_GND2
CHRG_SW1
105
106
CHRG_SW2
CHRG_INPUT1
107
108
CHRG_INPUT2
CHRG_SYSVCC1
109
110
CHRG_SYSVCC2
CHRG_BAT1
111
112
113
114
115
CHRG_BAT2
CHRG_CLSEN
CHRG_ICHRG
CHRG_GATE
CHRG_NTC
CHARGER
116
CHRG_VNTC
GPIO_TSC
(See Pins
001-006
also)
117
118
119
120
GND_BAT/ADCGND
DGND
POR_OUT
SW_DET
DESCRIPTION
Pins 102 & 103 are the Power GND Pins for the Switching Regulator in the
Charger. Due to their higher current requirement they are internally tied
together & must be connected externally at the PC board also.
Pins 104 and 105 connect to the inductor of the switch-mode step-down
regulator for the Battery Charger. Due to their higher current requirement
they are internally tied together & must be connected externally at the PC
board also.
Pins 106 and 107 provide 5V VBUS Input Power from the USB or from an
external wall mounted external supply. Due to their higher current
requirement they are internally tied together & must be connected externally
at the PC board also.
Pins 108 and 109 are System VCC Output (VSYS). Due to their higher
current requirement they are internally tied together & must be connected
externally at the PC board also.
Pins 110 and 111 form the positive battery lead connection to a single cell LiIon/Li-Poly battery. Due to their higher current requirement they are internally
tied together & must be connected externally at the PC board also.
Input Current Limit Sense/filtering pin for current limit detection
Current setting. Connect to a current sense resistor
Gate Drive for (Optional) External Ideal Diode
Thermal Sense, Connect to a battery‟s thermistor
NTC Power output. This pin provides power to the NTC resistor string.
This output is automatically CHRG_SYSVCC level but only enabled when
NTC measurement is necessary to save power.
GND_BAT & ADCGND: Shared analog ground pin for battery charger and
ADC.
Digital Ground
Power-On-Reset Output, Active Low
Switch Detect Input
I/O TYPE
A-I
A-I
A-O
A-O
AP-I
AP-I
A-O
A-O
AP-I/O
AP-I/O
A-I
AP-I/O
A-O
A-I
AP-O
GND
GND
GPIO-OUT
GPIO
GPIO 1: General Purpose I/O # 1
SW_OUT: Switch Detect Output
121
GPIO1/SW_OUT/PENDOWN
PENDOWN: PENDOWN Detect Output
GPIO
GPIO 2: General Purpose I/O # 2
122
GPIO2/LED1
LED1: Charger LED # 1 Indicates charging in progress
GPIO
GPIO 3: General Purpose I/O # 3
123
124
GPIO3/LED2
LED2: Charger LED # 2 Indicates charging complete
GPIO
GPIO4/CHRG_ILIM
GPIO 4: General Purpose I/O # 4
CHRG_ILIM: Control the current limit of the Charger Pre-Regulator.
CHRG_ILIM = 0, limit current to 500mA; CHRG_ILIM = 1, limit current to
1.5A
GPIO
Table 2 - NQG132 Pin Functions by Pin Number (see Figure 3)
MODULE
GPIO_TSC
(See Pins
B57 – A71
also)
AUDIO
Revision 0.7.10
PIN #
PIN NAME
A1
A2
GPIO5/INT_OUT
NC
B1
GPIO7/ADC3
A3
GPIO6/ADC1
B2
GPIO8/ADC2
A4
B3
A5
GPIO9/ADC0/MCLK_IN
GPIO10
MIC_R-
B4
MIC_R+/DMICDAT2
A6
MICBIAS_R/DMICSEL
B5
MICBIAS_L/DMICCLK
A7
MIC_L+/DMICDAT1
DESCRIPTION
GPIO 5: General Purpose I/O # 5
INT_OUT : Interrupt Output
No Connect
GPIO 7: General Purpose I/O # 7
ADC3 : Auxiliary Input Channel 4 / Y- pin to 4 wire resistive touch screen
GPIO 6: General Purpose I/O # 6
ADC1 : Auxiliary Input Channel 2 / X- pin to 4-wire resistive touch screen
GPIO 8: General Purpose I/O # 8
ADC2 : Auxiliary Input Channel 3 / Y+ pin to 4-wire resistive touch screen
GPIO 9: General Purpose I/O # 9
ADC0 : Auxiliary Input Channel 1 / X+ pin to 4-wire resistive touch screen
MCLK_IN : Master Clock Input
GPIO 10: General Purpose I/O # 10
MIC_R-: Analog Microphone Differential Stereo Right Inverting Input
MIC_R+: Analog Microphone Differential Stereo Right Non-Inverting Input
DMICDAT2: Digital Microphone 2 Data Input
MICBIAS : Microphone Right Bias
DMICSEL : Digital Microphone Select (Common to both inputs)
MICBIAS : Microphone Left Bias
DMICCLK : Digital Microphone Clock (Common to both inputs)
MIC_L+ : Analog Microphone Differential Stereo Left Non-Inverting Input
DMICDAT1 : Digital Microphone 1 Data Input
11
I/O TYPE
GPIO
NC
GPIO
GPIO
GPIO
GPIO
GPIO
A-I
A-I
D-I
A-O
D-O
A-O
D-O
A-I
D-I
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
MODULE
LDO
CK_GEN
I2C_I2S
Revision 0.7.10
PIN #
B6
A8
B7
A9
B8
A10
B9
A11
B10
A12
B11
A13
B12
A14
B13
A15
B14
PIN NAME
MIC_LAFILT2
AFILT1
AGND_MIC
LISLP
LISLM
LISRP
LISRM
LLO_L
AVREF
LLO_R
ADC_REF
VDD_AUDIO33
HP_L
HP_R
VIRT_GND
AGND
A16
B15
A17
LDO_IN3
LDO_GND
NC
A18
A19
A20
B16
A21
B17
LDO_LP
LDO_050_3
NC
LDO_050_2
LDO_IN2
LDO_050_1
A22
B18
A23
B19
A24
B20
A25
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
32KHZ_OUT2
CKGEN_GND
B21
32KHZ_CLKIN/XTALIN
A26
B22
XTALOUT/32KHZ_OUT1
VDD_CKGEN18
A27
B23
HXTALOUT/TCXO_IN
VDD_CKGEN33
A28
HXTALIN/TCXO_OUT1
B24
A29
B25
A30
B26
TCXO_OUT2
SYS_CLK
CKGEN_GND
USB_CLK
VDDIO_CK
A31
B27
A32
B28
A33
B29
A34
B30
A35
A36
EX_ROM
DGND
I2S_BCLK2
I2S_WS2
I2S_SDIN2
I2S_SDOUT2
I2S_WS1
I2S_BCLK1
NC
NC
DESCRIPTION
MIC_L- : Analog Microphone Differential Stereo Left Inverting Input
Microphone ADC Anti-Aliasing Filter Capacitor #2
Microphone ADC Anti-Aliasing Filter Capacitor #1
Microphone Ground (Analog Ground)
Line Input Stereo Left Non-Inverting
Line Input Stereo Left Inverting
Line Input Stereo Right Non-Inverting
Line Input Stereo Right Inverting
Line Level Output, Left
Analog Reference
Line Level Output, Right
ADC Reference Bypass Capacitor
Filter Capacitor for Internal 3.3V AUDIO LDO
Left Headphone Output
Right Headphone Output
Virtual Ground for Cap-Less Output
Analog Ground
Input Voltage to LDOs for AUDIO Power
(VDD_AUDIO33 & VDD_AUDIO18)
LDO Ground
No Connect
Always on Low Power LDO Output
(Voltage Programmable to 3.0 V or 3.3 V)
50mA LDO Output #3 (Voltage Range: 0.75-3.7 V)
No Connect
50mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
Input Voltage to LDO_050_0, LDO_050_1, LDO_050_2 & LDO_050_3
50mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
50mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Note: This LDO also serves as the internal power source for I2S1, I2S2 and
I2CS. The external function of this pin is not affected but the voltage
register setting for this LDO will also govern the I/O level for I2S1, I2S2 and
I2CS.
150mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
Input Voltage to LDO_150_0, LDO_150_1 & LDO_150_2
150mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
150mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Buffered 32.768kHz Output #2
PLL Analog Ground
32KHZ_CLKIN: External 32.768kHz Clock Input;
XTALIN : Input Pin when used with an external crystal
XTALOUT: Output Pin when used with an external crystal
32KHZ_OUT1: when XTALIN is connected to a 32kHz input this pin can be
a 32kHz Output when CKGEN_PLL_STATUS register, 32KOUT1_EN (bit
4) is set to 1.
Filter Capacitor for Internal 1.8V CKGEN LDO
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz output
TCXO_IN: External 12 MHz, 13 MHz, 19.2 MHz or 26 MHz clock input
Filter Capacitor for Internal 3.3V CKGEN LDO
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz, or 26 MHz crystal oscillator input
TCXO_OUT1: Buffered HXTALOUT/TCXO_IN Clock Output #1, 32.7638
KHz Output or 24 MHz PLL Output
Buffered HXTALOUT/TXCO_IN Clock Output #2, 12 MHz PLL Output or 48
MHz PLL Output
12MHz Output or Buffered Output of TCXO_IN
PLL Analog Ground
24 MHz or 48 MHz Output
Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V)
ROM Select. EX_ROM = 1, read contents of external ROM. EX_ROM = 0,
read contents of internal ROM into internal shadow memory.
Digital Ground (1)
I²S Bit Clock Channel 2
I²S Word Select (Left/Right) Channel 2
I²S Serial Data IN Channel 2
I²S Serial Data OUT Channel 2
I²S Word Select (Left/Right) Channel 1
I²S Bit Clock Channel 1
No Connect
No Connect
12
I/O TYPE
A-I
A-I
A-I
GND
A-I
A-I
A-I
A-I
A-O
A-O
A-O
A-I
A-O
A-O
A-O
A-O
GND
AP-I
GND
NC
AP-O
AP-O
NC
AP-O
AP-I
AP-O
AP-O
AP-O
AP-I
AP-O
AP-O
D-O
GND
A-I
A-O
A-IO
TCXO-D-I
A-IO
TCXO-D-O
TCXO-D-O
D-O
GND
D-O
AP-I
D-I
GND
D-I
D-I
D-I
D-O
D-I
D-I
NC
NC
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
MODULE
CLASS_D
DC_DC
HOTSWAP
CHARGER
Revision 0.7.10
PIN #
A37
A38
B31
A39
B32
A40
B33
A41
B34
A42
B35
PIN NAME
I2S_SDOUT1
I2S_SDIN1
I2CS_SCL
I2CS_SDA
I2CM_SCL
I2CM_SDA
GND
CLASS_DPGND
PVDD
CLASS_D+
A43
B36
BOOST5_SW2
BOOST5_OUT
A44
B37
A45
B38
A46
B39
A47
B40
A48
B41
A49
B42
A50
B43
A51
B44
A52
B45
A53
A54
A55
A56
B46
A57
B47
A58
B48
A59
B49
A60
BOOST5_SW1
BOOST5_GND
BUCK1000_FDBK
BUCK1000_IN
BUCK1000_OUT
BUCK1000_GND
BUCK500_1_FDBK
BUCK500_1_GND
BUCK500_1_OUT
BUCK500_1_IN
BUCK500_0_FDBK
BUCK500_0_GND
BUCK500_0_OUT
BUCK500_0_IN
LED_BOOST_VSENSE
LED_BOOST_VIN
LED_BOOST_ISENSE
LED_BOOST_GATE
NC
LED_BOOST_GND
LED_BOOST_SINK1
NC
PSCREF
LED_BOOST_SINK2
HSCTRL1
HSO1
HSPWR
HSO2
HSCTRL2
CHRG_GND1
B50
A61
CHRG_GND2
CHRG_SW1
B51
A62
CHRG_SW2
CHRG_INPUT1
B52
A63
CHRG_INPUT2
CHRG_SYSVCC1
B53
A64
CHRG_SYSVCC2
CHRG_BAT1
B54
A65
B55
A66
B56
CHRG_BAT2
CHRG_CLSEN
CHRG_ICHRG
CHRG_GATE
CHRG_NTC
A67
CHRG_VNTC
DESCRIPTION
I²S Serial Data OUT Channel 1
I²S Serial Data IN Channel 1
I²C Slave clock
I²C Slave data
I²C Master clock
I²C Master data
GND : Ground
Class-D Inverting Output
Ground for Class D BTL Power Stage
Input Power for CLASS_D BTL Power Stage
Class-D Non-Inverting Output
BOOST5 Converter Power Switch
Internally connected to pin A44 (BOOST_SW1)
BOOST5 Converter Output
BOOST5 Converter Power Switch
Internally connected to pin A43 (BOOST_SW2)
Ground for BOOST5 Power Supply
BUCK2 Converter #2 - Feedback
BUCK2 Converter #2 - Input
BUCK2 Converter Output #2 – 1000mA
Ground for BUCK2 Converter #2
BUCK1 Converter #1 – Feedback
Ground for BUCK1 Converter #1
BUCK1 Converter Output #1 - 500mA
BUCK1 Converter #1 Input
BUCK0 Converter #0 feedback
Ground for BUCK0 Converter #0
BUCK0 Converter Output #0 - 500mA
BUCK0 Converter #0 Input
LED_BOOST Converter Output Voltage Sense Input to PWM Controller
LED_BOOST Converter GATE BIAS Supply
LED_BOOST Converter Output Current Sense Input to PWM Controller
LED_BOOST Converter GATE Drive to Power FET
No Connect
Ground for LED_BOOST
LED_BOOST Converter Current Sink for LED String #1
No Connect
Power Supply Current Reference
LED_BOOST Converter Current Sink for LED String #2
Hot Swap Control Input 1
Hot Swap Output 1
Hot Swap Switches Power Input
Hot Swap Output 2
Hot Swap Control Input 2
Pins A60 & B50 are the Power GND Pins for the Switching Regulator in the
Charger. Due to their higher current requirement they are internally tied
together & must be connected externally at the PC board also.
Pins A61 & B51connect to the inductor of the switch-mode step-down
regulator for the Battery Charger. Due to their higher current requirement
they are internally tied together & must be connected externally at the PC
board also.
Pins A62 & B52 provide 5V VBUS Input Power from the USB or from an
external wall mounted external supply. Due to their higher current
requirement they are internally tied together & must be connected
externally at the PC board also.
Pins A63 & B53 are System VCC Output (VSYS). Due to their higher current
requirement they are internally tied together & must be connected
externally at the PC board also.
Pins A64 & B64 form the positive battery lead connection to a single cell LiIon/Li-Poly battery. Due to their higher current requirement they are internally
tied together & must be connected externally at the PC board also.
Input Current Limit Sense/filtering pin for current limit detection
Current setting. Connect to a current sense resistor
Gate Drive for (Optional) External Ideal Diode
Thermal Sense, Connect to a battery‟s thermistor
NTC Power output. This pin provides power to the NTC resistor string.
This output is automatically CHRG_SYSVCC level but only enabled when
NTC measurement is necessary to save power.
13
I/O TYPE
D-O
D-I
I2C-I/O
I2C-O
I2C-O
I2C-I/O
GND
A-O
GND
A-I
A-O
AP-O
AP-O
AP-O
AP-I
AP-I
AP-I
AP-O
GND
AP-I
GND
AP-O
AP-I
AP-I
GND
AP-O
AP-I
AP-I
AP-I
AP-I
AP-I
NC
AP-I
AP-I
NC
AP-O
AP-I
D-I
A-O
AP-I
A-O
D-I
A-I
A-I
A-O
A-O
AP-I
AP-I
A-O
A-O
AP-I/O
AP-I/O
A-I
AP-I/O
A-O
A-I
AP-O
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
MODULE
GPIO_TSC
PIN #
PIN NAME
B57
A68
B58
A69
GND_BAT/ADCGND
DGND
POR_OUT
SW_DET
B59
GPIO1/SW_OUT/PENDOWN
A70
GPIO3/LED2
B60
A71
GPIO2/LED1
NC
A72
GPIO4/CHRG_ILIM
DESCRIPTION
GND_BAT & ADCGND: Shared analog ground pin for battery charger and
ADC.
Digital Ground
Power-On-Reset Output, Active Low
Switch Detect Input
GPIO 1: General Purpose I/O # 1
SW_OUT: Switch Detect Output
PENDOWN: PENDOWN Detect Output
GPIO 3: General Purpose I/O # 3
LED2: Charger LED # 2 Indicates charging complete
GPIO 2: General Purpose I/O # 2
LED1: Charger LED # 1 Indicates charging in progress
No Connect
GPIO 4: General Purpose I/O # 4
CHRG_ILIM: Control the limit of the Charger Pre-Regulator. CHRG_ILIM =
0, limit current to 500mA; CHRG_ILIM = 1, limit current to 1.5A.
I/O TYPE
GND
GND
GPIO-OUT
GPIO
GPIO
GPIO
GPIO
NC
GPIO
I/O LEVELS BY TYPE
I/O TYPE
A-I, A-O & A-IO
AP-I, AP-O & AP-I/O
D-I, D-O
GND
GPIO-IN, GPIO-OUT, GPIO
I2C-I, I2C-O & I2CIO
TCXO-D-I, TCXO-D-O, TCXO-IO
Revision 0.7.10
DESCRIPTION
Analog Levels: Input, Output & Input/Output
Power Supply: Input, Output & Input/Output
Digital Levels: Input, Output
Voltage levels are all digital levels (nominally 3.3V)
Ground: Any connection to Ground
General Purpose: Input, Output, Input/Output.
Inputs are 3.3V
Outputs are VSYS with open-drain capable
I²C: Input, Output & Input/Output
Inputs are CMOS
Outputs are open-drain.
Clock: Input, Output, Input/Output
Inputs are 1.8V, Outputs are 1.1V to 1.9V
14
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
ABSOLUTE MAXIMUM RATINGS
Stresses above the ratings listed below can cause permanent damage to the P95020. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect
product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
SYMBOL
PARAMETER
CHRG_INPUT to CHRG_GND
CHRG_BAT to DGND
CHRG_SYSVCC to DGND
PVDD to PGND
LDO_IN1, IN2, IN3 to DGND
BUCK500_0_IN to BUCK500_0_GND
BUCK500_1_IN to BUCK500_1_GND
BUCK1000_IN to BUCK1000_GND
USB or Wall Charger Input
Battery Input Source
System VCC Output (Vsys)
CLASS_D BTL Input Power
Input voltage for LDO
BUCK0 Input voltage
BUCK1 Input voltage
BUCK2 Input voltage
BUCK0, 1, 2 feedback
voltage
LED_BOOST Converter
gate bias supply
LED_BOOST Converter
Gate Drive to Power FET
FDBK to DGND
LED_BOOST_VIN to LED_BOOST_GND
LED_BOOST_GATE to
LED_BOOST_GND
LED_BOOST_VSENSE to
LED_BOOST_GND
LED_BOOST_ISENSE to
LED_BOOST_GND
LED_BOOST_SINK to
LED_BOOST_GND
BOOST5_OUT to BOOST5_GND
BOOST5_SW to BOOST5_GND
HSPWR to DGND
HSCTRL1, HSCTRL2 to DGND
VDDIO_CK to CKGEN_GND
TCXO_IN to CKGEN_GND
32KHZ_CLKIN to CKGEN_GND
GPIO to DGND
SDA, SCL to DGND
BCLK, WS, SDOUT, SDIN to DGND
EX_ROM to DGND
AGND, LDO_GND, CKGEN_GND, GND,
PGND, BOOST5_GND,
BCUCK500_0_GND,
BCUCK500_1_GND, BUCK1000_GND,
LED_BOOST_GND, CHRG_GND,
GND_BAT/ADCGND to DGND
TA
TJ
TS
TSOLDER
MIN
MAX
UNIT
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
7
5.5
5.5
6
6
6
6
6
V
V
V
V
V
V
V
V
-0.3
6
V
-0.3
6
V
-0.3
LED_BOOST_VIN + 0.3
V
Voltage Sense Input
-0.3
LED_BOOST_VIN + 0.3
V
Current Sense Input
Current Sink for LED String
#1 or String #2
BOOST5 Converter Output
BOOST5 Converter Power
Switch1 and Switch2
Hot Swap Switches Power
Input voltage for Hot Swap
Control
Power Supply for
TCXO_OUT1, TCXO_OUT2
Input voltage for TCXO_IN
Input voltage for
32KHZ_CLK
Input voltage for GPIO
Input voltage for I2C Master
or Slave
Input volatge for I2S
channel 1 or 2
External ROM enable
-0.3
LED_BOOST_VIN + 0.3
V
-0.3
-0.3
6
6
V
V
-0.3
-0.3
6
6
V
V
-0.3
HSPWR + 0.3
V
-0.3
-0.3
2.5
VDD_CKGEN18 + 0.3
V
V
-0.3
-0.3
LDO_LP + 0.3
CHRG_SYSVCC + 0.3
V
V
-0.3
CHRG_SYSVCC + 0.3
V
-0.3
-0.3
LDO_050_0 + 0.3
CHRG_SYSVCC + 0.3
V
V
-0.3
0.3
V
-40 to +85
°C
-40 to +125
-40 to +150
260°C for 10 seconds
°C
°C
-
Operating Ambient
Temperature
Operating Junction
Temperature
Storage Temperature
Soldering Temperature
CONDITIONS
Transient t < 1ms,
Duty Cycle < 1%
ESD:
The P95020 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can
accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the P95020
implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the
functionality or performance.
Revision 0.7.10
15
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
RECOMMENDED OPERATING CONDITIONS
SYMBOL
CHRG_INPUT
CHRG_BAT
PVDD
LDO_IN1, IN2, IN3
BUCK500_0_IN,
BUCK500_1_IN,
BUCK1000_IN
LED_BOOST_VIN
VDDIO_CK voltage
HSPWR
LDO_050_0
TA
TJ
PARAMETER
USB or Wall Charger Input
Battery Input Source
CASS_D BTL Input Power Supply
Input voltage for LDO
BUCK0, 1, 2 Input voltage
CONDITIONS
When Vbat providing power
LED Boost Converter gate bias supply
Power Supply for TCXO_OUT1,
TCXO_OUT2
Hot Swap Switches Power Supply
Power Supply for I2C Slave Channel,
I2S Channel 1 and 2
Ambient Operating Temperature
Operating Junction Temperature
Do not tie to ground or floating
MIN
4.35V
3.0V
3.0V
3.0V
3.0V
TYP
MAX
5.5V
4.5V
5.0V
5.5V
4.5V
UNIT
V
V
V
V
V
3.0V
1.1V
5.5V
1.9V
V
V
3.0V
1.7V
5.5V
3.6V
V
V
-40
-40
85
125
°C
°C
DIGITAL INTERFACES - DC ELECTRICAL CHARACTERISTICS
I2C MASTER - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, VLD0_LP=3.3V, TA = -40°C to +85°C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Voltage
0.7x VLD0_LP
VSYS + 0.3
V
VIL
Input Low Voltage
Output Low Voltage
(Open Drain)
-0.3
0.3x VLD0_LP
V
0.4
V
MAX
UNIT
VOL
IOL = 3 mA
I2C SLAVE - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, TA = -40°C to +85°C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VLDO_050_0
Input Power Supply
1.7
3.6
V
VIH
Input High Voltage
0.7x VLDO_050_0
VSYS + 0.3
V
VIL
Input Low Voltage
-0.3
0.3x VLDO_050_0
V
VOL
Output Low Voltage
0.4
V
MAX
UNIT
IOL = +3 mA
I2S - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, TA = -40°C to +85°C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VLDO_050_0
Input Power Supply
1.7
3.6
V
VIH
Input High Voltage
0.7x VLDO_050_0
VSYS + 0.3
V
VIL
Input Low Voltage
-0.3
0.3x VLDO_050_0
V
VOH
Output High Voltage
VOL
Output Low Voltage
IOH = -1mA, VLDO_050_0 = 3.3V
0.9x VLDO_050_0
V
IOH = -1mA, VLDO_050_0 = 2.5V
0.9x VLDO_050_0
V
IOH = -100uA, VLDO_050_0 = 1.8V
VLDO_050_0 - 0.2
IOL = 1mA
V
0.1x VLDO_050_0
V
MAX
UNIT
GPIO - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, VLD0_LP=3.3V, TA = -40°C to +85°C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VIH
Input High Voltage
0.7x VLD0_LP
VSYS + 0.3
V
VIL
Input Low Voltage
-0.3
0.3x VLD0_LP
V
VOH
Output High Voltage
IOH = -2mA
VOL
Output Low Voltage
IOL = 2mA
Revision 0.7.10
0.9x VSYS
V
0.1x VSYS
16
V
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
OVERALL POWER CONSUMPTION
MODE
DESCRIPTION
Sleep
USB or Wall Adaptor is not present, a main battery is present and well-chaged. Always
on LDO_LP is on, RTC is on and RTC registers are maintained. Wake-up capabilities
(Switch Detect Input) are available.
USB or Wall Adaptor is not present, a main battery is present and well-chaged. Always
on LDO_LP is on, all DC-DC Bucks in PFM mode. All LDO's are on, no load.
USB or Wall Adaptor is not present, a main battery is present and well-charged.
Always on LDO_LP is on, touch screen controller is on, LDO_050_0 is on.
Standby
Touch
Controller
Standby
CHARGE_BAT
Vbat = 3.8V
TYPICAL
CONSUMPTION
TBD
Vbat = 3.8V
TBD
Vbat = 3.8V
TBD
AUDIO POWER CONSUMPTION
MODE
Playback to 4Ω
speaker, sampling at
96 kHz, no signal
Playback to 4Ω
speaker, sampling at
96 kHz, 0dB FS 1 kHz
signal
Playback to 8Ω
speaker, sampling at
48 kHz, no signal
Playback to 8Ω
speaker, sampling at
48 kHz, 0dB FS 1 kHz
signal
Playback to 16Ω
headphone, sampling
at 96 kHz, no signal
Playback to 16Ω
headphone, sampling
at 96 kHz, 0dB FS 1
kHz signal
Playback to 16Ω capless headphone,
sampling at 96 kHz,
no signal
Playback to 16Ω capless headphone,
sampling at 96 kHz,
0dB FS 1 kHz signal
Stereo playback
bypassing ADC and
DAC to Class-D 4Ω
speaker, no signal
Record mode –
Stereo Line-In to
ADC0 sampling at 96
kHz, no signal
Record mode –
Analog microphone
I/P to ADC1 sampling
at 16 kHz, no signal
Record mode –
Analog microphone
I/P to ADC1 sampling
at 96 kHz, no signal
Revision 0.7.10
CHRG_BAT
LDO_050_0
VDD_AUDIO18
VDD_AUDIO33
PVDD
CHRG_BAT
PVDD
(V)
3.3
3.8
4.2
3.3
3.8
4.2
(V)
2.3
3.3
3.6
2.3
3.3
3.6
(V)
1.5
1.8
1.8
1.5
1.8
1.8
(V)
3.0
3.3
3.6
3.0
3.3
3.6
(V)
3.0
3.3
5.0
3.0
3.3
5.0
(mA)
52
60
60
53
61
61
(mA)
7
7
10
155
170
258
Total
Power
(mW)
192
252
302
640
793
1546
3.3
3.8
4.2
3.3
3.8
4.2
2.3
3.3
3.6
2.3
3.3
3.6
1.5
1.8
1.8
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
5.0
3.0
3.3
5.0
52
59
59
52
60
60
6
6
10
96
105
163
190
244
298
460
575
1067
3.3
3.8
4.2
3.3
3.8
4.2
2.3
3.3
3.6
1.7
3.3
3.6
1.5
1.8
1.8
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
5.0
3.0
3.3
5.0
54
58
60
120
133
135
0
0
0
0
0
0
178
220
252
396
506
567
3.3
3.8
4.2
2.3
3.3
3.6
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
5.0
55
60
62
0
0
0
182
228
260
3.3
3.8
4.2
2.3
3.3
3.6
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
5.0
122
135
137
0
0
0
403
513
576
3.3
3.8
4.2
2.3
3.3
3.6
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
5.0
41
48
48
7
7
10
156
206
252
3.3
3.8
4.2
2.3
3.3
3.6
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
5.0
45
49
50
0
0
0
149
186
210
3.3
3.8
4.2
2.3
3.3
3.6
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
5.0
43
47
47
0
0
0
142
179
198
3.3
3.8
4.2
2.3
3.3
3.6
1.5
1.8
1.8
3.0
3.3
3.6
3.0
3.3
5.0
45
49
50
0
0
0
149
186
210
17
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
1.0 OVERVIEW
The P95020 is an integrated device that combines a microcontroller, power management, battery charging, touch screen
controller, system monitoring, clock synthesis, real time clock and audio functionality. All of these subsystems are
configured, monitored and controlled by either the on-chip Microcontroller or by an external controller (Application
Processor) over an I²C interface. The external Application Processor can monitor and control functions within P95020
even when the internal Microcontroller is enabled. The registers for the various sub functions allow access from more
than one controller through an arbitration mechanism implemented in hardware.
VBUS
(From USB VBUS
or wall adpapter)
PWM
Charger
or
Discharger
CLSEN
NTC
VNTC
ICHRG
Battery
Charger
SDA
SCL
I2C Master
SDA
SCL
I2C Slave
SW_DET
SW_DET
BOOST_LED
Backlight Driver &
Current Sinks for
LEDs
LDO 150 mA
(0.75v-3.7V)
Real Time
Clock
POR_OUT
HSPWR
HSCTRL1
HSO1
HSCTRL2
HSO2
V_Output
Mic In
Line In
I S Channel 1 In
I2S Channel 2 In
2
I S Channel 1 Out
I2S Channel 2 Out
Line Out
Headphone Out
Class-D Out
2
TCXO_OUT
SYS_CLK
USB_CLK
M
U
X
VSYS to System
External
PMOS
Ideal Diode
(Optional)
VSYS
Ideal
Diode
0V
Microcontroller
10 pin
interface
L
SW
GATE
VBAT
+
Single Cell
Li-Ion Battery
VIN
Voltage to LEDs
VSENSE
SINK 1
SINK 2
ISENSE
LDO_IN1
V_Output
LDO 150 mA
(0.75v-3.7V)
V_Output
LDO 150 mA
(0.75v-3.7V)
V_Output
LDO 50 mA
(0.75v-3.7V)
V_Output
LDO_IN2
ADC/Touch
LDO 50 mA
(0.75v-3.7V)
V_Output
10 GPIO
POR_OUT
LDO 50 mA
(0.75v-3.7V)
V_Output
LDO 50 mA
(0.75v-3.7V)
V_Output
LDO 1mA (3.0V
or 3.3V)
V_Output
5V Boost
DC-DC Buck
1000 mA
V_Output
Audio Codec
Headphone
Amp
Class-D
Amp
DC-DC Buck_1
500 mA
V_Output
DC-DC Buck_0
500 mA
V_Output
Hot Swap
Switches
Clock
Generator
Oscillator
Power
On
Reset
Figure 4 – Overall System Functional Diagram.
Revision 0.7.10
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1.1
FUNCTIONAL MODES
There are two primary functional modes for operation: external processor only or simultaneous internal and external
processor operation.
External Processor Control
In this mode of operation the external processor can access all internal registers via the I²C interface and receive
interrupts via an interrupt pin, and the internal Microcontroller can be powered down or clock gated off.
Combined Internal and External Processor Operation
In this mode of operation the Microcontroller in the P95020 will function autonomously or semi-autonomously based on
the content of the on-board or external ROM. The external Application Processor may or may not perform additional
control functions through the I²C bus interface. Individual time-based or event-based interrupts generated inside the
P95020 device may be routed internally or externally to be handled separately. All I²C registers can be simultaneously
2
accessed by either the external Application Processor or the internal Microcontroller. Access to the I C registers is
arbitrated via on-chip hardware arbitration.
Revision 0.7.10
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1.2
REGISTER MAP
All the P95020 control and status registers accessible to the Microprocessor are mapped to a 1024 location address
space. This address space maps to:
4 x 256 Bytes of I²C pages for the I²C slave interface
1024 consecutive addresses in the embedded Microprocessor address space
For easy access from the I²C slave interface (by default 256 Bytes oriented) the first 16 registers of each page are global
for all the pages.
Each Module is allocated a consecutive address space.
Register address computation: Address = Base Address + Offset Address
The Base addresses (for both I²C and embedded uP) are listed in the following table. The Offset addresses are defined in
different functional Modules. The offset address is labeled as “Offset Address” in the Module Register definition sections.
Table 3 – Register Address Global Mapping
Base Address
(6811 P)
Size
(Bytes)
Base Address
(I²C)
Global Registers
16
Page-x:
000(0x00)
0xA000
Page 120 Section 15.7
ACCM
16
Page-0:
016(0x10)
0xA010
Page 123 Section 15.8
PCON
32
Page-0:
032(0x20)
0xA020
RTC
32
LDO
32
DC_DC
16
CHARGER
16
GPT
16
RESERVED
16
ADC_TSC
64
AUDIO
240
CLASS_D_DIG
240
RESERVED
240
Module
Revision 0.7.10
Register Definition
Location
Module Description
Page 64 Section 4.7
Global registers are used by the Access
Manager, the first 16 registers of each page
are global for all the pages.
Access manager, including an I²C slave and
bus arbiter
Power controller, including registers that
control the on/off of the regulators, and
control/sense of the GPIO, power states
Clock Generator Registers
0xA040
Page 67 Section 5.2
Real Time Clock
0xA060
Page 127 Section 16.6
Page-0:
128(0x80)
0xA080
Page 74 Section 7.0
Page-0:
144(0x90)
0xA090
Page 55 Section 3.5
0xA0A0
Page 71 Section 6.2
Page-0:
064(0x40)
Page-0:
096(0x60)
Page-0:
160(0xA0)
Page-0:
176(0xB0)
Page-0:
192(0xC0)
Page-1:
000(0x00)
Page-2:
000(0x00)
Page-3:
000(0x00)
Page 108 Section 13.7.1
0xA0B0
Linear regulators, including regulators for
external and internal usage
Switching regulators and Class-D BTL driver
consisting of three bucks, one 5V boost , one
white LED driver and one Class-D BTL driver
Battery Charger, including a dedicated
switching buck regulator, an ideal diode, a
precision reference and thermal sensor
General purpose timers
RESERVED
0xA0C0
Page 100 Section 12.4
Touch-screen (ADC, pendown detect and
switches, temperature and battery voltage
monitoring), and GPIOs
0xA100
Page 40 Section 2.15
Audio subsystem, excluding class-D amplifier
0xA200
Page 32 Section 2.13
Class-D amplifier digital processing part
0xA300
RESERVED
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P95020 / Preliminary Datasheet
1.3
BYTE ORDERING AND OFFSET
Most registers are defined within one byte width and occupy one byte in the address space. Some registers occupy more
than one byte. Please refer to the individual register descriptions for information on how that register is stored in address
space.
1.4
1.5
REGISTER ACCESS TYPES
TYPE
MEANING
RW
R
RW1C
RW1A
Readable and Writeable
Read only
Readable and Write 1 to this bit to clear it (for interrupt status)
Readable and Write 1 to this bit to take actions
RESERVED BIT FIELDS
Bit fields and Bytes labeled RESERVED are reserved for future use. When writing to a register containing some
RESERVED bits, the user should do a “read-modify-write” such that only the bits which are intended to be written are
modified.
DO NOT WRITE to registers containing all RESERVED bits.
Revision 0.7.10
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2.0 AUDIO MODULE
FEATURES
4 Channels (2 stereo DACs and 2 stereo ADCs) with 24-bit
resolution
Supports full-duplex stereo audio
Provides a mono output
2.5W mono speaker amplifier @ 4 ohms and 5V
Stereo cap-less headphone amplifier
Two digital microphone inputs
DESCRIPTION
The audio system is a low power optimized, high fidelity,
4-channel audio codec with integrated Class D speaker
amplifier, cap-less headphone amplifier. It provides high
quality HD Audio capability for handheld applications.
Mono or stereo operation
Up to 4 microphones in a system
High performance analog mixer
2 adjustable analog microphone bias outputs
Figure 5 – Audio Block Diagram
2.1 AUDIO - PIN DEFINITIONS
Pin #
007
008
009
010
011
PIN_ID
MIC_RMIC_R+/DMICDAT2
MICBIAS_R/DMICSEL
MICBIAS_L/DMICCLK
MIC_L+/DMICDAT1
Revision 0.7.10
DESCRIPTION
Differential Analog microphone negative input (right channel)
Differential Analog microphone positive input (right channel) or second digital microphone data input
Analog microphone supply (right channel) or digital microphone select output (GPO)
Analog microphone supply (left channel) or digital microphone clock output
Differential Analog microphone positive input (left channel) or first digital microphone data input
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P95020 / Preliminary Datasheet
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
MIC_LAFILT2
AFILT1
AGND_MIC
LISLP
LISLM
LISRP
LISRM
LLO_L
LLO_R
AVREF
VDD_AUDIO33
ADC_REF
HP_R
HP_L
AGND
VIRT_GND
Differential Analog microphone negative input (left channel)
ADC filter cap
ADC filter cap
Return path for microphone supply (MICBIAS_L/R )
Differential Analog Line Level positive input (left channel)
Differential Analog Line Level negative input (left channel)
Differential Analog Line Level positive input (right channel)
Differential Analog Line Level negative input (right channel)
Single Ended Line Level Output (Left channel)
Single Ended Line Level Output (Right channel)
Analog reference (virtual ground) bypass cap
Filter Capacitor for Internal 3.3V Audio LDO
ADC reference bypass cap
Cap-less headphone output (right channel)
Cap-less headphone output (left channel)
Analog (audio) return
Cap-less headphone signal return (virtual ground)
2.2 AUDIO - SECTION OVERVIEW
The Audio section can be divided into seven subsections.
Analog Input Buffer & Converter Block
DAC, ADC
Audio Mixer Block
Analog and Class D Output Blocks
Sub System Control and Interface Blocks
Note: All register settings are lost when power is removed.
2.3 AUDIO - ANALOG PERFORMANCE CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 5V, TA = -40°C to +85°C,
(VCC_AUDIO33 = 3.3V, VDD_AUDIO18 = 1.8V, AGND = DGND = 0V, TA = 25 ° C; 1 kHz input sine wave, Sample Frequency = 48 kHz, 0 dB = 1 VRMS
into 10 KΩ)
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNIT
Full Scale Input Voltage:
All Analog Inputs except Mic (0 dB gain)
1.0
V rms
Differential Mic Inputs (+30dB gain)
30.0
mV rms
Differentail Mic Inputs (0 dB gain)
1.0
V rms
1.0
V rms
0.707
V rms
Full Scale Output Voltage:
Line Input to Line Output
HP Output
Per channel / 16 ohm load
PCM (DAC) to LINE_OUT
1.0
Headphone output power
Per channel / 16 ohm load
45
Analog Frequency Response
± 1 dB limits. The max frequency response is 40 kHz if the
sample rate is 96 kHz or more.
10
Digital S/N
The ratio of the rms output level with 1 kHz full scale input to
the rms output level with all zeros into the digital input.
Measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-tonoise ratio) – At Line_Out pins.
50
V rms
55
mWpk
30,000
Hz
D/A PCM (DAC) to LINE_OUT
95
dB
A/D LINE_IN to PCM
90
dB
LINE_IN to LINE_OUT (direct)
98
dB
LINE_IN to LINE_OUT (mixer)
95
dB
LINE_IN to HP (direct)
90
dB
Dynamic Range: -60dB signal level
Revision 0.7.10
Ratio of Full Scale signal to noise output with -60 dB signal,
measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.
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LINE_IN to HP (mixer)
90
dB
DAC to LINE_OUT
93
dB
LINE_IN to A/D
90
dB
LINE_IN to LINE_OUT (direct)
90
dB
LINE_IN to LINE_OUT (mixer)
80
dB
DAC to LINE_OUT
85
dB
DAC to HP (10 KΩ)
80
dB
DAC to HP (16 Ω)
55
dB
LINE_IN to ADC
80
dB
80
dB
Total Harmonic Distortion:
THD+N ratio as defined in AES17 and outlined in AES6id,
non-weighted, at 1 kHz. Tested at -3 dB FS or equivalent for
analog only paths. 0 dB gain (PCM data -3 dB FS, analog
input set to achieve -3 dB full scale port output level)
AMIC to ADC
A/D Frequency Response
± 0.25 dB limits. The D/A freq. response becomes 40 kHz
with sampling rates > 96 kHz. At ±3 dB the response range
is from 20-22,500 Hz at 48 kHz, or 20-20,000 Hz @
44.1 kHz or 20-45,000 Hz @ 96 kHz.
Transition Band
Transition band is 40-60% of sample rate.
19,200
Stop Band
Stop band begins at 60% of sample rate
28,800
Hz
85
dB
45
dB
70
dB
D/A Frequency Response
Stop Band Rejection
Out-of-Band Rejection
The integrated Out-of-Band noise generated by the DAC
process, during normal PCM audio playback, over a
bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC
output.
Power Supply Rejection Ratio (1 kHz)
18
22,000
Hz
20
20,000
Hz
28,800
Hz
Crosstalk between Input channels
85
dB
DAC Volume/Gain Step Size
0.75
dB
ADC/Mixer Volume/Gain Step Size
1.5
dB
Analog Mic Boost Step Size
10
dB
Input Impedance
50
K
Differential Input Impedance
20
K
Input Capacitance
15
pF
2.97
V
Mic Bias
External Load Impedance
6
k
2.4 AUDIO - MICROPHONE INPUT PORT
The microphone input port supports either analog or digital microphones. The analog and digital modes share pins so
only one mode is supported in a typical application.
2.4.1 AUDIO - Analog Microphone Input mode
The Analog Microphone input path consists of:
Stereo Differential Input Analog Microphone Buffer
L/R swap
Mono or stereo
Microphone Bias Generator with 2 independent bias outputs.
Microphone Boost Amplifier with selectable gain of 10, 20, or 30dB
The analog microphone interface provides a stereo differential input for supporting common electret cartridge
microphones in a balanced configuration (a single-ended configuration is also supported). A boost amplifier provides up
to 30dB of gain to align typical microphone full scale outputs to the ADC input range. The microphone input is then routed
Revision 0.7.10
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to both ADC1 and the analog mixer for further processing. By using the analog mixer the analog microphone input may
be routed to ADC0, the line output port or the headphone output port.
2.4.2 AUDIO - Digital Microphone Input mode
The Digital Microphone Input path consists of:
Digital Microphone input buffer and MUX with the following features:
One or two microphones per DMICDATx input.
Mono data sampled during high or low clock level.
L/R swap
Versatile DMICSEL output pin for control of digital microphone modules or other external circuitry. (Used primarily to
enable/disable microphones that do not support power management using the clock pin.)
The digital microphone interface permits connection of a digital microphone(s) via the DMICDAT1, DMICDAT2, and
DMICCLK 3-pin interface. The DMICDAT1 and DMICDAT2 signals are inputs that carry individual channels of digital
microphone data to the ADC. In the event that a single microphone is used, the data is ported to both ADC channels.
This mode is selected using a register setting and the left time slot is copied to the ADC left and right inputs. The digital
microphone input is only available at ADC1.
The DMICCLK output is controllable from 4.704 MHz, 3.528 MHz, 2.352 MHz, 1.176 MHz and is synchronous to the
internal master clock (MCLK). The default frequency is 2.352 MHz.
To conserve power, the analog portion of the ADC and the analog boost amplifier will be turned off if the D-mic input is
selected. When switching from the digital microphone to an analog input to the ADC, the analog portion of the ADC will
be brought back to a full power state and allowed to stabilize before switching from the digital microphone to the analog
input. This should take less than 10mS.
The P95020 codec supports the following digital microphone configurations:
Table 4 - Valid Digital Mic Configurations
MODE
DIGITAL
MICS
DATA
SAMPLE
INPUT
NOTES
0
0
N/A
N/A
No Digital Microphones (1010 bit pattern sent to ADC to avoid pops)
1
2
Double Edge
DMICDAT1
Two microphones connected to DMICDAT1. PhAdj settings apply to Left microphone.
Right Microphone sampled on opposite phase. DMICDAT2 ignored.
2
2
Double Edge
DMICDAT2
Two microphones connected to DMICDAT2. PhAdj settings apply to Left microphone.
Right Microphone sampled on opposite phase. DMICDAT1 ignored.
3
2
Single Edge
3
2
Double Edge
Revision 0.7.10
DMICDAT1
and
DMICDAT2
DMICDAT1
and
DMICDAT2
DMICDAT1 used for left data and DMICDAT2 used for right data.
Two microphones, one on each data input. “Left” microphone used for each channel. Two
“Right” microphones may be used by inverting the microphone clock or adjusting the
sample phase.
25
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Off-Chip
Digital
Microphones
On-Chip
On-Chip
Multiplexer
DMICDAT1
Left
MUX
Pin
DMICDAT2
Left/Right
Stereo Channels
Output
STEREO
ADC1
Right
DMICCLK
Pin
Microphone not supporting multiplexed output.
Left
Channel
DMICDAT1
Valid Data
Valid Data
Valid Data
Right
Channel
DMICDAT2
Valid Data
Valid Data
Valid Data
Left & Right
Channel
DMICCLK
Dual “Left” Microphone. Mics support multiplexed output.
Valid
Valid
Valid
Left
DMICDAT1
Data
Data
Data
Channel
AND
Valid
Valid
Right DMICDAT2 Valid
Data
Data
Data
Channel
Left & Right
Channel
Valid
Data
Valid
Data
DMICCLK
Figure 6 –Stereo Digital Microphone (Mode 3)
Revision 0.7.10
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P95020 / Preliminary Datasheet
Off-Chip
Digital
Microphones
On-Chip
On-Chip
Multiplexer
DMICDAT1
OR
DMICDAT2
Stereo Channels
Output
MUX
Pin
Shared
Data Input
STEREO
ADC1
DMICCLK
Pin
DMICDAT1
OR
DMICDAT2
Valid
Valid
Data R Data L
Right
Left
Channel Channel
Valid
Data R
Valid
Data L
Valid
Data R
DMICCLK
Figure 7 –Stereo Digital Microphone (Mode 1 & 2)
2.5 AUDIO - ANALOG LINE INPUT
The Analog Line Input path consists of a stereo differential input analog buffer that is routed to the analog mixer and
ADC0. By using the analog mixer, the analog line input may be routed to ADC0, the line output port or the headphone
output port.
2.6 AUDIO - DAC, ADC
There are 2 stereo DACs and 2 stereo ADCs. All converters support sample rates of 8kHz, 11.025khz, 12kHz,
22.050kHz, 16kHz, 24kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz. Word lengths of 16, 20 and 24-bits are selectable.
2.6.1 AUDIO - DAC 0/1
The DAC sample rate and word length are programmed at the I²S input port and the DAC may select either I²S port as the
data source.
Digital volume control provides -95.25 dB to 0dB gain in 0.75 dB steps and mute. The output of DAC0 and DAC1 is sent
to the analog mixer, the headphone output and the line output.
2.6.2 AUDIO - ADC 0/1
Each ADC includes a high pass filter to remove DC offsets present in the input path. Sample rate, word length, and
source ADC are programmed at the I²S output port. If an ADC is selected as the data source for more than one sink (I²S
output or DAC) then the rates must be programmed the same at all sinks. If the rates are not identical, then the highest
priority sink will dominate (I2Sout1, I2Sout2, and DAC). The other sink will be muted under these circumstances. ADC0
Revision 0.7.10
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includes an analog amplifier (0-22.5dB gain in 1.5dB steps) and a multiplexer to select between the line input path or the
analog mixer output.
Note: there is only 1 L/R clock per I²S I/O port. Therefore the input and output rates for that port match.
2.7 AUDIO - AUTOMATIC GAIN CONTROL
The P95020 incorporates digital automatic gain control in the ADC1 record path to help maintain a constant record level
for voice recordings. The AGC maintains the recording level by monitoring the output of the ADC and adjusting the Boost
(analog for analog microphone path or digital for digital microphone path) and digital record gain to compensate for
varying input levels. While the AGC is enabled, the digital record gain and boost register values are ignored.
The AGC target level may be set from -1.5 dB to -22.5
dB relative to the ADC full scale output code in 1.5 dB
steps. The maximum gain allowed may be
programmed to prevent the AGC from using the entire
gain range. The AGC may be applied to either both
channels or only the right or left channel. The AGC
uses both channels to determine proper record level
unless only one channel is selected. When only one
channel is enabled, the other channel is ignored and
that channel‟s gain is controlled by its record gain and
boost register values.
Delay time is the amount of delay between when the
peak record level falls below the target level and when
the AGC starts to adjust gain. The delay time may be
set from 0 ms to 5.9 seconds in 16 steps. Each step is
twice as long as the previous step where 0 is the first
step.
AGC Target
Level
Each additional step may be calculated by:
n
((8*2 )/44100) seconds
where n is the register value from 1 to 15
Decay time is the time that the AGC takes to ramp up
across its gain range. The time needed to adjust the
Delay
Decay
Attack
recording level depends on the decay time and the
Figure 8 – Automatic Gain Control
amount of gain adjustment needed. If the input level is
close to the target level then a relatively small gain adjustment will be needed and will take much less than the
n+10
programmed decay time. Decay time is adjustable from 23.2 ms to 23.8 seconds and may be calculated as (2
/44100)
where n is the register value from 0 to 10. Register values above 10 set the decay to 23.8 seconds.
Attack time is the time that it takes the AGC to ramp down across its gain range. As with the decay time, the actual time
needed to reach the target recording level depends on the attack time and the gain adjustment needed. The attack time
n+8
is adjustable from 5.8 ms to 5.9 seconds and may be calculated as (2 /44100) where n is the register value from 0 to 10.
Register values above 10 set the decay to 5.9 seconds.
The P95020 also provides a peak limiter function. When the AGC is on, quiet passages will cause the gain to be set to
the maximum level allowed. When a large input signal follows a quiet passage, many samples will become clipped as the
AGC adjusts the gain to reach the target record level. Long attack times aggravate this situation. To reduce the number
of clipped samples the peak limiter will force the attack rate to be as fast as possible (equivalent to zero (0) value in the
attack register) until the record level is 87.5% of full scale or less.
To prevent excessive hiss during quiet periods, a signal threshold level may be programmed to prevent the AGC circuit
from increasing the gain in the absence of audio. This is often referred to as a „noise gate‟ or „squelch‟ function. The
signal threshold may be programmed from -72 dB FS to -24 dB FS in 1.5 dB increments.
Under some circumstances, it is desirable to force a minimum amount of gain in the record path. When the AGC is in
use, the minimum gain may be set from 0 to 30 dB to compensate for microphone sensitivity or other needs.
2.8 AUDIO - ANALOG MIXER BLOCK
The Audio subsection implements an analog mixing block for use as an input or output mixer.
The Audio Mixer Block consists of:
Revision 0.7.10
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Input Volume Controls
DAC0
DAC1
Line Input
Analog Mic (in analog mic mode only.)
Master Volume Control
The analog mixer has 4 input sources. Each input has an independent volume control that provides gain from -34.5 dB to
+12 dB (1.5 dB steps) and mute. After mixing, the output may be attenuated up to 46.5 dB (1.5 dB steps) before being
sent to ADC0, the headphone output port and the line output port.
2.9 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE
The Digital Audio Input/ Output Interface consists of:
Dual I²S input/output interface with independent bit rate/depth
Each I²S input/output pair will operate at same bit rate/depth
MCLK is shared and may be programmed for 64, 128, 256, or 384 times the base rate (44.1 kHz or 48 kHz)
The MCLK is used to align the I²S port signals to the host.
PCON Register – MCLK_CFG: I²C Address = Page-0: 55(0x37), µC Address = 0xA037
Bit
Bit Name
Default
Settings
User
Type
[2:0]
MCLK_RATE
000b
RW
3
MCLK_DIV2
0b
RW
4
MCLK_FROM_I2S
0b
RW
5
MCLK_REMAP_EN
0b
RW
6
RESERVED
0b
RW
7
MCLK_SEL
0b
RW
Value
Description / Comments
Only meaningful when MCLK_SEL bit is set. See
table below.
Only meaningful when MCLK_SEL bit is set. See
table below.
0 = MCLK to audio selected from
GPIO9 pin
1 = MCLK to audio selected from
I2S_BCLK2 pin
0 = MCLK is selected from MCLK I/O
MCLK I/O does not bond out due to pin-count
1 = MCLK is selected from I2S or
constraint
GPIO9 pin
RESERVED
0 = Audio clock source from 48 MHz
clock from CLKGEN
MCLK source selection
1 = Audio Clock source from MCLK
Table 5 - MCLK Rate selection: MCLK_DIV2: MCLK_RATE
MCLK_DIV2:MCLK_RATE[2:0]
00xx
0100
0101
0110
0111
10xx
1100
1101
1110
1111
Revision 0.7.10
MCLK Input frequency
12.288M
11.2896M
18.432M
16.9344
12M
24.576M
22.5792M
36.864M
33.8688M
24M
29
Comments
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
Table 6 – MCLK/Sample Rate
Mclk (div = 0)
Mclk (div = 1)
Sample Rate
USB Mode
Mclk/Sample Rate
12.288MHz
24.576MHz
96KHz
0
128
11.2896MHz
18.432MHz
16.9344MHz
12.000MHz
22.5792MHz
36.864MHz
33.8688MHz
24.000MHz
48KHz
256
24KHz
512
16KHz
768
12KHz
1024
8KHz
1536
88.2KHz
128
44.1KHz
256
22.050KHz
512
11.025KHz
1024
96KHz
192
48KHz
384
24KHz
768
16KHz
1152
12KHz
1536
8KHz
2304
88.2KHz
192
44.1KHz
384
22.050KHz
768
11.025KHz
1536
96KHz
1
125
48KHz
250
24KHz
500
16KHz
750
12KHz
1000
8KHz
1500
88.2KHz
20000/147
44.1KHz
40000/147
22.050KHz
80000/147
11.025KHz
160000/147
Two independent serial digital I/O ports provide access to the internal converters. Each port provides a stereo input and
output with shared clocks. The ports support slave mode operation only (clocks supplied by host). Each port may be
programmed for 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.050 kHz, 24 kHz, 44.1 kHz, 48 kHz, 88.2 kHz or 96 kHz
operation. I²S, Left justified and Right justified formats support 16, 20 and 24-bit word lengths.
Revision 0.7.10
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P95020 / Preliminary Datasheet
2.10
AUDIO - REFERENCE VOLTAGE GENERATOR, BUFFER, & FILTERING CAPS
AVREF
The AVREF pin is part of the internal virtual ground reference generator. A capacitor placed between AVREF and
AGND is necessary for acceptable power supply rejection and anti-pop performance. A capacitor of 10 F is
recommended to provide about a 10 second ramp-up time.
ADCREF
The ADC reference also requires a capacitor of at least 1 µF for proper operation.
AFILT
ADC1 augments its internal filter capacitors with external filter capacitors to reduce noise outside of the audio
band before sampling. 1000 pF capacitors connected from the AFILT1 and AFILT2 pins to AGND are
recommended but larger capacitors may be used if reduced signal bandwidth is acceptable. Process variation
will cause bandwidth to vary from part to part. A 1000 pF capacitor will place the filter pole far outside of the 20
kHz bandwidth supported so that the ±1 dB 20 kHz bandwidth limit is guaranteed.
2.11
AUDIO - ANALOG AND CLASS D OUTPUT BLOCK
The Audio subsection provides support for line level, headphone and speaker outputs.
The analog line output port features a source MUX and single ended output buffer designed to drive high impedance
loads. This port has selectable 0/3/6 db gain for -6 dBV, -3 dBV or 0 dBV DAC output levels respectively. The Cap-less
Stereo Headphone Output port is similar to the line level output port but can drive 32 ohm headphones and may operate
without DC blocking capacitors by connecting the physical headphone‟s ground return to the VIRT_GND pin.
A CLASS_D Mono BTL Output and Class D Stereo Processor w/ digital volume control (See CLASS_D section for more
information) provides up to 2.5 W of output power into a 4 ohm speaker.
The line output port, headphone port and CLASS_D BTL Power Output can select from the mixer, DAC0, DAC1 or the
line input (LINE_IN). The line input selection is intended for very low power LINE_IN to LINE_OUT pass-thru when
VDD_AUDIO33 and VDD_AUDIO18 power on, and config LINE_OUT_SCTRL (Setting 2h, see Section 2.15.24) to select
LINE_OUT from LINE_IN.
Revision 0.7.10
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P95020 / Preliminary Datasheet
2.12
AUDIO - CLASS-D BTL AMPLIFIER
P95020 implements a digital Class-D 2.5W (4 ) BTL amplifier which supports both 8 and 4 loads. Gain for the BTL
amplifier is programmable from -91 dB to +36 dB in 0.5 dB steps using the Volume 0/1 registers. Gain changes and mute
may be applied immediately, on zero crossing or ramped from the current to target value slowly. These settings are
controlled using the Gain Control HI/LO registers.
2.12.1 AUDIO - EQ
There are 5 bands of parametric EQ (bi-quad) per channel. Due to the flexibility of the bi-quad implementation, each filter
band may be configured as a high-pass, low-pass, band-pass, high shelving, low shelving or other function.
Each band has an independent set of coefficients. A bi-quad filter has 6 coefficients. One coefficient is normalized to 1
and 5 are programmed into the core. Each band supports up to +15 dB boost or up to -36 dB cut.
2.12.2 AUDIO - Coefficients
The following equations describe each filter band. The fundamental equation is a bi-quadratic of the form:
H ( z)
b0 b1z 1 b2 z 2
a 0 a1z 1 a 2 z 2
Rearranging slightly we can see that normalizing a0 or b0 can reduce the number of stored coefficients.
b1 z 1 b2 z 2
1
b0
b0
b0
H ( z )
a
1
a2 2
a 0 1
z 1
z
a0
a0
Implementation generally takes the form:
b0
b1
b2
a1
a2
yn xn xn 1 xn 2 yn 1 yn 2
a0
a0
a0
a0
a0
It can be seen that 5 coefficients are needed, and if a0 is set to 1 then only b0, b1, b2, a1, and a2 are needed. To
compensate for the total gain realized from all 5 bands the EQ amplitude is adjusted to prevent saturation. Each channel
has an inverse gain coefficient that is used to compensate for the gain in the EQ bands. So, for 5 bands/channel with 5
coefficients/band + inverse gain/channel, there are a total of 52 values needed.
These values are pre-calculated and programmed into RAM before use. The default values should be benign such as an
all-pass implementation, but it is permissible to implement other transfer functions.
2.12.3 AUDIO - Software Requirements
The EQ must be programmed before enabling (bypass turned off). {Coefficients are random at power-on.}
When changing coefficients, the EQ must be bypassed before programming. Muting the path is not sufficient and may not
prevent issues. Changing coefficients while the filter is in use may cause stability issues, clicks and pops, or other
problems.
All coefficients are calculated by software. Software must verify amplifier stability. Programming incorrect coefficients can
cause oscillation, clipping, or other undesirable effects. After calculating coefficients, software must calculate the inverse
gain (normalize the response) for each channel (Left and Right) to prevent saturation or inadequate output levels. All
values are then either programmed directly into the device or stored in a table for use in a configuration file or firmware.
2.13
AUDIO CLASS_D - REGISTERS
The Audio Class-D Module can be controlled and monitored by writing 8-bit control words to the various Registers.
The Base addresses are defined in Table 3 – Register Address Global Mapping on page 20.
2.13.1 AUDIO CLASS_D – RESERVED Registers
These registers are reserved. Do not write to them.
Revision 0.7.10
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P95020 / Preliminary Datasheet
I²C
I²C
I²C
I²C
I²C
Address =
Address =
Address =
Address =
Address =
thru
I²C Address =
thru
Page-2:
Page-2:
Page-2:
Page-2:
Page-2:
Page-2:
Page-2:
Page-2:
26(0x1A), µC Address = 0xA21A
27(0x1B), µC Address = 0xA21B
37(0x25), µC Address = 0xA225
47(0x2F), µC Address = 0xA22F
49(0x31), µC Address = 0xA231
53(0x35), µC Address = 0xA235
64(0x40), µC Address = 0xA240
255(0xFF), µC Address = 0xA2FF
2.13.2 AUDIO CLASS_D – ID HI & LO Registers
This 24 bit read-only register contains a unique ID for each block.
ID_HI: I²C Address = Page-2: 16(0x10), µC Address = 0xA210
ID_LO: I²C Address = Page-2: 17(0x11), µC Address = 0xA211
Bit
Bit Name
[15:0]
ID
Default
Setting
4D52h
User
Type
R
Value
Description / Comments
Unique identifier
2.13.3 AUDIO CLASS_D – VERSION HI & LO Registers
This 24 bit read-only register contains a unique version identifier for each block.
VERSION_HI: I²C Address = Page-2: 18(0x12), µC Address = 0xA212
VERSION_LO: I²C Address = Page-2: 19(0x13), µC Address = 0xA213
Bit
Bit Name
Default
Setting
User
Type
[15:0]
VERSION
0100h
R
Value
Description / Comments
Bits[15:8] updated on major RTL code change.
Bits[7:4] updated on minor RTL code change.
Bits[3:0] updated on metal layer bug fix.
2.13.4 AUDIO CLASS_D – STATUS Registers
These are read-only status registers which provide feedback on the operation of the DSP Filtering functions
STATUS0: I²C Address = Page-2: 20(0x14), µC Address = 0xA214
Bit
Bit Name
Default
Settings
User
Type
[3:0]
fs_clk_synced_loss_cnt
0
0h
R
[6:4]
den_jitter
000b
R
7
fs_clk_synced
0b
R
Value
Description / Comments
Count of the number of times synchronization to i_den is lost since
last initialize.
latched max value of i_den jitter detected after fs_clk_synced.
Cleared on initialize. How many fclks is i_den for ch0 jittering
between samples.
1 = Input sample rate (i_den for ch0) is properly locked to fclk (within
tolerance).
STATUS1: I²C Address = Page-2: 21(0x15), µC Address = 0xA215
Bit
Bit Name
[7:0]
fclks_per_ch0_in_
sample
Default
Settings
00h
User
Type
Value
Description / Comments
Multiply this value by 32 to get the number of fclks between each ch0
input data sample. Knowing the fclk frequency you can then
determine sample rate. Also useful in making sure there are enough
fclks to allow the DSP filtering processes to complete before the next
input sample.
R
STATUS2: I²C Address = Page-2: 22(0x16), µC Address = 0xA216
zerodet_flag
Default
Settings
0b
User
Type
R
limit1
0b
R
2
limit1
0b
R
[5:3]
6
7
RESERVED
limit0latch
limit1latch
000b
0b
0b
R
R
R
Bit
Bit Name
0
1
Revision 0.7.10
Value
Description / Comments
set when input zero detect of long string of zeros.
1 = set if regz saturation after gain multiply for ch0. May change on a
sample by sample basis.
1 = set if regz saturation after gain multiply for ch0. May change on a
sample by sample basis.
RESERVED
Latched version of limit0, clear via GAINCTRL[7].
Latched version of limit1, clear via GAINCTRL[7].
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©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
STATUS3: I²C Address = Page-2: 23(0x17), µC Address = 0xA217
Bit
Bit Name
Default
Settings
User
Type
0
timing_error
0b
R
[7:1]
RESERVED
0000000b
R
Value
Description / Comments
Set if DSP filtering processes didn‟t finish before the next input data
sample. Cleared on initialize.
RESERVED
2.13.5 AUDIO CLASS_D – CONFIG Registers
This 16 bit control register primarily controls operation of the DSP Filter block.
CONFIG0: I²C Address = Page-2: 24(0x18), µC Address = 0xA218
Bit
Bit Name
0
1
2
3
4
5
6
7
eapd
mute
Initialize
offset180
debug_sel_ns
eapd_polarity
RESERVED
swap_pwm_ch
Default
Settings
1b
0b
0b
0b
0b
1b
0b
0b
User
Type
RW
RW
RW
RW
RW
RW
RW
RW
Value
Description / Comments
1 = force External Amp Power Down (EAPD) output to ON.
1 = Mute all channels
1 = initialize/soft reset datapath, CSRs not reset
1 = PWM ch1 offset from ch 0 by 180deg, 0 = 90deg
1 = debug output is from NS/PWM, 0 = NS input
1 = invert eapd
RESERVED
1 = swap ch0/1 on filter output to Noise Shaper
CONFIG1: I²C Address = Page-2: 25(0x19), µC Address = 0xA219
Bit
Bit Name
0
dc_bypass
Default
Settings
0b
User
Type
RW
[2:1]
fira_ratio
01b
R
3
4
5
6
7
firb_bypass
firc_bypass
eq_bypass
prescale_bypass
RESERVED
0b
0b
1b
1b
0b
RW
RW
RW
RW
RW
Revision 0.7.10
Value
Description / Comments
1 = bypass DC Filter
00 = interpolate by 2
01 = bypass
10 = decimate by 2
11 = reserved
Fira ratio
1 = bypass firb interpolation
1 = bypass firc interpolation
1 = bypass equalization filter (must init EQRAM)
1 = bypass EQ prescaler (must init EQRAM)
RESERVED
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©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
2.13.6 AUDIO CLASS_D – PWM Registers
This is a 32-bit register = {PWM3, PWM2, PWM1, PWM0}.
PWM3: I²C Address = Page-2: 28(0x1C), µC Address
PWM2: I²C Address = Page-2: 29(0x1D), µC Address
PWM1: I²C Address = Page-2: 30(0x1E), µC Address
PWM0: I²C Address = Page-2: 31(0x1F), µC Address
RESERVED
RESERVED
Default
Settings
0b
0b
User
Type
RW
RW
2
fourthorder
1b
RW
3
4
5
[7:6]
8
9
[14:10]
15
16
17
[23:18]
[29:24]
RESERVED
roundup
clk320mode
RESERVED
RESERVED
RESERVED
Dithpos
RESERVED
RESERVED
pwm_outflip
dvalue
cvalue
0b
1b
1b
00b
0b
0b
00000b
0b
1b
0b
011000b
001010b
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
[31:30]
outctrl
00b
RW
Bit
Bit Name
0
1
Value
=
=
=
=
0xA21C
0xA21D
0xA21E
0xA21F
Description / Comments
RESERVED
RESERVED
1 = 4th order binomial filter, 0 = 3rd order, noise improve of 6dB by
setting this bit to 0
RESERVED
1 = roundup, 0 = truncate for quantizer
1 = PCA clock mode, pclk = 2560*Fs, 0 = 2048*Fs
RESERVED
RESERVED
RESERVED
Dither position
RESERVED
RESERVED
1 = swap pwm a/b output pair for all channels
dvalue constant field
tristate constant field, must be even and not 0
pwm output muxing, 0 = normal, 1 = swap 0/1, 2 = ch0 on both, 3 =
ch1 on both
2.13.7 AUDIO CLASS_D – LMTCTRL Register
Controls operation of the Volume Limiter (Compressor).
LMTCTRL: I²C Address = Page-2: 32(0x20), µC Address = 0xA220
Bit
Bit Name
0
limiter_en
Default
Settings
0b
User
Type
RW
[2:1]
stepsize
00b
RW
3
[7:4 ]
zerocross
RESERVED
0b
0000b
RW
RW
Value
Description / Comments
1 = enable limiter (compressor)
0 = 0.5 dB
1 = 1.0 dB
2 = 2.0 dB
3 = 4.0 dB
Gain stepsize when incrementing or decrementing:
1 = only change limiter gain value on zero cross.
RESERVED
2.13.8 AUDIO CLASS_D – LMTATKTIME Register
Controls operation of the Volume Limiter (Compressor) Attack Time.
LMTATKTIME: I²C Address = Page-2: 33(0x21), µC Address = 0xA221
Bit
Bit Name
[6:0]
time
7
time10ms
Default
Settings
0000000b
0b
User
Type
RW
RW
Value
Description / Comments
Timer value in units of 1 ms or 10 ms.
0 = value in bits [6:0]
is in 1 ms units
1 = value in bits [6:0]
is in 10 ms units
1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.
2.13.9 AUDIO CLASS_D – LMTRELTIME Register
Controls operation of the Volume Limiter (Compressor) Release Time.
LMTRELTIME: I²C Address = Page-2: 34(0x22), µC Address = 0xA222
Bit
Bit Name
[6:0]
time
7
time10ms
Revision 0.7.10
Default
Settings
0000000b
0b
User
Type
RW
RW
Value
Description / Comments
Timer value in units of 1 ms or 10 ms.
0 = value in bits [6:0]
is in 1 ms units
1 = value in bits [6:0]
is in 10 ms units
35
1 = value in bits 6:0 is in 10ms units, otherwise 1ms units.
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
2.13.10 AUDIO CLASS_D - GAINCTRL Registers
This is a 16-bit register = {GAINCTRL_HI, GAINCTRL_LO}.
GAINCTRL_HI: I²C Address = Page-2: 35(0x23), µC Address = 0xA223
GAINCTRL_LO: I²C Address = Page-2: 36(0x24), µC Address = 0xA224
Bit
Bit Name
Default
Settings
User
Type
0
mute_mode
1b
RW
1
change_mode
0b
RW
2
auto_mute
1b
RW
3
disable_gain
0b
RW
4
stepped_change
0b
RW
5
step_10ms
0b
RW
6
RESERVED
0b
RW
7
clr_latch
0b
RW
[10:8]
step_time
101b
RW
[12:11]
zerodetlen
10b
RW
[15:13]
RESERVED
000b
RW
Value
Description / Comments
0 = soft mute
1 = hard mute
0 = change on zero
cross
1 = change gain
immediately
0 = Don‟t Auto Mute
1 = Auto Mute
0 = Don‟t Disable
1 = Disable
0 = Don‟t Step
1 = Step
0 = 1 ms
1 = 10 ms
Mute After Reset
Gain Change Mode
Auto Mute if long string of zeros detected on input
Disable All Gain Functions (Bypass Gain Multiply)
Step Volume Progressively to New Setting
Units for step_time Value
RESERVED
0 = Don‟t Clear
1 = Clear Limit
0 = 1 units
1 = 2 units
2 = 4 units
3 = 8 units
4 = 16 units
5 = 32 units
6 = 64 units
7 = 128 units
0 = 512 Samples
1 = 1k Samples
2 = 2k Samples
3 = 4k Samples
1 = clear limit 0/1 latches, see STATUS2 reg
Step time units = 1 10,
use n=10
[7:4]
DECAY
0h
RW
2^(n+11)*base_time
Attack time is the time that it takes the AGC to ramp down across its
gain range.
Attack time is the time that it takes the AGC to ramp up across its
gain range
Revision 0.7.10
46
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P95020 / Preliminary Datasheet
AGCSET3 = I²C Address = Page-1: 190(0xBE), µC Address = 0xA1BE
Bit
Bit Name
Def.
Set.
User
Type
[5:0]
THRESHOLD
000000b RW
6
AGCEN_RIGHT
0b
RW
7
AGCEN_LEFT
0b
RW
Value
Description / Comments
000000b = -24 dB
100000b = -72 dB
0 = Disable
1 = Enable
0 = Disable
1 = Enable
-72 dB ~ -24 dB, in 1.5 dB per step
Right Channel AGC Enable
Left Channel AGC Enable
AGCSET4 = I²C Address = Page-1: 191(0xBF), µC Address = 0xA1BF
Bit
Bit Name
Def.
Set.
[4:0]
MIN_GAIN
00000b
[7:5]
BASETIME_CTRL
000b
_MAG
User
Value
Type
00000b = 0 dB
RW
10100b = 30 dB
000 = a, 001 = 2a, 010 =
RW
4a, 011 = 8a, 101 = a/2,
110 = a/4, 111 = a/8
Description / Comments
0 ~ 30 dB, 1.5 dB per step
AGC basetime unit. a = 1/(8 x 44100) second
AGC5_MISC = I²C Address = Page-1: 192(0xC0), µC Address = 0xA1C0
Bit
0
[7:1]
Bit Name
FASTEST_ATTACK
_DIS
RESERVED
Def.
Set.
User
Type
Value
Description / Comments
0b
RW
0 = Not Disabled
1 = Disabled
Disable fastest attack when >85% peak
0000000b
RW
RESERVED
2.15.21 AUDIO - DAC0/1 Control Register Set
DAC_CTRL = I²C Address = Page-1: 193(0xC1), µC Address = 0xA1C1
Bit
Bit Name
[7:0]
RESERVED
Revision 0.7.10
Def.
Set.
00h
User
Type
RW
Value
Description / Comments
RESERVED
47
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
2.15.22 AUDIO - Source Control for Output Converters Registers
There are 4 output converters available: I2SOUT1, I2SOUT2, DAC0 and DAC1. Each may select one of the 4 available
digital data sources: I2SIN1, I2SIN2, ADC0 or ADC1. The output converters assume the characteristics of the selected
source. There is no rate translation. If I²S port 1 is routed to I²S port 2 then the rates of both ports must be the same. If
the rates are not the same, then the output from the sink port will be forced to 0 and will retain the rate programmed for
that port. If data widths are not the same, the data will be truncated or zero-padded as necessary. If an ADC is chosen
as the source for an I²S output then the I²S output characteristics will be used to set the ADC rate and data width. If an
ADC is connected to both I2SOUT1 and I2SOUT2, the characteristics of I2SOUT1 will be used. If a DAC is connected to
an ADC and the ADC is not connected to an I²S port, the ADC and DAC will default to 48 kHz/24-bit.
I2S1_SOURCE: I²C Address = Page-1: 194(0xC2), µC Address = 0xA1C2
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
00b = I2SIN1
01b = I2SIN2
10b = ADC0
11b = ADC1
I2S1 source select
[1:0]
I2S1_SOURCE_SE
00b
L
RW
[7:2]
RESERVED
RW
000000b
RESERVED
I2S2_SOURCE: I²C Address = Page-1: 195(0xC3), µC Address = 0xA1C3
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
00b = I2SIN1
01b = I2SIN2
10b = ADC0
11b = ADC1
I2S2 source select
[1:0]
I2S2_SOURCE_SE
00b
L
RW
[7:2]
RESERVED
RW
000000b
RESERVED
DAC0_SOURCE: I²C Address = Page-1: 196(0xC4), µC Address = 0xA1C4
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
00b = I2SIN1
01b = I2SIN2
10b = ADC0
11b = ADC1
DAC0 source select
[1:0]
DAC0_SOURCE_S
00b
EL
RW
[7:2]
RESERVED
RW
000000b
RESERVED
DAC1_SOURCE: I²C Address = Page-1: 197(0xC5), µC Address = 0xA1C5
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
00b = I2SIN1
01b = I2SIN2
10b = ADC0
11b = ADC1
I2S0 source select
[1:0]
DAC1_SOURCE_S
00b
EL
RW
[7:2]
RESERVED
RW
000000b
RESERVED
2.15.23 AUDIO – Class D BTL Amplifier Source Control Register
There are 4 audio sources available for the BTL amplifier. The left and right sources may be selected independently. The
DAC and mixer outputs are a nominal -6 dBV and are amplified at the output port to achieve the desired output level.
CLASSD_SOURCE: I²C Address = Page-1: 198(0xC6), µC Address = 0xA1C6
Bit
Bit Name
Def.
Set.
User
Type
[1:0]
RIGHT_SEL
00b
RW
[3:2]
LEFT_SEL
00b
RW
[5:4]
6
RESERVED
RIGHT_MUTE
00b
0b
RW
RW
7
LEFT_MUTE
0b
RW
Revision 0.7.10
Value
Description / Comments
00b = Mixer
01b = DAC0
10b = DAC1
11b = LINE IN
00b = Mixer
01b = DAC0
10b = DAC1
11b = LINE IN
Class-D right source select
Class-D left source select
RESERVED
ADC2-right(for class-D) mute
0 = Normal
1 = Mute
0 = Normal
1 = Mute
ADC2-left (for class-D) mute
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©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
2.15.24 AUDIO - Source control for Line Output Register
There are 4 audio sources available for the Line Output port. The left and right sources may be selected independently.
The DAC and mixer outputs are a nominal -6 dBV and are amplified at the output port to achieve the desired output level.
LINE_OUT_SCTRL: I²C Address = Page-1: 199(0xC7), µC Address = 0xA1C7
Bit
Bit Name
Default
Setting
User
Type
[1:0]
RIGHT_SEL
00b
R/W
[3:2]
LEFT_SEL
00b
R/W
MUTE
RESERVED
1b
0b
R/W
R/W
4
5
[7:6]
LOG
10b
R/W
Value
Description / Comments
00b = Mixer
01b = DAC0
10b = DAC1
11b = Line-in
00b = mixer
01b = DAC0
10b = DAC1
11b = line-in
0 = Mute
1 = Normal operation
Right line-out select
Left line-out select
RESERVED
00 = 0 dB
01b = +3 dB
10b = +6 dB
11b = Reserved
Line-out Port Gain
2.15.25 AUDIO - Source control for Headphone Output Register
There are 3 audio sources available for the Headphone Output port. The left and right sources may be selected
independently. The DAC and mixer outputs are a nominal -6dBV and are amplified at the output port to achieve the
desired output level.
I²C Address = Page-1: 200(0xC8), µC Address = 0xA1C8, Offset = 0xC8
Bit
Bit Name
Default
Setting
User
Type
[1:0]
RIGHT_SEL
00b
R/W
[3:2]
LEFT_SEL
00b
R/W
MUTE
RESERVED
0b
0b
R/W
R/W
4
5
[7:6]
HPG
0b
R/W
Value
Description / Comments
00b = Mixer
01b = DAC0
10b = DAC1
11b = Line-in
00b = Mixer
01b = DAC0
10b = DAC1
11b = Line-in
0 = Mute
1 = Normal operation
Right headphone output select
Left headphone output select
RESERVED
00b = 0 dB
01b = +3 dB
10b = +6 dB
11b = Reserved
Headphone gain
2.15.26 AUDIO – Audio I2S1 Port Configuration 1
I²C Address = Page-1: 201(0xC9), µC Address = 0xA1C9, Offset = 0xC9
Bit
Bit Name
Def.
Set.
User
Type
[1:0]
BIT_PER_SAMP
00b
RW
[4:2]
DIV
000b
RW
[6:5]
7
MULT
00b
RW
BASE_RATE
0b
RW
Revision 0.7.10
Value
Description / Comments
00b = 16
01b = 20
10b = 24
11b = RESERVED
0 ~ 7 = div 1 ~ 8
00b = x1 or less
01b = x2
10b = RESERVED
11B = RESERVED
0b = 48 kHz
1b = 44.1 kHz
49
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
2.15.27 AUDIO – Audio I2S1 Port Configuration 2
I²C Address = Page-1: 202(0xCA), µC Address = 0xA1CA, Offset = 0xCA
Bit
Bit Name
Def.
Set.
User
Type
[1:0]
FRMT
00b
RW
2
RXEN
0b
RW
3
LR_SWAP
0b
RW
4
WSINV
0b
RW
5
BCLKINV
0b
RW
6
MSS
0b
RW
7
TXEN
0b
RW
Value
Description / Comments
00b = I2S
01b = Left justified
10b = Right justified
11b = RESERVED
0b = Disabled
1b = Port Rx enabled
0b = Normal operation
1b = L and R swap
0b = Normal Operation
1b = Invert word clock
0b = Normal Operation
1b = Invert bit clock
0b = Slave (only)
1b = Master
0b = Disabled
1b = Port Tx enabled
Link format
Rx enable
Swap left and right at output enable
Invert word clock
Invert bit clock
Master/slave
Tx enable
2.15.28 Audio I2S2 Port Configuration 1
I²C Address = Page-1: 203(0xCB), µC Address = 0xA1CB, Offset = 0xCB
Bit
Bit Name
Def.
Set.
User
Type
[1:0]
BIT_PER_SAMP
00b
RW
[4:2]
DIV
000b
RW
[6:5]
7
MULT
00b
RW
BASE_RATE
0b
RW
Value
Description / Comments
00b = 16
01b = 20
10b = 24
11b = RESERVED
0 ~ 7 = div 1 ~ 8
00b = x1 or less
01b = x2
10b = RESERVED
11B = RESERVED
0b = 48 kHz
1b = 44.1 kHz
2.15.29 Audio I2S2 Port Configuration 2
I²C Address = Page-1: 204(0xCC), µC Address = 0xA1CC, Offset = 0xCC
Bit
Bit Name
Def.
Set.
User
Type
[1:0]
FRMT
00b
RW
2
RXEN
0b
RW
3
LR_SWAP
0b
RW
4
WSINV
0b
RW
5
BCLKINV
0b
RW
6
MSS
0b
RW
7
TXEN
0b
RW
Revision 0.7.10
Value
Description / Comments
00b = I2S
01b = Left justified
10b = Right justified
11b = RESERVED
0b = Disabled
1b = Port Rx enabled
0b = Normal operation
1b = L and R swap
0b = Normal Operation
1b = Invert word clock
0b = Normal Operation
1b = Invert bit clock
0b = Slave (only)
1b = Master
0b = Disabled
1b = Port Tx enabled
50
Link format
Rx enable
Swap left and right at output enable
Invert word clock
Invert bit clock
Master/slave
Tx enable
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
2.15.30 AUDIO - Audio Subsection Power Control 1 Register
I²C Address = Page-1: 209(0xD1), µC Address = 0xA1D1, Offset = 0xD1
The Audio Subsection provides gross and fine power control. This register controls large blocks of the Audio Subsection.
Bit
0
1
2
Def.
Set.
Bit Name
LINE_IN_D2S_PWD
DIG _PWD
VREF_PWD
User
Type
0b
RW
0b
RW
0b
RW
3
ADC_PWD
0b
RW
4
DAC_PWD
0b
RW
5
STANDBY
0b
RW
[7:6]
RESERVED
Value
Description / Comments
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Normal operation
1 = Standby mode
Line Input D2S power down
RW
DIGITAL path power down (I²S)
Reference power down
ADC power down
DAC power down
Low power mode
RESERVED
2.15.31 AUDIO - Audio Subsection Power Control 2 Register
I²C Address = Page-1: 210(0xD2), µC Address = 0xA1D2, Offset = 0xD2
The Audio Subsection provides gross and fine power control. This register controls individual DAC and ADC channels of
the Audio Subsection.
Bit
0
1
2
3
4
5
6
7
Bit Name
DAC0L_PWD
DAC0R_PWD
DAC1L_PWD
DAC1R_PWD
ADC0L_PWD
ADC0R_PWD
ADC1L_PWD
ADC1R_PWD
Def.
Set.
User
Type
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
Value
Description / Comments
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
Power down Left half of DAC0
Power down Right half of DAC0
Power down Left half of DAC1
Power down Right half of DAC1
Power down Left half of ADC0
Power down Right half of ADC0
Power down Left half of ADC1
Power down Right half of ADC1
2.15.32 AUDIO - Audio Subsection Power Control 3 Register
I²C Address = Page-1: 211(0xD3), µC Address = 0xA1D3, Offset = 0xD3
The Audio Subsection provides gross and fine power control. This register controls individual DAC and ADC channels of
the Audio Subsection.
Bit
Bit Name
0
RESERVED
HP_VIRTBUF_PWD
1
2
3
4
5
6
7
HP_RIGHT_PWD
HP_LEFT_PWD
LINEOUT_RIGHT_PWD
LINEOUT_LEFT_PWD
ADC2_RIGHT_PWD
ADC2_LEFT_PWD
Revision 0.7.10
Def.
Set.
0h
User
Type
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
Value
Description / Comments
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
0 = Not powered down
1 = Powered down
51
RESERVED
Power down Headphone Virtual Ground Buffer
Power down Right channel of Headphone out
Power down Left channel of Headphone out
Power down Right channel of Line out
Power down Left channel of Line out
Power down Right half of ADC2
Power down Left half of ADC2
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
3.0 CHARGER MODULE
Battery Charger, including switching buck regulator, charger, ideal diode and precision reference
CHARGER FEATURES
High Efficiency Switch Mode Pre-Regulator for System
Power (VSYS)
Programmable USB or Wall current limit
(100mA/500mA/1A/1.5A/2A)
Low Headroom Linear Charger
1.5A Maximum Charge Current
Internal 180mIdeal Diode + External Ideal Diode
Automatic load prioritization
Independent Die-Temperature Sensor for Charger
Battery Temperature Monitor
Optional Discharger for Battery Safety
Independent Precision Bandgap Reference
Battery Voltage Monitor
Power-On Reset Circuit
CHARGER DESCRIPTION
The CHARGER module is the input power manager for
the P95020. It consists of the switch-mode Battery
Charger, a Precision Reference and an Ideal Diode. It
also generates the VSYS power-on-reset when the system
is powered up or when a battery or power adapter is
attached.
The CHARGER consists of three power sources:
VBUS: Wall Adapter or USB provided power
VBAT: Battery on VBAT will either deliver power to VSYS
through the ideal diode or be charged from VSYS via the
charger.
VSYS: Output voltage of the Switch Mode Pre-Regulator
and Input Voltage of the Battery Charger.
VBUS INPUT
ILIM / CLSEN
106
107
112
P
Register
Interface
Pre-Regulator:
Buck + UVLO
P
VSYS
108
109
SW
104
105
PGND
102
103
clk1k
P
Die Temperature
Sensor
Ref_Gnd
A
ICHRG
Linear Charger,
Safety Discharger,
Ideal Diode &
Control
Precision
Reference
113
P
VBAT
110
111
Battery Voltage
Monitor
NTC
Battery
Temperature
Sensor
115
Battery
Pack
VNTC
116
P
Power-On
Reset
POR
Figure 9 – Charger Block Diagram
3.1
CHARGER - OVERVIEW
The Charger operation is hardware autonomous with software redundancy and configuration. On powerup it is configured
for a generic charging algorithm by default, however this is mask defined. Input current limiting selection is set by current
limit configuration register on powerup. After powerup the current limit can be set by GPIO4/CHRG_ILIM (write INT_ILIM
of Current Limit Configuration Register to 0), low stands for 500mA current limit while high stands for 1.5A current limit.
The GPIO pin configuration is defined in the GPIO_TSC Module and the Current Limit Configuration is defined in the
CHARGER MODULE. Both Charger and GPIO_TSC settings must be consistent to ensure that the P95020 works
properly. For example, if the charger registers are programmed such that current limiting is set via an external pin then
that GPIO must also be properly set in the GPIO_TSC registers to prevent it from being assigned to other functions.
3.2
CHARGER – SUB-BLOCKS
The CHARGER block includes the following sub- blocks:
Revision 0.7.10
52
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
A switching Pre-Regulator to regulate/power the system power (VSYS) when adapter input is present
A low-headroom Linear Charger which charges the Li-Ion/Li-Poly battery when adapter input is present and the battery is
not fully charged, and optionally discharges the battery for safety when the battery temperature is too high and the
battery is fully charged.
A Die-Temperature Sensor which monitors the die temperature so hardware autonomous actions can be taken to lower
the charging current when the die-temperature is too high;
A Battery Temperature Monitor which monitors the battery pack temperature through the NTC pin, charging is paused
when the battery‟s temperature is out of range (higher than 40°C or lower than 0°C);
A precision Bandgap for a reference for the charging voltage control;
A Battery Voltage Monitor which monitors the VBAT level solely for the charger (not for system level monitoring);
A Power-On Reset circuit which generates a reset for the system when VSYS is first powered on.
A Configuration Register Block with Register Access Interface, which allows system to access registers implemented
in this module.
3.3
CHARGER – DC ELECTRICAL CHARACTERISTICS
3.3.1
CHARGER - Buck Regulator Electrical Characteristics
Unless otherwise specified, typical values at TA =25C, VBUS = 5V, TA = -40°C to +85°C, COUT=10µF, L=2.2µH, CIN=1µF, CHRG_BAT=3.8V, RICHRG=1K,
RCLSEN=600
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VBUS
Input Supply Voltage
4.35
5.5
V
1x
90
95
100
5x
440
470
500
10x
950
1000
1050
IBUSLIM
Input Current Limit
mA
15x
1425
1500
1575
20x
1900
2000
2100
IVBUSQ
VBUS Quiescent Current
RCLSEN
Ratio of Measured VBUS Program Current
VCLSEN
CLSEN Detect Voltage In Current Limit
VBUS_UVLO
VBUS Under Voltage Lockout
VSYS
System Output Voltage (During Charging)
FOSC
RHS
RLS
Switching Frequency
High Side Switch On Resistance
Low Side Switch On Resistance
IPEAKLIM
Peak Switch Current Limit
DMAX
tSOFTSTART
ILEAKSW
PWM Max Duty Cycle
Soft Start Rise Time
Leakage Current Into SW pin
Revision 0.7.10
1x
5x
10x
15x
20x
1x
5x
10x
15x
20x
1x
5x
10x
15x
20x
Rising edge
Hysteresis
1X,5X,10X,15X,20X Modes,
0 V < VBAT 120°C
0 = Temp ≤ 120°C
In Process of Charging
Charge Complete
VSYS < 3.6 V
1: Charger thermal sensor detected Temperature > 120°C
3.5.8
CHARGER - Interrupt Status Register
I²C Address = Page-0: 151(0x97), µC Address = 0xA097
Bit
Bit Name
Def.
Set.
User
Type
0
ADAPTER_INT
0b
RW1C
1
CUR_LIM_INT
0b
RW1C
2
CHRG_DONE_INT
0b
RW1C
[7:3]
RESERVED
00000b
RW
Value
Description / Comments
1 = IN_STAT Changed
0 = IN_STAT Not Changed
1 = CL_STATUS Changed
0 = CL_STATUS Not Changed
1 = Charge Done status low to high
0 = Charge Done status not change
Adapter Input Status Changed
Current Limit Status Changed
Set when rising edge of CHRG_DONE status detected
3.5.9
CHARGER - Interrupt Enable Register
I²C Address = Page-0: 152(0x98), µC Address = 0xA098
Bit
Bit Name
Def.
Set.
User
Type
0
ADAPTER_INT_EN
1b
RW
1
CUR_LIM_INT_EN
0b
RW
2
CHRG_DONE_INT_
EN
0b
RW
00000b
RW
[7:3]
RESERVED
Value
Description / Comments
1 = Interrupt
Enabled
0 = Interrupt Not
Enabled
1 = Interrupt
Enabled
0 = Interrupt Not
Enabled
1 = Interrupt
Enabled
0 = Interrupt Not
Enabled
Adapter Input Interrupt Enable
Current Limit Interrupt Enable
Charging DONE Interrupt Enable
3.5.10
CHARGER - RESERVED Registers:
Do not write to these registers. They are all RESERVED registers.
I²C Address = Page-0: 153(0x99), µC Address = 0xA099
Thru = Page-0: 159(0x9F), µC Address = 0xA09F
3.6
CHARGER - PRE-REGULATOR
The Pre-Regulator is a buck converter which can provide currents up to 2A. It monitors the external input voltage and,
when this voltage is high enough, it regulates VSYS to 3.6V or (VBAT+0.3V) whichever is greater. The regulator will stop
running if the input voltage is too low (UVLO).
This block will generate a status of whether the adapter input (VBUS) is ready/powered so system will be aware of the
power source of the whole system, and can adjust the operating parameters accordingly.
The average input current is monitored and limited by the current limit settings. A resistor (600 from CLSEN to ground
determines the upper limit of the current drwan from the VBUS pin. A fraction of the VBUS current is send to the CLSEN pin
when the synchronous switch of the Pre-Regulator is on. Several VBUS current limit settings are available via input pin or
Revision 0.7.10
58
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
current limit configuration registers. If INT_ILIM (bit7) of current limit configuration register (0xA090) is 1, the current limit
is defined by I_ILIM[2:0]. If INT_ILIM is 0, the current limit is defined by GPIO4/CHRG_ILIM pin. Low stands for 500mA
current limit while high stands for 1.5A current limit. The default setting is 100mA when VSYS is not ready at start up.
When VSYS is ready, the current limit value is obtained from the internal register setting, which can be a default setting
(power up) or dynamic setting (after the external application processor programs it).
VSYS drives both the system load and the battery charger. If the combined load does not cause the switching regulator to
exceed the programmed input current limit, VSYS will track approximately 0.3V above the battery. By keeping the voltage
across the battery charger low, efficiency is optimized because power lost to the linear battery charger is minimized.
Power available to the external load is therfore optimized.
If the combined system load at VSYS is large enough to cause the switching power supply to reach the programmed input
current limit, VSYS will drop. Depending on the configuration, the battery charger will reduce its charge current when the
VSYS drop below 3.6V to enable the external load to be satisfied.
If the voltage at VBAT is below 3.3V and the load requirement does not cause the switching regulator to exceed the
programmed input current limit, VSYS will regulate at 3.6V. If the load exceeds the available power, VSYS will drop to a
voltage between 3.6V and the battery voltage. Figure 10 shows the range of possible voltages at VSYS as function of
battery voltage.
For very low battery voltage, due to limited input power, charging current will tend to pull VSYS below the 3.6V “instant-on”
voltage. If instant-on operation under low battery conditions is a requirement then DIS_INST_ON of Charger Special
Control Register (0xA094) should be set to 0. An under voltage circuit will automatic detects that VSYS is falling below 3.6V
and disable the battery charging. If maximun charge current at low battery voltage is preferred, the instant-on function
should be disabled by setting DIS_INST_ON to 1. If the load exceed the current limit at VBUS and the system is not in the
instant-on mode, the battery charger will reduce its charge current when under voltage circuit detects VSYS is falling below
3.6V.
2.4V
2.7V
3.0V
3.3V
3.6V
3.9V
4.2V
4.5V
VSYS
VBAT
2.4V
2.7V
3.0V
3.3V
3.6V
3.9V
4.2V
Figure 13 – VSYS Regulation Curve (Tracking VBAT )
3.7
IDEAL DIODE FROM VBAT TO VSYS
The charger has and internal ideal diode as well as a controller for an optional external ideal diode. The ideal diode
controller is always on and will respond quickly whenever VSYS drops below VBAT. If the load current increases beyond the
power allowed from the switching regulator, additional power will be pulled from the battery via the ideal diode.
Furthermore, if power to VBUS (USB or wall power) is removed, then all of the application power will be provided by the
battery via the ideal diode. The ideal diode consists of a precision amplifier that enables a large on-chip P-channel
MOSFET transistor whenever the voltage at VSYS is approximately 15mV below the voltage at VBAT. The resistance of the
internal ideal diode is approximately 180mIf this is sufficient for the application, then no external components are
necessary. However, if more current is needed, an external P-channel MOSFET transistor can be added from VBAT to
Revision 0.7.10
59
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
VSYS. When an external P-channel MOSFET transistor is present, the CHRG_GATE pin of P95020 drives its gate for
automatic ideal diode control. The source of the external P-channel MOSFET should be connected to VSYS and the drain
should be connected to VBAT.
3.8
CHARGER - CHARGER/DISCHARGER
The system includes a constant-current/constant-volatge battery charger with automatic recharge, automatic termination
by termination current and safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out
of temperature charge pausing.
Battery Preconditioning
When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery
voltage is below VTRKL, typically 2.8V, an automatic trickle charge feature sets the battery charge current to recover charge
current (7 step 25mA/step programmable by Application Setting Register). If the low voltage persists for more than ½
hour, the battery charger automatically terminates and indicates via battery fault flag in the Status 1 Register that the
battery is defective. Once the battery voltage is above VTRKL, the battery charger begins charging in full power constant
current mode. The current delivered to the battery will try to reach ICHG (step 100mA, 1X ~15X programmable by Charging
Configuration Register), the battery charger may or may not be able to charge at the full programmed rate. The external
load will always be prioritized over the battery charge current. The USB (or Wall adapter) current limit programming will
always be observed.
Charge Termination
When the voltage on the battery reaches the pre-programmed float voltage (4.1V or 4.2V), the battery charger enters
constant voltage mode and the charge current will decrease as the battery becomes fully charged.The charger offers
several methods to terminate a charge cycle by setting the Charging Termination Control Register bits[1:0]. Refer to the
register definition section for the details.
Intelligent Start and Automatic Recharge
When the charger is initially powered on, the charger checks the battery voltage. If the VBAT pin is below the recharge
threshold of 3.9V (which corresponds to approximately 50-60% battery capacity), the charger enters charge mode and
begines a full charge cycle. If the VBAT pin is above 3.9V, the charger enters standby mode and does not begine charging.
This feature reduces unnecessary charge cycle thus prolongs battery life. When the charger is in standby mode, the
charger continuously monitors the voltage on the VBAT pin. When the voltage drops below 3.9V and the temperature below
40°C, the charge cycle is automatically restarted and the safety timer and termination timer (if time termination is used) is
reset to 50% of the programmed time. This feature eliminates the need for periodic charge cycle initiations and ensures
the battery is always fully charged.
Battery Temperature Monitor
The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery
pack. To use this feature, connect the NTC thermistor, RNTC, between the NTC and ground and a resistor, RNOM, from
VNTC to the NTC pin. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at
25°C(R25). For applications requiring greater than 750mA of charging current, a 10k NTC thermistor is recommended.
The charger will pause charging when the NTC thermistor drops to 0.54 times the value of R25 or approximately 5.4k. For
a Vishay “Curve 1” thermistor, this corresponds to approximately 40°C. As the temperature drops, the resistance of the
NTC thermistor rises. The charger will also pause charging when the value of the NTC thermistor increase to 3.25 times
the value of R25. For Vishay “Curve 1” this resistance, 32.5k, corresponds to approximately 0°C. Grounding the NTC pin
disables the NTC charge pausing function.
There is also a battery-discharge feature: when the battery is full and battery temperature go beyond 60°C, the NTC
thermistor drops to 0.25 times the value of R25. The charger can discharge the battery to 3.9V for safety
The VNTC pin output is dynamically enabled to save power. The NTC measurement is triggered every 5 seconds. Each
measurement takes 16ms.
3.9
CHARGER - THERMAL MONITORING
A thermal sensor is used in charging control, An internal thermal feedback loop reduces the charge current if the die
temperature attempt to rise above the preset value of approximately 120°C. This feature protects the charger from
excessive temperature and allows the pushing of the limits of the power handling capability of a given circuit board without
the risk of damagingThis thermal sensor is not used for system level die-temperature detection.
3.10 CHARGER - POWER ON RESET
A Power-On reset circuit will generate a reset when the VSYS power goes from low to high. The signal is used to reset all
the logic powered directly or indirectly by VSYS.
Revision 0.7.10
60
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
4.0 CLOCK GENERATOR MODULE
FEATURES
High-quality, high-frequency external clock outputs
generated from a TCXO input or a crysal contected
between HXTALIN and HXTALOUT.
32.768 kHz crystal oscillator or 32.768 kHz clock input
for system start-up
3.3V core operating voltage
1.2V/1.8V TCXO output voltage
3.3V SYS_CLK, USB_CLK and 32KHZ clock output
DESCRIPTION
The P95020 includes a highly accurate, low power clock
synthesizer designed exclusively for portable applications.
The P95020 will generate high quality, high-frequency
clock outputs from a 12 MHz, 13 MHz, 19.2 MHz or 26
MHz TCXO input or crystal oscillator. The P95020‟s clock
generator (CKGEN) module also includes a 32 kHz
oscillator and output, which are connected to a separate
low power supply, to facilitate system start-up.
voltages
VDDIO_CK
VDDIO_CK
12MHz
TCXO_OUT2
48MHz
VDD_CKGEN33
SYS_CLK
HXTAL
OSC
PLL
dividers
24MHz
VDD_CKGEN33
VDDIO_CK
USB_CLK
VDD_CKGEN33
Xtal oscillator,
RC-Oscillator
CLK32K
32KHZ_OUT2
I2C
SUB-BLOCK
MICROCONTROLLER
SUB-BLOCK
UPPER BYTE
OFFSET: 0xA0
CKGEN PLL CONFIGURATION REGISTER
0x34 [7:0]
CKGEN_GND
32KHZ_OUT1/
XTALOUT
32KHZ_CLKIN/
XTALIN
HXTALIN/
TCXO_OUT1
HXTALOUT/
TCXO_IN
PLL STATUS REGISTER
0x35 [7:0]
Figure 14 – Clock Generator Block Diagram
4.1
PIN #
041
042
CKGEN - PIN DEFINITIONS
PIN_ID
32KHZ_OUT2
CKGEN_GND
043
32KHZ_CLKIN/XTALIN
044
XTALOUT/32KHZ_OUT1
045
046
VDD_CKGEN18
HXTALOUT/TCXO_IN
Revision 0.7.10
DESCRIPTION
Buffered 32.768 kHz Output #2
PLL Analog Ground
32KHZ_CLKIN: External 32.768 kHz clock input
XTALIN : Input pin when used with an external crystal
XTALOUT: Output pin when used with an external crystal
32KHZ_OUT1: When XTALIN is connected to a 32 kHz input this pin can be a 32 kHz output when bit 4 of
the CKGEN_PLL_STATUS register is set to 1.
Internal 1.8V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal oscillator output
61
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
047
VDD_CKGEN33
048
HXTALIN/TCXO_OUT1
049
050
051
052
053
TCXO_OUT2
SYS_CLKOUT
CKGEN_GND
USB_CLKOUT
VDDIO_CK
4.2
TCXO_IN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz TXCO Clock Input
Internal 3.3V CKGEN LDO. Connect filter capacitor from this pin to CKGEN_GND
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz Crystal Oscillator Input
TCXO_OUT1: Buffered TXCO_IN/HXTAL Clock Output #1, 32.768 kHz Output, 24 MHz PLL Output
Buffered TXCO_IN/HXTAL Clock Output #2, 12 MHz PLL Output, 48 MHz PLL Output
12 MHz Output or Buffered Output of TCXO_IN/HXTAL
PLL Analog Ground
24 MHz or 48 MHz Output
Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V – 1.9V)
CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VDD_CKGEN33 = 3.3V, VDD_CKGEN18 = 1.8V, VSYS = 3.8V, TA = -40°C to +85°C,
SYMBOL
VDD_CKGEN33
VDD_CKGEN18
PARAMETER
Operating Voltage
VDDIO_CK
CONDITIONS
Internal LDO Regulator
MIN
2.97
TYP
3.3
MAX
3.63
UNIT
V
Internal LDO Regulator
1.62
1.8
1.98
V
Power Input for TCXO_OUT1 and
TCXO_OUT2
1.1
1.9
V
IDD_CKGEN33
IDD_CKGEN18
Supply Current
VDDIO_CK
VIH
TCXO_IN High Level Input
Voltage
VIL
VOH
TCXO_IN Low Level Input
Voltage
32KHZ_CLKIN High Level Input
Voltage
32KHZ_CLKIN Low Level Input
Voltage
Output High for SYS_CLK,
USB_CLK
Output Low for SYS_CLK,
USB_CLK
Output High for 32KHZ_OUT2
VOL
Output Low for 32KHZ_OUT2
IOL = 1mA
VOH
Output High for TCXO_OUT
VDDIO_CK = 1.8V, IOH = -4mA
VOL
Output Low for TCXO_OUT
VDDIO_CK = 1.8V, IOL = 4mA
VOH
Output High for TCXO_OUT
VDDIO_CK = 1.2V, IOH = -1mA
VOL
Output Low for TCXO_OUT
VDDIO_CK = 1.2V, IOL = 1mA
fo_CLK32
Input Frequency
32 kHz Clock
fo_CLKTCXO
Input Frequency
TCXO_IN
ESRCLK32
Series Resistance
CL_CLK32
Load Capacitance
tOR/tOF
tSKEW
Output Rise Time/Fall Time
32 kHz output, Note 1
Output Rise Time/Fall Time
SYS_CLK, USB_CLK output,
Note 3
Output Rise Time/Fall Time
Other outputs, Note 1
Output-Output Skew
IOS
Short Circuit Current
RO
Output Impedance
DCLOCKOUT
Output Clock Duty Cycle,
Oscillator Buffered Output
Output Clock Duty Cycle, PLL
Output
Frequency Synthesis Error
VIH
VIL
VOH
VOL
tOR/tOF
tOR/tOF
DCLOCKOUT
FSYN-ERR
Revision 0.7.10
4
mA
1
mA
2
mA
0.7xVDD_
CKGEN18
VDD_CKG
EN18 +
0.3
0.3xVDD_
CKGEN18
VLD0_LP +
0.3
0.3x
VLD0_LP
-0.3
0.7x
VLD0_LP
-0.3
IOH = -4mA
0.7xVDD_
CKGEN33
V
V
V
V
IOL = 4mA
IOH = -1mA
V
0.3xVDD_
CKGEN33
0.7xVDD_
CKGEN33
V
V
0.3xVDD_
CKGEN33
0.7xVDDI
O_CK
V
V
0.3xVDDI
O_CK
0.7xVDDI
O_CK
V
V
0.3xVDDI
O_CK
32.768
V
kHz
12MHZ, 13MHZ, 19.2MHZ,
26MHZ
45
k
6
pF
Between 20% to 80%,
5.0
ns
Between 20% to 80%,
1.2
ns
Between 20% to 80%,
1.8
ns
TCXO_1 to TXCO_2
±50
ps
Clock outputs
±70
mA
20
40
60
%
45
55
%
0
62
ppm
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
STJITTER
24, 48 MHz Output
32 kHz Output
From minimum VDD_CKGEN18 and
VDD_CKGEN33 to outputs stable to
±1% Note 2
From stable crystal 32kHz input to
stable output
Short Term Jitter (peak-to-peak)
Power-up Time
tPU
200
300
3
ps
ns
ms
300
ms
Notes:
1. Measured with a 5pF load.
2. Power-up time for TCXO derived output frequencies only after TCXO has stabilized.
4.3
CKGEN - PLL CONTROL
The PLL in the CKGEN module is powered on/off by setting bits [2:0] in the CKGEN_PLL_CFG register as shown below.
S2
0
S1
0
S0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PLL behavior
PLL OFF
PLL power up with 26MHz TCXO_IN as
reference clock
PLL power up with 32kHz XTAL_IN as
reference clock
PLL power up with 26MHz TCXO_IN
as reference clock
PLL OFF
PLL power up with 12MHz TCXO_IN as
reference clock
PLL power up with 13MHz TCXO_IN as
reference clock
PLL power up with 19.2MHz TCXO_IN
as reference clock
The 12 MHz and 48 MHz outputs are enabled/disabled by setting bits [7:6] in the CKGEN_PLL_CFG register. One or
both of the clock outputs will be enabled when a “1” is written into the corresponding register location for the output in
question.
4.4
CKGEN – OSCILLATOR CIRCUIT
The CKGEN module may use an external 32.768 kHz crystal connected to the XTALIN pin. The oscillator circuit does not
require any external resistors or capacitors to operate. Table 15 specifies several crystal parameters for the external
crystal. The typical startup time is less than one second when using a crystal with the specified characteristics.
4.5
SYMBOL
fo
PARAMETER
Nominal Frequency
ESR
Series Resistance
CL
Load Capacitance
MIN
Table 15 - Crystal Specifications
TYP
MAX
UNITS
32.768
kHz
80
12
COMMENTS
k
pF
CKGEN - CKGEN POWER SOURCE
The CKGEN module receives its power from an on-chip LDO. The CKGEN power is controlled via the “PSTATE_ON” bit
in the Power State and Switch Control Register (see section 13.3.10). Setting that register is automatic whenever there is
an interrupt targeting the embedded processor pending. The “PSTATE_ON” bit can be cleared by writing a logic “1” if
software wants to power down the CKGEN. Please be aware that powering down the CKGEN should be the last
operation by the software, since once CKGEN is powered down, there will be no clock for the internal register access bus
and I²C. The P95020 has a minor delay when the PSTATE_ON bit is cleared to allow the “cleaning” access to be
finished.
When CKGEN is powered, the 8M clock will be available so the I²C/processor will be active. The chip‟s registers can be
accessed. However, the PLLs will still not be on. To turn on the PLLs, S2:S0 registers need to be set.
4.6
CKGEN – CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added
Revision 0.7.10
63
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result
in the clock running fast. Pay attention to PC board layout for isolating the crystal and oscillator from noise.
4.7
CKGEN – CLOCK GENERATOR REGISTERS
4.7.1
CKGEN – CLOCK GENERATOR PLL CONFIGURATION REGISTER
I²C Address = Page-0: 52(0x34), µC Address = 0xA034
Bit
Bit Name
Def.
Set.
User
Type
[2:0]
S2/S1/SO
000b
R/W
3
CLK2M_RATE
0b
R/W
4
SSC_DELTA
0b
R/W
5
SSC_EN
0b
R/W
6
SYS_CLK_OUT_EN 1b
R/W
7
USB_CLK_OUT_EN 1b
R/W
Value
Description / Comments
000b = PLL off
001b = PLL on, 26MHz
TCXO_IN as reference clock
010b = PLL on, 32kHz
XTAL_IN as reference clock
011b = PLL on, 26MHz
TCXO_IN as reference clock
100b = PLL off
101 = PLL on, 12MHz
TCXO_IN is reference clock
110b = PLL on, 13 MHz
TCXO_IN is reference clock
111b = PLL on, 19.2 MHz
TCXO_IN is reference clock
0b = 2 MHz
1b = 1 MHz
0b = +/- 1%
1b= +/- 2%
0b = Disabled
1b = Enabled
0b = Disabled
1b = Enabled
0b = Disabled
1b = Enabled
Tuch Screen Controller Clock
SSC frequency offset setting
DCDC 24MHz clock SSC enable
SYS_CLK clock output enabled
USB_CLK clock output enable
4.7.2
CKGEN – PLL STATUS REGISTER
I²C Address = Page-0: 53(0x35), µC Address = 0xA035
Bit
Bit Name
Def.
Set.
User
Type
0
PLL_LOCK1
0b
R
1
TCXO1_EN
0b
R/W
2
TCXO2_EN
0b
R/W
3
RESERVED
0b
R/W
4
32KOUT1_EN
0b
R/W
5
32KOUT2_EN
0b
R/W
6
32K_STABLE
0b
R
7
RESERVED
0b
R
Revision 0.7.10
Value
Description / Comments
0b = Not locked
1b = Locked
0b = Disabled
1b = Enabled
0b = Disabled
1b = Enabled
Main PLL lock status
TCXO #1 enable
TCXO #2 enable
RESERVED
0b = Disabled
1b = Enabled
0b = Disabled
1b = Enabled
0b = Unstable
1b = Stable
32K clock #1 enable
32K clock #2 enable
32K oscillator or input stable
RESERVED
64
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
4.7.3
CKGEN – CKGEN CONFIGURATION REGISTER
I²C Address = Page-0: 61(0x3D), µC Address = 0xA03D
Bit
Bit Name
Def.
Set.
User
Type
0
OEB_HXTAL
1b
R/W
1
OUT48M_C
0b
R/W
2
OUT12M_C
0b
R/W
[4:3]
TCXO2_C
00b
R/W
[6:5]
TCXO1_C
0b
R/W
7
TCXO_HV_ENB
0b
R/W
Revision 0.7.10
Value
Description / Comments
0b = HXTALIN/TCXO_OUT1 is HXTALIN and
HXTALOUT/TCXO_IN is HXTALOUT
1b = HXTALIN/TCXO_OUT1 is TCXO_OUT1
and HXTALOUT/TCXO_IN is TCXO_IN
0b = Output is 48MHz clock from PLL
1b = Output is 24MHz clock from PLL
0b = Output is 12MHz clock from PLL
1b = Output is from HXTALOUT/TCXO_IN
00b = TCXO_OUT2 is from
HXTALOUT/TCXO_IN
01b = TCXO_OUT2 is 12 MHz clock from PLL
10b = 11b = TCXO_OUT2 is 48 MHz clock from
PLL
00b = TCXO_OUT1 is from
HXTALOUT/TCXO_IN
01b = TCXO_OUT1 is from 32KHZ_CLKIN
10b = 11b = TCXO_OUT1 is 24 MHz clock from
PLL
0b = VDDIO_CK is 1.8V, TCXO_OUT1/2 drive
strength weak
1b = TCXO VDDIO_CK is 1.2V, TCXO_OUT1/2
drive strength strong
65
HXTALIN/TCXO_OUT1 and
HXTALOUT/TCXO_IN Select
USB_CLK Select
SYS_CLK Select
TCXO_OUT2 Select
TCXO_OUT1 Select
VDDIO_CK
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
5.0 RTC MODULE
FEATURES
DESCRIPTION
The low power serial real-time clock (RTC) device has two
programmable time-of-day alarms. Address and data are
transferred serially through the I²C bus. The device
provides seconds, minutes, hours, day, date, month and
year information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either 24-hour format or 12-hour format with
AM/PM indicator.
Real Time Clock (RTC) Counts Seconds, Minutes,
Hours, Day, Date, Month and Year (with Leap-Year
Compensation Valid Up to year 2100
Two time-of-day alarms
Low power
5.1
RTC - GENERAL DESCRIPTION
The Real-Time Clock (RTC) block is a low-power clock/date device with two programmable time-of-day/date alarms. The
clock/date provides seconds, minutes, hours, day, date, month and year information. The date at the end of the month is
automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock operates in
either the 24-hour or 12-hour format with an AM/PM indicator. The RTC cannot be disabled while the system is powered
on. The register settings and logic are only reset the first time the system is powered on by inserting either the wall
adapter or the battery. After reset, the time keeping registers are reset and must be synchronized to the real time by
programming its time keeping registers. The alarm interrupts are disabled by default.
The time and date information is set and monitored by writing and reading the appropriate register bytes. Sections 5.2
and 5.3 below show the RTC TIMEKEEPER and RTC DATE registers. The contents of the time and date registers are in
BCD format. The RTC block can be run in either 12-hour or 24-hour mode. Bit 6 of the HOUR register is defined as the
12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In 12-hour mode, bit 5 is the PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). All hour values, including the
alarms, must be re-entered whenever the TIME_12 mode bit is changed. The century bit (bit 7 of the month register) is
toggled when the YEAR register overflows from 99 to 0. The days register increments at midnight. Values that
correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday
and so on). Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal
registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers at
the time of reading address pointing to zero. The countdown chain is reset whenever the seconds register is written.
Write transfer occurs when the processor bus receives a write command. To avoid rollover issues, once the countdown
chain is reset, the remaining time and date registers must be written within 0.5 second.
The RTC block contains two time-of-day/date alarms. The alarms can be programmed (via the alarm enable and INT_EN
bits of the control registers defined in section 5.5) to activate the interrupt (INT) output when an alarm match condition
occurs. Bit 7 of each of the time of day/date alarm registers are mask bits (Table 2). When all the mask bits for each
alarm are logic 0 an alarm occurs only when the values in the timekeeping registers 00h to 04h match the values stored in
the time-of-day/date alarm register. The alarms can also be programmed to repeat every second, minute, hour, day or
date. Table 16 shows the possible settings.
Table 16 - Alarm mask bits
Revision 0.7.10
DY1
X
X
X
X
0
1
A1M4
1
1
1
1
0
0
A1M3
1
1
1
0
0
0
A1M2
1
1
0
0
0
0
A1M1
1
0
0
0
0
0
Alarm rate
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
DY2
X
X
X
X
0
1
A2M4
1
1
1
1
0
0
A2M3
1
1
1
0
0
0
A2M2
1
1
0
0
0
0
A2M1
1
0
0
0
0
0
Alarm rate
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
66
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
The DY1 bit (bit 6 of the day/date alarm 1 value register) control whether the alarm value stored in bits 0 to 5 of that
register reflects the day of the week or the date of the month. If DY1 is written to a logic 0, the alarm is the result of a
match with date of the month. If DY1 is written to a logic 1, the alarm is the result of a match with day of the week. The
DY2 bit serves the same function for the day/date alarm 2 value register.
The RTC block checks for an alarm match once per second. When the RTC register values match the alarm register
settings, the corresponding Alarm Flag (A1_FLAG or A2_FLAG) bit is set to logic 1. If the corresponding Alarm Interrupt
Enable “A1_EN” or “A2_EN” is also set to logic 1, the alarm condition activates the INT signal. The INT remains active
until the alarm flag is cleared by the user.
5.2
RTC - TIMEKEEPER REGISTERS
The time for the RTC module can be controlled and monitored by writing and reading 8-bit control words to the various
registers described below.
5.2.1
RTC_SEC – RTC Seconds Register
The full range of the seconds counter is 0 through 59.
I²C Address = Page-0: 64(0x40), µC Address = 0xA040
Bit
Bit Name
[3:0]
[6:4]
7
SECOND
SECOND_10
RESERVED
Def.
Set.
0h
000b
User
Type
R/W
R/W
R/W
Value
Description / Comments
0000 = 0, 0001 = 1, etc.
000 = 0, 001 = 1, etc.
Second counter, BCD format, low bits. Range: 0~9
Second counter, BCD format, high bits. Range: 0~5
RESERVED
5.2.2
RTC_MIN – RTC Minutes Register
The full range of the minutes counter is 0 through 59.
I²C Address = Page-0: 65(0x41), µC Address = 0xA041
Bit
Bit Name
[3:0]
[6:4]
7
MINUTE
MINUTE_10
RESERVED
Def.
Set.
0h
000b
User
Type
R/W
R/W
R/W
Value
Description / Comments
0000 = 0, 0001 = 1, etc.
000 = 0, 001 = 1, etc.
Minute counter, BCD format, low bits. Range: 0~9
Minute counter, BCD format, high bits. Range: 0~5
RESERVED
5.2.3
RTC_HR – RTC Hours Register
The full range of the hour counter is 1 through 12 when 12-hour mode is selected, or 0 through 23 when 24-hour mode is
selected.
I²C Address = Page-0: 66(0x42), µC Address = 0xA042
HOUR
HOUR_10
Def.
Set.
0h
0b
User
Type
R/W
R/W
PM
0b
R/W
Bit
Bit Name
[3:0]
4
5
6
TIME_12
7
RESERVED
5.3
0b
R/W
Value
Description / Comments
Hour counter, BCD format, low bits. Range: 0~9
Hour counter, BCD format, high bits. LSB of HOUR_10.
When 12-hour mode is selected, 1 = PM, 0 = AM
When 24-hour mode is selected, this bit is MSB of HOUR_10
1 = 12-hour mode is
selected
0 = 24-hour mode is
selected
R/W
12-hour or 24-hour mode selection bit.
RESERVED
RTC - DATE REGISTERS
The date for the RTC module can be controlled and monitored by reading and writing 8-bit control words to the various
registers described below.
5.3.1
RTC_DAY – RTC Day Register
I²C Address = Page-0: 67(0x43), µC Address = 0xA043
Bit
Bit Name
[2:0]
[7:3]
DAY
RESERVED
Revision 0.7.10
Def.
Set.
000b
User
Type
R/W
R/W
Value
Description / Comments
Day counter, BCD format. Range: 1~7
RESERVED
67
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
5.3.2
RTC_DATE – RTC Date Register
The full range of the date counter is 1 through 31.
I²C Address = Page-0: 68(0x44), µC Address = 0xA044
Bit
Bit Name
[3:0]
[5:4]
[7:6]
DATE
DATE_10
RESERVED
Def.
Set.
1h
00b
User
Type
R/W
R/W
R/W
Value
Description / Comments
Check default
Date counter, BCD format, low bits. Range: 0~9
Date counter, BCD format, high bits. Range: 0~3
RESERVED
5.3.3
RTC_MONTH – RTC Month Register
The full range of the month counter is 1 through 12.
I²C Address = Page-0: 69(0x45), µC Address = 0xA045
Bit
Bit Name
[3:0]
4
[6:5]
MONTH
MONTH_10
RESERVED
7
CENTURY
Def.
Set.
1h
0b
User
Type
R/W
R/W
R/W
0b
R/W
Value
Description / Comments
Check default
Month counter, BCD format, low bits. Range: 0~9
Month counter, BCD format, high bit. Range: 0~1
RESERVED
1 - 100 years
0 = 0 year
Century bit is toggled when the year counter overflows from 99 to 0.
5.3.4
RTC – Year Register
The full range of the year counter is 0 through 99.
I²C Address = Page-0: 70(0x46), µC Address = 0xA046
Bit
Bit Name
[3:0]
[7:4]
YEAR
YEAR_10
5.4
Def.
Set.
0h
0h
User
Type
R/W
R/W
Value
Description / Comments
Year counter, BCD format, low bits. Range: 0~9
Year counter, BCD format, high bit. Range: 0~9
RTC - ALARM REGISTERS
The two alarms supported by the RTC module can be controlled and monitored by writing 8-bit control words to the
various registers described below.
5.4.1
RTC_AL1_SEC – RTC Second Alarm 1 Value Register
I²C Address = Page-0: 71(0x47), µC Address = 0xA047
Def.
Set.
0h
Bit
Bit Name
[3:0]
SECOND_VAL1
SECOND_10_VAL
000b
1
A1M1
0b
[6:4]
7
User
Type
R/W
Value
Description / Comments
Second alarm value, BCD format, low bits. Range: 0~9
R/W
Second alarm value, BCD format, high bits. Range: 0~5
R/W
Alarm 1, mask bit 1
5.4.2
RTC_AL1_MIN – RTC Minute Alarm 1 Value Register
I²C Address = Page-0: 72(0x48), µC Address = 0xA048
Bit
[3:0]
[6:4]
7
Def.
Set.
MINUTE_VAL1
0h
MINUTE_10_VAL1 000b
A1M2
0b
Bit Name
User
Type
R/W
R/W
R/W
Value
Description / Comments
Second alarm value, BCD format, low bits. Range: 0~9
Second alarm value, BCD format, high bits. Range: 0~5
Alarm 1, mask bit 2
5.4.3
RTC_AL1_HR – RTC Hour Alarm 1 Value Register
I²C Address = Page-0: 73(0x49), µC Address = 0xA049
HOUR_VAL1
HOUR_10_VAL1
Def.
Set.
0h
0b
User
Type
R/W
R/W
PM_VAL1
0b
R/W
Bit
Bit Name
[3:0]
4
5
6
TIME_12_VAL1
0b
R/W
7
A1M3
0b
R/W
Revision 0.7.10
Value
Description / Comments
Hour alarm value, BCD format, low bits. Range: 0~9
Hour alarm value, BCD format, high bits. LSB of HOUR_10_VAL.
When TIME_12_VAL equals to 1: 1 = PM, 0 = AM
When TIME_12_VAL equals to 0, this bit is MSB of HOUR_10_VAL.
1 = 12-hour alarm mode is
selected
0 = 24-hour alarm mode is
selected
12-hour alarm or 24-hour alarm mode selection bit.
Alarm 1, mask bit 3
68
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
5.4.4
RTC_AL1_DAY – Day or Date Alarm 1 Value Register
I²C Address = Page-0: 74(0x4A), µC Address = 0xA04A
Def.
Set.
User
Type
Bit
Bit Name
[3:0]
DAY_DATE_VAL1 0h
R/W
[5:4]
DATE_10_VAL1
R/W
00b
6
DY1
0b
R/W
7
A1M4
0b
R/W
Value
Description / Comments
Day alarm value or date alarm value, low bits. BCD format.
When DY equals to 1, This value is day alarm value, Range: 1~7.
When DY equals to 0, This value is date alarm value, Range: 0~9
Date alarm value, BCD format, high bits. Range: 0~3
1 = last 4 bits of this
register are day alarm
value.
0 = last 4 bits of this
register are date alarm
value.
Day/Date alarm select
Alarm 1, mask bit 4
5.4.5
RTC_AL2_SEC – Second Alarm 2 Value Register
I²C Address = Page-0: 75(0x4B), µC Address = 0xA04B
Def.
Set.
0h
Bit
Bit Name
[3:0]
SECOND_VAL1
SECOND_10_VAL
000b
1
A2M1
0b
[6:4]
7
User
Type
R/W
Value
Description / Comments
Second alarm value, BCD format, low bits. Range: 0~9
R/W
Second alarm value, BCD format, high bits. Range: 0~5
R/W
Alarm 2, mask bit 1
5.4.6
RTC_AL2_MIN – Minute Alarm 2 Value Register
I²C Address = Page-0: 76(0x4C), µC Address = 0xA04C
Bit
[3:0]
[6:4]
7
Def.
Set.
MINUTE_VAL2
0h
MINUTE_10_VAL2 000b
A2M2
0b
Bit Name
User
Type
R/W
R/W
R/W
Value
Description / Comments
Second alarm value, BCD format, low bits. Range: 0~9
Second alarm value, BCD format, high bits. Range: 0~5
Alarm 2, mask bit 2
5.4.7
RTC_AL2_HR - Hour Alarm 2 Value Register
I²C Address = Page-0: 77(0x4D), µC Address = 0xA04D
HOUR_VAL2
HOUR_10_VAL2
Def.
Set.
0h
0b
User
Type
R/W
R/W
PM_VAL2
0b
R/W
Bit
Bit Name
[3:0]
4
5
6
TIME_12_VAL2
0b
R/W
7
A2M3
0b
R/W
Value
Description / Comments
Hour alarm value, BCD format, low bits. Range: 0~9
Hour alarm value, BCD format, high bits. LSB of HOUR_10_VAL.
When TIME_12_VAL equals to 1: 1 = PM, 0 = AM
When TIME_12_VAL equals to 0, this bit is MSB of HOUR_10_VAL.
1 = 12-hour alarm mode is
selected
0 = 24-hour alarm mode is
selected
12-hour alarm or 24-hour alarm mode selection bit.
Alarm 2, mask bit 3
5.4.8
RTC_AL2_DAY – Day or Date Alarm 2 Value Register
I²C Address = Page-0: 78(0x4E), µC Address = 0xA04E
Def.
Set.
User
Type
Bit
Bit Name
[3:0]
DAY_DATE_VAL2 0h
R/W
[5:4]
DATE_10_VAL2
00b
R/W
6
DY2
0b
R/W
7
A2M4
0b
R/W
5.5
Value
Description / Comments
Day alarm value or date alarm value, low bits. BCD format.
When DY equals to 1, This value is day alarm value, Range: 1~7.
When DY equals to 0, This value is date alarm value, Range: 0~9
Date alarm value, BCD format, high bits. Range: 0~3
1 = last 4 bits of this register are day alarm value.
0 = last 4 bits of this register are date alarm value.
Alarm 2, mask bit 4
RTC - INTERRUPT REGISTERS
The interrupts for the RTC module can be controlled and monitored by writing 8-bit control words to the various registers
described below.
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5.5.1
RTC_INT_CTL – RTC Interrupt Control Register
I²C Address = Page-0: 79(0x4F), µC Address = 0xA04F
Bit
Bit Name
Def.
Set.
User
Type
0
A1_EN
0b
R/W
1
A2_EN
0b
R/W
[7:2]
RESERVED
Value
Description / Comments
1: interrupt enable
0: interrupt disable
1: interrupt enable
0: interrupt disable
R/W
Alarm 1 interrupt enable
Alarm 2 interrupt enable
RESERVED
5.5.2
RTC_INT_ST – RTC Interrupt Status Register
A logic „1‟ in the A1_FLAG bit indicates that the time matched the value programmed into the registers for alarm 1. If the
A1_EN bit is set to a logic „1‟ at the time the A1_FLAG goes to logic „1‟, the INT pin will be asserted. The A1_FLAG is
cleared when a logic „1‟ is written to this register location. This bit can only be written to logic „1‟. Attempting to write a
logic „0‟ leaves the value unchanged.
A logic „1‟ in the A2_FLAG bit indicates that the time matched the value programmed into the registers for alarm 2. If the
A2_EN bit is set to a logic „1‟ at the time the A2_FLAG goes to logic „1‟, the INT pin will be asserted. The A2_FLAG is
cleared when a logic „1‟ is written to this register location. This bit can only be written to logic „1‟. Attempting to write a
logic „0‟ leaves the value unchanged.
I²C Address = Page-0: 80(0x50), µC Address = 0xA050
Bit
Bit Name
Def.
Set.
User
Type
0
A1_FLAG
0b
RW1C
1
A2_FLAG
0b
RW1C
[7:2]
RESERVED
5.6
R/W
Value
Description / Comments
1: time match alarm 1 value
Alarm 1 interrupt flag
0: No match
1: time match alarm 2 value
Alarm 2 interrupt flag
0: No match
RESERVED
RTC RESERVED REGISTERS
5.6.1
RTC - RESERVED Registers
These registers are reserved. Do not write to them.
I²C Address = Page-0: 81(0x51), µC Address = 0xA051
I²C Address = Page-0: 94(0x5F), µC Address = 0xA05F
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6.0 GENERAL PURPOSE TIMERS
6.1
GENERAL PURPOSE TIMERS – GENERAL DESCRIPTION
The P95020 includes two independent general purpose timers. The first is an 8-bit General Purpose Timer that operates
on a user-selectable time base of 32.768 kHz, 1024 Hz, 1Hz, or 1 Minute. The second is an 8-bit Watchdog Timer that
operates on a user-selectable time base of 8Hz, 1Hz, 0.5Hz, or 1 Minute
6.1.1
GENERAL PURPOSE TIMER
To use the General Purpose Timer (GP), an 8-bit value must be loaded in to the General Purpose Timer Count Register
and a time base (count interval) value must also be loaded into bits [1:0] of the General Purpose Timer Timebase
Register. The General Purpose Timer can then be enabled by writing a logic „1‟ into bit 0 (GPT_EN) of the General
Purpose Timer Enable Register. The General Purpose Timer will then begin counting and continue until the count value
is equal to the value specified in the General Purpose Timer Count Register (timeout value). When the timeout value is
reached, the GPTIMEOUT bit is set to a logic „1‟ in the Timer Interrupt Status Register. If the General Purpose Timer
Interrupt has been enabled by setting bit 0 in the Timer Interupt Register to a logic „1‟ then an interrupt is generated to
alert the system that the timeout value has been reached. THE GPTIMEOUT bit is cleared by writing a logic „1‟ to the
GPTIMEOUT bit in the Timer Interrupt Status Register. Following the interrupt, the General Purpose Timer will stop and
reset to 0. Bit 0 of the General Purpose Timer Enable Register is also reset to 0 following the interrupt. However, the
content of General Purpose Timer Count Register and the General Purpose Timer Timebase Value Registers are
maintained and the count cycle can be repeated by writing a logic „1‟ to GPT_EN. When the General Purpose Timer is
counting, writing a logic „0‟ to GPT_EN will reset and stop the timer.
6.1.2
WATCHDOG TIMER
To use the Watchdog Timer (WD), an 8-bit value must be loaded in to the Watchdog Timer Count Register and a time
base (count interval) value must also be loaded into bits [5:4] of the General Purpose Timer Timebase Register. The
Watchdog Timer can then be enabled by writing a logic „1‟ into bit 0 (WDT_EN) of the Watchdog Timer Enable Register.
The Watchdog Timer will then begin counting and continue until the count value is equal to the value specified in the
Watchdog Timer Count Register (timeout value). When the timeout value is reached, the WDTIMEOUT bit is set to a
logic „1‟ in the Timer Interrupt Status Register. If the Watchdog Timer Interrupt has been enabled by setting bit 4 in the
Timer Interrupt Register to a logic „1‟ then an interrupt is generated to alert the system that the timeout value has been
reached. THE WDTIMEOUT bit is cleared by writing a logic „1‟ to the WDTIMEOUT bit in the Timer Interrupt Status
Register. Following the interrupt, the Watchdog Timer will stop and reset to 0. Bit 0 of the Watchdog Timer Enable
Register is also reset to 0 following the interrupt. The Watchdog Timer can be reset anytime during the count interval by
writing a logic „1‟ to bit 4 of the Watchdog Timer Enable Register before the timer times out to prevent an interrupt from
being generated. After reset the Watchdog Timer restarts automatically.
6.2
GENERAL PURPOSE TIMERS – REGISTERS
6.2.1
PCON_GPT - GENERAL PURPOSE TIMER GLOBAL ENABLE REGISTER
I²C Address = Page-0: 58(0x3A), µC Address = 0xA03A
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
GPT_G_EN
0b
R/W
0 = Disabled
1 = Enabled
[7:1]
RESERVED
Enable GPT. Disabled GPT retains time value settings but the clock
is gated (low power mode).
RESERVED
R/W
6.2.2
WATCHDOG TIMER ENABLE REGISTER
I²C Address = Page-0: 160(0xA0), µC Address = 0xA0A0
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
WDT_EN
0b
R/W
0 = Reset
1 = enable count
Watchdog timer enable/disable
[3:1]
RESERVED
4
WDT_RST
[7:5]
RESERVED
Revision 0.7.10
R/W
0b
R/W1A
RESERVED
Write 1 to reset. Read
always returns 0.
R/W
Watchdog timer reset. Write 1 to reset. Read always returns 0.
RESERVED
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P95020 / Preliminary Datasheet
6.2.3
GENERAL PURPOSE TIMER ENABLE REGISTER
I²C Address = Page-0: 161(0xA1), µC Address = 0xA0A1
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
GPT_EN
0b
R/W
0 = Reset
1 = Enable Count
General Purpose Timer Enable
[7:1]
RESERVED
R/W
RESERVED
6.2.4
TIMER INTERRUPT STATUS REGISTER
I²C Address = Page-0: 162(0xA2), µC Address = 0xA0A2
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
1: Reached Timeout Count
0: Timeout Count Not
Reached
General Purpose Timer Timeout. Write „1‟ to clear.
0
GPTIMEOUT
0b
RW1C
[3:1]
RESERVED
000b
R/W
4
WDTIMEOUT
0b
RW1C
[7:5]
RESERVED
000b
R/W
RESERVED
1: Reached Timeout Count
0: Timeout Count Not
Reached
Watchdog Timer Timeout. Write „1‟ to clear.
RESERVED
6.2.5
GENERAL PURPOSE TIMER COUNT REGISTER
I²C Address = Page-0: 163(0xA3), µC Address = 0xA0A3
Bit
[7:0]
Bit Name
GPTIME
Def.
Set.
FFh
User
Type
Value
Description / Comments
R/W
User programmed number
of cycles to timeout
General Purpose Timer Count
6.2.6
WATCHDOG TIMER COUNT REGISTER
I²C Address = Page-0: 164(0xA4), µC Address = 0xA0A4
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[7:0]
WDTIME
FFh
R/W
User programmed number
of cycles to timeout
Watchdog Timer Count
6.2.7
GENERAL PURPOSE TIMER TIMEBASE REGISTER
I²C Address = Page-0: 165(0xA5), µC Address = 0xA0A5
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[1:0]
GPTB
00b
R/W
00: 32.768 kHz
01: 1024 Hz
10: 1 Hz
11: 1 Minute
General Purpose Timer Timebase
[3:2]
RESERVED
[5:4]
WDTB
[7:6]
RESERVED
R/W
00b
R/W
RESERVED
00: 8 Hz
01: 1 Hz
10: 0.5 Hz
11: 1 Minute
Watchdog Timer Timebase
R/W
RESERVED
6.2.8
TIMER INTERRUPT ENABLE REGISTER
I²C Address = Page-0: 166(0xA6), µC Address = 0xA0A6
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
1: Enabled
0: Disabled
General Purpose Timer Interrupt Enable
0
GPT_INTEN
0b
R/W
[3:1]
RESERVED
000b
R/W
4
WDT_INTEN
0b
R/W
[7:5]
RESERVED
000b
R/W
Revision 0.7.10
RESERVED
1: Enabled
0: Disabled
Watchdog Timer Interrupt Enable
RESERVED
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6.2.9
GP TIMER - RESERVED Registers
These registers are reserved. Do not write to them.
I²C Address = Page-0: 167(0xA7), µC Address = 0xA0A7
Thru = Page-0: 175(0xAF), µC Address = 0Xa0AF
Revision 0.7.10
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7.0 DC_DC MODULE
To use the DC_DC regulators, the CKGEN PLLs need to be powered on since the DC_DC needs a 24 MHz clock to
operate. To turn on DC_DC regulators, the global enable bits need to be programmed to “enable”. First, program the
DC_DC voltage/ current limit settings and then set the “enable” bit for that particular DC_DC regulator.
The DC_DC Module can be controlled and monitored by writing 8-bit control words to the various registers. The Base
addresses are defined in Table 3 – Register Address Global Mapping on page 20.
Table 17 – DC-DC Block Registers (Including the CLASS_D BTL Power Bridge)
Name
BUCK500_0 (BC0)
BUCK500_1 (BC1)
BUCK1000 (BC2)
LED_BOOST
BOOST5
CLASS_D
RESERVED
Size
(Bytes)
2
2
2
2
2
4
2
I²C
Address
Page-0: 128(0x80)
Page-0: 128(0x82)
Page-0: 128(0x84)
Page-0: 128(0x86)
Page-0: 128(0x88)
Page-0: 140(0x8A)
Page-0: 140(0x8E)
Base
Address
0xA080
0xA082
0xA084
0xA086
0xA088
0xA08A
0xA08E
Vsys
Description
Register Definition Location
Buck Converter #0, 500 mA
Buck Converter #1, 500 mA
Buck Converter #2, 1000 mA
LED_BOOST LED Driver, Including Sinks
BOOST5 5V Boost Converter
CLASS_D BTL Power Bridge
RESERVED
Page 76
Page 76
Page 76
Page 83
Page 89
Page 93
Section 8.2
Section 8.2
Section 8.2
Section 0
Section 0
Section 11.1
GND
BUCK500_0
500 mA BUCK
Block
Control/
Status
Register
Access
Interface
BUCK500_1
500 mA BUCK
BUCK1000
1 A BUCK
Register access
bus interface
Package
Pins
BOOST5
1.5A BOOST
Reference
& Bias
LED_BOOST
LED Power
LED_BOOST
Current-Sinks
Class D
Signal
Processing
CLASS_D
Power Stage
Figure 15 DC_DC Block Diagram
Revision 0.7.10
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8.0 2MHz, 500mA & 1000mA SYNCHRONOUS BUCK REGULATORS
FEATURES
Output Voltage from 0.75V to 3.70V
DESCRIPTION
There are three Buck Converters in the P95020. They are
identical except for their output current ratings.
Current Output:
The two BUCK500 power supplies (BUCK500_0 and
BUCK500_1) each provide 0.75V to 3.70V at up to
500 mA.
Programmable in 25mV steps
Default is mask programmed
BUCK500_0: 500 mA
BUCK500_1: 500 mA
BUCK1000: 1000 mA
Peak Efficiency up to 93%
Current Mode Control, internally compensated
Selectable Operation in PWM or PFM Mode
Initialization and Power Sequencing can be controlled
by a host & registers
Short Circuit Protection and Programmable Cycle by
The BUCK1000 power supply provides 0.75V to 3.70V at
up to 1000 mA.
All Buck Converters are internally compensated, each
requiring a single input bypass capacitor and an output
filter consisting of one L and one C component.
APPLICATIONS
The primary usage is to power Digital Cores, Application
Processors, and RF Power Amplifiers.
Cycle Overcurrent Limit
Internal inductor current sensing
Four (4) preset current limit steps:
25%, 50%, 75% and 100% of full current limit
Soft Start - Slew Rate Controlled
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BUCK500_0_IN
BUCK
CONTROL
REGISTER &
STATUS
BUCK500_0
BUCK500_0_OUT
STEP_DOWN
CONVERTER
BUCK500_0_GND
500mA
BUCK VOUT
REGISTER
ADJ
0.75V TO 3.7V
BUCK500_0_FDBK
REGISTER
ACCESS BUS
INTERFACE
BUCK500_1_IN
BUCK
CONTROL
REGISTER &
STATUS
BUCK500_1
BUCK500_1_OUT
STEP_DOWN
CONVERTER
BUCK500_1_GND
500mA
BUCK VOUT
REGISTER
ADJ
0.75V TO 3.7V
BUCK500_1_FDBK
REFERENCE
& BIAS
BUCK1000_IN
BUCK
CONTROL
REGISTER &
STATUS
BUCK1000
BUCK1000_OUT
STEP_DOWN
CONVERTER
BUCK1000_GND
1000mA
BUCK VOUT
REGISTER
ADJ
0.75V TO 3.7V
BUCK1000_FDBK
Figure 16 – BUCK500 / BUCK1000 Block Diagram
8.1
BUCK1000 & BUCK500 - PIN DEFINITIONS
DIAGRAM ID
FEEDBACK
GND
OUT
VIN
8.2
Pin #
085
086
087
088
BUCK500_0
BC0_ FDBK
BC0_GND
BC0_OUT
BC0_IN
Pin #
081
082
083
084
BUCK500_1
BC1_FDBK
BC1_GND
BC1_OUT
BC1_IN
Pin #
077
078
079
080
BUCK1000
BC2_FDBK
BC2_GND
BC2_OUT
BC2_IN
BUCK1000 & BUCK500 - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA=25C, VIN = VSYS =3.8V, TA = -40°C to +85°C (VIN must be connected to VSYS)
SYMBOL
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
VIN
Input voltage
VIN = VSYS
3.0
4.5
VOUT
Programmable Output Voltage Range
Note 2
0.75
3.70
Output Voltage Step Size
25
VOUT
VIN = 3.0V to 4.5V, IOUT = 0 to Imax,
OVERALL
Overall Output Voltage Accuracy
-3
+3
Note 1, Note 3
Maximum Output Current in PFM Mode,
(BUCK500)
100
IOUT-PFM
VIN = 3.0V to 4.5V, Note 1, Note 3
Maximum Output Current in PFM Mode,
200
(BUCK1000)
Maximum Output Current in PWM Mode,
500
IOUT-PWM
(BUCK500)
VIN = 3.0V to 4.5V, Note 1, Note 3
1000
Maximum Output Current in PWM Mode,
Revision 0.7.10
76
UNIT
V
V
mV
%
mA
mA
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
SYMBOL
ICLP
ICLP
DESCRIPTION
(BUCK1000)
Full Scale Cycle by Cycle Current Limit
(BUCK500)
Full Scale Cycle by Cycle Current Limit
(BUCK1000)
Cycle by Cycle Current Limit Step Size
Switch Peak Short Circuit Current (BUCK500)
Switch Peak Short Circuit Current (BUCK1000)
ISCP
RDS-ON-HS
RDS-ON-LS
fPWML
fPWMH
DMAX
tON(MIN)
tSFTSLEW
High Side Switch On Resistance (BUCK500)
High Side Switch On Resistance (BUCK1000)
Low Side Switch On Resistance (BUCK500)
Low Side Switch On Resistance (BUCK1000)
PWM Mode Clock Frequency (Low)
PWM Mode Clock Frequency (High)
PWM Mode Max Duty Cycle
Minimum Output On Time
Soft Start Output Slew Rate
IQS
IQPFM
IQPWM
Quiescent Operating Current
ILEAKSW
Leakage Current Into SW pin,
ILEAKVIN
Leakage Current Into VIN pin
IFDBK
ZFDBK_OFF
UVLO
UVLOHYST
Input Current Into FDBK pins
FDBK Pull Down Resistance in Shutdown
Under Voltage Lock Out Threshold
Under Voltage Lock Out Hysteresis
CONDITIONS
MIN
0xA081 [3:2], 0xA083 [3:2],
0xA085 [3:2] both bits set to 1
650
1200
4 preset levels
ISCP is a secondary current
protection to prevent over current
runaway.
TYP
MAX
UNIT
1050
1800
mAPK
25
%
1.3
2.25
APK
0.5
0.25
0.5
0.25
1
2
ISW = -50mA
ISW = 50mA
Note 1, Note 4, Note 6
Note 1, Note 4, Note 6
12.5
MHz
MHz
%
ns
mV/µs
1
60
3.5
µA
µA
mA
1
µA
1
µA
100
75
Not operating – Shutdown Mode
Operating (No Load) PFM Mode
Operating (No Load) PWM Mode
Note 1, Note 5
Shutdown Mode, VSW=4.5V,
DCDC_GLOBAL_EN (0x05)=0;
Shutdown Mode, VIN = 4.5V,
VSW=0V
DCDC_GLOBAL_EN (0x05) = 0;
Operation Mode
Shutdown Mode
VSYS Rising
-1
+1
7.1
2.85
150
2.95
µA
k
V
mV
Notes:
1.
2.
3.
4.
Guaranteed by design and/or characterization.
Maximum output voltage limited to (VIN - IPEAK x RDS-ON_P).
Component value is COUT =22 µF, L=4.7µH, CIN=10µF.
Buck clock will be coming from external crystal through PLL. The resultant frequency will be in 1% range from the
nominal.
5. BUCK1000, BUCK500 control register addresses / bits.
Description
Not Operating
Operating (No Load) PFM Mode
Operating (No Load) PWM
Mode
Address (I2C)
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
Value
0x05 [0:0] = 0
0x05 [1:1] = 0
0x05 [2:2] = 0
0x80 [0:0] = 1
0x82 [0:0] = 1
0x84 [0:0] = 1
0x80 [0:0] = 0
0x82 [0:0] = 0
0x84 [0:0] = 0
6. Buck regulator clock frequency control register addresses.
Description
1 MHz
2 MHz
8.3
Address (I2C)
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
Value
0x80 [1:1] = 0
0x82 [1:1] = 0
0x84 [1:1] = 0
0x80 [1:1] = 1
0x82 [1:1] = 1
0x84 [1:1] = 1
BUCK CONVERTERS – TYPICAL PERFORMANCE CHARACTERISTICS
Revision 0.7.10
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Buck500_0 PWM efficency Vinp 3.8V
100
90
efficency %
80
70
60
50
40
30
1
10
100
1000
load mA
efficiency % 1.8V
efficiency % 3.3V
efficiency % 1.2V
Figure 17 – BUCK500 DC-DC Regulator Efficiency vs Load Current PWM Mode
Buck1000 PWM efficiency Vinp 3.8V
100
90
efficiency %
80
70
60
50
40
30
1
10
100
1000
Load mA
efficiency % 1.2V
efficiency % 1.8V
efficiency % 3.3V
Figure 18 – BUCK1000 DC-DC Regulator Efficiency vs Load Current PWM Mode
Revision 0.7.10
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Buck500_0 PFM efficiency Vinp 3.7V Vout 2.30V
88
87.5
87
86.5
efficiency
86
85.5
85
84.5
84
83.5
83
82.5
0
2
4
6
8
10
12
14
16
load mA
Figure 19 – BUCK500 DC-DC Regulator Efficiency vs Load Current PFM Mode
8.4
BUCK1000 & BUCK500 - REGISTER ADDRESSES
All three Buck Converters can be controlled and monitored by writing 8-bit control words to either the Output Voltage
Register or the Control Register. The Base addresses are defined in Table 3 – Register Address Global Mapping on page
20. The offset addresses are defined as the Base Address in the following table.
Table 18 – BUCK500_0, BUCK500_1 and BUCK1000 Register Addresses
Name
Description
BUCK500_0
BUCK500_1
BUCK1000
Buck Converter # 0 (500 mA)
Buck Converter # 1 (500 mA)
Buck Converter # 2 (1000 mA)
Output Voltage Register
I²C Address
Base Address
Page-0: 128(0x80)
0xA080
Page-0: 130(0x82)
0xA082
Page-0: 132(0x84)
0xA084
Control Register
I²C Address
Page-0: 129(0x81)
Page-0: 131(0x83)
Page-0: 133(0x85)
Base Address
0xA081
0xA083
0xA085
8.4.1
BUCK500 & BUCK1000 - Output Voltage Registers: (See Table 18 above for addresses)
The Output Voltage Register contains the Enable bit and the Output Voltage setting bits.
Bit
Bit Name
[6:0]
VOUT
7
ENABLE
Def.
Set.
[See
]
User
Type
Value
Description / Comments
RW
(See Table 19)
Output Voltage = VOUT * 0.025V + 0.75V
0h
RW
1 = Enable
0 = Disable
Enable Output
Table 19 – Output Voltage Register Settings, Bits [6:0]
Bit
Setting
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
Revision 0.7.10
Output
Voltage
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
Bit
Setting
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
Output
Voltage
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
Bit
Setting
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
79
Output
Voltage
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.225
2.250
2.275
2.300
2.325
Bit
Setting
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
Output
Voltage
2.550
2.575
2.600
2.625
2.650
2.675
2.700
2.725
2.750
2.775
2.800
2.825
2.850
2.875
2.900
2.925
Bit
Setting
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
Output
Voltage
3.150
3.175
3.200
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
3.425
3.450
3.475
3.500
3.525
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
Bit
Output
Bit
Output
Bit
Output
Bit
Output
Bit
Setting
Voltage
Setting
Voltage
Setting
Voltage
Setting
Voltage
Setting
0010000
1.150
0101000
1.750
1000000
2.350
1011000
2.950
1110000
0010001
1.175
0101001
1.775
1000001
2.375
1011001
2.975
1110001
0010010
1.200
0101010
1.800
1000010
2.400
1011010
3.000
1110010
0010011
1.225
0101011
1.825
1000011
2.425
1011011
3.025
1110011
0010100
1.250
0101100
1.850
1000100
2.450
1011100
3.050
1110100
0010101
1.275
0101101
1.875
1000101
2.475
1011101
3.075
1110101
0010110
1.300
0101110
1.900
1000110
2.500
1011110
3.100
1110110
0010111
1.325
0101111
1.925
1000111
2.525
1011111
3.125
Note – Contains an initial 0.75V offset. Performance and accuracy are not guaranteed with bit combinations above 1110110.
Output
Voltage
3.550
3.575
3.600
3.625
3.650
3.675
3.700
8.4.2
BUCK1000 & BUCK500 - Control Register: (See Table 18 for addresses)
The Control Register contains the Current Limit setting bits, Control bits and Status bits.
Bit
Def.
Set.
Bit Name
User
Type
0
PWM_PFM
0
RW
1
CLK_SEL
1
RW
[3:2]
I_LIM
3h
RW
4
SC_FAULT
N/A
R
5
PGOOD
N/A
R
6
RESERVED
1b
RW
7
DAC_MSB_EN
1b
RW
Value
Description / Comments
1 = PFM mode
0 = PWM mode
1 = 2 MHz
0 = 1 MHz
(See Table 20)
1 = Fault
0 = OK
1 = Power Good
0 = Power Not
Good
PWM/PFM Mode Select
Clock Frequency
Cycle by Cycle Current Limit (%)
Short Circuit Fault
Power Good
RESERVED
1 = Enable writes to
BUCK 3 MSB bits in
DAC
0 = Disable writes to
BUCK 3 MSB bits in
DAC
BUCK VOUT 3 MSB bits write protection
Table 20 – Control Register Cycle by Cycle Current Limit (I_LIM) Settings
for Bits [3:2] [Note ]
Bit
Bit 3
Description
2
0
0
Current Limit = 25 %
0
1
Current Limit = 50 %
1
0
Current Limit = 75 %
1
1
Current Limit = 100 %
Note – Current Limit is at maximum when bits [3:2] are both set to 1.
8.5
BUCK1000 & BUCK500 - ENABLING & DISABLING
There are two methods of disabling each Buck Converter: the Global Enable bit and the local ENABLE bit (Output Voltage
Register, Bit 7). Table 21 shows the interoperation of the two methods.
Table 21 – Interoperability of enabling/disabling methods vs. loading default values.
Internal POR
0
0
0
1
Global Enable
X
0
1
X
ENABLE
0
X
1
X
ON/OFF status
OFF
OFF
ON
OFF
REGISTER VALUE STATUS
PREVIOUS SETTINGS
PREVIOUS SETTINGS
PREVIOUS SETTINGS
LOAD DEFAULT VALUES
8.5.1
BUCK1000 & BUCK500 - Initialization and Power-Up
During an IC re-initialization or “cold boot” an internal POR disables the Buck Converter and loads the default values into
the registers. The default values are only loaded into the registers when there is a POR event.
The default settings for the Output Voltage Register are:
Function
Local Enable Bit
Output Voltage
Default Setting
Disabled
3.3V (BUCK500_0)
1.8V (BUCK500_1)
1.2V (BUCK1000)
The default settings for the Control Register are:
Revision 0.7.10
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©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
Function
Current Limit
Clock Frequency
Operating Mode
Default Setting
100%
2 MHz
PWM
After the external POR releases, the individual Global Enable bits can be set to HIGH. Since the default value of the local
ENABLE bit is LOW, the supply will not start at this time.
To enable a converter, the local ENABLE bit is set to HIGH by writing the voltage value to the Output Voltage Register.
The Output Voltage value must be included each time the converter is enabled or disabled. There is a default value for
each converter that can be read and written back along with the ENABLE bit or a different value can be written. When the
ENABLE bit becomes set the Buck Converter will then enter its soft-start sequence, and transition to the programmed
voltage.
NOTE: Changes to the Output Voltage Register settings can be written directly without disabling the converter.
8.5.2
BUCK1000 & BUCK500 - Normal Disabling / Enabling
Setting either the Global Enable bit to LOW or the local ENABLE bit to LOW will turn off the Buck Converter.
The Global Enable bit‟s sole purpose is to shut down the converter into its lowest power shutdown mode. It is not
intended to be used to toggle the Buck Converter off and on. Proper operation is only guaranteed by toggling the
ENABLE bit once the Global Enable bit is set HIGH to take it out of low power shutdown mode.
8.5.3
BUCK1000 & BUCK500 - Soft Start Sequence
There is a 50 µs delay after the ENABLE bit is set and then an internal counter ramps up, requiring 80 µs/volt from zero to
the programmed Output Voltage setting. Once the Soft Start sequence is initiated, any changes to the values in the
Output Voltage Register are ignored until the Soft Start sequence is complete.
8.5.4
BUCK1000 & BUCK500 - Current Limit Protection
The Buck Converter includes pulse by pulse peak current limiting circuitry for over-current conditions. The limit can be set
at various percentages of maximum setting (See Table 20). During an over-current condition the output voltage is allowed
to drop below the specified voltage and will be indicated by the status of the PGOOD bit. When the over-current state is
ended the output returns to normal operation.
8.5.5
BUCK1000 & BUCK500 - Short Circuit Protection
The Buck Converter includes short-circuit protection circuitry. When a short circuit occurs, the output will be latched into a
disabled mode and a fault will be indicated in the SC_FAULT bit. The local ENABLE bit must be first toggled LOW and
then back to HIGH again to clear the short circuit latch. Any subsequent Short Circuit will override the local ENABLE bit
setting and re-latch the output to a disabled mode.
8.6
BUCK1000 & BUCK500 - APPLICATIONS INFORMATION
VIN = 3.8V
VIN
CONTROL &
MONITORING
CIN
FEEDBACK
BUCK
CONTROLLER
OUT
L
1
VOUT
2
COUT
GND
P
Figure 20 – BUCK500 or BUCK 1000 Applications Diagram
8.6.1
BUCK500 - Recommended External Components
ID
Description
CIN
COUT
L
10 µF, 10V, Ceramic, X5R
22 µF, 10V, Ceramic, X5R
4.7 µH, 1.5A (for 1 MHz or 2 MHz operation)
Revision 0.7.10
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P95020 / Preliminary Datasheet
8.6.2
BUCK1000 - Recommended External Components
ID
Description
CIN
COUT
10 µF, 10V, Ceramic, X5R
22 µF, 10V, Ceramic, X5R
4.7 µH, 3.0A (for 1 MHz operation)
4.7 µH, 3.0A (for 2 MHz operation)
L
Revision 0.7.10
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9.0 HIGH EFFICIENCY 10 LED BOOST CONVERTER AND SINKS
FEATURES
DESCRIPTION
Fully controllable by a host or I2C interface
Peak efficiency > 88% with two strings of 10 LEDs
Low Shutdown Current ( threshold + margin
Status will be asserted. When
Result = threshold + margin
Status will be de-asserted.
Threshold bit
map
11
10
9
8
Margin bit
+/map
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
The 4 bits of margin registers are mapped to threshold as figure above. If sum (+/-) operation result is larger than 0xfff or
smaller than 0, then 0xfff or 0 will be used as the real threshold setting.
12.4.37
Equation
12.4.38 ADC - RESERVED Registers
These registers are reserved. Do not write to them.
I²C Address = Page-0: 233(0xE9), µC Address = 0xA0E9
I²C Address = Page-0: 236(0xF1), µC Address = 0xA0F1
Thru = Page-0: 255(0xFF), µC Address = 0xA0FF
Revision 0.7.10
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13.0 PCON MODULE – POWER CONTROLLER AND GENERAL PURPOSE I/O
PCON Module is the power controller of the device. It also manages the registers associated with GPIO and CKGEN.
13.1 GPIO PIN DEFINITIONS
PIN #
118
119
120
PIN_ID
GND_BAT/ADCGND
DGND
POR_OUT
SW_DET
121
GPIO1 / SW_OUT / PENDOWN
122
GPIO2 / LED1
123
GPIO3 / LED2
124
GPIO4 / CHRG_ILIM
001
GPIO5 / INT_OUT
002
GPIO6 / ADC1
003
GPIO7 / ADC3
004
GPIO8 / ADC2
005
GPIO9 / ADC0 / MCLK_IN
006
GPIO10
13.1
117
DESCRIPTION
GND_BAT & ADCGND: Shared analog ground pin for battery charger and ADC
Digital Ground
Power-On Reset Output, Open-drain Output, Active Low
Switch Detect Input
GPIO 1: General Purpose I/O # 1
SW_OUT: Switch Detect Output
PENDOWN: Pen down
GPIO 2: General Purpose I/O # 2
LED1: Charger LED # 1 Indicates charging in progress
GPIO 3: General Purpose I/O # 3
LED2: Charger LED # 2 Indicates charging complete
GPIO 4: General Purpose I/O # 4
CHRG_ILIM
GPIO 5: General Purpose I/O # 5
INT_OUT : Interrupt Output
GPIO 6: General Purpose I/O # 6
ADC1 : ADC Input Channel 1 (X-)
GPIO 7: General Purpose I/O # 7
ADC3 : ADC Input Channel 3 (Y-)
GPIO 8: General Purpose I/O # 8
ADC2 : ADC Input Channel 2 (Y+)
GPIO 9: General Purpose I/O # 9
ADC0 : ADC Input Channel 0 (X+)
MCLK_IN : Master Clock Input
GPIO 10: General Purpose I/O # 10
13.2 POWER STATES
P95020 device has two hardware power states.
OFF State:
P95020 enters OFF state after the first time battery insertion. The system power (VSYS ) is provided by the battery via the
ideal diode. VSYS powering up will issue a power-on-reset to reset all the logic on the device to default state and P95020
enters OFF state. In this state;
32K crystal oscillator (or associate RC oscillator) is running and generates 32k/4k/1k clocks.
The RTC module is enabled and the RTC registers are maintained.
The always on LDO is enabled and provides power to system.
The power switch detection (SW_DET) circuit is running.
Ideal diode driver is running.
All regulators, touch screen controller and audio are in power down or inactive mode.
Wait for interrupts to wake up CPU and bring system to ON state.
ON State:
P95020 enters ON state after momentarily pressing and releasing a button attached to SW_DET or AC adaptor insertion.
The CKGEN (Clock generator module) power is enabled and the 8MHz I2C and processor clock is available.
13.3 POWER SEQUENCING BY EMBEDDED MICROCONTROLLER
Pending embedded uP interrupt will trigger the following actions;
Hardware actions:
Set PSTATE_ON bit of POWER STATE AND SWITCH CONTROL REGISTER (0xA031) to 1, turn on the power
of CKGEN (VDD_CKGEN18, VDD_CKGEN33) and hence 8MHz (processor and I2C clock) clock is available.
Turn on the power of Embedded Microcontroller (VDD_EMBUP18) and release processor reset automatically
after 4ms. Processor start to execute code stroed in the internal ROM or external ROM.
Firmware actions:
Embedded microcontroller (6811) sub-system start with the boot sequence.
Revision 0.7.10
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The firmware (boot sequence) starts with checking whether the external ROM is available (read EX_ROM bit in
the global registers). If it exists, load the EX_ROM data into internal RAM. Other wise, execute code in the
internal ROM.
Firmware execute the code according the context and interrupt to sequence the power.
After the sequence is done, processor enter low power mode and wait for interrupts.
13.4 POWER ON RESET OUTPUT (POR_OUT)
The POR_OUT pin is an open drain GPIO output pin which controlled by firmware as part of the power up sequence. This
signal is used to reset the devices in the system that are powered by P95020 device while the power is not yet ready. The
output state of POR_OUT is defined by the power up sequence.
13.5 POWER SWITCH DETECTOR (SW_DET)
The PCON module also includes special power switch detection circuitry to provide a “push-on/push-off” interface via the
switch detect (SW_DET) pin. By connecting a button to this pin, three different events can be triggered. The first is a
short switch interrupt (>100ms) which is generated by momentarily pressing and releasing a button attached to SW_DET.
The second is a medium switch interrupt which is generated by pressing and holding the button and releasing it after 2
seconds (configurable to 2/3/4/5 seconds). The status of each of these switches can be monitored in the Switch Control
Register (0xA031). The third switch function is triggered when the button is pressed and held for longer than 15 seconds.
This event will not generate an interrupt but will generate system reset and force P95020 into OFF state.
13.6 GPIO GENERAL DESCRIPTION
The GPIO pins are turned on and off using the GPIO Off Register. This register is used like a multiplexer to allow the
GPIO and TSC/ADC subsystems to share external pins. When in GPIO mode (GPIO_OFF bits set to logic „0‟) the GPIO
Function Register configures the pin to operate as a GPIO or some other special function such as a status LED output. If
not configured to perform a special function, each GPIO can be configured as an input or output by setting the
corresponding bit in the GPIO Direction Register.
When configured as an output, each GPIO pin can be configured as a CMOS output or an open drain output by setting
the corresponding bit in the GPIO Output Mode Register. Each GPIO pin configured as an output will reflect the value
held in the GPIO Data Register with a logic „0‟ causing the pin to be low and a logic „1‟ causing the pin to be high.
Reading from the GPIO Data Register will return the last value written to it.
When configured as an input, each GPIO can be configured as level or edge sensitive by setting the corresponding bit in
the GPIO Input Mode Select Register. When set to level sensitive, the corresponding bit in the GPIO Data Register will
follow the logic level of the GPIO pin. When set to edge sensitive the corresponding bit in the GPIO Data Register will
change from a logic „0‟ to a logic „1‟ when the input transitions from low to high (rising edge) or high to low (falling edge) as
determined by the setting in the GPIO Input Edge Select Register. The value in the GPIO Data Register will remain a
logic „1‟ until a logic „0‟ is written into the register throuigh host or I2C interface. In level sensitive mode, writing to the
GPIO Data Register through host or I2C will have no effect.
When configured as an input, a GPIO may also generate an interrupt. Interrupts are always edge sensitive. The GPIO
Input Edge Select Register is used to select which edge, rising or falling, is used to generate an interrupt. When as edge
is detected, the GPIO Interrupt Status Register will show a logic „1‟ in the corresponding bit and an interrupt will be
generated provided the appropriate bit has been enabled by writing a logic „1‟ to the GPIO Interrupt Enable Register. The
GPIO Interrupt Status Register is cleared by writing a logic „1‟ to the appropriate bit. Writing a logic „0‟ will have no effect.
13.7 PCON REGISTERS
13.7.1
GPIO DIRECTION REGISTER
I²C Address = Page-0: 32(0x20), µC Address = 0xA020
I²C Address = Page-0: 33(0x21), µC Address = 0xA021
Bit
Bit Name
0
RESERVED
[10:1]
GPIO_DIR
[15:11]
RESERVED
Def.
Set.
0b
0000000000b
User
Type
R/W
R/W
Value
Description / Comments
RESERVED
0 = Input
1 = Output
R/W
Each bit sets the corresponding GPIO to either input or output
RESERVED
13.7.2
GPIO DATA REGISTER
I²C Address = Page-0: 34(0x22), µC Address = 0xA022
I²C Address = Page-0: 35(0x23), µC Address = 0xA023
Revision 0.7.10
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RESERVED
Def.
Set.
0b
User
Type
R/W
[10:1]
GPIO_DAT
0000000000b
R/W
[15:11]
RESERVED
Bit
Bit Name
0
Value
Description / Comments
RESERVED
Pins configured as an output will reflect the value held in the
GPIO_DAT register. The GPIO_DAT register will follow the logic
level at the pin for pins configured as a level sentitive inputs. The
GPIO_DAT register will change from a 0 to a 1 when the input
transitions state from low to high (rising edge) or high to low
(falling edge) as determined by the GPIO INPUT EDGE SELECT
register for pins configured as level sensitive inputs.
RESERVED
R/W
13.7.3
GPIO INPUT MODE SELECT REGISTER
I²C Address = Page-0: 36(0x24), µC Address = 0xA024
I²C Address = Page-0: 37(0x25), µC Address = 0xA025
RESERVED
Def.
Set.
0b
User
Type
R/W
[10:1]
GPIO_IN_MODE
0000000000b
R/W
[15:11]
RESERVED
Bit
Bit Name
0
Value
Description / Comments
0 = Level
sensitive
1 = Edge
sensitive
RESERVED
0 = Level sensitive, GPIO_DAT reflects the input data for the
corresponding GPIO; 1 = Edge sensitive, rising/falling edges
trigger interrupts as defined in GPIO_IN_EDGE. Requires the
associated bit in the GPIO Direction Register to be set as an
input.
RESERVED
R/W
13.7.4
GPIO INTERRUPT ENABLE REGISTER
I²C Address = Page-0: 38(0x26), µC Address = 0xA026
I²C Address = Page-0: 39(0x27), µC Address = 0xA027
Bit
Bit Name
0
RESERVED
[10:1]
GPIO_INT_EN
[15:11]
RESERVED
Def.
Set.
0b
0000000000b
User
Type
R/W
R/W
Value
Description / Comments
RESERVED
0 = Interrupt
Disabled
1 = Interrupt
Enabled
R/W
Each bit enabled/disables the corresponding GPIO interrupt
RESERVED
13.7.5
GPIO INPUT EDGE REGISTER
I²C Address = Page-0: 40(0x28), µC Address = 0xA028
I²C Address = Page-0: 41(0x29), µC Address = 0xA029
Bit
Bit Name
0
RESERVED
[10:1]
GPIO_IN_EDGE
[15:11]
RESERVED
Def.
Set.
0b
1111111111b
User
Type
R/W
R/W
Value
Description / Comments
RESERVED
0 = Rising edge
trigger
1 = Rising and
falling edge trigger
R/W
0 = Rising edge generates interrupt. 1 = Rising edge and
falling edge generates interrupt.
RESERVED
13.7.6
GPIO INTERRUPT STATUS REGISTER
I²C Address = Page-0: 42(0x2A), µC Address = 0xA02A
I²C Address = Page-0: 43(0x2B), µC Address = 0xA02B
Bit
Bit Name
0
RESERVED
[10:1]
GPIO_INT_STATUS
[15:11]
RESERVED
Def.
Set.
0b
0000000000b
User
Type
R/W
RW1C
Value
Description / Comments
RESERVED
0 = No interrupt
1 = Interrupt
R/W
Event is defined by GPIO_IN_EDGE register
RESERVED
13.7.7
GPIO OUTPUT MODE REGISTER
I²C Address = Page-0: 44(0x2C), µC Address = 0xA02C
I²C Address = Page-0: 45(0x2D), µC Address = 0xA02D
RESERVED
Def.
Set.
0b
User
Type
R/W
GPIO_OUT_MODE
1111111111b
R/W
Bit
Bit Name
0
[10:1]
[15:11]
RESERVED
Revision 0.7.10
Value
Description / Comments
RESERVED
0 = CMOS output
1 = Open drain output
R/W
Sets the output mode for each corresponding GPIO
RESERVED
109
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
13.7.8
GPIO OFF REGISTER
I²C Address = Page-0: 46(0x2E), µC Address = 0xA02E
I²C Address = Page-0: 47(0x2F), µC Address = 0xA02F
Bit
Bit Name
0
RESERVED
[10:1]
GPIO_OFF
[15:11]
RESERVED
Def.
Set.
0b
User
Type
R/W
1111100000b
R/W
Value
Description / Comments
0 = GPIO on
1 = GPIO off
RESERVED
Each bit shuts off the corresponding GPIO allowing the external
pin to be used for the TSC or ADC functions.
RESERVED
R/W
13.7.9
GPIO FUNCTION REGISTER
I²C Address = Page-0: 48(0x30), µC Address = 0xA030
Bit
Bit Name
0
RESERVED
Def.
Set.
1b
User
Type
R/W
1
GPIO1_SWO_PD
1b
R/W
2
GPIO2_LED1
1b
R/W
3
GPIO3_LED2
1b
R/W
4
GPIO4_CHRG_ILIM
1b
R/W
5
GPIO5_INT_OUT
1b
R/W
6
GPIO1_PENDOWN
0b
R/W
7
PENDOWN_POL
0b
R/W
Value
Description / Comments
RESERVED
0 = Normal operation
1 = Switch detect output
or PENDOWN
0 = Normal operation
1 = GPIO2 will be charger
LED1
0 = Normal operation
1 = GPIO3 will be charger
LED2
0 = Normal operation
1 = GPIO4 will be
CHRG_ILIM
0 = Normal operation
1 = GPIO will be interrupt
output
0 = GPIO1 is switch
detect output
1 = GPIO1 is PENDOWN
0 = Active low
1 = Active high
Sets GPIO1 to operate as a normal GPIO or as a switch detect or
PENDOWN detect
Sets GPIO2 to operate as a normal GPIO or as charger LED1
Sets GPIO3 to operate as a normal GPIO or as charger LED2
Sets GPIO4 to operate as a normal GPIO or as CHRG_ILIM
Sets GPIO5 to operate as a normal GPIO or as an interrupt
output
Sets GPIO1 as switch detect or PENDOWN detect when
GPIO1_SWO_PD = 1
Sets PENDOWN polarity
13.7.10 POWER STATE AND SWITCH CONTROL REGISTER
I²C Address = Page-0: 49(0x31), µC Address = 0xA031
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
SW_DET_STATUS_0
0b
RW1C
0 = Switch inactive
1 = Switch active
Short switch detect
1
RESERVED
0b
RW
2
SW_DET_STATUS_2
0b
RW1C
3
RESERVED
0b
R/W
4
PSTATE_ON
0b
RW1C
[7:5]
RESERVED
000b
R/W
RESERVED
0 = Switch inactive
1 = Switch active
Medium switch detect
0 = Off
1 = On
RESERVED
When PSTATE _ON = 0 the clock generator is powered off and
only the 32 kHz clock will be available. When PSTATE_ON = 1
the clock generator is on.
RESERVED
13.7.11 GPIO SWITCH INTERRUPT ENABLE
I²C Address = Page-0: 50(0x32), µC Address = 0xA032
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
SSW_INT_EN
1b
R/W
0 = Interrupt
disabled
1 = Interrupt
enabled
Short switch interrupt enable
1
RESERVED
0b
R/W
2
MSW_INT_EN
1b
R/W
3
RESERVED
0b
R/W
4
RST_OVER_TEMP
Revision 0.7.10
0b
R/W
RESERVED
0 = Interrupt
disabled
1 = Interrupt
enabled
Medium switch interrupt enable
RESERVED
0 = System reset
disabled
1 = System reset
enabled
110
Enable system reset at temperatuer above 155°C
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
5
RST_UNDER_VOL
0b
R/W
6
RST_DC2DC_UVLO
0b
R/W
7
RESERVED
0b
R/W
0 = System reset
disabled
1 = System reset
enabled
0 = System reset
disabled
1 = System reset
enabled
Enable system reset at low system voltage (VSYS < 3.0V)
Enable system reset when DC2DC module detects UVLO
condition
RESERVED
13.7.12 DCDC INTERRUPT ENABLE
I²C Address = Page-0: 51(0x33), µC Address = 0xA033
Bit
Bit Name
Def.
Set.
User
Type
0
BUCK_500_0_FAULT_INT
0b
_EN
R/W
1
BUCK_500_1_FAULT_INT
0b
_EN
R/W
2
BUCK_1000_FAULT_INT_
0b
EN
R/W
3
BST5_FAULT_INT_EN
0b
R/W
4
BST40_FAULT_INT_EN
0b
R/W
5
CLSD_FAULT_INT_EN
0b
R/W
[7:6]
RESERVED
00b
R/W
Value
Description / Comments
0 = Interrupt
disabled
1 = Interrupt
enabled
0 = Interrupt
disabled
1 = Interrupt
enabled
0 = Interrupt
disabled
1 = Interrupt
enabled
0 = Interrupt
disabled
1 = Interrupt
enabled
0 = Interrupt
disabled
1 = Interrupt
enabled
0 = Interrupt
disabled
1 = Interrupt
enabled
BUCK_500_0 fault interrupt enable
BUCK_500_1 fault interrupt enable
BUCK_1000 fault interrupt enable
BOOST5 fault interrupt enable
BOOST40 fault interrupt enable
CLASSD fault interrupt enable
RESERVED
13.7.13 POWER ON RESET STATE CONTROL REGISTER
I²C Address = Page-0: 60(0x3C), µC Address = 0xA03C
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
POR_OUT
0b
R/W
0=0
1 = Hi-Z
[7:2]
RESERVED
0000000b
R/W
POR_OUT pin state control. POR_OUT pin should be pulled
high by an external resistor
RESERVED
13.7.14 MID-BUTTON CONFIGURATION REGISTER
I²C Address = Page-0: 62(0x3E), µC Address = 0xA03E
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[1:0]
MID_BTN_CFG
00b
R/W
00 = 2 sec.
01 = 3 sec.
10 = 4 sec.
11 = 5 sec.
Mid-button push duration configuration.
[7:2]
RESERVED
000000b
R/W
13.7.15 OTHER PCON REGISTERS
I²C Address = Page-0: 52(0x34),
I²C Address = Page-0: 53(0x35),
I²C Address = Page-0: 54(0x36),
I²C Address = Page-0: 55(0x37),
I²C Address = Page-0: 56(0x38),
I²C Address = Page-0: 39(0x39),
I²C Address = Page-0: 58(0x3A),
I²C Address = Page-0: 61(0x3D),
Revision 0.7.10
µC
µC
µC
µC
µC
µC
µC
µC
RESERVED
Address
Address
Address
Address
Address
Address
Address
Address
=
=
=
=
=
=
=
=
111
0xA034
0xA035
0xA036
0xA037
0xA038
0xA039
0xA03A
0xA03D
(See
(See
(See
(See
(See
(See
(See
(See
Section
Section
Section
Section
Section
Section
Section
Section
4.7)
4.7)
14.4)
2.9)
2.15.2)
12.4.1)
6.2.1)
4.7)
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
13.7.16 GPIO RESERVED REGISTERS
These registers are reserved. Do not write to them.
I²C Address = Page-0: 59(0x3B), µC Address = 0xA03B,
I²C Address = Page-0: 63(0x3F), µC Address = 0xA03F
Thru Page-0: 63(0x3F), µC Address = 0xA03F
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14.0 HOTSWAP MODULE
FEATURES
DESCRIPTION
The HOTSWAP module is intended to provide an output
voltage that tracks the input voltage with minimal DC
losses (up to 150mA max.). The primary purpose for these
outputs is to provide short circuit protection to peripheral
devices such as SD cards when connected to the host
device. The input supply to the switches is shared though
each switch has an independent, active high, control
input.
VSYS
Controlled via external pin or internal registers
Current Output 150mA maximum.
Overcurrent / Short Circuit Protection
HSCTRL1
I2C
SUB-BLOCK
SW Ctrl
HSO1
FORCE INTERNAL
SWITCH CTRL
HSPWR
REGISTER
BUS
HS_CTRL_REG
0x36 [4:0]
SW Ctrl
HSO2
HSCTRL2
MICROCONTROLLER
SUB-BLOCK
UPPER BYTE OFFSET: 0xA0
Figure 29 – Hotswap Block Diagram
14.1 HOT SWAP (LOAD SWITCHES) – ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VSYS = 3.8V, VHSPWR=4.5V, TA = -40°C to +85°C,
SYMBOL
VHSPWR
PARAMETER
Input voltage Range
IQ(SW-ON)
Quiescent Current from HSPWR
IQ(SW-OFF)
Off-Supply Current from HSPWR
RDS(ON)
ILIM (MIN)
tRESP
On Resistance
Current Limit
Current Limit Response Time
HSCTRL1, HSCTRL2, Input Low
Voltage
HSCTRL1, HSCTRL2, Input High
Voltage
HSCTRL1, HSCTRL2 Leakage
Turn-Off Time
Turn-On Time
VIL
VIH
IOSINK
tOFF
tON
CONDITIONS
Mosfet Inputs
VSYS =4.5V,HSPWR = 3.3V, IOUT=0
HS_CTRL_REG
0x36 [3:0] = 1= ON
MIN
3.0
VSYS = 4.5V,HSPWR = 3.3V, HSCTRL1,
HSCTRL2 = GND
HS_CTRL_REG
0x36 [3:0] = 0 = OFF
VHSPWR = 3.0V to 5.0V
VHSPWR = 3.0V to 5.0V
1.2
180
10
VHSPWR = 3V to 4.5V
VHSPWR = 3V to 4.5V
VHSPWR = 5V Note 1
VHSPWR = 5V Note 1
TYP
3.3
0.7 x
VHSPWR
MAX
5.5
UNIT
V
24
uA
1
uA
1.6
250
mA
µs
0.3 x
VHSPWR
VHSPWR
+ 0.3
1
1
15
V
V
uA
µs
µs
Notes:
1. Guaraneteed by design and/or characterization.
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14.2 HOTSWAP – TYPICAL PERFORMANCE CHARACTERISTICS
Hotswap #1 RDSON vs. Temperature
1.7
1.6
RDSON (ohm)
1.5
1.4
VSYS = 3.6V
VSYS = 4.5V
1.3
1.2
1.1
1
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
85
TEMPERATURE (C)
Figure 30 – Hotswap #1 ON Resistance vs Temperature
Hotswap #2 RDSON vs. Temperature
1.7
1.6
RDSON (ohm)
1.5
1.4
VSYS = 3.6V
VSYS = 4.5V
1.3
1.2
1.1
1
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
85
Tem perature (C)
Figure 31 – Hotswap #2 ON Resistance vs Temperature
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14.3 HOTSWAP – PIN DEFINITIONS
PIN #
097
098
099
100
101
PIN_ID
HSCTRL1
HSO1
HSPWR
HSO2
HSCTRL2
DESCRIPTION
Hot Swap Control Input 1
Hot Swap Output 1
Hot Swap Switches Power Input
Hot Swap Output 2
Hot Swap Control Input 2
14.4 PCON REGISTER - HOTSWAP CONFIGURATION
I²C Address = Page-0: 54(0x36), µC Address = 0xA036
Bit
Bit Name
Def.
Set.
User
Type
0
FORCE_SW2_ON
0b
RW
1
FORCE_SW1_ON
0b
RW
2
FORCE_SW2_EN
0b
RW
3
FORCE_SW1_EN
0b
RW
4
CTRL_INV
0b
RW
[7:5]
RESERVED
000b
RW
Value
Description / Comments
0 = SW2 OFF
1 = SW2 ON
0 = SW1 OFF
1 = SW1 ON
0 = NORMAL SW2
1 = FORCE SW2
0 = NORMAL SW1
1 = FORCE SW1
0 = HSCTRL1 (1 turns on the switch)
1 = HSCRTL1 (0 turns on the switch)
Force SW2 On
Force SW1 On
Force SW2 Enable
Force SW1 Enable
Inverts Hotswap Control Pin Polarity
RESERVED
Notes:
To enable HOTSWAP Switch 1, first program FORCE_SW1_ON to 1 then enable the switch by programming
FORCE_SW1_EN to 1 or by forcing the HSCTRL1 to high (for CTRL_INV = 0).
Revision 0.7.10
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15.0 I2C_I2S MODULE
FEATURES
DESCRIPTION
I²C Master supports interface to external ROM
I²C Slave supports interface to external I²C Masters
400 kHz fast I2C protocol
Two I²S interfaces
Access arbiter that arbitrates the access request from
The P95020‟s I²C master port is intended for I²C ROM
access only. The contents of an external ROM that are
attached to the I²C Master port are automatically read into
an internal 1.5 kbyte shadow memory. The I²C Master
port conforms to the 400 kHz fast I²C bus protocol and
supports 7-bit device/page addressing.
I2C slave or embedded microcontroller
Interrupt handler which merge or re-direct the interrupts
from functional module to internal or external processor
The P95020‟s I²C Slave port follows I2C bus protocol
during register reads or writes that are initiated by an
external I²C Master (typcially an application processor).
The I²C Slave port operates at up to 400 kHz and
supports 7-bit device/page addressing.
The P95020 includes two I²S interfaces that provide audio
inputs to the Audio Module described in Section 2.0.
15.1 I2C_I2S - PIN DEFINITIONS
Pin #
054
PIN_ID
EX_ROM
055
056
057
058
059
060
061
062
063
064
065
066
067
068
DGND
I2S_BCLK2
I2S_WS2
I2S_SDOUT2
I2S_SDIN2
I2S_BCLK1
I2S_WS1
I2S_SDOUT1
I2S_SDIN1
I2CS_SCL
I2CS_SDA
I2CM_SCL
I2CM_SDA
GND
DESCRIPTION
ROM Select. EX_ROM = 1, read contents of external ROM into internal shadow memory. EX_ROM = 0, read contents
of internal ROM.
Digital Ground (1)
I²S Bit Clock Channel 2
I²S Word Select Channel 2
I²S Serial Data OUT Channel 2
I²S Serial Data IN Channel 2
I²S Bit Clock Channel 1
I²S Word Select (Left/Right) Channel 1
I²S Serial Data OUT Channel 1
I²S Serial Data IN Channel 1
I²C Slave clock
I²C Slave data
I²C Master clock
I²C Master data
GND : Ground
15.2 I²C SLAVE
15.2.1
I²C Slave - Address and Timing Mode
The I²C ports on the P95020 operate at a maximum speed of 400 kHz. The I²C slave address that the P95020 responds
to is defined in the I2C_SLAVE_ADDR global register. The default I²C device address after reset is 0101010, and can be
changed by firmware during the start up sequence.
The I²C slave supports two interface timing modes: Non-Stretching and Stretching.
In Non-Stretching Mode, the I²C slave does not stretch the input clock signal. The registers are pre-fetched to speed up
the read access in order to meet the 400 kHz speed. This is the default mode of operation and is intended for use with
I²C masters that do not supporting clock stretching.
In Stretching Mode, the I²C slave may stretch the clock signal (hold I2CS_SCL low) during the ACK / NAK phase (byte
level stretching) when the internal read access request is not finished. Stretching is not supported during write accesses.
15.2.2
I²C Slave - Write/Read Operation
The configuration and status registers for the various functional blocks are mapped to 3 consecutive 256 byte pages. The
page ID is encoded to 0,1, and 2. The definition and mapping is defined in Table 3 – Register Address Global Mapping
on page 20. The first 16 bytes in any of the 3 pages map to the same set of global registers. The “current active page” ID
for I²C access is defined in the global page ID register.
The I²C uses an 8-bit register address (Reg_addr in below) to define the register access start address in an I²C access in
the current page. The register address can be programmed by writing the register value immediately after device
address. Subsequent write accesses will be directed to the register defined by the register address in the current active
page. Read accesses will return the register defined by the register address. The register address is incremented
automatically byte-per-byte during each read/write access.
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S
0101010
W A
S
0101010
R
S
0101010
W A
S
0101010
R
Legend:
A
A
S: Start
Reg_addr
A
Data[reg_addr]
A
Data[reg_addr+1]
A
Data[reg_addr+n+
1]
A
Data[reg_addr+n+
Data[reg_addr]
2]
A
Data[reg_addr]+1
Data[...]
A
Reg_addr
A
Data[reg_addr+3]
A
Sr: Repeat
Start
Sr
0101010
Data[reg_addr+4]
Data[reg_addr]
R
A
R:Read (1)
A
A
A
Data[reg_addr+n+
N
m]
Data[reg_addr]
Data[reg_addr]+1
Data[...]
W:Write (0)
Data[…]
A
Data[reg_addr+n]
A
P
P
Data[reg_addr]+1
Data[reg_addr+1]
Data[reg_addr+k]
N
A:ACK
N:NAK
A
Data[reg_addr+2]
N
P
P
P:Stop
2
Figure 32 – I C Read / Write Operation
15.3 INTERRUPT DISPATCHER
The interrupt dispatcher of the P95020 directs interrupts to the internal or external processor according to the INT_DIR
configuration stored in the ACCM Register. Please note that the configuration register is in the same address space of
other functional modules and hence can be accessed by internal and external processor. Interrupts mapped to the
internal processor are merged and dispatched to embedded microcontroller. Interrupts mapped to the external processor
are merged and dispatched to the external pin (INT_OUT). To ease the interrupt indexing of the external processor, two
interrupt index registers (one for internal and the other for external) are defined to reflect the status of different types of
interrupt status bits. Please note that the index register is just reflects the interrupt status of the various modules and
there are no real registers implemented. Therefore, clearing a particular interrupt status must be performed in the module
which generated the interrupt.
15.4 ACCESS ARBITER
Access request from I²C slave and embedded processor will be arbitrated with strict high priority to I²C. The access is split
to byte-perbyte basis.
15.5 DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between the host processor and the P95020 via the digital audio data serial interface, or audio
bus. The audio bus on this device is flexible, including left or right justified data options, support for I²S protocols,
programmable data length options.
The audio bus of P95020 can be configured for left or right justified, I²S slave modes of operation. These modes are all
MSB-first, with data width programmable as 16, 20, 24 bits.
The world clock (I2S_WS1 or I2S_WS2) is used to define the beginning of a frame. The frequency of this clock
corresponds to the maximum of the selected ADC and DAC sampling frequency. The bit clock (I2S_BCLK1 or
I2S_BCLK2) is used to clock in and out the digital audio data across the serial bus. Each port may be programmed for 8
kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.050 kHz, 24 kHz, 44.1 kHz, 48 kHz, 88.2 kHz or 96 kHz sample rate.
Revision 0.7.10
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15.6 I2C_I2S – INTERFACE TIMING
15.6.1
I2C Interface Timing
tSCL
tSCLHIGH
tSCLLOW
IICSCL
tSTOPH
tBLF
tSDAS
tSDAH
tSTARTS
IICSDA
Parameter
SCL Clock Frequency
Symbol
Min.
Typ.
tSCL
-
-
SCL High Level Pulse Width
tSCLHIGH
SCL Low Level Pulse Witdh
tSCLLOW
Bus Free Time Between
STOP and START
START Hold Time
tBUF
tSTARTS
SDA Hold Time
tSDAH
SDA setup time
tSDAS
STOP Setup Time
tSTOPH
Std. 4.0
Fast 0.6
Std. 4.7
Fast 1.3
Std. 4.7
Fast 1.3
Std. 4.0
Fast 0.6
Std. 0
Fast 0
Std. 250
Fast 100
Std. 4.0
Fast 0.6
Max.
Std. 100
Fast 400
Unit
-
-
µs
-
-
µs
-
-
µs
-
-
µs
-
3.45
0.9
µs
-
-
ns
-
-
µs
kHz
Table 28 – I2C Interface Timing
Revision 0.7.10
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15.6.2
I2S Interface Timing – I2S Slave Mode
Left Channel
Right Channel
I2S_WS
10
16
11 11
17
16
I2S_BCLK
I2S_SDIN
14
14
14
14
13
13
13
13
23
22
1
8 dummy bits
15
15
I2S_SDOUT
0
23
22
1
22
1
15
0
Parameter
I2S_BCLK Cycle Time
I2S_BCLK Pulse Width High
I2S_BCLK Pulse Width Low
I2S_WS Set-up Time To I2S_BCLK
High
I2S_WS Hold Time to I2S_BCLK High
I2S_SDIN Set-up Time to I2S_BCLK
High
I2S_SDIN Hold Time to I2S_BCLK
High
I2S_SDOUT Delay Time from
I2S_BCLK Falling Edge
23
8 dummy bits
Notation
10
11
11
16
0
8 dummy bits
15
23
22
1
0
8 dummy bits
Min.
1/64 x Fs
0.45 x P
0.45 x P
Typ.
-
Max.
0.55 x P
0.55 x P
Unit
ns
ns
ns
tWS
10
-
-
ns
tWH
10
-
-
ns
tDS
10
-
-
ns
tDH
10
-
-
ns
tDD
-
-
10
ns
14
15
22
23
22
15
Symbol
tCYC
tCH
tCL
17
13
23
Table 29 – I2S Interface Timing
Notes: Fs = 8 to 96 kHz, P = I2S_BCLK period
Revision 0.7.10
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15.7 GLOBAL REGISTER SETTINGS (I²C-page 0)
Global Registers are used by the Access Manager, which includes an I²C Slave and Bus Arbiter. For easy access from
the I²C slave interface (by default 256 Bytes oriented) the first 16 registers of each page are global for all the pages
(Page 0 thru Page 3). The Base addresses are defined in Table 3 – Register Address Global Mapping on page 20.
15.7.1
Global Register – RESET_ID
I²C Address = Page-x: 00(0x00), µC Address = 0xA000
Bit
Bit Name
[6:0]
ID
7
RESET
Def.
Set.
1010101b
0b
User
Type
R
RW1A
Value
Description / Comments
0 = Normal
1 = System Reset
Chip ID
Master Reset. Write “1” to this register to trigger a system reset.
System reset will reset P95020 device into OFF state.
15.7.2
Global Register – PAGE_ID
I²C Address = Page-x: 01(0x01), µC Address = 0xA001
Bit
Bit Name
[1:0]
[7:2]
PAGE
RESERVED
Def.
Set.
00b
000000b
User
Type
RW
RW
Value
Description / Comments
Page ID
RESERVED
15.7.3
Global Register – DCDC_FAULT
I²C Address = Page-x: 02(0x02), µC Address = 0xA002
Bit
Bit Name
Def.
Set.
User
Type
0
BUCK500_0_FAULT
0b
R
1
BUCK500_1_FAULT
0b
R
2
BUCK1000_FAULT
0b
R
3
BOOST5_FAULT
0b
R
[7:4]
RESERVED
0h
RW
Value
Description / Comments
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
Fault in 500 mA Buck Converter #0
Fault in 500 mA Buck Converter # 1
Fault in 1000 mA Buck Converter
Fault in BOOST5 Converter
RESERVED
15.7.4
Global Register – LDO_FAULT
I²C Address = Page-x: 03(0x03), µC Address = 0xA003
Bit
Bit Name
0
LDO_050_0_FAULT
1
LDO_050_1_FAULT
2
LDO_050_2_FAULT
3
LDO_050_3_FAULT
4
LDO_150_0_FAULT
5
LDO_150_1_FAULT
6
LDO_150_2_FAULT
7
LDO_LP_FAULT
Revision 0.7.10
Def.
Set.
0b
0b
0b
0b
0b
0b
0b
0b
User
Type
R
R
R
R
R
R
R
R
Value
Description / Comments
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
0 = Normal
1 = Fault
120
Fault in LDO_050_0
Fault in LDO_050_1
Fault in LDO_050_2
Fault in LDO_050_3
Fault in LDO_150_0
Fault in LDO_150_1
Fault in LDO_150_2
Fault in LDO_LP
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
15.7.5
Global Register – LDO_GLOBAL_EN
I²C Address = Page-x: 04(0x04), µC Address = 0xA004
Bit
Bit Name
0
LDO_050_0_ENABLE
1
LDO_050_1_ENABLE
2
LDO_050_2_ENABLE
3
LDO_050_3_ENABLE
4
LDO_150_0_ENABLE
5
LDO_150_1_ENABLE
6
LDO_150_2_ENABLE
7
RESERVED
Def.
Set.
0b
User
Type
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
RW
Value
Description / Comments
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
Enable LDO_050_0
Enable LDO_050_1
Enable LDO_050_2
Enable LDO_050_3
Enable LDO_150_0
Enable LDO_150_1
Enable LDO_150_2
RESERVED
15.7.6
Global Register – DCDC_GLOBAL_EN
I²C Address = Page-x: 05(0x05), µC Address = 0xA005
Bit
0
Bit Name
BUCK500_0_ENABLE
1
BUCK500_1_ENABLE
2
BUCK1000_ENABLE
3
BOOST5_ENABLE
4
LED_BOOST_ENABLE
[6:5]
RESERVED
7
CLASS_D_ENABLE
Def.
Set.
0b
User
Type
RW
0b
RW
0b
RW
0b
RW
0b
RW
00b
RW
0b
RW
Value
Description / Comments
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
Enable BUCK500_0 Converter
Enable BUCK500_1 Converter
Enable BUCK1000 Converter
Enable BOOST5 Converter
Enable LED_BOOST Converter
RESERVED
0 = Disabled
1 = Enabled
15.7.7
Global Register – EXT_INT_STATUS INDEX
I²C Address = Page-x: 06(0x06), µC Address
I²C Address = Page-x: 07(0x07), µC Address
I²C Address = Page-x: 08(0x08), µC Address
I²C Address = Page-x: 09(0x09), µC Address
Enable Class D BTL Power Stage
=
=
=
=
0xA006
0xA007
0xA008
0xA009
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[31:0]
EXT_INT_STATUS
00000000h
R
Please refer to below.
External interrupt status index.
Note that the actual interrupt status bit is implemented in the
individual functional modules.
15.7.8
Global Register – INT_INT_STATUS INDEX
I²C Address = Page-x: 10(0x0A), µC Address
I²C Address = Page-x: 11(0x0B), µC Address
I²C Address = Page-x: 12(0x0C), µC Address
I²C Address = Page-x: 13(0x0D), µC Address
=
=
=
=
0xA00A
0xA00B
0xA00C
0xA00D
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[31:0]
INT_INT_STATUS
00000000h
R
Please refer to below.
Internal interrupt status index.
Note that the actual interrupt status bit is implemented in the
individual functional modules.
Revision 0.7.10
121
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
The following table lists the bit mapping for interrupt direction control and internal / external processor interrupt status
index register.
Table 30 - Interrupt Source Mapping
Byte
ID
0
1
Bit
Field
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
2
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Mapping
RESERVED
GPIO1 (Pin 121)
GPIO2 (Pin 122)
GPIO3 (Pin 123)
GPIO4 (Pin 124)
GPIO5 (Pin 001)
GPIO6 (Pin 002)
GPIO7 (Pin 003)
GPIO8 (Pin 004)
GPIO9 (Pin 005)
GPIO10 (Pin 006)
RESERVED
Short_SW
RESERVED
Mid_SW
“Both” flag, only meaningful for interrupt direction control.
If this bit is set, interrupts will be dispatched to both internal and external processors.
WatchDog (Time-out)
GPTimer (Time-out)
RTC_Alarm1 (Time-out)
RTC_Alarm2 (Time-out)
LDO Fault - A „1‟ indicates that one of the LDOs (Register 0xAx03, at least one of bits [7:0]) has faulted.
DCDC Fault – A „1‟ indicates that one of the DC to DC Converters (Register 0xAx02, at least one of bits [3:0]) has faulted.
Charger (Adapter in/charging state change)
ClassD Fault – The CLASS_D BTL Power Output has faulted. (Registers 0xA08B & 0xA08D, bit 4 must be set in both regs.)
Touch screen Pendown
Die temperature high (High temperature defined in A0E4h/A0E3h)
Battery voltage low
VSYS voltage low
ADC other interrupt except temperature high, battery low and VSYS low
Battery voltage extremely low (3.0V)
Die temperature extremely high (>155°C)
RESERVED
15.7.9
Global Register – I2C_SLAVE_ADDR
I²C Address = Page-x: 14(0x0E), µC Address = 0xA00E
Bit
Bit Name
0
RESERVED
[7:1]
I²C_SLAVE_ADDR
Def.
Set.
0b
0101010b
(2Ah)
User
Type
RW
Value
Description / Comments
RESERVED
RW
I²C slave address (Default = 0b0101010)
15.7.10 Global Register – I2C_CLOCK_STRETCH
I²C Address = Page-x: 15(0x0F), µC Address = 0xA00F
Bit
Bit Name
Def.
Set.
User
Type
0
STRETCH_EN
0b
RW
1
CLK_GATE_EN
0b
RW
[7:2]
RESERVED
000000b
RW
Revision 0.7.10
Value
Description / Comments
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
I²C interface stretch function enable
I²C interface clock-gating (for low power) function enable
RESERVED
122
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
15.8 ACCM REGISTERS
INT_DIR CONFIGURATION: I²C
I²C
I²C
I²C
Address
Address
Address
Address
=
=
=
=
Page-0:
Page-0:
Page-0:
Page-0:
16(0x10),
17(0x11),
18(0x12),
19(0x13),
µC
µC
µC
µC
Address
Address
Address
Address
=
=
=
=
0xA010
0xA011
0xA012
0xA013
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
[31:0]
INT_DIR
FFFF77FFh
RW
Please refer to
above.
Interrupt direction (“1” map to internal processor).
EXT_INT_DATA_IN: I²C Address = Page-0: 20(0x14), µC Address = 0xA014
Bit
Bit Name
Def.
Set.
User
Type
[7:0]
EXT_INT_DATA
00h
RW
Value
Description / Comments
External processor generated interrupt associated data. External
processor write to this register will set EXT_INT_STATUS bit.
EXT_INT_STATUS_IN: I²C Address = Page-0: 21(0x15), µC Address = 0xA015
Bit
Def.
Set.
Bit Name
User
Type
Value
Description / Comments
0 = Normal operation
1 = Interrupt
External processor interrupt status
0
EXT_INT_STATUS
0b
RW1C
[7:1]
RESERVED
0000000b
RW
RESERVED
INT_INT_DATA_IN: I²C Address = Page-0: 22(0x16), µC Address = 0xA016
Bit
Bit Name
Def.
Set.
User
Type
[7:0]
INT_INT_DATA
00h
RW
Value
Description / Comments
Internal processor generated interrupt associated data. Internal
processor write to this register will set INT_INT_STATUS bit
INT_INT_STATUS_IN: I²C Address = Page-0: 23(0x17), µC Address = 0xA017
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
INT_INT_STATUS
0b
RW1C
0 = Normal operation
1= Interrupt
Internal processor interrupt status
[7:1]
RESERVED
00h
RW
RESERVED
UP_CONTEXT: I²C Address = Page-0: 24(0x18), µC Address = 0xA018
I²C Address = Page-0: 25(0x19), µC Address = 0xA019
Bit
Bit Name
[15:0]
UP_CONTEXT
DATA_BUF: I²C
I²C
I²C
I²C
Address
Address
Address
Address
Def.
Set.
0000h
=
=
=
=
Page-0:
Page-0:
Page-0:
Page-0:
User
Type
RW
Value
Description / Comments
Reserved for Processor context
26(0x1A),
27(0x1B),
28(0x1C),
29(0x1D),
Bit
Bit Name
Def.
Set.
User
Type
[31:0]
DAT_BUF
00000000h
RW
µC
µC
µC
µC
Value
Address
Address
Address
Address
=
=
=
=
0xA01A
0xA01B
0xA01C
0xA01D
Description / Comments
Can be read or write by internal or external processor, this
register is for interprocessor communication.
CHIP_OPTIONS: I²C Address = Page-0: 30(0x1E), µC Address = 0xA01E
Bit
Bit Name
[1:0]
[3:2]
4
5
[7:6]
RESERVED
RESERVED
EX_ROM
RESERVED
CHIP_OPT
Def.
Set.
00b
00b
0b
0b
00b
User
Type
R
R
R
R
R
Value
Description / Comments
RESERVED
RESERVED
EX_ROM pin value
RESERVED
Chip metal option (metal changeable bit in metal fixed version)
DEV_REV: I²C Address = Page-0: 31(0x1F), µC Address = 0xA01F
Bit
Bit Name
[7:0]
DEV_REV
Revision 0.7.10
Def.
Set.
00h
User
Type
R
Value
Description / Comments
Device revision
123
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
16.0 LDO MODULE
FEATURES
DESCRIPTION
The P95020 includes two types of LDOs for external use:
normal LDOs (NMLDO) and one low-power, always on
LDO (LPLDO). There are seven NMLDOs which are
powered by external power inputs.
The LPLDO is
powered by VSYS. All of the external use LDOs share a
common ground pin.
Four external use LDOs with current output up to 50mA
Initialization and power sequencing controlled by an
external CPU or the Embedded Microcontroller
Output voltage adjustable in 25mV steps from 0.75V
to 3.7V
Programmable Overcurrent / Short Circuit Protection
The P95020 also includes LDOs which are used by other
functional blocks within the device. The LDOs used by
the Audio module (LDO_AUDIO_18 and LDO_AUDIO_33)
are powered by a dedicated power input. The remaining
internal-use LDOs are powered by VSYS.
Three external use LDOs with current output up to
The power-up of each LDO is controlled by a built-in
current-limiter. After each LDO is enabled, its currentlimiter will be turned-on (~100-200 s) and then the LDO
will ramp up to the configured current-limit setting.
LDO_LP
CKGEN_GND
VDD_CKGEN33
The global enable control and each local enable control
(defined in each local LDO register) are AND-ed together
to enable each specific LDO.
VDD_CKGEN18
VSYS
DGND
150mA
Initialization and power sequencing controlled by an
external CPU or the Embedded Microcontroller
Output voltage adjustable in 25mV steps from 0.75V
to 3.7V
Programmable Overcurrent / Short Circuit Protection
One user-selectable (3.0V or 3.3V), always-on low-power
LDO
10mA maximum output current
Programmable Over Current / Short Circuit Protection
LDO_IN1
VDD_CKGEN18
VDD_CKGEN33
DACVOUT: 0x60 [6:0]
LDO_150_0
LDO_150_0
DACILIM: 0x61 [1:0]
DACVOUT: 0x62 [6:0]
GLOBAL POR
LDO_150_1
Internal Sub-Blocks
LDO_150_1
DACILIM: 0x63 [1:0]
DACVOUT: 0x64 [6:0]
LDO_150_2
REGISTER BUS
LDO_LP
I2C/I2S
SUB-BLOCK
VOUTSEL33_30
0x72 [0:0]
LDO_150_2
DACILIM: 0x65 [1:0]
LDO_GND
LDO_IN2
DACVOUT: 0x66 [6:0]
LDO_50_0
MICROCONTROLLER
SUB-BLOCK
UPPER BYTE OFFSET: 0xA0
LDO_50_0
DACILIM: 0x67 [1:0]
DACVOUT: 0x68 [6:0]
LDO_50_1
LDO_50_1
DACILIM: 0x69 [1:0]
LDO
EMBUP18
DACVOUT: 0x6A [6:0]
LDO_50_2
LDO_50_2
DACILIM: 0x6B [1:0]
DACVOUT: 0x6C [6:0]
LDO_50_3
LDO_50_3
DACILIM: 0x6D [1:0]
LDO_IN3
VDD_AUDIO18
AGND
VDD_AUDIO33
VDD_AUDIO33
Figure 33 – LDO_050 / LDO_150 Block Diagram
Revision 0.7.10
124
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
16.1 LDO - PIN DEFINITIONS
PIN #
023
029
030
031
032
033
034
035
036
037
038
039
040
045
047
PIN_ID
VDD_AUDIO33
LDO_GND
LDO_IN3
LDO_LP
LDO_050_3
LDO_IN2
LDO_050_2
LDO_050_1
LDO_050_0
LDO_150_2
LDO_IN1
LDO_150_1
LDO_150_0
VDD_CKGEN18
VDD_CKGEN33
DESCRIPTION
Filter capacitor for internal 3.3V audio LDO. Do not draw power from this pin.
Common GROUND for all LDOs.
Input Voltage to AUDIO LDOs (VDD_AUDIO33 & VDD_AUDIO18)
Always-On Low Power LDO for RTC.
50 mA LDO Output #3
Input Voltage to LDO_050_3, LDO_050_2, LDO_050_1 and LDO_050_0.
50 mA LDO Output #2
50 mA LDO Output #1
50 mA LDO Output #0
150 mA LDO Output #2
Input Voltage to LDO_150_2, LDO_150_1 and LDO_150_0.
150 mA LDO Output #1
150 mA LDO Output #0
Filter Capacitor for Internal 1.8V CKGEN LDO
Filter Capacitor for Internal 3.3V CKGEN LDO
16.2 LDO - LDO_150 & LDO_050 ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VIN1=VIN2=VSYS= 3.8V, TA = -40°C to +85°C, COUT=CIN=1µF
SYMBOL
VIN1, VIN2
VOUT
VSTEP
PARAMETER
Input Voltage Requirements
Output Voltage Range
Output Voltage Step Size
VO
Output Accuracy
VDROPOUT
Dropout voltage (VIN-VOUT)
IRATED
Maximum Rated Output Current
ILIM
Maximum Programmable Current
Limit
ISTEP_SIZE
Current Limit Step Size
ILIM_RANGE
IQ150
Current Limit Programming Range
Quiescent Current Into LDO_150
(IN#1)
CONDITIONS
MIN
3
0.75
TYP
MAX
5.5
3.7
UNIT
V
V
mV
+4
%
74
102
150
200
mV
210
300
25
Iout = 0 to Rated Current
VIN = 3V to 5.5V
Over Line And Load Conditions
-4
(IRATED/3 load)
(IRATED/2 load)
(IRATED load)
Note 1
LDO_050
LDO_150
LDO_050
LDO_150
50
150
65
195
mA
125
375
% of
Maximum
Programmable
Current Limit
25
LDO150_0 @ 0x61 [1:0];
LDO150_1 @ 0x63 [1:0];
LDO150_2 @ 0x65 [1:0];
LDO50_0 @ 0x67 [1:0];
LDO50_1 @ 0x69 [1:0];
LDO50_2 @ 0x6B [1:0];
LDO50_3 @ 0x6D [1:0];
mA
100
% of
Maximum
Programmable
Current Limit
40
53
µA
53
71
µA
25
Standard Operation All Three
LDOs Active, Measured At
VIN_IN1
LDO150_0 @ 0x60 [7:7] = 1;
LDO150_1 @ 0x62 [7:7] = 1;
LDO150_2 @ 0x64 [7:7] = 1;
Standard Operation All Four
LDOs Active, Measured At
VIN_IN2
IQ50
Quiescent Current Into LDO_50
(IN#2)
LDO50_0 @ 0x66 [7:7] = 1;
LDO50_1 @ 0x68 [7:7] = 1;
LDO50_2 @ 0x6A [7:7] = 1;
LDO50_3 @ 0x6C [7:7] = 1;
Notes:
1. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at 1V differential. Not applicable to output voltages less than 3V.
Revision 0.7.10
125
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
16.3 LDO – TYPICAL PERFORMANCE CHARACTERISTICS
LDO_50_n Load Regulation
3.4
3.38
VOUT (V)
3.36
3.34
3.32
3.3
3.28
3.26
0
5
10
15
20
25
30
35
40
45
50
Load (mA)
Figure 34 – LDO_050_n 50mA LDO Load Regulation
LDO_150_n Load Regulation
3.4
3.38
Vout (V)
3.36
3.34
3.32
3.3
3.28
3.26
0
25
50
75
100
125
150
Load (mA)
Figure 35 – LDO_150_n 150mA LDO Load Regulation
Revision 0.7.10
126
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
16.4 LDO - LDO_LP - ELECTRICAL CHARACTERISTICS
Unless otherwise specified, typical values at TA =25C, VIN=VSYS = 3.8V, TJ = 0°C to +85°C, COUT=CIN=1µF
SYMBOL
VSYS
VOUT
VDROPOUT
IOUT
PARAMETER
SYS Input Voltage Requirements
Output Voltage
Dropout voltage (VIN-VOUT)
Output Current
CONDITIONS
TA=25C, Over Line And Load
IOUT = 10 mA, Note 2.
MIN
3
3.15
TYP
3.3
150
MAX
5.5
3.45
TBD
10
UNIT
V
V
mV
mA
Notes:
2. Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at 1V differential. Not applicable to output voltages less than 3V.
16.5 LDO - LIST OF ALL LDOS
LDO Name
Source
LDO_150
LDO_IN1
LDO_050
LDO_IN2
LDO_LP
VDD_CKGEN33
VDD_CKGEN18
VDD_AUDIO33
VDD_AUDIO18
VDD_EMBUP18
VSYS
VSYS
VSYS
LDO_IN3
LDO_IN3
VSYS
VOUT
0.75V –
3.7V
0.75V –
3.7V
3.3 / 3.0
3.3
1.8
3.3
1.8
1.8
Comments
For Module
150 mA max. LDO
External Usage
50 mA max. LDO
External Usage
Always on LDO, selectable 3.3V or 3.0V output voltage
Turn On/Off depending on PSTAT_ON register (Cyrus “ON” flag)
Turn On/Off depending on PSTAT_ON register (Cyrus “ON” flag)
Can be turned on/off via enable bits in LDO_AUDIO18 and
LDO_AUDIO33 registers
Turn On/Off depending on whether there is an interrupt pending
CKGEN
AUDIO &
CLASS_D_DIG
EMBUP
16.6 LDO – REGISTER SETTINGS
The LDO Module can be controlled and monitored by writing 8-bit control words to the various registers. The base
addresses are defined in Table 3 – Register Address Global Mapping on page 20.
16.6.1
LDO_150 AND LDO_050 – OPERATION REGISTERS
The Output Voltage Registers for the LDO_150 & LDO_050 LDOs contain the enable bit and setting bits for the output
voltage.
LDO_150_0
LDO_150_1
LDO_150_2
LDO_050_0
LDO_050_1
LDO_050_2
LDO_050_3
=
=
=
=
=
=
=
I²C Address = Page-0: 96(0x60), µC Address = 0xA060
I²C Address = Page-0: 98(0x62), µC Address = 0xA062
I²C Address = Page-0: 100(0x64), µC Address = 0xA064
I²C Address = Page-0: 102(0x66), µC Address = 0xA066
I²C Address = Page-0: 104(0x68), µC Address = 0xA068
I²C Address = Page-0: 106(0x6A), µC Address = 0xA06A
I²C Address = Page-0: 108(0x6C), µC Address = 0xA06C
Bit
Bit Name
Def.
Set.
User
Type
[6:0]
VOUT
[]
RW
7
ENABLE
0b
RW
Revision 0.7.10
Value
Description / Comments
Output Voltage =
VOUT * 25 mV +
750 mV
1 = Enable
0 = Disable
127
Performance and accuracy are not guaranteed with bit combinations
above 1110110.
LDO local enable bit for the LDO_150 and LDO_050 LDOs
Reserved bit for LDO_050_0
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
16.6.2
LDO_150 AND LDO_050 – CONTROL REGISTERS
The Control Registers contains bits for setting the Current Limit.
LDO_150_0
LDO_150_1
LDO_150_2
LDO_050_0
LDO_050_1
LDO_050_2
LDO_050_3
=
=
=
=
=
=
=
I²C
I²C
I²C
I²C
I²C
I²C
I²C
Bit
Bit Name
[1:0]
[7:2]
I_LIM
RESERVED
Address
Address
Address
Address
Address
Address
Address
=
=
=
=
=
=
=
Def.
Set.
00b
000000b
Page-0:
Page-0:
Page-0:
Page-0:
Page-0:
Page-0:
Page-0:
User
Type
RW
RW
97(0x61), µC Address = 0xA061
99(0x63), µC Address = 0xA063
101(0x65), µC Address = 0xA065
103(0x67), µC Address = 0xA067
105(0x69), µC Address = 0xA069
107(0x6B), µC Address = 0xA06B
109(0x6D), µC Address = 0xA06D
Value
Description / Comments
(See Table 31)
Current Limit (%)
RESERVED
Table 31 – Control Register Current Limit (I_LIM) Settings for Bits [1:0]
Bit 3
0
0
1
1
Bit 2
0
1
0
1
Description
Current Limit = 120 % of Rating
Current Limit = 90 % of Rating
Current Limit = 60 % of Rating
Current Limit = 30 % of Rating
Note – Current Limit is at maximum when bits [1:0] are both set to 0.
16.6.3
VDD_AUDIO18 LDO REGISTER
The VDD_AUDIO18 Register contains the enable bit and the output voltage bit.
I²C Address = Page-0: 110(0x6E), µC Address = 0xA06E
Bit
Def.
Set.
Bit Name
User
Type
Value
Description / Comments
0 = 1.8 V
1 = 1.5 V
Select VDD_Audio18 Output Voltage (1.8V or 1.5V)
0
SEL_15V
0b
RW
[6:1]
RESERVED
000000b
RW
7
EN_AUDIO18
0b
RW
RESERVED
0 = Not Enabled
1 = Enabled
Enable VDD_AUDIO18 LDO
16.6.4
VDD_AUDIO33 LDO REGISTER
The VDD_AUDIO33 Voltage Register contains the enable bit and the output voltage bits.
I²C Address = Page-0: 111(0x6F), µC Address = 0xA06F
Bit
Bit Name
Def.
Set.
User
Type
[6:0]
VOUT
1100110b
RW
7
EN_AUDIO33
0b
RW
Value
Description / Comments
Output Voltage =
VOUT * 25 mV +
750 mV
0 = Disable
1 = Enable
Default = 3.3 V. Performance and accuracy are not guaranteed with bit
combinations above 1110110 (3.7V).
Enable Audio_33 LDO
16.6.5
EXTERNAL LDO POWER GOOD REGISTER
The LDO_STATUS1 Register contains the power good bits for the LDO_150 and LDO_050 LDOs.
I²C Address = Page-0: 112(0x70), µC Address = 0xA070
Bit
Bit Name
0
1
2
3
4
5
6
7
LDO_150_0_PG
LDO_150_1_PG
LDO_150_2_PG
LDO_050_0_PG
LDO_050_1_PG
LDO_050_2_PG
LDO_050_3_PG
RESERVED
Revision 0.7.10
Def.
Set.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0b
User
Type
R
R
R
R
R
R
R
R
Value
Description / Comments
0 = Power NOT
Good
1 = Power IS Good
128
Power Good Status for LDO_150_0
Power Good Status for LDO_150_1
Power Good Status for LDO_150_2
Power Good Status for LDO_050_0
Power Good Status for LDO_050_1
Power Good Status for LDO_050_2
Power Good Status for LDO_050_3
RESERVED
©2010 Integrated Device Technology, Inc.
P95020 / Preliminary Datasheet
16.6.6
INTERNAL LDO POWER GOOD REGISTER
The LDO_STATUS2 Register contains power good bits for internal LDOs: VDD_AUDIO33, VDD_CKGEN18 and
VDD_CKGEN33.
I²C Address = Page-0: 113(0x71), µC Address = 0xA071
Bit
Bit Name
0
1
2
VDD_AUDIO33_PG
VDD_CKGEN18_PG
VDD_CKGEN33_PG
[7:3]
RESERVED
Def.
Set.
N/A
N/A
N/A
00000
b
User
Type
R
R
R
Value
Description / Comments
0 = Power NOT Good
1 = Power IS Good
Power Good Status for AUDIO33 LDO
Power Good Status for CKGEN18 LDO
Power Good Status for CKGEN33 LDO
R
RESERVED
16.6.7
LOW POWER LDO VOLTAGE REGISTER
The LDO_LP Voltage Register contains one voltage select bit.
LDO_LP_VOL: I²C Address = Page-0: 114(0x72), µC Address = 0xA072
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0 = 3.3 V
1 = 3.0 V
Select “Always-On” LDO Output Voltage (Default = 3.3V, Optional = 3.0V)
0
LDO_LP_VOL
0b
RW
[7:1]
RESERVED
0000000b
RW
RESERVED
16.6.8
EXTERNAL LDO FAULT INTERRUPT ENABLE REGISTER
The EXT_LDO_FAULT_INT_EN Register contains the fault interrupt enable bits for the 7 external LDOs.
LDO_FAULT: I²C Address = Page-0: 115(0x73), µC Address = 0xA073
Bit
Bit Name
0
1
2
3
4
5
6
7
LDO_050_0_FLT_INT_EN
LDO_050_1_FLT_INT_EN
LDO_050_2_FLT_INT_EN
LDO_050_3_FLT_INT_EN
LDO_150_0_FLT_INT_EN
LDO_150_1_FLT_INT_EN
LDO_150_2_FLT_INT_EN
RESERVED
Def.
Set.
0b
0b
0b
0b
0b
0b
0b
0b
User
Type
RW
RW
RW
RW
RW
RW
RW
RW
Value
Description / Comments
0 = Disable
1 = Enable
Fault interrupt enable for LDO_050_0
Fault interrupt enable for LDO_050_1
Fault interrupt enable for LDO_050_2
Fault interrupt enable for LDO_050_3
Fault interrupt enable for LDO_150_0
Fault interrupt enable for LDO_150_1
Fault interrupt enable for LDO_150_2
RESERVED
16.6.9
LDO - INT_LDO_FAULT_INT Interrupt Register
The INT_LDO_FAULT_INT Register contains contains the Fault Status bits for the internal LDOs
I²C Address = Page-0: 117(0x75), µC Address = 0xA075
Bit
Bit Name
0
1
2
3
[7:4]
VDD_AUDIO33_FLT
VDD_CKGEN18_FLT
VDD_CKGEN33_FLT
LDO_LP_FAULT
RESERVED
Def.
Set.
0b
0b
0b
0b
0000b
User
Type
R
R
R
R
R
Value
Description / Comments
0 = No Fault
1 = Fault Exists
Fault in VDD_AUDIO33 regulator
Fault in VDD_CKGEN18 regulator
Fault in VDD_CKGEN33 regulator
Fault in LDO_LP regulator
RESERVED
16.6.10 LDO SECURITY REGISTER
I²C Address = Page-0: 119(0x77), µC Address = 0xA077h
Bit
Bit Name
Def.
Set.
User
Type
0
LDO_SEC_0
0b
RW
1
LDO_SEC_1
0b
RW
2
LDO_SEC_2
0b
RW
[7:3]
RESERVED
00000b
RW
Revision 0.7.10
Value
Description / Comments
0 = Access allowed
1 = Access blocked
0 = Access allowed
1 = Access blocked
0 = Access allowed
1 = Access blocked
Allows or blocks the user from programming bit 4 in all of the external LDO
Output Voltage Registers.
Allows or blocks the user from programming bit 5 in all of the external LDO
Output Voltage Registers.
Allows or blocks the user from programming bit 6 in all of the external LDO
Output Voltage Registers.
RESERVED
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16.6.11 LDO - RESERVED Registers
These registers are reserved. Do not write to them.
I²C Address = Page-0: 118(0x76), µC Address = 0xA076
I²C Address = Page-0: 120(0x78), µC Address = 0xA078
Thru Page-0: 127(0x7F), µC Address = 0xA07F
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17.0 EMBUP – EMBEDDED MICROCONTROLLER SUBSYSTEM & I/O
FEATURES
Power Up/Down Sequencing
Eliminates the need for the AP or another external
controller (PLD/PIC) to perform this function.
Improves system power consumption by offloading this task
from the higher power application processor.
General monitoring and action based on external or
internal events such as:
ADC Result
Power Supply Fault Monitoring
Other System Interrupts
DESCRIPTION
The Embedded Microcontroller (EMBUP) of the P95020
can operate in one of two modes: mixed mode or standalone mode.
In mixed mode, both the internal
microcontroller and an external Application Processor
(AP) can also control some or all of the P95020
subsystems.
In stand-alone mode, the EMBUP
completely offloads power sequencing and other functions
from the application processor so that the processor can
perform other functions or spend more time in sleep
mode.
The microcontroller core runs at 8 MHz with a 1.8V power
supply and can be shut off if required. It interfaces
through VSYS level signals (3.0 to 5.5V) and supports the
following functions:
Device initialization
Power sequencing for power state transitioning
Keyboard scanning
Enable/Disable of all Interfaces and Sub-Modules
17.1
OVERVIEW
Module
Interrupts
ACCM
CHGR
CLASSD-Driver
DCDC
GPTIMER
LDO
GPIO
RTC
TSC
Message signaling
Adapter In/ Charging state change
Fault
Fault
General purpose timer, Watchdog timer
Fault
GPIO/SW_DET
Alarm-1, Alarm-2
Pendown
Die temperature high,
Battery voltage low,
VSYS voltage low
TSC
Interrupts
1
3
1
1
2
1
10/2
2
1
Usage
Internal /external processor communication
Charger state detection
System power on/off
3
17.2 FUNCTIONAL DESCRIPTION
After a Power on Reset (POR), the P95020 embedded microcontroller will look for the presence of an external ROM via
the EX_ROM pin. If an external ROM is present, the P95020 embedded microcontroller will disable the internal ROM,
and load the contents into a 1.5 KB internal RAM from which it can be executed. If no external ROM is present, then the
internal ROM will be used for program code.
The P95020 embedded microcontroller will execute the start-up sequence contained in the internal or external ROM and
will set the various registers accordingly (all internal registers are available for manipulation by an external application
processor through the I²C interface at all times). Once the registers have been programmed, the embedded
microcontroller will either run additional program code or go into standby until an interrupt or other activity generates a
wake event. Various events will be customer specific but could include power saving modes, sleep modes, overtemperature conditions, etc.
Contention caused by requests from both the embedded microcontroller and external processor is resolved through a bus
arbitration scheme. There is no support for data concurrency in the register set. The P95020 will execute the latest (last)
data/command programmed into any individual control register(s) regardless of the source (embedded microcontroller or
external application processor). Care should be taken during the code development stage to avoid command contention.
17.3 ON-CHIP RAM & ROM
Memory Type
Size
ROM
RAM
4 k Bytes Maximum
1.5 k Bytes Maximum
17.4 I²C SLAVE INTERFACE
Please see the separate I2C_I2S Module in Section 15.0 for details (including register definitions).
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17.5 PERIPHERALS
The peripherals of the subsystem are comprised of a timer, an interrupt controller and an I²C master. The embedded
processor‟s peripherals are not visible to the external application processor.
The I²C master is used to optionally load data or code from an external serial EEPROM. The target EEPROM address is
hardwired to 1010000. The P95020 supports EEPROMs using 16-bit addressing in the range of 4 kB to 64KB.
17.6 INTERRUPT CONTROLLER
17.6.1
OVERVIEW
The interrupt controller is built in to the EMBUP core and is only used to monitor subsystem interrupts.
CHGR:
Charger
LDO
I2CS_OTP
DCDC
FAULT
CKGEN
GPTIMER
TSCD: touch
screen digital
RTC
ACCM:
I2C-Slave/Bus
Arbiter
pendown
GPIO_TSCA
EMBUP
Embedded uP
subsystem, I2C
Master
HSWP:
Hot swap
AUDIO
PCON:
Power controller
AP
TSCA
GPIO
INT
Pendown
CLASSD_DIG
Figure 36 - Top level Interrupt routing
17.6.2
INTERRUPT HANDLING SCHEME
Each of the different functional modules may generate interrupts and these interrupts can be enabled or disabled using
their associated interrupt enable registers. The generated interrupts may also be handled by either the internal
microcontroller or an external processor. The interrupts generated from the functional modules are routed to the access
manager (ACCM) module. The ACCM module will direct the interrupts to the appropriate processor (internal or external)
according to the configurable defined in the ACCM Register.
Please note that there is no hardware level protection in to prevent interrupts that have been processed by one processor
from being cleared by the other other processor. Care must be taken in software to prevent this usage scenario.
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18.0 APPLICATIONS INFORMATION
18.1 EXTERNAL COMPONENTS
The P95020 requires a minimum number of external components for proper operation.
18.2 DIGITAL LOGIC DECOUPLING CAPACITORS
As with any high-performance mixed-signal IC, the P95020 must be isolated from the system power supply noise to
perform optimally. A decoupling capacitor of 0.01 μF must be connected between each power supply and the PCB
ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
18.3 CLASS_D CONSIDERATIONS
The CLASS_D amplifier should have one 330uF and one 0.1uF capacitor to ground at its VDD pin.
The CLASS_D output also should have a series connected snubber consisting of a 5.1 ohm, 0603 resistor and a 220pF
capacitor across the speaker output pins. No other filtering is required.
The CLASS_D BTL plus and minus output traces must be routed side by side in pairs.
18.4 SERIES TERMINATION RESISTORS
Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
18.5 I²C EXTERNAL RESISTOR CONNECTION
The SCK and SDATA pins can be connected to any voltage between 1.71 V and 3.6 V.
18.6 CRYSTAL LOAD CAPACITORS
To save discrete component cost, the P95020 integrates on-chip capacitance to support a crystal with CL=10 pF. It is
important to keep stray capacitance to a minimum by using very short PCB traces between the crystal and device. Avoid
the use of vias if possible.
18.7 PCB LAYOUT CONSIDERATIONS
For optimum device performance and lowest output phase noise, the following guidelines should be observed.
1. The 0.01μF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to each VDD pin
should be kept as short as possible, as should the PCB trace to the ground via.
2. The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead they should be separated and away from other traces.
3. To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output.
4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the P95020. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used by the device.
18.8 POWER DISSIPATION AND THERMAL REQUIREMENTS
120
110
100
90
Rated Power (%)
The power dissipated in the P95020 will depend primarily
on the total internal power dissipation and the junction
temperature. Careful consideration must be given to the
overall thermal design. Actual thermal resistance JA
must be determined at the customer‟s end product level,
being based on the end package design parameters and
available device internal cooling. See Figure 37 for
required package power de-rating.
80
70
60
50
40
30
18.9 TYPICAL BLOCK PERFORMANCE
CHARACTERISTICS GRAPHS
20
10
This section is TBD.
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120 130
Junction Temperature (°C)
Figure 37 – Power Derating Curve (Typical)
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18.10 APPLICATIONS REFERENCE DESIGN(S)
This section is TBD.
19.0 SOLDERING PROFILE
This section is TBD.
20.0 PACKAGE OUTLINE DRAWING
20.1 LLG124 PACKAGE OUTLINE
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20.2 NQG132 PACKAGE OUTLINE (Exposed Die Paddle Size D2 = E2 = 5.5 mm)
21.0 ORDERING INFORMATION
Part / Order Number Shipping Packaging
Package
Temperature
P95020ZLLG
Tubes
124-pin LLGA
0 to +70 C
P95020ZLLG8
Tape and Reel
124-pin LLGA
0 to +70 C
P95020ZLLGI
Tubes
124-pin LLGA
-40 to +85 C
P95020ZLLGI8
Tape and Reel
124-pin LLGA
-40 to +85 C
P95020ZNQG
Tubes
132-pin QFN
0 to +70 C
P95020NQG8
Tape and Reel
132-pin QFN
0 to +70 C
P95020ZNQGI
Tubes
132-pin QFN
-40 to +85 C
P95020ZNQGI8
Tape and Reel
132-pin QFN
-40 to +85 C
Revision 0.7.10
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While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from
its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any
other applications such as those requiring extended temperature ranges, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or
specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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