PS8551AL4-V-AX

Preliminary Data Sheet PS8551AL4 R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 ANALOG OUTPUT TYPE OPTICAL COUPLED ISOLATION AMPLIFIER DESCRIPTION The PS8551AL4 is an optically coupled isolation amplifier that uses an IC with a high-accuracy sigma-delta A/D converter and a GaAIAs light-emitting diode with high-speed response and high luminance efficiency on the input side, and an IC with a high-accuracy D/A converter on the output side. The PS8551AL4 is designed specifically for high common mode transient immunity (CMTI) and high linearity (nonlinearity). The PS8551AL4 is designed for current and voltage sensing. FEATURES PIN CONNECTION (Top View) 1 2 3 Gain: 8 V/V TYP. • Package: 8-pin DIP lead bending type (Gull-wing) for long creepage distance for surface mount (L4) • Embossed tape product: PS8551AL4-E3: 1 000 pcs/reel 6 – 7 + • Gain tolerance (G = 7.92 to 8.08 (±1%)) 8 – • High isolation voltage (BV = 5 000 Vr.m.s.) + • High common mode transient immunity (CMTI = 10 kV/μs MIN.) 5 SHIELD • Non-linearity (NL200 = 0.35% MAX.) 4 1. VDD1 2. VIN+ 3. VIN– 4. GND1 5. GND2 6. VOUT– 7. VOUT+ 8. VDD2 • Pb-Free product • Safety standards • UL approved: No. E72422 • CSA approved: No. CA 101391 (CA5A, CAN/CSA-C22.2 60065, 60950) • SEMKO approved (EN60065, EN60950) • DIN EN60747-5-5 (VDE0884-5) approved (Option) APPLICATIONS • AC Servo, inverter • Solar power conditioner • Measurement equipment R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 1 of 18 PS8551AL4 Chapter Title PACKAGE DIMENSIONS (UNIT: mm) Lead Bending Type (Gull-wing) For Long Creepage Distance For Surface Mount (L4) +0.5 9.25–0.25 10.05±0.4 +0.4 –0.2 +0.5 1.01 0.5±0.15 2.54 3.7±0.35 3.5±0.2 0.2±0.15 6.5–0.1 0.62±0.25 PHOTOCOUPLER CONSTRUCTION Parameter Unit (MIN.) Air Distance 8 mm Outer Creepage Distance 8 mm Isolation Distance R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 0.4 mm Page 2 of 18 PS8551AL4 Chapter Title MARKING EXAMPLE No. 1 pin Mark R 8551A NT131 Company Initial Type Number Assembly Lot N T 1 31 Week Assembled Year Assembled (Last 1 Digit) In-house Code (T: Pb-Free) Rank Code ORDERING INFORMATION Part Number Order Number Solder Plating Specification Packing Style Safety Standard Approval PS8551AL4 PS8551AL4-AX Pb-Free Magazine case 50 pcs Standard products PS8551AL4-E3 PS8551AL4-E3-AX (Ni/Pd/Au) Embossed Tape 1 000 pcs/reel (UL, CSA, SEMKO approved) PS8551AL4-V PS8551AL4-V-AX Magazine case 50 pcs UL, CSA, SEMKO, PS8551AL4-V-E3 PS8551AL4-V-E3-AX Embossed Tape 1 000 DIN EN60747-5-2 pcs/reel (VDE0884-5) Application Part 1 Number* PS8551AL4 Approved *1 For the application of the Safety Standard, following part number should be used. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 3 of 18 PS8551AL4 Chapter Title ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified) Parameter Symbol Ratings Unit Operating Ambient Temperature TA －40 to ＋105 °C Storage Temperature Tstg －55 to＋125 °C VDD1, VDD2 0 to 5.5 V Input Voltage VIN+, VIN− －2 to VDD1＋0.5 V 2 Seconds Transient Input Voltage VIN+, VIN− －6 to VDD1＋0.5 V VOUT+, VOUT− －0.5 to VDD2＋0.5 V BV 5 000 Vr.m.s. Supply Voltage Output Voltage Isolation Voltage *1 *1 AC voltage for 1 minute at TA = 25°C, RH = 60% between input and output. Pins 1-4 shorted together, 5-8 shorted together. RECOMMENDED OPERATING CONDITIONS Parameter Operating Ambient Temperature Supply Voltage Input Voltage *1 (Accurate and Linear) Symbol MIN. MAX. Unit TA −40 105 °C VDD1, VDD2 4.5 5.5 V VIN+, VIN− −200 200 mV *1 Using VIN− = 0 V (to be connected to GND1) is recommended. Avoid using VIN− of 2.5 V or more, because the internal test mode is activated when the voltage VIN− reaches more than 2.5 V. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 4 of 18 PS8551AL4 Chapter Title ELECTRICAL CHARACTERISTICS (DC Characteristics) (TYP.: TA = 25°C, VIN+ = VIN− = 0 V, VDD1 = VDD2 = 5 V, MIN., MAX.: refer to RECOMMENDED OPERATING CONDITIONS, unless otherwise specified) Parameter Symbol Input Offset Voltage Vos TA = 25°C MIN. TYP. MAX. Unit −2 −0.25 2 mV −3 −0.25 3 1.6 10 μV/°C 8 8.08 V/V ⏐dVos/dTA⏐ Input Offset Voltage Drift vs. Temperature Gain Conditions *1 G −200 mV ≤ VIN+ ≤ 200 mV, 7.92 TA = 25°C ⏐dG/dTA⏐ Gain Drift vs. Temperature VOUT Non-linearity (200 mV) *2 VOUT Non-linearity (200 mV) Drift NL200 0.0006 −200 mV ≤ VIN+ ≤ 200 mV 0.014 ⏐dNL200/dTA⏐ V/V°C 0.35 0.0001 % %/°C vs. Temperature VOUT Non-linearity (100 mV) *2 Maximum Input Voltage before VOUT Clipping NL100 −100 mV ≤ VIN+ ≤ 100 mV 0.011 ⏐VIN+⏐MAX. 0.2 320 % mV Input Supply Current IDD1 VIN+ = 400 mV 13.5 16 mA Output Supply Current IDD2 VIN+ = −400 mV 7.8 16 mA Input Bias Current IIN+ VIN+ = 0V −0.65 1 μA Input Bias Current Drift −1 ⏐dIIN+/dTA⏐ 0.3 nA/°C vs. Temperature Low Level Saturated Output Voltage VOL VIN+ = −400 mV 1.29 V High Level Saturated Output Voltage VOH VIN+ = 400 mV 3.8 V Output Voltage (VIN+ = VIN− = 0 V) VOCM VIN+ = VIN− = 0 V 2.2 2.55 2.8 V Output Short-circuit Current ⏐IOSC⏐ 20 mA Equivalent Input Resistance RIN 450 kΩ ROUT 4 Ω CMRRIN 76 dB VOUT Output Resistance Input DC Common-Mode Rejection Ratio *3 *1 The differential output voltage (VOUT+ − VOUT−) with respect to the differential input voltage (VIN+ − VIN−), where VIN+ = −200 mV to 200 mV and VIN− = 0 V) is measured under the circuit shown in Fig. 2 NL200, G Test Circuit. Upon the resulting chart, the gain is defined as the slope of the optimum line obtained by using the method of least squares. *2 The differential output voltage (VOUT+ − VOUT−) with respect to the differential input voltage (VIN+ − VIN−) is measured under the circuit shown in Fig. 2 NL200, G Test Circuit. Upon the resulting chart, the optimum line is obtained by using the method of least squares. Non-linearity is defined as the ratio (%) of the optimum line obtained by dividing [Half of the peak to peak value of the (residual) deviation] by [full-scale differential output voltage]. For example, if the differential output voltage is 3.2 V, and the peak to peak value of the (residual) deviation is 22.4 mV, while the input VIN+ is ±200 mV, the output non-linearity is obtained as follows: NL200 = 22.4/(2 × 3 200) = 0.35% *3 CMRRIN is defined as the ratio of the differential signal gain (when the differential signal is applied between the input pins) to the common-mode signal gain (when both input pins are connected and the signal is applied). This value is indicated in dB. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 5 of 18 PS8551AL4 Chapter Title ELECTRICAL CHARACTERISTICS (AC Characteristics) (TYP.: TA = 25°C, VIN+ = VIN− = 0 V, VDD1 = VDD2 = 5 V, MIN., MAX.: refer to RECOMMENDED OPERATING CONDITIONS, unless otherwise specified) Parameter Symbol VOUT Bandwidth (−3 dB) fC Conditions VIN+ = 200 mVp-p, sine wave MIN. TYP. MAX. 50 100 kHz mVr.m.s. VOUT Noise NOUT VIN+ = 0 V 15.6 VIN to VOUT Signal Delay (50 to 10%) tPD10 VIN+ = 0 to 150 mV step 2.4 3.3 VIN to VOUT Signal Delay (50 to 50%) tPD50 4.2 5.6 VIN to VOUT Signal Delay (50 to 90%) tPD90 6.1 9.9 3.1 6.6 VOUT Rise Time/Fall Time (10 to 90%) *1 Common Mode Transient Immunity Power Supply Noise Rejection *2 tr/tf VIN+ = 0 to 150 mV step CMTI VCM = 0.5 kV, tr = 20 ns, TA = 25°C PSR f = 1 MHz 10 Unit μs μs 28 kV/μs 40 mVr.m.s. *1 CMTI is tested by applying a pulse that rises and falls suddenly (VCM = 0.5 kV) between GND1 on the input side and GND2 on the output side (pins 4 and 5) by using the circuit shown in Fig. 9 CMTI Test Circuit. CMTI is defined at the point where the differential output voltage (VOUT+ − VOUT−) fluctuates 200 mV (>1 μs) or more from the average output voltage. *2 This is the value of the transient voltage at the differential output when 1 Vp-p, 1 MHz, and 40 ns rise/fall time square wave is applied to both VDD1 and VDD2. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 6 of 18 PS8551AL4 Chapter Title TEST CIRCUIT Fig. 1 VOS Test Circuit VDD2 VDD1 +15 V 1 8 0.1 μF 2 7 0.1 μF + + 3 – – 4 0.1 μF 10 kΩ + 6 10 kΩ AD624CD (x100) 5 0.47 μF 0.47 μF VOUT − 0.1 μF SHIELD –15 V Fig. 2 NL200, G Test Circuit VDD2 VDD1 +15 V 1 VIN 404 Ω 13.2 Ω 0.1 μF 2 7 0.1 μF + + 3 0.01 μF +15 V 8 – – 4 0.1 μF 10 kΩ + 6 10 kΩ AD624CD (x4) 5 0.47 μF 0.47 μF 0.1 μF + AD624CD (x10) − VOUT − 0.1 μF SHIELD 0.1 μF –15 V 10 kΩ –15 V 0.47 μF Fig. 3 IDD1 Test Circuit IDD1 Fig. 4 IDD2 Test Circuit 1 2 + 0.1μ F 5V 0.01 μF 400 mV 3 – + – 4 1 7 2 8 0.1μ F 6 5V – 400 mV 0.01 μF IDD2 7 + 5 SHIELD R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 8 3 – + – 4 6 5 0.1μ F 5V SHIELD Page 7 of 18 PS8551AL4 Chapter Title Fig. 5 IIN+ Test Circuit 8 1 IIN+ 2 7 + 0.1μ F 0.01 μF + 3 – – 4 5V 6 5 SHIELD Fig. 6 VOUT Test Circuit VOL 8 1 2 7 + 0.1μ F 5V – 400 0.01 μF mV 3 – + – 4 VOL 6 5 0.1μ F 5V SHIELD VOCM 1 8 2 7 + 0.1μ F 0.01 μF 3 – + – 4 5V VOCM 6 5 0.1μ F 5V SHIELD VOH 8 1 2 7 + 0.1μ F 5V 400 mV 0.01 μF 3 – + – 4 VOH 6 5 0.1μ F 5V SHIELD R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 8 of 18 PS8551AL4 Chapter Title Fig. 7 |IOSC| Test Circuit 1 8 2 7 + 0.1μ F 0.01 μF 3 – + – 4 5V 1 IOSC 8 2 7 + 6 0.1μ F 0.1μ F 5 5V 0.01 μF + 3 – – 4 5V 6 5 SHIELD IOSC 0.1μ F 5V SHIELD Fig. 8 tPD Test Circuit 10 kΩ VDD2 VDD1 +15 V 1 0.1 μF 2 VIN 8 + + 3 0.01 μF – – 4 7 0.1 μF 2 kΩ 6 2 kΩ 0.1 μF − VOUT NE5534 + 5 0.1 μF 10 kΩ SHIELD –15 V Fig. 9 CMTI Test Circuit 150 pF 10 kΩ VDD2 78L05 IN 9V OUT 0.1 μF +15 V 1 0.1 μF 2 8 + + 3 – – 4 7 0.1 μF 2 kΩ 6 2 kΩ 5 SHIELD + – − μPC813 + 0.1 μF VOUT 0.1 μF 150 pF 10 kΩ –15 V VCM R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 9 of 18 PS8551AL4 Chapter Title TYPICAL CHARACTERISTICS (TA = 25°C, unless otherwise specified) INPUT OFFSET VOLTAGE vs. AMBIENT TEMPERATURE 2.0 VDD1 = VDD2 = 5 V VIN+ = VIN- = 0 V 2.0 Input Offset Voltage VOS (mV) Input Offset Voltage VOS (mV) 3.0 INPUT OFFSET VOLTAGE vs. SUPPLY VOLTAGE 1.0 0.0 −1.0 −2.0 −3.0 −50 −25 0 25 50 75 100 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 4.5 125 Ambient Temperature TA (°C) −25 0 25 50 75 100 VIN+ = −200 mV to +200 mV, VIN- = 0 V 8.0 7.8 4.5 125 4.75 5 5.25 Ambient Temperature TA (°C) Supply Voltage VDD1, VDD2 (V) NON-LINEARITY vs. AMBIENT TEMPERATURE NON-LINEARITY vs. SUPPLY VOLTAGE 0.35 0.35 0.25 0.20 0.15 0.10 0.05 5.5 VIN+ = −200 mV to +200 mV, VIN- = 0 V 0.30 Non-linearity NL200 (%) VDD1 = VDD2 = 5 V VIN+ = −200 mV to +200 mV, VIN- = 0 V 0.30 Non-linearity NL200 (%) 5.5 7.9 7.9 0.00 −50 5.25 8.1 Gain G (V/V) Gain G (V/V) 8.0 7.8 −50 5 GAIN vs. SUPPLY VOLTAGE 8.2 VDD1 = VDD2 = 5 V VIN+ = −200 mV to +200 mV, VIN- = 0 V 8.1 4.75 Supply Voltage VDD1, VDD2 (V) GAIN vs. AMBIENT TEMPERATURE 8.2 VIN+ = VIN- = 0 V 1.5 0.25 0.20 0.15 0.10 0.05 −25 0 25 50 75 100 125 Ambient Temperature TA (°C) 0.00 4.5 4.75 5 5.25 5.5 Supply Voltage VDD1, VDD2 (V) Remark The graphs indicate nominal characteristics. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 10 of 18 PS8551AL4 Chapter Title OUTPUT VOLTAGE vs. INPUT VOLTAGE SUPPLY CURRENT vs. INPUT VOLTAGE 4 16 14 Supply Current IDD (mA) 3.5 Output Voltage VO (V) VOUT− 3 2.5 2 VOUT+ 1.5 0 8 4 0.2 0 −0.4 0.4 VDD1 = VDD2 = 5 V −0.2 0 0.2 Input Voltage VIN (V) INPUT CURRENT vs. INPUT VOLTAGE GAIN vs. FREQUENCY 2 0 −1 Gain GV (dB) 1 0 −1 −3 −0.4 0.4 1 VDD1 = VDD2 = 5 V VIN- = 0 V −2 −3 −4 −5 −6 VDD1 = VDD2 = 5 V, −7 VIN- = 0 V −8 VIN+ = 200 mVp-p sine wave 10 100 1 000 10 000 100 000 −2 −0.2 0 0.2 0.4 Input Voltage VIN+ (V) FREQUENCY vs. SUPPLY VOLTAGE 120 100 100 Frequency fC−3 dB (Hz) 120 80 60 40 20 VDD1 = VDD2 = 5 V, VIN- = 0 V VIN+ = 200 mVp-p sine wave 0 −50 −25 0 25 50 75 1 000 000 Frequency f (Hz) FREQUENCY vs. AMBIENT TEMPERATURE Frequency fC−3 dB (Hz) IDD2 6 Input Voltage VIN+ (V) 3 Input Current IIN+ (μA) −0.2 10 2 VDD1 = VDD2 = 5 V 1 −0.4 IDD1 12 100 125 Ambient Temperature TA (°C) 80 60 40 20 VDD1 = VDD2 = 5 V, VIN- = 0 V VIN+ = 200 mVp-p sine wave 0 4.5 4.75 5 5.25 5.5 Supply Voltage VDD1, VDD2 (V) Remark The graphs indicate nominal characteristics. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 11 of 18 PS8551AL4 Chapter Title SIGNAL DELAY TIME vs. AMBIENT TEMPERATURE Signal Delay Time PD (μs) 7 6 tPD90 5 tPD50 4 tf 3 tr tPD10 2 1 VDD1 = VDD2 = 5 V, VIN- = 0 V VIN+ = 0 to 150 mVstep 0 −50 −25 0 25 50 75 100 125 Ambient Temperature TA (°C) Remark The graphs indicate nominal characteristics. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 12 of 18 PS8551AL4 Chapter Title TAPING SPECIFICATIONS (UNIT: mm) 4.65 MAX. 10.55±0.1 7.5±0.1 1.5 +0.1 –0 16.0±0.3 2.0±0.1 4.0±0.1 1.75±0.1 Outline and Dimensions (Tape) 4.2±0.1 9.95±0.1 1.55±0.1 12.0±0.1 0.3±0.05 Tape Direction PS8551AL4-E3 Outline and Dimensions (Reel) 2.0±0.5 21.0±0.8 100±1.0 R 1.0 330±2.0 2.0±0.5 13.0±0.2 17.5±1.0 21.5±1.0 Packing: 1 000 pcs/reel R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 13 of 18 PS8551AL4 Chapter Title RECOMMENDED MOUNT PAD DIMENSIONS (UNIT: mm) B C D A Part Number Lead Bending PS8551AL4 lead bending type (Gull-wing) for surface mount R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 A B C D 9.0 2.54 1.7 2.0 Page 14 of 18 PS8551AL4 Chapter Title NOTES ON HANDLING 1. Recommended soldering conditions (1) Infrared reflow soldering • Peak reflow temperature 260°C or below (package surface temperature) • Time of peak reflow temperature 10 seconds or less • Time of temperature higher than 220°C 60 seconds or less • Time to preheat temperature from 120 to 180°C 120±30 s • Number of reflows Three • Flux Rosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt% is recommended.) Package Surface Temperature T (°C) Recommended Temperature Profile of Infrared Reflow (heating) to 10 s 260°C MAX. 220°C to 60 s 180°C 120°C 120±30 s (preheating) Time (s) (2) Wave soldering • Temperature 260°C or below (molten solder temperature) • Time 10 seconds or less • Preheating conditions 120°C or below (package surface temperature) • Number of times One (Allowed to be dipped in solder including plastic mold portion.) • Flux Rosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt% is recommended.) (3) Soldering by Soldering Iron • Peak Temperature (lead part temperature) 350°C or below • Time (each pins) 3 seconds or less • Flux Rosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt% is recommended.) (a) Soldering of leads should be made at the point 1.5 to 2.0 mm from the root of the lead R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 15 of 18 PS8551AL4 Chapter Title (4) Cautions • Fluxes Avoid removing the residual flux with freon-based and chlorine-based cleaning solvent. 2. Cautions regarding noise Be aware that when voltage is applied suddenly between the photocoupler’s input and output at startup, the output transistor may enter the on state, even if the voltage is within the absolute maximum ratings. USAGE CAUTIONS 1. This product is weak for static electricity by designed with high-speed integrated circuit so protect against static electricity when handling. 2. Board designing (1) By-pass capacitor of more than 0.1 μF is used between VCC and GND near device. Also, ensure that the distance between the leads of the photocoupler and capacitor is no more than 10 mm. (2) Keep the pattern connected the input (VIN+, VIN-) and the output (VOUT+, VOUT-), respectively, as short as possible. (3) Do not connect any routing to the portion of the frame exposed between the pins on the package of the photocoupler. If connected, it will affect the photocoupler's internal voltage and the photocoupler will not operate normally. (4) Because the maximum frequency of the signal input to the photocoupler must be lower than the allowable frequency band, be sure to connect an anti-aliasing filter (an RC filter with R = 68 Ω and C = 0.01 μF, for example). (5) The signals output from the PS8551A include noise elements such as chopping noise and quantization noise generated internally. Therefore, be sure to restrict the output frequency to the required bandwidth by adding a low-pass filter function (an RC filter with R =10 kΩ and C = 150 pF, for example) to the operational amplifier (post amplifier) in the next stage to the PS8551A. (6) When the primary power supply (VDD1) is off and only the secondary power supply (VDD2) is being applied (VDD1 = 0 V and VDD2 = 5 V), VOUT+ outputs a low level, and VOUT− outputs a high level (VOUT+ = 1.3 V TYP., VOUT– = 3.8 V TYP.), regardless of the input voltages (VIN+ and VIN−). (7) The output level of VOUT+ and VOUT− might be unstable for several seconds immediately after the secondary power supply (VDD2) is applied while the primary power supply (VDD1) is being applied. 3. Avoid storage at a high temperature and high humidity. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 16 of 18 PS8551AL4 Chapter Title SPECIFICATION OF VDE MARKS LICENSE DOCUMENT Parameter Symbol Climatic test class (IEC 60068-1/DIN EN 60068-1) Spec. Unit 40/105/21 Dielectric strength maximum operating isolation voltage Test voltage (partial discharge test, procedure a for type test and random test) Upr = 1.5 × UIORM, Pd < 5 pC Test voltage (partial discharge test, procedure b for all devices) UIORM Upr 1 130 1 695 Vpeak Vpeak Upr 2 119 Vpeak UTR 8 000 Vpeak Upr = 1.875 × UIORM, Pd < 5 pC Highest permissible overvoltage Degree of pollution (DIN EN 60664-1 VDE0110 Part 1) Comparative tracking index (IEC 60112/DIN EN 60112 (VDE 0303 Part 11)) 2 CTI Material group (DIN EN 60664-1 VDE0110 Part 1) 175 III a Storage temperature range Tstg –55 to +125 °C Operating temperature range TA –40 to +105 °C Ris MIN. Ris MIN. 10 11 10 Package temperature Tsi 175 °C Current (input current IF, Psi = 0) Isi 400 mA Power (output or total power dissipation) Psi 700 mW Ris MIN. 10 Isolation resistance, minimum value VIO = 500 V dc at TA = 25°C VIO = 500 V dc at TA MAX. at least 100°C 12 Ω Ω Safety maximum ratings (maximum permissible in case of fault, see thermal derating curve) Isolation resistance VIO = 500 V dc at TA = Tsi R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 9 Ω Page 17 of 18 PS8551AL4 Caution Chapter Title GaAs Products This product uses gallium arsenide (GaAs). GaAs vapor and powder are hazardous to human health if inhaled or ingested, so please observe the following points. • Follow related laws and ordinances when disposing of the product. If there are no applicable laws and/or ordinances, dispose of the product as recommended below. 1. Commission a disposal company able to (with a license to) collect, transport and dispose of materials that contain arsenic and other such industrial waste materials. 2. Exclude the product from general industrial waste and household garbage, and ensure that the product is controlled (as industrial waste subject to special control) up until final disposal. • Do not burn, destroy, cut, crush, or chemically dissolve the product. • Do not lick the product or in any way allow it to enter the mouth. R08DS0123EJ0100 Rev.1.00 Jun 27, 2014 Page 18 of 18 Revision History PS8551AL4 Data Sheet Description Rev. Date 1.00 Jun 27, 2014 Page − Summary First edition issued All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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China 200333 Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Ku, Seoul, 135-920, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2014 Renesas Electronics Corporation. All rights reserved. Colophon 4.0