PX3511A, PX3511B
®
Data Sheet
February 26, 2007
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The PX3511A and PX3511B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with the
ISL6595 Digital Multi-Phase Buck PWM controller and
N-Channel MOSFETs form a complete core-voltage
regulator solution for advanced microprocessors.
The PX3511A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The PX3511B drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses.
An adaptive zero shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize the dead time. These
products add an overvoltage protection feature operational
before VCC exceeds its turn-on threshold, at which the
PHASE node is connected to the gate of the low side
MOSFET (LGATE). The output voltage of the converter is
then limited by the threshold of the low side MOSFET, which
provides some protection to the microprocessor if the upper
MOSFET(s) is shorted during initial start-up.
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
FN6462.0
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
PX3511A, PX3511B
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
PX3511ADAG (Note)
PX3511 ADAG
0 to +85
8 Ld SOIC (Pb-free)
M8.15
PX3511ADAG-R3 (Note)
PX3511 ADAG
0 to +85
8 Ld SOIC (Pb-free) Tape and Reel
M8.15
PX3511ADDG
11AD
0 to +85
10 Ld 3x3 DFN
L10.3x3
PX3511ADDG-RA
11AD
0 to +85
10 Ld 3x3 DFN Tape and Reel
L10.3x3
PX3511BDAG (Note)
PX351 BDAG
0 to +85
8 Ld SOIC (Pb-free)
M8.15
PX3511BDAG-R3 (Note)
PX3511 BDAG
0 to +85
8 Ld SOIC (Pb-free) Tape and Reel
M8.15
PX3511BDDG
11BD
0 to +85
10 Ld 3x3 DFN
L10.3x3
PX3511BDDG-RA
11BD
0 to +85
10 Ld 3x3 DFN Tape and Reel
L10.3x3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
PX3511ACR, PX3511BCR
(10 LD 3x3 DFN)
TOP VIEW
PX3511ACB, PX3511BCB
(8 LD SOIC)
TOP VIEW
UGATE
1
8
PHASE
BOOT
2
7
PVCC
PWM
3
6
VCC
4
GND
5
LGATE
CRD L
UGATE
1
10
BAT
PHASE
BOOT
USB
2
9
PVCC
ICDL
N/C
PPR
3
8
GND
N/C
PW
M
C HG
4
7
VCC
USBP
NTC orGND
OVP
5
6
IUSB
LGATE
or EN
Block Diagram
PX3511A AND PX3511B
UVCC
BOOT
VCC
UGATE
Pre-POR OVP
FEATURES
+5V
10K
POR/
PWM
SHOOTTHROUGH
PROTECTION
PHASE
(LVCC)
PVCC
UVCC = VCC FOR PX3511A
UVCC = PVCC FOR PX3511B
CONTROL
8K
LOGIC
LGATE
GND
PAD
2
FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OF
THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.
FN6462.0
February 26, 2007
Typical Application - 4 Channel Converter Using ISL6595 and PX3511A Gate Drivers
+12V
PX3511
+5V
1 UGATE
PHASE 8
2 BOOT
PVCC 7
3 PWM
VCC 6
4 GND
LGATE 5
3
+3.3V
VDD
V12_SEN
PHASE 8
OUT1
2 BOOT
PVCC 7
VID4
OUT2
3 PWM
VCC 6
VID3
ISEN1
4 GND
LGATE 5
VID2
OUT3
VID1
OUT4
VID0
ISEN2
VID5
OUT5
LL0
OUT6
LL1
ISEN3
OUTEN
OUT7
OUT8
TO µP
VCC_PWRGD
Vout
PX3511
1 UGATE
PHASE 8
2 BOOT
PVCC 7
3 PWM
VCC 6
4 GND
LGATE 5
RTN
ISEN4
OUT9
RESET_N
OUT10
PX3511
ISEN5
1 UGATE
PHASE 8
PVCC 7
FAULT
FAULT1
OUT11
2 BOOT
OUTPUTS
FAULT2
OUT12
3 PWM
VCC 6
ISEN6
4 GND
LGATE 5
FN6462.0
February 26, 2007
I2C I/F
BUS
SDA
TEMP_SEN
SCL
CAL_CUR_EN
RTHERM
SADDR
CAL_CUR_SEN
VSENP
VSENN
PX3511A, PX3511B
1 UGATE
ISL6595
FROM µP
PX3511
GND
PX3511A, PX3511B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (
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