R1EX24004ATAS0I#S0

R1LV0108E Series 1Mb Advanced LPSRAM (128k word x 8bit) R10DS0271EJ0200 Rev.2.00 2019.10.29 Description The R1LV0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LV0108E Series has realized higher density, higher performance and low power consumption. The R1LV0108E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 32-pin SOP, 32-pin TSOP and 32-pin sTSOP. Features         Single 2.7V~3.6V power supply Small stand-by current: 0.6µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1# and CS2 Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Orderable part name Access time Temperature range R1LV0108ESN-5SI#B* R1LV0108ESN-5SI#S* R1LV0108ESA-5SI#B* R1LV0108ESA-5SI#S* R1LV0108ESF-5SI#B* R1LV0108ESF-5SI#S* 55 ns -40 ~ +85°C Package Shipping container 525-mil 32-pin plastic SOP Tube (Magazine) 8mm×13.4mm 32-pin plastic sTSOP Tray 8mm×20mm 32-pin plastic TSOP Embossed tape Embossed tape Tray Embossed tape Note 1. ＊= Revision code for Assembly site change, etc. (＊= 0, 1, etc.) R10DS0271EJ0200 Rev.2.00 2019.10.29 Page 1 of 11 R1LV0108E Series Pin Arrangement R10DS0271EJ0200 Rev.2.00 2019.10.29 NC 1 32 Vcc A16 2 31 A15 A14 3 30 CS2 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE# A2 10 23 A10 A1 11 22 CS1# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 32-pin SOP A11 1 32 OE# A9 2 31 A10 A8 3 30 CS1# A13 4 29 DQ7 WE# 5 28 DQ6 CS2 6 27 DQ5 A15 7 26 DQ4 Vcc 8 25 DQ3 NC 9 24 GND A16 10 23 DQ2 A14 11 22 DQ1 A12 12 21 DQ0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 A11 1 32 OE# A9 2 31 A10 A8 3 30 CS1# A13 4 29 DQ7 WE# 5 28 DQ6 CS2 6 27 DQ5 A15 7 26 DQ4 Vcc 8 25 DQ3 NC 9 24 GND A16 10 23 DQ2 A14 11 22 DQ1 A12 12 21 DQ0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 32-pin sTSOP 32-pin TSOP Page 2 of 11 R1LV0108E Series Pin Description Pin name Vcc Vss (GND) A0 to A16 DQ0 to DQ7 CS1# CS2 WE# OE# NC Function Power supply Ground Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Non connection Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 128k-word x8-bit A16 DQ0 DQ DQ1 BUFFER SENSE / WRITE AMPLIFIER DQ7 COLUMN DECODER CLOCK GENERATOR WE# Vcc Vss CS1# CS2 OE# R10DS0271EJ0200 Rev.2.00 2019.10.29 Page 3 of 11 R1LV0108E Series Operation Table CS1# CS2 WE# OE# DQ0~7 Operation X L X X High-Z Stand-by H X X X High-Z Stand-by L H L X Din Write L H H L Dout Read H H High-Z Output disable L Note 1. H H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr Tstg Tbias Value -0.3 to +4.6 -0.3*1 to Vcc+0.3*2 0.7 -40 to +85 -65 to 150 -40 to +85 unit V V W °C °C °C 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +4.6V. R10DS0271EJ0200 Rev.2.00 2019.10.29 Page 4 of 11 R1LV0108E Series DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 2.7 3.0 3.6 V Supply voltage Vss 0 0 0 V Input high voltage VIH 2.0 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.6 V Ambient temperature range Ta -40 - +85 °C Note Note 1 1. –3.0V for pulse ≤ 30ns (full width at half maximum) DC Characteristics Parameter Input leakage current Output leakage current Average operating current Symbol | ILI | Min. - Typ. - Max. 1 Unit A | ILO | - - 1 A ICC1 - 15 25 mA ICC2 - 2 5 mA ISB - - 0.33 mA - 0.6*1 2 A - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C VOH 2.4 - - V IOH = -0.5mA VOH2 Vcc - 0.5 - - V IOH = -0.05mA VOL - - 0.4 V IOL = 2mA Standby current Standby current Test conditions Vin = Vss to Vcc CS1# =VIH or CS2 =VIL or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA, CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA, CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V “CS2 =VIL“ or “CS2 = VIH and CS1# =VIH”, Others = Vss to Vcc Vin = Vss to Vcc, ~+25°C (1) CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V ISB1 Output high voltage Output low voltage Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in Input / output capacitance C I/O Note 1. This parameter is sampled and not 100% tested. R10DS0271EJ0200 Rev.2.00 2019.10.29 Typ. - Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 1 1 Page 5 of 11 R1LV0108E Series AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)     Input pulse levels: VIL = 0.4V, VIH = 2.2V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ CL = 30 pF R10DS0271EJ0200 Rev.2.00 2019.10.29 Page 6 of 11 R1LV0108E Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol Min. Max. Unit Note tRC tAA tCHZ1 tCHZ2 tOHZ 55 5 5 5 5 0 0 0 55 55 55 30 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 Symbol Min. Max. Unit Note tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ 55 50 50 45 0 0 25 0 5 0 0 20 20 ns ns ns ns ns ns ns ns ns ns ns tACS1 tACS2 tOE tOH tCLZ1 tCLZ2 tOLZ Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note 5 4 6 7 2 1,2 1,2 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#. A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low. A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode. R10DS0271EJ0200 Rev.2.00 2019.10.29 Page 7 of 11 R1LV0108E Series Timing Waveforms Read Cycle tRC A0~16 tOH tAA tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 WE# tCHZ2 VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~7 R10DS0271EJ0200 Rev.2.00 2019.10.29 Valid Data Page 8 of 11 R1LV0108E Series Write Cycle (1) (WE# CLOCK) tWC A0~16 tCW CS1# tCW CS2 tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~7 tOW Valid Data tDW R10DS0271EJ0200 Rev.2.00 2019.10.29 tDH Page 9 of 11 R1LV0108E Series Write Cycle (2) (CS1#, CS2 CLOCK) tWC A0~16 tAW tAS tCW tWR tAS tCW tWR CS1# CS2 tWP WE# OE# VIH OE# = “H” level tDW DQ0~7 R10DS0271EJ0200 Rev.2.00 2019.10.29 tDH Valid Data Page 10 of 11 R1LV0108E Series Low Vcc Data Retention Characteristics Parameter Symbol VCC for data retention Min. VDR Typ. Max. Test conditions*2 Unit 2.0 - 3.6 V Vin ≥ 0V, (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V - 0.6*1 2 A ~+25°C Vcc=3.0V, Vin ≥ 0V, Data retention current - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C ICCDR (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ns See retention waveform. Operation recovery time tR 5 ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#, DQ) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms (1) CS1# Controlled Vcc tCDR 2.7V 2.7V tR VDR 2.2V 2.2V CS1# ≥ Vcc - 0.2V CS1# (2) CS2 Controlled Vcc tCDR CS2 2.7V 2.7V tR VDR 0.2V 0.2V 0V ≤ CS2 ≤ 0.2V R10DS0271EJ0200 Rev.2.00 2019.10.29 Page 11 of 11 Revision History Rev. 1.00 2.00 Date 2017.1.27 2019.10.29 R1LV0108E Series Data Sheet Page p.1 Description Summary First Edition issued Revised orderable part name information. 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