R1EX24008ASAS0I#U0

RMLV0408E Series 4Mb Advanced LPSRAM (512-kword × 8-bit) R10DS0206EJ0300 Rev.3.00 2021.8.18 Description The RMLV0408E Series is a family of 4-Mbit static RAMs organized 524,288-word × 8-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0408E Series has realized higher density, higher performance and low power consumption. The RMLV0408E Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP, 32-pin TSOP (II) or 32-pin sTSOP. Features • Single 3V supply: 2.7V to 3.6V • Access time: 45ns (max.) • Current consumption: ── Standby: 0.3µA (typ.) • Equal access and cycle times • Common data input and output ── Three state output • Directly TTL compatible ── All inputs and outputs • Battery backup operation Orderable part number information Orderable part number Access time Temperature range Package Tray RMLV0408EGSA-4S2#AA* 8mm×13.4mm 32-pin plastic sTSOP RMLV0408EGSA-4S2#KA* Embossed tape RMLV0408EGSB-4S2#AA* Tray 45 ns -40 ~ +85°C 400-mil 32pin plastic TSOP (II) Embossed tape RMLV0408EGSB-4S2#HA* RMLV0408EGSP-4S2#CA* RMLV0408EGSP-4S2#HA* Note Shipping container 1. Tube 525-mil 32-pin plastic SOP Embossed tape * = Revision code for Assembly site change, etc. (* = 0, 1, etc.) R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 1 of 10 RMLV0408E Series Pin Arrangement 32-pin SOP 32-pin TSOP (II) 32-pin sTSOP A18 1 32 Vcc A11 1 32 OE# A16 2 31 A15 A9 2 31 A10 A14 3 30 A17 A8 3 30 CS# A12 4 29 WE# A13 4 29 I/O7 A7 5 28 A13 WE# 5 28 I/O6 A6 6 27 A8 A18 6 27 I/O5 A5 7 26 A9 A15 7 26 I/O4 A4 8 25 A11 Vcc 8 25 I/O3 A3 9 24 OE# A17 9 24 Vss A2 10 23 A10 A16 10 23 I/O2 A1 11 22 CS# A14 11 22 I/O1 A0 12 21 I/O7 A12 12 21 I/O0 I/O0 13 20 I/O6 A7 13 20 A0 I/O1 14 19 I/O5 A6 14 19 A1 I/O2 15 18 I/O4 A5 15 18 A2 Vss 16 17 I/O3 A4 16 17 A3 (Top view) (Top view) Pin Description Pin name VCC VSS A0 to A18 I/O0 to I/O7 CS# WE# OE# Function Power supply Ground Address input Data input/output Chip select Write enable Output enable R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 2 of 10 RMLV0408E Series Block Diagram VCC A0 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 VSS Row Decoder I/O0 ・ ・ ・ ・ ・ Memory Matrix ・ ・ Column I/O 2,048 x 2,048 ・ ・ Column Decoder Input Data Control I/O7 A1 A2 A3 A14 A15 A16 A17 A18 ・ ・ CS# Timing Pulse Generator WE# Read/Write Control OE# Operation Table CS# WE# OE# I/O0 to I/O7 Operation H X X High-Z Standby L H L Dout Read L L X Din Write L H H High-Z Output disable Note 2. H: VIH L:VIL X: VIH or VIL Absolute Maximum Ratings Parameter Symbol Power supply voltage relative to VSS VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 3. -3.0V for pulse ≤ 30ns (full width at half maximum) 4. Maximum voltage is +4.6V. R10DS0206EJ0300 Rev.3.00 2021.8.18 Value -0.5 to +4.6 -0.5*3 to VCC+0.3*4 0.7 -40 to +85 -65 to +150 -40 to +85 unit V V W °C °C °C Page 3 of 10 RMLV0408E Series DC Operating Conditions Parameter Symbol Supply voltage VCC VSS Input high voltage VIH Input low voltage VIL Ambient temperature range Ta Note 5. -3.0V for pulse ≤ 30ns (full width at half maximum) Min. 2.7 0 2.2 -0.3 -40 Typ. 3.0 0 ─ ─ ─ Max. 3.6 0 VCC+0.3 0.6 +85 Unit V V V V °C Note 5 DC Characteristics Parameter Input leakage current Output leakage current Operating current Symbol Min. Typ. Max. Unit | ILI | ─ ─ 1 µA | ILO | ─ ─ 1 µA ICC ─ ─ 10 mA ─ ─ 20 mA ─ ─ 25 mA ICC2 ─ ─ 2.5 mA ISB ─ 0.1*6 0.3 mA ─ 0.3*6 2 µA ~+25°C ─ ─ 3 µA ~+40°C ─ ─ 5 µA ~+70°C ─ ─ 7 µA ~+85°C VOH 2.4 ─ ─ V IOH = -1mA VOH2 VCC-0.2 ─ ─ V IOH = -0.1mA VOL ─ ─ 0.4 V IOL = 2.1mA VOL2 ─ ─ 0.2 V IOL = 0.1mA Average operating current ICC1 Standby current Standby current Test conditions Vin = VSS to VCC CS# = VIH or OE# =VIH or WE#= VIL, VI/O = VSS to VCC CS# =VIL, Others = VIH/VIL, II/O = 0mA Cycle = 55ns, duty = 100%, II/O = 0mA, CS# = VIL, Others = VIH/VIL Cycle = 45ns, duty = 100%, II/O = 0mA, CS# = VIL, Others = VIH/VIL Cycle = 1µs, duty = 100%, II/O = 0mA, CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V CS# =VIH, Others = VSS to VCC Vin = VSS to VCC, CS# ≥ VCC-0.2V ISB1 Output high voltage Output low voltage Note 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 7. This parameter is sampled and not 100% tested. R10DS0206EJ0300 Rev.3.00 2021.8.18 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 7 7 Page 4 of 10 RMLV0408E Series AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) 1.4V RL = 500 ohm I/O CL = 30 pF Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol Min. Max. Unit Note tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 45 ─ ─ ─ 10 10 5 0 0 ─ 45 45 22 ─ ─ ─ 18 18 ns ns ns ns ns ns ns ns ns 8,9 8,9 8,9,10 8,9,10 Symbol Min. Max. Unit Note Write Cycle Parameter Write cycle time tWC 45 ─ ns Address valid to write end tAW 35 ─ ns Chip select to write end tCW 35 ─ ns Write pulse width tWP 35 ─ ns 11 Address setup time to write start tAS 0 ─ ns Write recovery time from write end tWR 0 ─ ns Data to write time overlap tDW 25 ─ ns Data hold from write end tDH 0 ─ ns Output enable from write end tOW 5 ─ ns 8 Output disable to output in high-Z tOHZ 0 18 ns 8,10 Write to output in high-Z tWHZ 0 18 ns 8,10 Note 8. This parameter is sampled and not 100% tested. 9. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, and tOHZ max is less than tOLZ min, for any device. 10. tCHZ, tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 11. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active A write is performed during the overlap of a low CS#, a low WE# A write ends when any of CS#, WE# becomes inactive. R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 5 of 10 RMLV0408E Series Timing Waveforms Read Cycle tRC Valid address A0~18 tAA tACS CS# tCHZ *12,13,14 tCLZ *13,14 WE# VIH WE# = “H” level tOHZ *12,13,14 tOE OE# tOLZ I/O0~7 High impedance tOH *13,14 Valid Data Note 12. tCHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 13. This parameter is sampled and not 100% tested. 14. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 6 of 10 RMLV0408E Series Write Cycle (1) (WE# CLOCK, OE#=”H” while writing) tWC Valid address A0~18 tCW CS# tAW WE# tAS OE# tWHZ *16,17 tOHZ *16,17 I/O0~7 tWR tWP *15 *18 tDW tDH Valid Data Note 15. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active. A write is performed during the overlap of a low CS# and a low WE#. A write ends when any of CS# or WE# becomes inactive. 16. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 17. This parameter is sampled and not 100% tested. 18. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 7 of 10 RMLV0408E Series Write Cycle (2) (WE# CLOCK, OE# Low Fixed) tWC Valid address A0~18 tCW CS# tAW WE# OE# OE# = “L” level tWP tWR *19 tAS VIL tWHZ I/O0~7 *22 *20,21 tOW Valid Data tDW *22 tDH Note 19. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active. A write is performed during the overlap of a low CS# and a low WE#. A write ends when any of CS# or WE# becomes inactive. 20. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 21. This parameter is sampled and not 100% tested. 22. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 8 of 10 RMLV0408E Series Write Cycle (3) (CS# CLOCK) tWC Valid address A0~18 tAW tAS tWR tCW CS# tWP *23 WE# OE# OE# = “H” level VIH I/O0~7 tDW tDH Valid Data Note 23. tWP is the interval between write start and write end. A write starts when both of CS# and WE# become active. A write is performed during the overlap of a low CS# and a low WE#. A write ends when any of CS# or WE# becomes inactive. R10DS0206EJ0300 Rev.3.00 2021.8.18 Page 9 of 10 RMLV0408E Series Low VCC Data Retention Characteristics Parameter Symbol Min. Typ. Max. Unit VCC for data retention VDR 1.5 ─ ─ V Vin ≥ 0V, CS# ≥ VCC-0.2V ─ 0.3*24 2 µA ~+25°C ─ ─ 3 µA ~+40°C ─ ─ 5 µA ~+70°C ─ ─ 7 µA ~+85°C Data retention current Test conditions*25 ICCDR VCC=3.0V, Vin ≥ 0V, CS# ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 24. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 25. CS# controls address buffer, WE# buffer, OE# buffer, and I/O buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high-impedance state. Low Vcc Data Retention Timing Waveforms (CS# controlled) CS# Controlled VCC tCDR 2.2V CS# R10DS0206EJ0300 Rev.3.00 2021.8.18 2.7V 2.7V VDR tR 2.2V CS# ≥ VCC - 0.2V Page 10 of 10 Revision History RMLV0408E Series Data Sheet Rev. 1.00 2.00 Date 2014.2.27 2016.1.12 Page ─ 1 2.01 3.00 2020.2.20 2021.8.18 Last page 1,4,10 Description Summary First edition issued Changed section from “Part Name Information” to “Orderable part number information” Updated the Notice to the latest version Changed the typical value of ISB1 and ICCDR from 0.4µA to 0.3µA. Revised orderable part number information All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2021 Renesas Electronics Corporation. All rights reserved.