R1EX25008ATA00I#S0

RMLV0414E Series 4Mb Advanced LPSRAM (256-kword × 16-bit) R10DS0216EJ0300 Rev.3.00 2021.8.18 Description The RMLV0414E Series is a family of 4-Mbit static RAMs organized 262,144-word × 16-bit, fabricated by Renesas’s high-performance Advanced LPSRAM technologies. The RMLV0414E Series has realized higher density, higher performance and low power consumption. The RMLV0414E Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 44-pin TSOP (II). Features • Single 3V supply: 2.7V to 3.6V • Access time: 45ns (max.) • Current consumption: ── Standby: 0.3µA (typ.) • Equal access and cycle times • Common data input and output ── Three state output • Directly TTL compatible ── All inputs and outputs • Battery backup operation Orderable part number information Part name Access time Temperature range Package Tray RMLV0414EGSB-4S2#AA* 45 ns -40 ~ +85°C 400-mil 44pin plastic TSOP (II) RMLV0414EGSB-4S2#HA* Note 1. Shipping container Embossed tape * = Revision code for Assembly site change, etc. (* = 0, 1, etc.) R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 1 of 12 RMLV0414E Series Pin Arrangement 44pin TSOP (II) A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CS# 6 39 LB# I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 Vcc 11 34 Vss Vss 12 33 Vcc I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE# 17 28 NC A17 18 27 A8 A16 19 26 A9 A15 20 25 A10 A14 21 24 A11 A13 22 23 A12 (Top view) Pin Description Pin name VCC VSS A0 to A17 I/O0 to I/O15 CS# OE# WE# LB# UB# NC Function Power supply Ground Address input Data input/output Chip select Output enable Write enable Lower byte select Upper byte select No connection R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 2 of 12 RMLV0414E Series Block Diagram VCC A1 A2 A3 A4 A6 A8 A13 A14 A15 A16 A17 VSS Row Decoder I/O0 ・ ・ ・ ・ ・ Memory Matrix ・ ・ Column I/O 2,048 x 2,048 ・ ・ Column Decoder Input Data Control I/O15 A0 A5 A7 A9 A10 A11 A12 ・ ・ CS# LB# UB# WE# Control logic OE# Operation Table CS# WE# OE# H X X X X X L H L L H L L H L L L X L L X LB# I/O0 to I/O7 I/O8 to I/O15 Operation X X High-Z High-Z Standby H H High-Z High-Z Standby L L Dout Dout Read H L Dout High-Z Lower byte read L H High-Z Dout Upper byte read L L Din Din Write H L Din High-Z Lower byte write UB# L L X L H High-Z Din Upper byte write L H H X X High-Z High-Z Output disable Note 2. H: VIH L:VIL X: VIH or VIL R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 3 of 12 RMLV0414E Series Absolute Maximum Ratings Parameter Symbol Power supply voltage relative to VSS VCC Terminal voltage on any pin relative to VSS VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 3. -3.0V for pulse ≤ 30ns (full width at half maximum) 4. Maximum voltage is +4.6V. Value -0.5 to +4.6 -0.5*3 to VCC+0.3*4 0.7 -40 to +85 -65 to +150 -40 to +85 unit V V W °C °C °C DC Operating Conditions Parameter Symbol VCC VSS Input high voltage VIH Input low voltage VIL Ambient temperature range Ta Note 5. -3.0V for pulse ≤ 30ns (full width at half maximum) Min. 2.7 0 2.2 -0.3 -40 Supply voltage Typ. 3.0 0 ─ ─ ─ Max. 3.6 0 VCC+0.3 0.6 +85 Unit V V V V °C Note 5 DC Characteristics Parameter Input leakage current Symbol Min. Typ. Max. Unit | ILI | ─ ─ 1 µA Vin = VSS to VCC | ILO | ─ ─ 1 µA CS# = VIH or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC ICC ─ ─ 10 mA Output leakage current Operating current Average operating current ─ 20 mA ─ ─ 25 mA ICC2 ─ ─ 2.5 mA ISB ─ 0.1*6 0.3 mA ─ 0.3 2 µA ~+25°C ─ ─ 3 µA ~+40°C ─ ─ 5 µA ~+70°C ─ ─ 7 µA ~+85°C VOH 2.4 ─ ─ V IOH = -1mA VOH2 VCC-0.2 ─ ─ V IOH = -0.1mA VOL ─ ─ 0.4 V IOL = 2mA VOL2 ─ ─ 0.2 V IOL = 0.1mA Standby current ISB1 Output high voltage Output low voltage Note CS# = VIL, Others = VIH/VIL, II/O = 0mA Cycle = 55ns, duty =100%, II/O = 0mA, CS# = VIL, Others = VIH/VIL Cycle = 45ns, duty =100%, II/O = 0mA, CS# = VIL, Others = VIH/VIL Cycle =1µs, duty =100%, II/O = 0mA CS# ≤ 0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V ─ ICC1 Standby current Test conditions *6 CS# = VIH, Others = VSS to VCC Vin = VSS to VCC, (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V 6. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 7. This parameter is sampled and not 100% tested. R10DS0216EJ0300 Rev.3.00 2021.8.18 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 7 7 Page 4 of 12 RMLV0414E Series AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) 1.4V RL = 500 ohm I/O CL = 30 pF Read Cycle Parameter Symbol Min. Max. Unit Note Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time tRC tAA tACS tOE tOH tBA 45 ─ ─ ─ 10 ─ ─ 45 45 22 ─ 45 ns ns ns ns ns ns Chip select to output in low-Z tCLZ 10 ─ ns 8,9 LB#, UB# enable to low-Z Output enable to output in low-Z tBLZ tOLZ 5 5 ─ ─ ns ns 8,9 8,9 Chip deselect to output in high-Z tCHZ 0 18 ns 8,9,10 LB#, UB# disable to high-Z tBHZ 0 18 ns 8,9,10 Output disable to output in high-Z tOHZ 0 18 ns 8,9,10 Note 8. This parameter is sampled and not 100% tested. 9. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. 10. tCHZ, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 5 of 12 RMLV0414E Series Write Cycle Parameter Symbol Min. Max. Unit Note Write cycle time tWC 45 ─ ns Address valid to write end tAW 35 ─ ns Chip select to write end tCW 35 ─ ns Write pulse width tWP 35 ─ ns 11 LB#,UB# valid to write end tBW 35 ─ ns Address setup time to write start tAS 0 ─ ns Write recovery time from write end tWR 0 ─ ns Data to write time overlap tDW 25 ─ ns Data hold from write end tDH 0 ─ ns Output enable from write end tOW 5 ─ ns 12 Output disable to output in high-Z tOHZ 0 18 ns 12,13 Write to output in high-Z tWHZ 0 18 ns 12,13 Note 11. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. 12. This parameter is sampled and not 100% tested. 13. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 6 of 12 RMLV0414E Series Timing Waveforms Read Cycle tRC Valid address A0~17 tAA tACS CS# tCHZ*14,15,16 tCLZ *15,16 tBA LB#,UB# tBLZ *15,16 WE# tBHZ*14,15,16 VIH WE# = “H” level tOHZ *14,15,16 tOE OE# tOLZ I/O0~15 High impedance tOH *15,16 Valid Data Note 14. tCHZ, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 15. This parameter is sampled and not 100% tested. 16. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 7 of 12 RMLV0414E Series Write Cycle (1) (WE# CLOCK, OE#=”H” while writing) tWC Valid address A0~17 tCW CS# tBW LB#,UB# tAW WE# tAS OE# tWHZ *18,19 tOHZ *18,19 I/O0~15 tWR tWP *17 *20 tDW tDH Valid Data Note 17. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. 18. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 19. This parameter is sampled and not 100% tested. 20. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 8 of 12 RMLV0414E Series Write Cycle (2) (WE# CLOCK, OE# Low Fixed) tWC Valid address A0~17 tCW CS# tBW LB#,UB# tAW WE# OE# OE# = “L” level tWR tWP *21 tAS VIL tWHZ *22,23 I/O0~15 *24 tOW Valid Data tDW *24 tDH Note 21. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. 22. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O levels. 23. This parameter is sampled and not 100% tested. 24. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 9 of 12 RMLV0414E Series Write Cycle (3) (CS# CLOCK) tWC Valid address A0~17 tAW tAS tWR tCW CS# tBW LB#,UB# tWP *25 WE# OE# OE# = “H” level VIH I/O0~15 tDW tDH Valid Data Note 25. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 10 of 12 RMLV0414E Series Write Cycle (4) (LB#,UB# CLOCK) tWC Valid address A0~17 tAW tCW CS# tAS tWR tBW LB#,UB# tWP *26 WE# OE# OE# = “H” level VIH I/O0~15 tDW tDH Valid Data Note 26. tWP is the interval between write start and write end. A write starts when all of (CS#), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write ends when any of (CS#), (WE#) or (one or both of LB# and UB#) becomes inactive. R10DS0216EJ0300 Rev.3.00 2021.8.18 Page 11 of 12 RMLV0414E Series Low VCC Data Retention Characteristics Parameter Symbol VCC for data retention Data retention current VDR ICCDR Min. Typ. Max. Unit Test conditions*28 1.5 ─ ─ V Vin ≥ 0V, (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V ─ 0.3*27 2 µA ~+25°C ─ ─ 3 µA ~+40°C ─ ─ 5 µA ~+70°C ─ ─ 7 µA ~+85°C VCC=3.0V, Vin ≥ 0V, (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 27. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 28. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and I/O buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, LB#,UB#, I/O) can be in the high-impedance state. Low Vcc Data Retention Timing Waveforms (CS# controlled) CS# Controlled VCC tCDR 2.7V 2.7V tR VDR 2.2V 2.2V CS# ≥ VCC - 0.2V CS# Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled) LB#,UB# Controlled VCC tCDR 2.2V LB#,UB# R10DS0216EJ0300 Rev.3.00 2021.8.18 2.7V 2.7V VDR tR 2.2V LB#,UB# ≥ VCC - 0.2V Page 12 of 12 Revision History RMLV0414E Series Data Sheet Rev. 1.00 2.00 Date 2014.2.27 2016.1.12 Page ─ 1 2.01 3.00 2020.2.20 2021.8.18 Last page 1,4,12 Description Summary First edition issued Changed section from “Part Name Information” to “Orderable part number information” Updated the Notice to the latest version Changed the typical value of ISB1 and ICCDR from 0.4µA to 0.3µA. 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