R1LP0408DSP-5SI#S1

R1LP0408D Series 4Mb Advanced LPSRAM (512-kword × 8-bit) R10DS0274EJ0200 Rev.2.00 2019.10.29 Description The R1LP0408D Series is a family of 4-Mbit static RAMs organized 512-kword × 8-bit, fabricated by Renesas’s highperformance CMOS and TFT technologies. The R1LP0408D Series has realized higher density, higher performance and low power consumption. The R1LP0408D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP and 32-pin TSOP. Features  Single 5V supply: 4.5V to 5.5V  Access time: 55ns (max.)  Power dissipation: ── Standby: 4µW (typ.)  Equal access and cycle times  Common data input and output ── Three state output  Directly TTL compatible ── All inputs and outputs  Battery backup operation Ordering Information Orderable part name Access time Temperature range R1LP0408DSP-5SI#B* R1LP0408DSP-5SI#S* R1LP0408DSB-5SI#B* R1LP0408DSB-5SI#S* 55 ns Package Shipping container 525-mil 32-pin plastic SOP Tube (Magazine) 400-mil 32-pin plastic TSOP (II) Tray -40 ~ +85°C Embossed tape Embossed tape Note 1. ＊= Revision code for Assembly site change, etc. (＊= 0, 1, etc.) R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 1 of 11 R1LP0408D Series Pin Arrangement A18 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE# A2 10 23 A10 A1 11 22 CS# A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 Vss 16 17 I/O3 32-pin SOP 32-pin TSOP Pin Description Pin name Function Vcc Vss A0 to A18 I/O0 to I/O7 CS# Power supply Ground Address input Data input/output Chip select WE# OE# Write enable Output enable R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 2 of 11 R1LP0408D Series Block Diagram LSB A11 A9 A8 A13 A17 A15 A18 A16 A14 A12 A7 Vcc Vss Row Decoder ・ ・ ・ ・ ・ Memory Matrix 2,048 x 2,048 MSB I/O0 ・ ・ Input Data Control Column I/O ・ ・ Column Decoder I/O7 LSB A5 A4 A10 A0 A1 A2 A3 A6 MSB ・・ CS# Timing Pulse Generator WE# Read/Write Control OE# R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 3 of 11 R1LP0408D Series Operation Table WE# CS# OE# Mode Vcc current I/O0 to I/O7 Ref. cycle × H × Not selected ISB, ISB1 High-Z ─ H L H Output disable Icc High-Z ─ H L L Read Icc Dout Read cycle L L H Write Icc Din Write cycle (1) L Write Icc Din Write cycle (2) L Note 1. L H: VIH L:VIL ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5*1 to Vcc+0.3*2 0.7 -40 to +85 -65 to 150 -40 to +85 unit V V W °C °C °C 1. -3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +7.0V. R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 4 of 11 R1LP0408D Series DC Operating Conditions Parameter Supply voltage Symbol Min. Typ. Max. Unit Vcc 4.5 5.0 5.5 V Vss 0 0 0 V Input high voltage VIH 2.2 ─ Vcc+0.3 V Input low voltage VIL -0.3 ─ 0.8 V Ambient temperature range Ta -40 ─ +85 °C Note Note 1 1. -3.0V for pulse ≤ 30ns (full width at half maximum) DC Characteristics Parameter Input leakage current Output leakage current Operating current Average operating current Standby current Symbol Min. Typ. Max. Unit | ILI | ─ ─ 1 A | ILO | ─ ─ 1 A Icc ─ 5*1 10 mA ICC1 ─ 15*1 25 mA ICC2 ─ 3*1 5 mA ISB ─ 0.1*1 0.5 mA ─ 0.8*1 2.5 A ~+25°C ─ 1*2 3 A ~+40°C ─ ─ 8 A ~+70°C ─ ─ 10 A ~+85°C VOH 2.4 ─ ─ V IOH = -1mA VOH2 Vcc-0.5 ─ ─ V IOH = -0.1mA VOL ─ ─ 0.4 V IOL = 2.1mA Standby current Test conditions Vin = Vss to Vcc CS# =VIH or OE# =VIH, VI/O =Vss to Vcc CS# =VIL, Others = VIH/VIL, II/O = 0mA Min. cycle, duty =100%, II/O = 0mA, CS# =VIL, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA, CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V CS# =VIH, Others = Vss to Vcc ISB1 Output high voltage Output low voltage Note Vin = Vss to Vcc, CS# ≥ Vcc-0.2V 1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta=25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 5.0V (Ta=40ºC), and not 100% tested. Capacitance (Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in ─ Input / output capacitance C I/O ─ Note 1. This parameter is sampled and not 100% tested. R10DS0274EJ0200 Rev.2.00 2019.10.29 Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 1 1 Page 5 of 11 R1LP0408D Series AC Characteristics Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = -40 ~ +85°C)     Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm I/O CL = 50 pF R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 6 of 11 R1LP0408D Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Output hold from address change Symbol Min. Max. Unit tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH 55 ─ ─ ─ 10 5 0 0 10 ─ 55 55 25 ─ ─ 20 20 ─ ns ns ns ns ns ns ns ns ns Symbol Min. Max. Unit tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW tOHZ 55 50 0 50 40 0 0 25 0 5 0 ─ ─ ─ ─ ─ ─ 20 ─ ─ ─ 20 ns ns ns ns ns ns ns ns ns ns ns Note 2 2 1,2 1,2 Write Cycle Parameter Write cycle time Chip select to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Note Note 4 5 3,12 6 1,2,7 2 1,2,7 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS# going low to end of write. 5. tAS is measured the address valid to the beginning of write. 6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 7 of 11 R1LP0408D Series Timing Waveforms Read Cycle (WE# = VIH ) tRC Valid address Address tAA tACS CS# tCLZ tCHZ tOE tOLZ OE# tOHZ Dout High impedance Valid Data tOH R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 8 of 11 R1LP0408D Series Write Cycle (1) (OE# CLOCK) tWC Valid address Address tWR tAW OE# tCW CS# tAS *8 tWP WE# tOHZ Dout High impedance tDW Din R10DS0274EJ0200 Rev.2.00 2019.10.29 tDH Valid Data Page 9 of 11 R1LP0408D Series Write Cycle (2) (OE# Low Fixed) tWC Valid address Address tWR tCW CS# *8 tAW tWP WE# tOH tAS tWHZ tOW *9 Dout *10 High impedance tDW tDH *11 Din R10DS0274EJ0200 Rev.2.00 2019.10.29 Valid Data Page 10 of 11 R1LP0408D Series Low Vcc Data Retention Characteristics Test conditions*3 Parameter Symbol Min. Typ. Max. Unit VCC for data retention VDR 2.0 ─ 5.5 V Vin ≥ 0V, CS# ≥ Vcc-0.2V ─ 0.8*1 2.5 A ~+25°C ─ 1*2 3 A ~+40°C ─ ─ 8 A ~+70°C ─ ─ 10 A ~+85°C Data retention current ICCDR Vcc=3.0V, Vin ≥ 0V, CS# ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. 3. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms CS# Controlled Vcc tCDR 2.2V 4.5V 4.5V VDR tR 2.2V CS# ≥ Vcc - 0.2V CS# R10DS0274EJ0200 Rev.2.00 2019.10.29 Page 11 of 11 Revision History Rev. 1.00 2.00 Date 2017.1.27 2019.10.29 R1LP0408D Series Data Sheet Page ─ p.1 Description Summary First Edition issued Revised orderable part name information. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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