R1LP5256ESA-7SR#S0

R1LP5256E Series 256Kb Advanced LPSRAM (32k word x 8bit) R10DS0268EJ0200 Rev.2.00 2019.10.29 Description The R1LP5256E Series is a family of low voltage 256-Kbit static RAMs organized as 32,768-word by 8-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LP5256E Series has realized higher density, higher performance and low power consumption. The R1LP5256E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 28-pin SOP and 28-pin TSOP. Features         Single 4.5V~5.5V power supply Small stand-by current: 0.6µA (5.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS# Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Orderable part name Access time Temperature range R1LP5256ESP-5SI#B* R1LP5256ESP-5SI#S* R1LP5256ESA-5SI#B* R1LP5256ESA-5SI#S* 55 ns Package Shipping container 450-mil 28-pin plastic SOP Tube (Magazine) 8mm×13.4mm 28-pin plastic TSOP Tray -40 ~ +85°C Embossed tape Embossed tape Note 1. ＊= Revision code for Assembly site change, etc. (＊= 0, 1, etc.) R10DS0268EJ0200 Rev.2.00 2019.10.29 Page 1 of 11 R1LP5256E Series Pin Arrangement A14 1 28 Vcc A12 2 27 WE# A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE# A2 8 21 A10 A1 9 20 CS# A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 28-pin SOP OE# 22 21 A10 A11 23 20 CS# A9 24 19 DQ7 A8 25 18 DQ6 A13 26 17 DQ5 WE# 27 16 DQ4 Vcc 28 15 DQ3 A14 1 14 GND A12 2 13 DQ2 A7 3 12 DQ1 A6 4 11 DQ0 A5 5 10 A0 A4 6 9 A1 A3 7 8 A2 28-pin TSOP Pin Description Pin name Vcc Vss (GND) A0 to A14 DQ0 to DQ7 CS# WE# OE# Function Power supply Ground Address input Data input/output Chip select Write enable Output enable R10DS0268EJ0200 Rev.2.00 2019.10.29 Page 2 of 11 R1LP5256E Series Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 32k-word x8-bit A14 DQ0 DQ DQ1 BUFFER SENSE / WRITE AMPLIFIER DQ7 COLUMN DECODER CLOCK GENERATOR WE# Vcc Vss CS# OE# R10DS0268EJ0200 Rev.2.00 2019.10.29 Page 3 of 11 R1LP5256E Series Operation Table CS# WE# OE# DQ0~7 Operation H X X High-Z Stand-by L L X Din Write L H L Dout Read L H H High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Symbol Power supply voltage relative to Vss Vcc Terminal voltage on any pin relative to Vss VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +7.0V. R10DS0268EJ0200 Rev.2.00 2019.10.29 Value -0.3 to +7.0 -0.3*1 to Vcc+0.3*2 0.7 -40 to +85 -65 to 150 -40 to +85 unit V V W °C °C °C Page 4 of 11 R1LP5256E Series DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 4.5 5.0 5.5 V Supply voltage Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.8 V Ambient temperature range Ta -40 - +85 °C Note Note 1 1. –3.0V for pulse ≤ 30ns (full width at half maximum) DC Characteristics Parameter Input leakage current Output leakage current Average operating current Standby current Symbol | ILI | Min. - Typ. - Max. 1 Unit A | ILO | - - 1 A ICC1 - 25 35 mA ICC2 - 2 4 mA ISB - - 3 mA - 0.6*1 2 A - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C VOH 2.4 - - V IOH = -1mA VOH2 Vcc - 0.5 - - V IOH = -0.1mA VOL - - 0.4 V IOL = 2mA Standby current Test conditions Vin = Vss to Vcc CS# =VIH or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA, CS# =VIL, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA, CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V CS# =VIH, Others = Vss to Vcc Vin = Vss to Vcc, ~+25°C CS# ≥ Vcc-0.2V ISB1 Output high voltage Output low voltage Note 1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta= 25ºC), and not 100% tested. Capacitance (Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in Input / output capacitance C I/O Note 1. This parameter is sampled and not 100% tested. R10DS0268EJ0200 Rev.2.00 2019.10.29 Typ. - Max. 6 8 Unit pF pF Test conditions Vin =0V VI/O =0V Note 1 1 Page 5 of 11 R1LP5256E Series AC Characteristics Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = -40 ~ +85°C)     Input pulse levels: VIL = 0.6V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ CL = 30 pF R10DS0268EJ0200 Rev.2.00 2019.10.29 Page 6 of 11 R1LP5256E Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol Min. Max. Unit Note tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 55 10 5 5 0 0 55 55 30 20 20 ns ns ns ns ns ns ns ns ns 2,3 2,3 1,2,3 1,2,3 Symbol Min. Max. Unit Note tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ 55 50 50 40 0 0 25 0 5 0 0 20 20 ns ns ns ns ns ns ns ns ns ns ns Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note 5 4 6 7 2 1,2 1,2 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS#, a low WE#. A write begins at the latest transition among CS# going low and WE# going low. A write ends at the earliest transition among CS# going high and WE# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS# going low to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS# or WE# going high to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode. R10DS0268EJ0200 Rev.2.00 2019.10.29 Page 7 of 11 R1LP5256E Series Timing Waveforms Read Cycle tRC A0~14 tOH tAA tACS CS# tCLZ WE# tCHZ VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~7 R10DS0268EJ0200 Rev.2.00 2019.10.29 Valid Data Page 8 of 11 R1LP5256E Series Write Cycle (1) (WE# CLOCK) tWC A0~14 tCW CS# tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~7 tOW Valid Data tDW R10DS0268EJ0200 Rev.2.00 2019.10.29 tDH Page 9 of 11 R1LP5256E Series Write Cycle (2) (CS# CLOCK) tWC A0~14 tAW tAS tCW tWR CS# tWP WE# OE# VIH OE# = “H” level tDW DQ0~7 R10DS0268EJ0200 Rev.2.00 2019.10.29 tDH Valid Data Page 10 of 11 R1LP5256E Series Low Vcc Data Retention Characteristics Test conditions*2 Parameter Symbol Min. Typ. Max. Unit VCC for data retention VDR 2.0 - 5.5 V Vin ≥ 0V, CS# ≥ Vcc-0.2V - 0.6*1 2 A ~+25°C - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C Data retention current ICCDR Vcc=3.0V, Vin ≥ 0V, CS# ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ns See retention waveform. Operation recovery time tR 5 ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, DQ) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms CS# Controlled Vcc tCDR 2.2V 4.5V 4.5V VDR tR 2.2V CS# ≥ Vcc - 0.2V CS# R10DS0268EJ0200 Rev.2.00 2019.10.29 Page 11 of 11 Revision History Rev. 1.00 2.00 Date 2017.1.27 2019.10.29 R1LP5256E Series Data Sheet Page p.1 Description Summary First Edition issued Revised orderable part name information. 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