R1LV0408DSP-7LR

R1LV0408D Series 4M SRAM (512-kword × 8-bit) REJ03C0310-0100 Rev.1.00 May.24.2007 Description The R1LV0408D is a 4-Mbit static RAM organized 512-kword × 8-bit, fabricated by Renesas’s highperformance 0.15µm CMOS and TFT technologies. R1LV0408D Series has realized higher density, higher performance and low power consumption. The R1LV0408D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32pin TSOP II and 32-pin STSOP. Features • Single 3 V supply: 2.7 V to 3.6 V • Access time: 55/70 ns (max) • Power dissipation:  Standby: 3 µW (typ) • Equal access and cycle times • Common data input and output.  Three state output • Directly TTL compatible.  All inputs and outputs • Battery backup operation. Rev.1.00, May.24.2007, page 1 of 12 R1LV0408D Series Ordering Information Type No. R1LV0408DSP-5S% R1LV0408DSP-7L% R1LV0408DSB-5S% R1LV0408DSB-7L% R1LV0408DSA-5S% R1LV0408DSA-7L% Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 8mm × 13.4mm STSOP (32P3K-B) 400-mil 32-pin plastic TSOP II (32P3Y-H) Package 525-mil 32-pin plastic SOP (32P2M-A) %: Temperature version; see table below. % R I Temperature Range 0 to +70°C −40 to +85°C Rev.1.00, May.24.2007, page 2 of 12 R1LV0408D Series Pin Arrangement 32-pin SOP 32-pin TSOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 32-pin STSOP A11 A9 A8 A13 WE# A18 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 Pin Description Pin name A0 to A18 I/O0 to I/O7 CS# (CS) OE# (OE) WE# (WE) VCC VSS Function Address input Data input/output Chip select Output enable Write enable Power supply Ground Rev.1.00, May.24.2007, page 3 of 12 R1LV0408D Series Block Diagram LSB A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 V CC V SS • • • • • Row Decoder Memory Matrix 2,048 × 2,048 MSB I/O0 Input Data Control I/O7 • • Column I/O Column Decoder • • LSB A0 A1 A2 A3 A4 A5 A17 A18 MSB • • CS# WE# OE# Timing Pulse Generator Read/Write Control Rev.1.00, May.24.2007, page 4 of 12 R1LV0408D Series Operation Table WE# × H H L L CS# H L L L L OE# × H L H L Mode Not selected Output disable Read Write Write VCC current ISB, ISB1 ICC ICC ICC ICC I/O0 to I/O7 High-Z High-Z Dout Din Din Ref. cycle   Read cycle Write cycle (1) Write cycle (2) Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Operating temperature Symbol VCC VT PT Topr R ver. I ver. Storage temperature range Storage temperature range under bias Tstg Tbias R ver. I ver. Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. 1 Value −0.5 to +4.6 −0.5* to VCC + 0.5* 0.7 0 to +70 −40 to +85 −65 to +150 0 to +70 −40 to +85 2 Unit V V W °C °C °C DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: R ver. I ver. 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. VIH VIL Ta Min 2.7 0 2.2 −0.3* 0 −40 1 Typ 3.0 0     Max 3.6 0 VCC + 0.3 0.6 +70 +85 Unit V V V V °C Rev.1.00, May.24.2007, page 5 of 12 R1LV0408D Series DC Characteristics Parameter Input leakage current Output leakage current Operating current Average operating current Symbol |ILI| |ILO| ICC ICC1 Min     Typ     Max Unit 1 1 10 25 Test conditions µA Vin = VSS to VCC µA CS# = VIH or OE# = VIH or WE# = VIL or VI/O = VSS to VCC mA CS# = VIL, Others = VIH/ VIL, II/O = 0 mA mA Min. cycle, duty = 100%, CS# = VIL, Others = VIH/VIL II/O = 0 mA mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS# ≤ 0.2 V, VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V mA CS# = VIH µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V µA Average values µA µA µA µA µA µA V V V V IOL = 2.1 mA IOL = 100 µA IOH = −1.0 mA IOH = −0.1 mA ICC2   5 Standby current Standby −5S% current to +85°C to +70°C to +40°C to +25°C −7L% to +85°C to +70°C to +40°C to +25°C Output low voltage ISB ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 VOL VOL2 VOH VOH2            2.4 VCC − 0.2 0.1*1    1* 1 0.3 10 8 3 2.5 20 16 10 10 0.4 0.2      1* 1     Output high voltage Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min   Typ   Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 1. This parameter is sampled and not 100% tested. Rev.1.00, May.24.2007, page 6 of 12 R1LV0408D Series AC Characteristics (Ta = 0 to +70°C / −40 to +85°C, VCC = 2.7 V to 3.6 V) Test Conditions • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + CL (50 pF) (R1LV0408D-5S%) 1 TTL Gate + CL (100 pF) (R1LV0408D-7L%) (Including scope and jig) Note: Temperature range depends on R/I-version. Please see table on page 2. Read Cycle R1LV0408D -5S% Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Output hold from address change Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH Min 55    10 5 0 0 10 Max  55 55 30   20 20  -7L% Min 70    10 5 0 0 10 Max  70 70 35   25 25  Unit ns ns ns ns ns ns ns ns ns 2 2 1, 2 1, 2 Notes Rev.1.00, May.24.2007, page 7 of 12 R1LV0408D Series Write Cycle R1LV0408D -5S% Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW tOHZ Min 55 50 0 50 40 0 0 25 0 5 0 Max       20    20 -7L% Min 70 60 0 60 50 0 0 30 0 5 0 Max       25    25 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 7 3, 12 6 1, 2, 7 4 5 Notes Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS# going low to the end of write. 5. tAS is measured from the address valid to the beginning of write. 6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max Rev.1.00, May.24.2007, page 8 of 12 R1LV0408D Series Timing Waveform Read Timing Waveform (WE# = VIH) tRC Address Valid address tAA tCO CS# tLZ tOE tOLZ OE# tOHZ tHZ Dout High impedance Valid data tOH Rev.1.00, May.24.2007, page 9 of 12 R1LV0408D Series Write Timing Waveform (1) (OE# Clock) tWC Address Valid address tAW OE# tCW CS# *8 tWR tAS tWP WE# tOHZ Dout High impedance tDW Din Valid data tDH Rev.1.00, May.24.2007, page 10 of 12 R1LV0408D Series Write Timing Waveform (2) (OE# Low Fixed) tWC Address Valid address tCW tWR CS# *8 tAW tWP WE# tAS tWHZ tOW tOH *9 *10 Dout High impedance tDW tDH *11 Din Valid data Rev.1.00, May.24.2007, page 11 of 12 R1LV0408D Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C / −40 to +85°C) Parameter VCC for data retention Data retention current −5S% to +85°C to +70°C to +40°C to +25°C −7L% to +85°C to +70°C to +40°C to +25°C Chip deselect to data retention time Operation recovery time Note: Symbol Min Typ Max Unit VDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR tCDR tR 2         0 5     1* 1 Test conditions CS# ≥ VCC − 0.2 V, Vin ≥ 0 V  10 8 3 2.5 20 16 10 10   V µA VCC = 3.0 V, Vin ≥ 0 V µA CS# ≥ VCC − 0.2 V µA Average values µA µA µA µA µA ns ms See retention waveform    1* 1   1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Low VCC Data Retention Timing Waveform (CS# Controlled) tCDR VCC 2.7 V Data retention mode tR 2.2 V VDR CS# 0V CS# ≥ VCC – 0.2 V Rev.1.00, May.24.2007, page 12 of 12 Revision History Rev. 0.01 1.00 Date Dec. 25, 2006 May. 24, 2007 R1LV0408D Series Data Sheet Contents of Modification Description Page  Initial issue 6 DC Characteristics ISB1 (-5S%) (to +25°C) max: 3 µA to 2.5 µA Low VCC Data Retention Characteristics 12 ICCDR (-5S%) (to +25°C) max: 3 µA to 2.5 µA Deletion of note 2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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