R1LV0816ABG-5SI#B0

R1LV0816ASB – 5SI, 7SI 8Mb Advanced LPSRAM (512k word x 16bit) REJ03C0387-0100 Rev.1.00 2009.12.07 Description The R1LV0816ASB is a family of low voltage 8-Mbit static RAMs organized as 524,288-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1LV0816ASB is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. The R1LV0816ASB is packaged in a 44pin thin small outline mount device [11.76mm×18.41mm 44-pin plastic TSOP (II)]. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • • • • • • • • • Single 2.4-3.6V power supply Small stand-by current: 1.2μA (Vcc=3.0V, typ.) No clocks, No refresh All inputs and outputs are TTL compatible Easy memory expansion by CS#, LB# and UB# Common Data I/O Three-state outputs: OR-tie capability OE# prevents data contention in the I/O bus Operation temperature: -40 ~ +85°C Ordering information Type No. R1LV0816ASB-5SI R1LV0816ASB-7SI Power supply Access time 2.7V to 3.6V 55 ns 2.4V to 2.7V 2.4V to 3.6V 70 ns 70 ns REJ03C0387-0100 Rev.1.00 2009.12.07 Page 1 of 15 Temperature Range Package -40 ~ +85°C 11.76mm×18.41mm 44-pin plastic TSOP (II) (normal-bend type) (44P3F) R1LV0816ASB –5SI, 7SI Pin Arrangement 44-pin TSOP (II) A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CS# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 VCC 11 34 GND GND 12 33 VCC DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 DQ7 16 29 DQ8 WE# 17 28 A8 A18 18 27 A9 A17 19 26 A10 A16 20 25 A11 A15 21 24 A12 A14 22 23 A13 REJ03C0387-0100 Rev.1.00 2009.12.07 Page 2 of 15 R1LV0816ASB –5SI, 7SI Pin Description Pin name Vcc Vss A0 to A18 DQ0 to DQ15 CS# WE# OE# LB# UB# Function Power supply Ground Address input (word mode) Data input/output Chip select Write enable Output enable Lower byte enable Upper byte enable REJ03C0387-0100 Rev.1.00 2009.12.07 Page 3 of 15 R1LV0816ASB –5SI, 7SI Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 512k-word x16-bit DQ0 DQ1 A18 DQ BUFFER DQ7 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ8 COLUMN DECODER DQ DQ9 BUFFER CLOCK DQ15 GENERATOR CS# LB# UB# WE# OE# REJ03C0387-0100 Rev.1.00 2009.12.07 Page 4 of 15 UPPER or LOWER BYTE CONTROL Vcc Vss R1LV0816ASB –5SI, 7SI Operation Table CS# WE# OE# UB# LB# DQ0~7 DQ8~15 Operation H X X X X High-Z High-Z Stand-by X X X H H High-Z High-Z Stand-by L L X H L Din High-Z Write in lower byte L H L H L Dout High-Z Read in lower byte L L X L H High-Z Din Write in upper byte L H L L H High-Z Dout Read in upper byte L L X L L Din Din Word write L H L L L Dout Dout Word read L H H L L High-Z High-Z Output disable L H H L H High-Z High-Z Output disable L H H H L High-Z High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note 1. -3.0V in case of AC (Pulse width ≤30ns) 2. Maximum voltage is +4.6V REJ03C0387-0100 Rev.1.00 2009.12.07 Page 5 of 15 Symbol Vcc VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5*1 to Vcc+0.3*2 0.7 -40 to +85 -65 to 150 -40 to +85 Unit V V W °C °C °C R1LV0816ASB –5SI, 7SI Recommend Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range Symbol Min. Typ. Max. Unit Test conditions Vcc Vss 2.4 0 2.0 2.2 -0.2 -0.2 -40 3.0 0 - 3.6 0 Vcc+0.2 Vcc+0.2 0.4 0.6 +85 V V V V V V °C Vcc=2.4V to 2.7V Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V Vcc=2.7V to 3.6V - VIH VIL Ta Note 1 1 Note 1. -3.0V in case of AC (Pulse width ≤30ns) DC Characteristics Parameter Input leakage current Output leakage current Average operating current Standby current Standby current Symbol Min. Typ. Max. Unit | ILI | - - 1 μA | ILO | - - 1 μA ICC1 - 20*1 35 mA ICC2 - 2*1 5 mA ISB - - 1 mA Vin = Vss to Vcc CS# =VIH or OE# =VIH or WE# =VIL or LB# = UB# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA CS# =VIL, Others = VIH/VIL Cycle =1 s, duty =100%, II/O = 0mA CS# ≤ 0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V CS# =VIH Test conditions - 1.2*1 4 μA ~+25°C - 3*2 6 μA ~+40°C - - 15 μA ~+70°C - - 20 μA ~+85°C ISB1 Output high voltage Vin ≥ 0V (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V, IOH = -1mA Vcc≥2.7V VOH2 2.0 V IOH = -0.1mA Output low voltage IOL = 2mA VOL 0.4 V Vcc≥2.7V 0.4 V IOL = 0.1mA VOL2 Note 1.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+25°C), and not 100% tested. 2.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+40°C), and not 100% tested. VOH REJ03C0387-0100 Rev.1.00 2009.12.07 Page 6 of 15 2.4 - - V R1LV0816ASB –5SI, 7SI Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Typ. Input capacitance C in Input / output capacitance C I/O Note 1.Typical parameter is sampled and not 100% tested. Max. 10 10 Unit pF pF Test conditions Vin =0V VI/O =0V AC Characteristics Test Conditions (Vcc = 2.4V ~ 3.6V, Ta = -40 ~ +85°C) • Input pulse levels: VIL = 0.4V, VIH = 2.4V (Vcc = 2.7V ~ 3.6 V) VIL = 0.4V, VIH = 2.2V (Vcc = 2.4V ~ 2.7 V) • Input rise and fall times: 5ns • Input and output timing reference level: 1.4V • Output load: See figures (Including scope and jig) 1.4V RL = 500 ohm DQ CL = 30 pF REJ03C0387-0100 Rev.1.00 2009.12.07 Page 7 of 15 Note 1 1 R1LV0816ASB –5SI, 7SI Read cycle R1LV0816ASB-5SI Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z Symbol tRC tAA tACS tOE tOH tBA tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ REJ03C0387-0100 Rev.1.00 2009.12.07 Page 8 of 15 (Note 0) Min. 55 10 10 5 5 0 0 0 Max. 55 55 30 55 20 20 20 R1LV0816ASB-7SI Min. 70 10 10 5 5 0 0 0 Max. 70 70 35 70 25 25 25 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 R1LV0816ASB –5SI, 7SI Write Cycle R1LV0816ASB-5SI Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ (Note 0) Min. 55 50 50 40 50 0 0 25 0 5 0 0 Max. 20 20 R1LV0816ASB-7SI Min. 70 65 65 55 65 0 0 35 0 5 0 0 Max. 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note 5 4 6 7 2 1,2 1,2 Note 0. If Vcc is 2.4-2.7V, parameters of R1LV0816ASB-7SI (70ns) are applied. 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. Typical parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for given device and from device to device. 4. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or low UB#. A write begins at the latest transitions among CS# going low, WE# going low and LB# going low or UB# going low. A write ends at the earliest transitions among CS# going high, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS# going low to the end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS# or WE# going high to the end of write cycle. REJ03C0387-0100 Rev.1.00 2009.12.07 Page 9 of 15 R1LV0816ASB –5SI, 7SI Timing Waveforms Read Cycle tRC A0~18 tOH tAA tBA LB#,UB# tBLZ tBHZ tACS CS# tCLZ WE# WE# = “H” level tCHZ VIH VIL tOE OE# tOLZ tOHZ High impedance DQ0~15 REJ03C0387-0100 Rev.1.00 2009.12.07 Page 10 of 15 Valid Data R1LV0816ASB –5SI, 7SI Write Cycle (1) (WE# CLOCK) tWC A0~18 tOH tBW LB#,UB# tCW CS# tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~15 tOW Valid Data tDW REJ03C0387-0100 Rev.1.00 2009.12.07 Page 11 of 15 tDH R1LV0816ASB –5SI, 7SI Write Cycle (2) (CS# CLOCK) tWC A0~18 tAW tBW LB#,UB# tAS tCW tWR CS# tWP WE# OE# OE# = “H” level VIH VIL tDW DQ0~15 REJ03C0387-0100 Rev.1.00 2009.12.07 Page 12 of 15 tDH Valid Data R1LV0816ASB –5SI, 7SI Write Cycle (3) (LB#, UB# CLOCK) tWC A0~18 tAW tAS tBW tWR LB#,UB# tCW CS# tWP WE# OE# OE# = “H” level VIH VIL tDW DQ0~15 REJ03C0387-0100 Rev.1.00 2009.12.07 Page 13 of 15 tDH Valid Data R1LV0816ASB –5SI, 7SI Data Retention Characteristics Parameter VCC for data retention Symbol VDR Min. Typ. Max. Test conditions*3 Unit 1.5 - 3.6 V Vin ≥ 0V (1) CS# ≥ VCC-0.2V, (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V, - 1.2*1 4 μA ~+25°C Vcc=3.0V, Vin ≥ 0V Data retention current *2 - 3 6 μA ~+40°C - - 15 μA ~+70°C - - 20 μA ~+85°C ICCDR (1) CS# ≥ VCC-0.2V or (2) LB# = UB# ≥ VCC-0.2V, CS# ≤ 0.2V, Chip select to data retention time tCDR 0 ns See retention waveform. Operation recovery time tR 5 ms Note 1.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+25°C), and not 100% tested. 2.Typical parameter indicates the value for the center of distribution at 3.0V(Ta=+40°C), and not 100% tested. 3.CS# controls address buffer, WE# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high impedance state. REJ03C0387-0100 Rev.1.00 2009.12.07 Page 14 of 15 R1LV0816ASB –5SI, 7SI Data Retention Timing Waveforms (1) CS# controlled Vcc tCDR 2.4V 2.4V tR VDR 2.0V 2.0V CS# ≥ Vcc - 0.2V CS# (2) LB#, UB# controlled Vcc tCDR 2.0V LB#, UB# REJ03C0387-0100 Rev.1.00 2009.12.07 Page 15 of 15 2.4V 2.4V VDR LB#, UB# ≥ Vcc - 0.2V tR 2.0V Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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