R1LV1616RSA-8SI

R1LV1616RBA-5SI 16Mb Advanced LPSRAM (1M wordx16bit / 2M wordx8bit) REJ03C0340-0001 Rev.0.01 2007.10.31 Description The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1LV1616R Series is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. The R1LV1616RBA Series is packaged in a 48balls Wafer Level Chip Scale Package[WL-CSP / 5.62mm x 5.84mm with the ball-pitch of 0.55mm and the height of 0.79mm]. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • Single 2.7-3.6V power supply • Small stand-by current:2µA (3.0V, typ.) • Data retention supply voltage =2.0V • No clocks, No refresh • All inputs and outputs are TTL compatible • Easy memory expansion by CS1#, CS2, LB# and UB# • Common Data I/O • Three-state outputs: OR-tie capability • OE# prevents data contention on the I/O bus • Process technology: 0.15um CMOS REJ03C0340-0001 Rev.0.01 2007.10.31 page 1 of 14 R1LV1616RBA Series Ordering Information Type No. R1LV1616RBA-5SI Access time 55 ns Package 5.62mmx5.84mm WL-CSP with 0.55mm pitch 48balls Pin Arrangement 48-pin WL-CSP (bottom view) 6 A B C D E F G H A0 CS1# 5 A4 A5 A6 A7 A8 CS2 A9 A10 4 A11 A12 A13 A14 A15 A16 A17 A18 3 BYTE# 2 1 UB# LB# DQ7 DQ15/ A-1 DQ14 WE# DQ5 DQ13 DQ6 Vcc Vss A1 A2 A3 DQ4 DQ12 Vss Vcc DQ2 Vss DQ9 DQ11 DQ10 DQ8 DQ3 OE# A19 DQ1 DQ0 REJ03C0340-0001 Rev.0.01 2007.10.31 page 2 of 14 R1LV1616RBA Series Pin Description Pin name A0 to A19 DQ 0 to DQ15 CS1# &CS2 WE# OE# LB# UB# Vcc Vss BYTE# NC Function Address input Data input/output Chip select Write enable Output enable Lower byte select Upper byte select Power supply Ground Byte (x8 mode) enable input Non connection Block Diagram SENSE Amp. DQ0 DATA SELECTOR OUTPUT BUFFER ADDRESS BUFFER A0 Memory Array DECODER SENSE Amp. A19 CS2 CS1# LB# UB# BYTE# WE# OE# OUTPUT BUFFER 1048576 Words x 16BITS OR 2097152 Words x 8BITS CLOCK GENERATOR DQ7 DQ8 DQ15 / A-1 DATA SELECTOR DATA INPUT BUFFER Vcc Vss REJ03C0340-0001 Rev.0.01 2007.10.31 page 3 of 14 DATA INPUT BUFFER x8/x16 SWITCHING CIRCUIT R1LV1616RBA Series Operating Table CS1# H X X L L L L L L L L L CS2 X L X H H H H H H H H H BYTE# X X H H H X H H H H L L LB# X X H L L X H H L L L L UB# X X H H H X L L L L L L WE# X X X L H H L H L H L H OE# X X X X L H X L X L X L DQ0-7 High-Z High-Z High-Z Din Dout High-Z High-Z High-Z Din Dout Din Dout DQ8-14 High-Z High-Z High-Z High-Z High-Z High-Z Din Dout Din Dout High-Z High-Z DQ15 High-Z High-Z High-Z High-Z High-Z High-Z Din Dout Din Dout A-1 A-1 Operation Stand by Stand by Stand by Write in lower byte Read from lower byte Output disable Write in upper byte Read from upper byte Write Read Write Read Note 1. H:VIH L:VIL X: VIH or VIL 2. When applying BYTE# =“L” , please assign LB#=UB#=“L”. Absolute Maximum Ratings Parameter Power supply voltage relative to Vss Terminal voltage on any pin relation toVss Power dissipation Operation temperature Storage temperature Storage temperature range under bias Symbol Vcc VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5*1 to Vcc+0.3*2 0.7 -40 to +85 -65 to +150 -40 to +85 Unit V V W ºC ºC ºC Note 1. -2.0V in case of AC (Pulse width ≤ 30ns) 2. Maximum voltage is +4.6V REJ03C0340-0001 Rev.0.01 2007.10.31 page 4 of 14 R1LV1616RBA Series Recommended Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range Symbol Vcc Vss VIH VIL Ta Min. 2.7 0 2.4 -0.2 -40 Typ. 3.0 0 - Max. 3.6 0 Vcc+0.2 0.4 +85 Unit V V V V ºC Note 1 2 Note 1. –2.0V in case of AC (Pulse width ≤ 30ns) DC Characteristics Parameter Input leakage current Output leakage current Symbol |ILI| |ILo| Min. - Typ.*1 - Max. 1 1 Unit µA µA Test conditions*2 Vin=Vss to Vcc CS1# =VIH or CS2=VIL or OE# = VIH or WE# =VIL or LB# =UB# =VIH,VI/O=Vss to Vcc Min. cycle, duty =100% I I/O = 0 mA, CS1# =VIL, CS2=VIH Others = VIH / VIL Cycle time = 1 µs, I I/O = 0 mA, CS1#≤ 0.2V, CS2 ≥ VCC-0.2V VIH ≥ VCC-0.2V , VIL ≤ 0.2V, duty=100% CS2=VIL ~+25ºC V in ≥ 0V ~+40ºC ~+70ºC ~+85ºC (1) 0V≤CS2≤0.2V or (2) CS2≥Vcc-0.2V, CS1# ≥Vcc-0.2V or (3)LB# =UB# ≥Vcc-0.2V, CS2≥Vcc-0.2V, CS1# ≤0.2V Average value Icc1 Average operating current - 25 40 mA Icc2 Standby current - 2 5 mA ISB - 0.1 2 4 - 0.3 6 12 25 40 0.4 mA µA µA µA µA V V Standby current ISB1 - Output hige voltage Output Low voltage VOH VOL 2.4 - IOH = -1mA IOL = 2mA Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V REJ03C0340-0001 Rev.0.01 2007.10.31 page 5 of 14 R1LV1616RBA Series Capacitance (Ta = +25ºC, f =1MHz) Parameter Input capacitance Input / output capacitance Symbol C in C I/O Min. - Typ. - Max. 10 10 Unit pF pF Test conditions V in = 0V V I/O = 0V Note 1 1 Note 1:This parameter is sampled and not 100% tested. AC Characteristics Test Conditions (Vcc=2.7~3.6V, Ta = -40~+85ºC *) • Input pulse levels: VIL= 0.4V,VIH=2.4V • Input rise and fall time : 5ns • Input and output timing reference levels : 1.4V • Output load : See figures (Including scope and jig) 1.4V RL=500Ω DQ CL=30pF REJ03C0340-0001 Rev.0.01 2007.10.31 page 6 of 14 R1LV1616RBA Series Read Cycle (note0) Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#,UB# access time Chip select to output in low-Z LB#,UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#,UB# disable to high-Z Output disable to output in high-Z Symbol Min. 55 10 10 5 5 0 0 0 0 Max. 70 55 55 35 55 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes tRC tAA tACS1 tACS2 tOE tOH tBA tCLZ tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 1,2,3 REJ03C0340-0001 Rev.0.01 2007.10.31 page 7 of 14 R1LV1616RBA Series Write Cycle Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#,UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol Vcc=2.7V to 3.6V Min. 55 50 55 40 50 0 0 25 0 5 0 0 Max. 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ 5 4 6 7 2 1,2 1,2 Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts. In case of tAA =70ns, tRC =70ns. 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. AT any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and form device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. REJ03C0340-0001 Rev.0.01 2007.10.31 page 8 of 14 R1LV1616RBA Series Timing condition for Byte enable Parameter Byte setup time Byte recovery time Symbol Min. 5 5 Max. Unit ms ms Notes tBS tBR BYTE# Timing Waveform CS2 CS1# tBS BYTE# tBR REJ03C0340-0001 Rev.0.01 2007.10.31 page 9 of 14 R1LV1616RBA Series Timing Waveform Read Cycle tRC A0~19 (Word Mode) Valid address A-1~19 (Byte Mode) tAA tBA tOH LB#,UB# tBHZ CS1# tACS1 tCHZ1 CS2 tACS2 tCHZ2 tOE OE# WE# = "H" level tOLZ tCLZ tBLZ tOHZ Valid data DQ0~15 (Word Mode) DQ0~7 (Byte Mode) REJ03C0340-0001 Rev.0.01 2007.10.31 page 10 of 14 R1LV1616RBA Series Write Cycle (1) (WE# Clock) tWC A 0~19 (Word Mode) A -1~19 (Byte Mode) Valid address tBW tCW tCW tAW tAS tWP tWHZ tOW tDW tDH tWR LB#,UB# CS1# CS2 WE# DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Valid data REJ03C0340-0001 Rev.0.01 2007.10.31 page 11 of 14 R1LV1616RBA Series Write Cycle (2) (CS1# ,CS2 Clock, OE#=VIH) tWC A0~19 (Word Mode) A-1~19 (Byte Mode) Valid address tBW LB#,UB# CS1# tAS CS2 tCW tCW tWP tDW tWR WE# DQ0~15 (Word Mode) tDH DQ0~7 (Byte Mode) Valid data REJ03C0340-0001 Rev.0.01 2007.10.31 page 12 of 14 R1LV1616RBA Series Write Cycle (3) ( LB#,UB# Clock, OE#=VIH) A0~19 (Word Mode) tWC Valid address A-1~19 (Byte Mode) tAS tBW tWR LB#,UB# CS1# tCW tCW CS2 WE# tWP tDW tDH DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Valid data REJ03C0340-0001 Rev.0.01 2007.10.31 page 13 of 14 R1LV1616RBA Series Data Retention Characteristics Parameter Symbol MIn. Typ.*1 Max. Unit Test conditions*2,3 V in ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS2 ≥ Vcc-0.2V, CS1# ≥ Vcc-0.2V or (3) LB# =UB# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V, CS1# ≤ 0.2V Vcc for data retention VDR 2.0 - 3.6 V Data retention current 2 4 - 6 12 25 40 - µA µA µA µA ns ~+25ºC ~+40ºC ~+70ºC ~+85ºC IccDR - Vcc=3.0V,Vin≥0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS2 ≥ Vcc-0.2V, CS1# ≥ Vcc-0.2V or (3) LB# =UB# ≥Vcc-0.2V, CS2 ≥ Vcc-0.2V, CS1# ≤ 0.2V Average value Chip deselect to data retention time Operation recovery time tCDR tR 0 5 See retention waveform ms Note 1. Typical parameter of IccDR indicates the value for the center of distribution at Vcc=3.0V and not 100% tested. 2. BYTE# pin supported only by TSOP and uTSOP types. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V 3. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer .If CS2 controls data retention mode,Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. Data Retention timing Waveform (1) (LB#,UB# Controlled) Vcc tCDR 2.4V LB# UB# 2.70V tR 2.4V LB# =UB# ≥ Vcc-0.2V Data Retention timing Waveform (2) (CS1# Controlled) Vcc tCDR 2.4V CS1# 2.70V tR 2.4V CS1# ≥ Vcc-0.2V Data Retention timing Waveform (3) (CS2 Controlled) Vcc CS2 tCDR 0.2V 2.70V tR 0.2V 0V ≤ CS2 ≤ 0.2V REJ03C0340-0001 Rev.0.01 2007.10.31 page 14 of 14 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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