R1LV5256ESA-7SI#S0

R1LV5256E Series 256Kb Advanced LPSRAM (32k word x 8bit) R10DS0068EJ0100 Rev.1.00 2011.04.13 Description The R1LV5256E Series is a family of low voltage 256-Kbit static RAMs organized as 32,768-word by 8-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LV5256E Series has realized higher density, higher performance and low power consumption. The R1LV5256E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 28-pin SOP and 28-pin TSOP. Features • • • • • • • • Single 2.7~3.6V power supply Small stand-by current: 1µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS# Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Orderable Part Name R1LV5256ESP-5SR#B0 R1LV5256ESP-5SI#B0 R1LV5256ESP-7SR#B0 R1LV5256ESP-7SI#B0 R1LV5256ESP-5SR#S0 R1LV5256ESP-5SI#S0 R1LV5256ESP-7SR#S0 R1LV5256ESP-7SI#S0 R1LV5256ESA-5SR#B0 R1LV5256ESA-5SI#B0 R1LV5256ESA-7SR#B0 R1LV5256ESA-7SI#B0 R1LV5256ESA-5SR#S0 R1LV5256ESA-5SI#S0 R1LV5256ESA-7SR#S0 R1LV5256ESA-7SI#S0 Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns R10DS0068EJ0100 Rev.1.00 2011.04.13 Temperature Range Package Shipping Container Quantity Tube Max. 30pcs/Tube Max. 300pcs/Inner Bag Max. 1200pcs/Inner Box Embossed tape 1000pcs/Reel Tray Max. 234pcs/Tray Max. 1872pcs/Inner Box Embossed tape 1000pcs/Reel 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 450-mil 28-pin plastic SOP PRSP0028DB-B (28P2W-C) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 8mm×13.4mm 28-pin plastic TSOP (normal-bend type) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C PTSA0028ZA-A (28P2C-A) -40 ~ +85°C Page 1 of 13 R1LV5256E Series Pin Arrangement A14 1 28 Vcc A12 2 27 WE# A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE# A2 8 21 A10 A1 9 20 CS# A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 28-pin SOP OE# 22 21 A10 A11 23 20 CS# A9 24 19 DQ7 A8 25 18 DQ6 A13 26 17 DQ5 WE# 27 16 DQ4 Vcc 28 15 DQ3 A14 1 14 GND A12 2 13 DQ2 A7 3 12 DQ1 A6 4 11 DQ0 A5 5 10 A0 A4 6 9 A1 A3 7 8 A2 28-pin TSOP Pin Description Pin name Vcc Vss A0 to A14 DQ0 to DQ7 CS# WE# OE# Function Power supply Ground Address input Data input/output Chip select Write enable Output enable R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 2 of 13 R1LV5256E Series Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 32k-word x8-bit A14 DQ0 DQ DQ1 BUFFER SENSE / WRITE AMPLIFIER DQ7 COLUMN DECODER CLOCK GENERATOR WE# Vcc Vss CS# OE# R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 3 of 13 R1LV5256E Series Operation Table CS# WE# OE# DQ0~7 Operation H X X High-Z Stand-by L L X Din Write L H L Dout Read L H H High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr*3 Value -0.3 to +4.6 -0.3*1 to Vcc+0.3*2 0.7 R Ver. 0 to +70 I Ver. -40 to +85 Tstg Tbias*3 -65 to 150 R Ver. I Ver. unit V V W °C °C 0 to +70 -40 to +85 °C 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +4.6V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 4 of 13 R1LV5256E Series DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 2.7 3.0 3.6 V Supply voltage Note Vss 0 0 0 V Input high voltage VIH 2.0 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.6 V 1 0 - +70 °C 2 -40 - +85 °C 2 Ambient temperature range Note R Ver. Ta I Ver. 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. DC Characteristics Parameter Input leakage current Output leakage current Average operating current Standby current Symbol Min. Typ. Max. Unit | ILI | - - 1 μA | ILO | - - 1 μA ICC1 - 14 25 mA ICC2 - 2 5 mA ISB - - 0.33 mA - 1*1 2 μA - - 3 μA ~+40°C - - 8 μA ~+70°C - - 10 μA ~+85°C VOH 2.4 - - V IOH = -0.5mA VOH2 Vcc - 0.5 - - V IOH = -0.05mA VOL - - 0.4 V IOL = 1mA Standby current Test conditions Vin = Vss to Vcc CS# =VIH or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA CS# =VIL, Others = VIH/VIL Cycle =1μs, duty =100%, II/O = 0mA CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V CS# =VIH, Others = Vss to Vcc Vin = Vss to Vcc ~+25°C CS# ≥ Vcc-0.2V ISB1 Output high voltage Output low voltage Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 5 of 13 R1LV5256E Series Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2) Parameter Symbol Min. Typ. Max. Unit Test conditions Input capacitance C in 6 pF Vin =0V Input / output capacitance C I/O 8 pF VI/O =0V Note 1. This parameter is sampled and not 100% tested. 2. Ambient temperature range depends on R/I-version. Please see table on page 1. Note 1 1 AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ CL = 30 pF Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 6 of 13 R1LV5256E Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z R10DS0068EJ0100 Rev.1.00 2011.04.13 Symbol tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ R1LV5256E**-5S* R1LV5256E**-7S* Min. 55 10 5 5 0 0 Min. 70 10 5 5 0 0 Max. 55 55 30 20 20 Max. 70 70 35 25 25 Unit Note ns ns ns ns ns ns ns ns ns 2,3 2,3 1,2,3 1,2,3 Page 7 of 13 R1LV5256E Series Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note Symbol tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ R1LV5256E**-5S* R1LV5256E**-7S* Min. 55 50 50 40 0 0 25 0 5 0 0 Min. 70 65 65 50 0 0 30 0 5 0 0 Max. 20 20 Max. 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns Note 5 4 6 7 2 1,2 1,2 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS#, a low WE#. A write begins at the latest transition among CS# going low and WE# going low. A write ends at the earliest transition among CS# going high and WE# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS# going low to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS# or WE# going high to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode. R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 8 of 13 R1LV5256E Series Timing Waveforms Read Cycle tRC A0~14 tOH tAA tACS CS# tCLZ WE# tCHZ VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~7 R10DS0068EJ0100 Rev.1.00 2011.04.13 Valid Data Page 9 of 13 R1LV5256E Series Write Cycle (1) (WE# CLOCK) tWC A0~14 tCW CS# tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~7 tOW Valid Data tDW R10DS0068EJ0100 Rev.1.00 2011.04.13 tDH Page 10 of 13 R1LV5256E Series Write Cycle (2) (CS# CLOCK) tWC A0~14 tAW tAS tCW tWR CS# tWP WE# OE# VIH OE# = “H” level tDW DQ0~7 R10DS0068EJ0100 Rev.1.00 2011.04.13 tDH Valid Data Page 11 of 13 R1LV5256E Series Low Vcc Data Retention Characteristics Test conditions*2 Parameter Symbol Min. Typ. Max. Unit VCC for data retention VDR 2.0 - 3.6 V - 1*1 2 μA ~+25°C - - 3 μA ~+40°C - - 8 μA ~+70°C - - 10 μA ~+85°C Data retention current Vin ≥ 0V CS# ≥ Vcc-0.2V ICCDR Vcc=3.0V, Vin ≥ 0V, CS# ≥ Vcc-0.2V Chip deselect to data retention time tCDR 0 ns See retention waveform. Operation recovery time tR 5 ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, DQ) can be in the high impedance state. R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 12 of 13 R1LV5256E Series Low Vcc Data Retention Timing Waveforms CS# Controlled Vcc tCDR 2.2V 2.7V 2.7V VDR tR 2.2V CS# ≥ Vcc - 0.2V CS# R10DS0068EJ0100 Rev.1.00 2011.04.13 Page 13 of 13 Revision History R1LV5256E Series Data Sheet Rev. Date Page 1.00 2011.04.13 - Description Summary First Edition issued All trademarks and registered trademarks are the property of their respective owners. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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