R1LV5256ESP-7SI#B0

R1LV0216BSB 2Mb Advanced LPSRAM (128k word x 16bit) R10DS0273EJ0101 Rev.1.01 2020.2.20 Description The R1LV0216BSB is a family of low voltage 2-Mbit static RAMs organized as 131,072-word by 16-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LV0216BSB has realized higher density, higher performance and low power consumption. The R1LV0216BSB is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. The R1LV0216BSB has been packaged in 44-pin TSOP. Features         Single 2.7V~3.6V power supply Small stand-by current: 1µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS#, LB# and UB# Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Orderable part name R1LV0216BSB-5SI#B1 R1LV0216BSB-5SI#S1 R10DS0273EJ0101 Rev.1.01 2020.2.20 Access time Temperature range Package 55 ns -40 ~ +85°C 400-mil 44pin plastic TSOP (II) Shipping container Tray Embossed tape Page 1 of 12 R1LV0216BSB Pin Arrangement A4 A3 A2 A1 A0 CS# DQ0 DQ1 DQ2 DQ3 Vcc GND DQ4 DQ5 DQ6 DQ7 WE# A16 A15 A14 A13 A12 1 44 A5 2 43 A6 3 42 A7 4 41 OE# 5 40 UB# 6 39 LB# 7 38 DQ15 37 DQ14 9 36 DQ13 10 35 DQ12 11 34 GND 12 33 Vcc 13 32 DQ11 14 31 DQ10 15 30 DQ9 16 29 DQ8 17 28 NC 18 27 A8 19 26 A9 20 25 A10 21 24 A11 22 23 NC 8 44-pin TSOP (II) Pin Description Pin name Function Vcc Vss (GND) A0 to A16 DQ0 to DQ15 CS# Power supply Ground Address input Data input/output Chip select WE# OE# LB# UB# NC Write enable Output enable Lower byte enable Upper byte enable Non connection R10DS0273EJ0101 Rev.1.01 2020.2.20 Page 2 of 12 R1LV0216BSB Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 128k-word x16-bit DQ0 DQ1 A16 DQ BUFFER DQ7 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ8 COLUMN DECODER DQ9 DQ BUFFER CLOCK DQ15 GENERATOR CS# LB# UB# UPPER or LOWER BYTE CONTROL Vcc Vss WE# OE# R10DS0273EJ0101 Rev.1.01 2020.2.20 Page 3 of 12 R1LV0216BSB Operation Table CS# LB# UB# WE# OE# DQ0~7 DQ8~15 Operation H X X X X High-Z High-Z Stand-by X H H X X High-Z High-Z Stand-by L L H L X Din High-Z Write in lower byte L L H H L Dout High-Z Read in lower byte L L H H H High-Z High-Z Output disable L H L L X High-Z Din Write in upper byte L H L H L High-Z Dout Read in upper byte L H L H H High-Z High-Z Output disable L L L L X Din Din Word write L L L H L Dout Dout Word read L H H High-Z High-Z Output disable L Note 1. L H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Symbol Power supply voltage relative to Vss Vcc Terminal voltage on any pin relative to Vss VT Power dissipation PT Operation temperature Topr Storage temperature range Tstg Storage temperature range under bias Tbias Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +4.6V. R10DS0273EJ0101 Rev.1.01 2020.2.20 Value unit -0.5 to +4.6 -0.5*1 to Vcc+0.5*2 0.7 -40 to +85 -65 to 150 -40 to +85 V V W °C °C °C Page 4 of 12 R1LV0216BSB DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 2.7 3.0 3.6 V Vss 0 0 0 V Supply voltage Input high voltage VIH 2.2 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.6 V Ambient temperature range Ta -40 - +85 °C Note Note 1 1. –3.0V for pulse ≤ 30ns (full width at half maximum) DC Characteristics Parameter Input leakage current Output leakage current Average operating current Standby current Symbol | ILI | Min. - Typ. - Max. 1 Unit A | ILO | - - 1 A ICC1 - 15 25 mA ICC2 - 2 5 mA ISB - - 0.5 mA - 1*1 2 A ~+25°C - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C VOH 2.4 - - V IOH = -0.5mA VOH2 Vcc - 0.5 - - V IOH = -0.05mA VOL - - 0.4 V IOL = 2mA Standby current Test conditions Vin = Vss to Vcc CS# = LB# = UB# = VIH or OE# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA, CS# =VIL, Others = VIH/VIL Cycle =1s, duty =100%, II/O = 0mA, CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V (1) CS# = VIH, Others =VIH/VIL or (2) LB# = UB# = VIH, Others =VIH/VIL ISB1 Output high voltage Output low voltage Note Vin = Vss to Vcc, (1) CS# ≥ Vcc-0.2V or (2) LB# = UB# ≥ Vcc-0.2V, CS# ≤ 0.2V 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. Capacitance (Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C) Parameter Symbol Min. Input capacitance C in Input / output capacitance C I/O Note 1. This parameter is sampled and not 100% tested. R10DS0273EJ0101 Rev.1.01 2020.2.20 Typ. - Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 1 1 Page 5 of 12 R1LV0216BSB AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)     Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ CL = 30 pF R10DS0273EJ0101 Rev.1.01 2020.2.20 Page 6 of 12 R1LV0216BSB Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z Symbol Min. Max. Unit Note tRC tAA tACS tOE tOH tBA tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ 55 10 10 10 5 0 0 0 55 55 30 55 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 Symbol Min. Max. Unit Note tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ 55 50 50 45 50 0 0 25 0 5 0 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Note 5 4 6 7 2 1,2 1,2 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS# going low, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS# going low to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode. R10DS0273EJ0101 Rev.1.01 2020.2.20 Page 7 of 12 R1LV0216BSB Timing Waveforms Read Cycle tRC A0~16 tOH tAA tACS CS# tCLZ tCHZ tBA LB#,UB# tBLZ WE# tBHZ VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~15 R10DS0273EJ0101 Rev.1.01 2020.2.20 Valid Data Page 8 of 12 R1LV0216BSB Write Cycle (1) (WE# CLOCK) tWC A0~16 tCW CS# tBW LB#,UB# tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~15 tOW Valid Data tDW R10DS0273EJ0101 Rev.1.01 2020.2.20 tDH Page 9 of 12 R1LV0216BSB Write Cycle (2) (CS# CLOCK) tWC A0~16 tAW tAS tCW tWR CS# tBW LB#,UB# tWP WE# OE# VIH OE# = “H” level tDW DQ0~15 R10DS0273EJ0101 Rev.1.01 2020.2.20 tDH Valid Data Page 10 of 12 R1LV0216BSB Write Cycle (3) (LB#, UB# CLOCK) tWC A0~16 tAW tAS tBW tWR LB#,UB# tCW CS# tWP WE# OE# VIH OE# = “H” level tDW DQ0~15 R10DS0273EJ0101 Rev.1.01 2020.2.20 tDH Valid Data Page 11 of 12 R1LV0216BSB Low Vcc Data Retention Characteristics Parameter Symbol VCC for data retention VDR Min. Typ. Max. Test conditions*2 Unit 2.0 - 3.6 V Vin ≥ 0V, (1) CS# ≥ Vcc-0.2V or (2) LB# = UB# ≥ Vcc-0.2V, CS# ≤ 0.2V - 1*1 2 A ~+25°C Vcc=3.0V, Vin ≥ 0V, Data retention current - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C ICCDR (1) CS# ≥ Vcc-0.2V or (2) LB# = UB# ≥ Vcc-0.2V, CS# ≤ 0.2V Chip deselect time to data retention tCDR 0 ns See retention waveform. Operation recovery time tR 5 ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and Din buffer. If CS# controls data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms (1) CS# Controlled Vcc tCDR 2.7V 2.7V tR VDR 2.2V 2.2V CS# ≥ Vcc - 0.2V CS# (2) LB#, UB# Controlled Vcc tCDR 2.2V LB#, UB# R10DS0273EJ0101 Rev.1.01 2020.2.20 2.7V 2.7V VDR tR 2.2V LB#, UB# ≥ Vcc - 0.2V Page 12 of 12 Revision History Rev. 1.00 1.01 Date 2017.1.27 2020.2.20 Page Last page R1LV0216BSB Data Sheet Description Summary First Edition issued Updated the Notice to the latest version All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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