R1Q5A3636B/R1Q5A3618B
36-Mbit DDRII SRAM 4-word Burst
REJ03C0344-0003 Preliminary Rev. 0.03 Apr.11, 2008
Description
The R1Q5A3636B is a 1,048,576-word by 36-bit, the R1Q5A3618B is a 2,097,152-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
• • • • • • • • • • • • • • 1.8 V ± 0.1 V power supply for core (VDD) 1.4 V to VDD power supply for I/O (VDDQ) DLL circuitry for wide output data valid window and future frequency scaling Pipelined double data rate operation Common data input/output bus Four-tick burst for reduced address frequency Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device Internally self-timed write control Clock-stop capability with µs restart User programmable impedance output Fast clock cycle time: 3.3 ns (300 MHz)/4.0 ns (250 MHz)/ 5.0 ns (200 MHz)/6.0 ns (167 MHz) Simple control logic for easy depth expansion JTAG boundary scan
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology's Sales Dept. regarding specifications
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 1 of 23
R1Q5A3636B/R1Q5A3618B .
Ordering Information
Part Number R1Q5A3636BBG-33R R1Q5A3636BBG-40R R1Q5A3636BBG-50R R1Q5A3636BBG-60R R1Q5A3618BBG-33R R1Q5A3618BBG-40R R1Q5A3618BBG-50R R1Q5A3618BBG-60R Notes: 1. Part Number (0:1) R1 (2:3) Q2 Q3 Q4 Q5 Q6 (4) (5:6) (7:8) A 36 72 36 18 09 2-M word × 18-bit Organization 1-M word × 36-bit Cycle time 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns Clock frequency 300 MHz 250 MHz 200 MHz 167 MHz 300 MHz 250 MHz 200 MHz 167 MHz Package Plastic FBGA 165-pin PLBG0165FB-A Notes
: Renesas Memory prefix : QDRII 2-word Burst SRAM : QDRII 4-word Burst SRAM : DDRII 2-word Burst SRAM : DDRII 4-word Burst SRAM : DDRII 2-word Burst SRAM Separate I/O : VDD=1.8V : Density = 36Mb : Density = 72Mb : Organization = x36 : Organization = x18 : Organization = x9
R : 1stGeneration A : 2ndGeneration B : 3rdGeneration (10:11) BG : Package type=BGA (12:13) 60 : Cycle time=6.0 ns 50 : Cycle time=5.0 ns 40 : Cycle time=4.0 ns 33 : Cycle time=3.3 ns (14) R : Temperature range= 0°C∼ 70°C I : Temperature range= -40°C ∼85°C (15) B : Pb-free T : Tape&Reel S : Pb-free and Tape&Reel None : Standard (Pb and Tray) (16) 0 ∼9 , A ∼Z:Renesas internal use (9)
2. Marking Name Marking Name(0:14) =Part Number (0:14) ------------Pb Marking Name(0:16) =Part Number (0:14)+Bx------------Pb-free (Example) R1Q5A3618BBG-60R ------------Pb R1Q5A3618BBG-60RB0 ------------Pb-free
(x= 0 ∼9 , A ∼Z)
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 2 of 23
R1Q5A3636B/R1Q5A3618B
Pin Arrangement
R1Q5A3636B series
A B C D E F G H J K L M N P R 1 /CQ NC NC NC NC NC NC /DOFF NC NC NC NC NC NC TDO 2 VSS DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R-/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 /BW2 /BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 /K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C /C 7 /BW1 /BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 /LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 NC NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
(Top View) R1Q5A3618B series
A B C D E F G H J K L M N P R 1 /CQ NC NC NC NC NC NC /DOFF NC NC NC NC NC NC TDO 2 VSS DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R-/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 /BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 /K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C /C 7 NC /BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 /LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
(Top View)
Notes: 1. Note that 7C is not SA1. The ×9 product does not permit random start address on the two least significant address bit. SA0, SA1 = 0 at the start of each address. : 2. Address expansion order for future higher density SRAMs (i.e. 72Mb → 144Mb →288Mb): (9A → 3A → 10A) → 2A → 7A → 5B.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 3 of 23
R1Q5A3636B/R1Q5A3618B
Pin Description
Name SAx I/O type Input Descriptions Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst-of-four words (two clock periods of bus activity). SA0 and SA1 are used as the lowest two address bits for burst READ and burst WRITE operations permitting a random burst start address on ×18 and ×36 devices. These inputs are ignored when device is deselected or once burst operation is in progress. Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This definition includes address and READ / WRITE direction. All transactions operate on a burst-of-four data (two clock periods of bus activity). Synchronous read / write Input: When /LD is low, this input designates the access type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R/W must meet the setup and hold times around the rising edge of K. Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first and third output data. The rising edge of C is used as the output timing reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied high to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain VREF level. DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency operation. Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K and /K. Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. The ×9 device uses DQ0 to DQ8. Remaining signals are not used. The ×18 device uses DQ0 to DQ17. Remaining signals are not used. The ×36 device uses DQ0 to DQ35. Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ tristates. IEEE 1149.1 test output: 1.8 V I/O level. Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC Characteristics and Operating Conditions for range. Power supply: Ground. HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. Notes
/LD
Input
R-/W
Input
/BWx
Input
K, /K
Input
C, /C
Input
/DOFF ZQ
Input Input
TMS TDI TCK DQ0 to DQn
Input Input Input/ output
CQ, /CQ TDO VDD VDDQ VSS VREF
Output
Output Supply Supply Supply
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 4 of 23
R1Q5A3636B/R1Q5A3618B
Name I/O type Descriptions No connect: These signals are not internally connected. These signals can be left floating or connected to ground to improve package heat dissipation. Notes
NC
Notes: 1. All power supply and ground balls must be connected for proper operation of the device.
Block Diagram (R1Q5A3636B / R1Q5A3618B series)
SA1 SA0
20/21
Burst Logic
SA1' SA0'
20/21
SA /LD R-/W K R-/W /LD
4/2
Address Registry and Logic
72 /36
Output SA0'' Control Logic
SA0''' ZQ CQ, /CQ
MUX
2 72 /36 72 /36
Write Driver
Sense Amp
Write Register
Output Register
DQ
/BWx K /K
36/18
Data Registry and Logic K
Memory Array
C
C,/C or K,/K
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 5 of 23
Output Select Outpu Buffer
36/18
R1Q5A3636B/R1Q5A3618B
General Description
Power-up and Initialization Sequence The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. After the stable power, there are three possible sequences. 1. Sequence when DLL disable (/DOFF pin fixed low) Just after the stable power and clock (K, /K, C, /C), 1024 NOP cycles (min.) are required for all operations, including JTAG functions, to become normal. 2a. Sequence controlled by /DOFF pin when DLL enable Just after the stable power and clock (K, /K, C, /C), take /DOFF to be high. The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal. 2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable If /DOFF pin is fixed high with unstable clock, the clock (K, /K, C, /C) must be stopped for 30ns (min.). During stop clock stage, C pin must tie low for 30ns (min.).C,/C,K and /K cannot remain VREF level. The additional 1024 NOP cycles (min.) are required to lock the DLL and for all operations to become normal. Notes: 1. After K or C clock is stopped, clock recovery cycles (1024 NOP cycles (min.)) are required for read/write operations to become normal. 2. When DLL is enable and the operating frequency is changed, DLL reset should be required again. After DLL reset again, the 1024 NOP cycles (min.) are needed to lock the DLL. 1. Sequence when DLL disable (/DOFF pin fixed low)
Status Power Up Unstable Clock Stage Stable Clock Stage NOP Stage Normal Operation
VDD VDDQ VREF VIN
1024cycle min.
C, /C,K, /K
2a. Sequence controlled by /DOFF pin when DLL enable
Status Power Up Unstable Clock Stage Stable Clock Stage NOP & DLL Locking Stage Normal Operation
VDD VDDQ VREF /DOFF
1024cycle min.
C, /C,K, /K
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 6 of 23
R1Q5A3636B/R1Q5A3618B 2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
Status
Power Up Unstable Clock Stage Stop Clock Stage NOP & DLL Locking Stage Normal Operation
VDD VDDQ VREF /DOFF
30ns min. 1024cycle min.
C, /C, K, /K
DLL Constraints 1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var. 2. The lower end of the frequency at which the DLL can operate is 119MHz. Programmable Output Impedance 1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5 pF.
Burst Sequence Linear Burst Sequence Table (R1Q5A3636B / R1Q5A3618B series)
SA1, SA0 External address 1st internal burst address 2nd internal burst address 3rd internal burst address 0, 0 0, 1 1, 0 1, 1 SA1, SA0 0, 1 1, 0 1, 1 0, 0 SA1, SA0 1, 0 1, 1 0, 0 0, 1 SA1, SA0 1, 1 0, 0 0, 1 1, 0 Notes
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 7 of 23
R1Q5A3636B/R1Q5A3618B
K Truth Table
Operation Write Cycle: Load address, input write data on consecutive K and /K rising edges Read Cycle: Load address, output read data on consecutive C and /C rising edges NOP (No operation) Standby (Clock stopped) K ↑ /R L /W L D or Q Data in Input data Output clock ↑ L H Data out Output data Output clock ↑ Stopped H × × × Q(A1) /C(t+1)↑ Q(A2) C(t+2)↑ Q(A3) /C(t+2)↑ Q(A4) C(t+3)↑ D(A1) K(t+1)↑ D(A2) /K(t+1)↑ D(A3) K(t+2)↑ D(A4) /K(t+2)↑
High-Z Previous state
Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising edges. 3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. A1 refers to the address input during a WRITE or READ cycle. A2, A3 and A4 refer to the 1st, 2nd and 3rd internal burst address, respectively, in accordance with the linear burst sequence.
Byte Write Truth Table (x36)
Operation Write D0 to D35 Write D0 to D8 Write D9 to D17 Write D18 to D26 Write D27 to D35 Write nothing K ↑ ↑ ↑ ↑ ↑ ↑ /K ↑ ↑ ↑ ↑ ↑ ↑ /BW0 L L L L H H H H H H H H /BW1 L L H H L L H H H H H H /BW2 L L H H H H L L H H H H /BW3 L L H H H H H H L L H H
Notes: 1. H: high level, L: low level, ↑: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 8 of 23
R1Q5A3636B/R1Q5A3618B
Byte Write Truth Table (x18)
Operation Write D0 to D17 Write D0 to D8 Write D9 to D17 Write nothing K ↑ ↑ ↑ ↑ /K ↑ ↑ ↑ ↑ /BW0 L L L L H H H H /BW1 L L H H L L H H
Notes: 1. H: high level, L: low level, ↑: rising edge. 2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
Bus Cycle State Diagram
/LD = H & Count = 4
R-/W = L /LD = L & Count = 4 /LD = L Load New Address Count = 0
Write Double Count = Count + 2
Count =2 Always
Advance Address by Two
/LD = H
NOP
Supply voltage provided Power Up
R-/W = H /LD = L & Count = 4 /LD = H & Count = 4
Read Double Count = Count + 2
Count =2 Always
Advance Address by Two
Notes: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. State machine control timing sequence is controlled by K.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 9 of 23
R1Q5A3636B/R1Q5A3618B
Absolute Maximum Ratings
Parameter Input voltage on any ball Input/output voltage Core supply voltage Output supply voltage Junction temperature Storage temperature Symbol VIN VI/O VDD VDDQ Tj TSTG Rating −0.5 to VDD + 0.5 (2.5 V max.) −0.5 to VDDQ + 0.5 (2.5 V max.) −0.5 to 2.5 −0.5 to VDD +125 (max) −55 to +125 Unit V V V V °C °C Notes 1, 4 1, 4 1, 4 1, 4
Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Notes Power supply voltage --core VDD 1.7 1.8 1.9 V Power supply voltage --I/O VDDQ 1.4 1.5 VDD V Input reference voltage --I/O VREF 0.68 0.75 0.95 V 1 Input high voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 2, 3 Input low voltage VIL (DC) −0.3 VREF − 0.1 V 2, 3 Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS. 3. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.
DC Characteristics
(Ta = 0 to +70°C, VDD = 1.8V ± 0.1V)
Parameter (×18) Operating supply current (×36) (READ / WRITE) Standby supply current (NOP) ×18 / ×36) Symbol IDD IDD −33 Max 700 750 −40 Max 650 700 −50 Max 600 650 −60 Max 550 600 Unit mA mA Notes 1, 2, 3 1, 2, 3
ISB1
380
350
340
330
mA
2, 4, 5
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 10 of 23
R1Q5A3636B/R1Q5A3618B
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Notes: 1. 2. 3. 4. 5. Symbol ILI ILO VOH (Low) VOH VOL (Low) VOL Min −2 −5 VDDQ −0.2 VDDQ/2 −0.08 VSS VDDQ/2 −0.08 Max 2 5 VDDQ VDDQ/2 +0.08 0.2 VDDQ/2 +0.08 Unit µA µA V V V V Test conditions Notes 10 11 8, 9 8, 9 8, 9 8, 9
|IOH| ≤ 0.1 mA Note 6 IOL ≤ 0.1 mA Note 7
All inputs (except ZQ, VREF) are held at either VIH or VIL. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. Operating supply currents are measured at 100% bus utilization. All address / data inputs are static at either VIN > VIH or VIN < VIL. Reference value (Condition=NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.) 6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. 8. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 9. HSTL outputs meet JEDEC HSTL Class I standards. 10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball). 11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Thermal Resistance
Parameter Symbol Typ Junction to Ambient θJA 24.5 Junction to Case θJC 5.6 Note: These parameters are calculated under the condition of wind velocity = 1 m/s. Unit °C/W °C/W Notes
Capacitance
(Ta = +25°C, f=1.0MHz, VDD = 1.8V, VDDQ = 1.5V)
Parameter Symbol Min Typ Input capacitance CIN 2 Clock input capacitance CCLK 2 Input/output capacitance (D, Q, ZQ) CI/O 3 Notes: 1. These parameters are sampled and not 100% tested. 2. Except JTAG (TCK, TMS, TDI, TDO) pins. Max 3 3 4.5 Unit pF pF pF Test conditions VIN = 0 V VCLK = 0 V VI/O = 0 V Notes 1, 2 1, 2 1, 2
AC Test Conditions
(Ta = 0 to +70°C, VDD = 1.8V ±0.1V) Input waveform (Rise/fall time ≤ 0.3 ns)
1.25 V 0.75 V 0.25 V Test points 0.75 V
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 11 of 23
R1Q5A3636B/R1Q5A3618B Output waveform
VDDQ /2
Test points
VDDQ /2
Output load condition
0.75 V VDDQ /2
VREF 50 Ω Z0 = 50 Ω 250 Ω ZQ
SRAM
Q
AC Operating Conditions
Parameter Input high voltage Input low voltage Symbol VIH (AC) VIL (AC) Min VREF + 0.2 Typ Max VREF − 0.2 Unit V V Notes 1, 2, 3, 4 1, 2, 3, 4
Notes: 1. All voltages referenced to VSS (GND). 2. These conditions are for AC functions only, not for AC parameter test. 3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). 4. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC).
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 12 of 23
R1Q5A3636B/R1Q5A3618B
AC Characteristics
(Ta = 0 to +70°C, VDD = 1.8V ± 0.1V)
Parameter Average clock cycle time (K, /K, C, /C) Clock phase jitter (K, /K, C, /C) Clock high time (K, /K, C, /C) Clock low time (K, /K, C, /C) Clock to /clock (K to /K, C to /C) /Clock to clock (/K to K, /C to C) Clock to data clock (K to C, /K to /C) DLL lock time (K, C) K static to DLL reset C, /C high to output valid C, /C high to output hold C, /C high to echo clock valid C, /C high to echo clock hold CQ, /CQ high to output valid CQ, /CQ high to output hold C, /C high to output high-Z Symbol -33 Min 3.30 Max 8.40 Min 4.00 -40 Max 8.40 Min 5.00 -50 Max 8.40 Min 6.00 -60 Max 8.40 Unit Notes
tKHKH
ns
tKC var
0.20
0.20
0.20
0.20
ns
3
tKHKL
1.32
1.60
2.00
2.40
ns
tKLKH
1.32
1.60
2.00
2.40
ns
tKH/KH
1.49
1.80
2.20
2.70
ns
t/KHKH
1.49
1.80
2.20
2.70
ns
tKHCH
0
0.75
0
1.10
0
1.60
0
2.10
ns
tKC lock tKC reset tCHQV
1,024 30
0.45
1,024 30
0.45
1,024 30
0.45
1,024 30
0.50
Cycle ns ns
2 7
tCHQX
-0.45
-0.45
-0.45
-0.50
ns
tCHCQV
0.45
0.45
0.45
0.50
ns
tCHCQX
-0.45
-0.45
-0.45
-0.50
ns
tCQHQV
0.27
0.30
0.35
0.40
ns
4, 7
tCQHQX
-0.27
-0.30
-0.35
-0.40
ns
4, 7
tCHQZ
0.45
0.45
0.45
0.50
ns
5
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 13 of 23
R1Q5A3636B/R1Q5A3618B
Parameter C, /C high to output low-Z Address valid to K rising edge Control inputs valid to K rising edge Data-in valid to K, /K rising edge K rising edge to address hold K rising edge to control inputs hold K, /K rising edge to data-in hold Symbol -33 Min -0.45 Max Min -0.45 -40 Max Min -0.45 -50 Max Min -0.50 -60 Max Unit Notes
tCHQX1
ns
5
tAVKH
0.40
0.50
0.60
0.70
ns
1
tIVKH
0.40
0.50
0.60
0.70
ns
1
tDVKH
0.30
0.35
0.40
0.50
ns
1
tKHAX
0.40
0.50
0.60
0.70
ns
1
tKHIX
0.40
0.50
0.60
0.70
ns
1
tKHDX
0.30
0.35
0.40
0.50
ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured ±100 mV from steady-state voltage. 6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV. 7. These parameters are sampled. Remarks: 1. 2. 3. 4. 5.
Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. Control input signals may not be operated with pulse widths less than tKHKL (min). If C, /C are tied high, K, /K become the references for C, /C timing parameters. VDDQ is +1.5 V DC. Control signals are /LD, R-/W, /BW, /BW0, /BW1, /BW2 and /BW3. BWn signals must operate at the same timing as Data in.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 14 of 23
Read and Write Timing
Timing Waveforms
R1Q5A3636B/R1Q5A3618B
REJ03C0344-0003 Rev.0.03 Apr.11, 2008
4 READ (burst of 4) NOP NOP WRITE (burst of 4) 5 7 8 10 13 READ (burst of 4) 6 9 12 11 WRITE (burst of 4) tKLKH 01 1x 00 1x 00 01 tKH/KH t/KHKH A1 A2 A3 A4 Q01 tCHQZ tCHQV -tCHQX tCQHQV -tCQHQX tDVKH tKHDX tCHQV -tCHQX tDVKH tKHDX Q02 Q03 Q04 Q11 Q12 Q13 Q14 D21 D22 D23 D24 D31 D32 D33 D34 Q41 tCHCQV -tCHCQX tCHCQV -tCHCQX tKH/KH tKLKH t/KHKH
page 15 of 23
1
2
3
NOP
READ (burst of 4)
K
K, /K
/K
tKHKH
tKHKL
/LD:R-/W
01
tIVKH
tKHIX
SA
A0
tAVKH Qx4
tKHAX
DQ
-tCHQX1
CQ
/CQ
tKHCH
tKHKH
C
tKHCH
tKHKL
/C
R1Q5A3636B/R1Q5A3618B
Notes: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disable (high-Z) one clock cycle after a NOP. 3. In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32, etc. Write data is forwarded immediately as read results. 4. To control read and write operations, /BW signals must operate at the same timing as Data in. 5. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention.
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1,and may be left unconnected. But they may also be tied to VDD through a 1kΩ resistor.TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O TCK TMS TDI Pin assignments 2R 10R 11R Description Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test mode select. This is the command input for the TAP controller state machine. Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Notes
TDO
1R
Notes: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
TAP DC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8V ± 0.1V)
Parameter Input high voltage Input low voltage Input leakage current Output leakage current Output low voltage Symbol VIH VIL ILI ILO Min +1.3 −0.3 −5.0 −5.0 Typ Max VDD + 0.3 +0.5 +5.0 +5.0 Unit V V µA µA Notes
0 V ≤ VIN ≤ VDD 0 V ≤ VIN ≤ VDD, output disabled IOLC = 100 µA IOLT = 2 mA |IOHC| = 100 µA |IOHT| = 2 mA
VOL1 0.2 V VOL2 0.4 V Output high voltage VOH1 1.6 V VOH2 1.4 V Notes: 1. All voltages referenced to VSS (GND). 2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms. 3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V. 4. ZQ: VIH = VDDQ.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 16 of 23
R1Q5A3636B/R1Q5A3618B
TAP AC Test Conditions
Parameter Temperature Input timing measurement reference levels Input pulse levels Input rise/fall time Output timing measurement reference levels Test load termination supply voltage (VTT) Output load Symbol Ta VREF VIL, VIH tr, tf Conditions 0 ≤ Ta ≤ +70 0.9 0 to 1.8 ≤ 1.0 0.9 0.9 See figures Unit °C V V ns V V Notes
Input waveform
1.8 V 0.9 V 0V Test points 0.9 V
Output waveform
0.9 V
Test points
0.9 V
Output load condition
VTT = 0.9 V DUT 50 Ω Z0 = 50 Ω 20 pF
TDO
External Load at Test
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 17 of 23
R1Q5A3636B/R1Q5A3618B
TAP AC Operating Characteristics
(Ta = 0 to +70°C, VDD = 1.8V ±0.1V)
Parameter Symbol Min Typ Max Unit Test clock (TCK) cycle time tTHTH 100 ns TCK high pulse width tTHTL 40 ns TCK low pulse width tTLTH 40 ns Test mode select (TMS) setup tMVTH 10 ns TMS hold tTHMX 10 ns Capture setup tCS 10 ns Capture hold tCH 10 ns TDI valid to TCK high tDVTH 10 ns TCK high to TDI invalid tTHDX 10 ns TCK low to TDO unknown tTLQX 0 ns TCK low to TDO valid tTLQV 20 ns Notes: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. Notes
1 1
TAP Controller Timing Diagram
tTHTH tTHTL tTLTH
TCK tMVTH tTHMX
TMS tDVTH tTHDX
TDI tTLQV
TDO tTLQX tCS tCH
PI (SRAM)
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 18 of 23
R1Q5A3636B/R1Q5A3618B
Test Access Port Registers
Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bits 32 bits 109 bits Symbol IR [2:0] BP ID [31:0] BS [109:1] Notes
TAP Controller Instruction Set
IR2 0 IR1 0 IR0 0 Instruction EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z), moving the TAP controller into the capture-DR state loads the data in the RAMs input into the boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. The RESERVED instructions are not implemented but are reserved for future use. Do not use these instructions. When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. 3 3, 4 Notes 1, 2, 3
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0 1
1 0
1 0
RESERVED SAMPLE (/PRELOAD)
1 1 1
0 1 1
1 0 1
RESERVED RESERVED BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. 3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. 4. Clock recovery initialization cycles are required to return from the SAMPLE-Z instruction.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 19 of 23
R1Q5A3636B/R1Q5A3618B
Boundary Scan Order Boundary Scan Order
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Ball ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A Signal names x18 x36 /C /C C C SA SA SA SA SA SA SA SA SA SA SA SA SA SA DQ0 DQ0 DNU DQ9 DNU DNU DNU DNU DQ1 DQ11 DNU DQ10 DNU DNU DNU DNU DQ2 DQ2 DNU DQ1 DNU DNU DNU DNU DQ3 DQ3 DNU DQ12 DNU DNU DNU DNU DQ4 DQ13 DNU DQ4 ZQ ZQ DNU DNU DNU DNU DQ5 DQ5 DNU DQ14 DNU DNU DNU DNU DQ6 DQ6 DNU DQ15 DNU DNU DNU DNU DQ7 DQ17 DNU DQ16 DNU DNU DQ8 DNU DNU DNU CQ SA SA DNU DNU DQ8 DQ7 DNU DNU CQ DNU SA Bit # 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Ball ID 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M Signal names x18 x36 SA SA SA1 SA1 SA0 SA0 /LD /LD DNU /BW1 /BW0 /BW0 K K /K /K DNU /BW3 /BW1 /BW2 R-/W R-/W SA SA SA SA SA SA VSS VSS /CQ /CQ DQ9 DQ27 DNU DQ18 DNU DNU DNU DNU DQ10 DQ19 DNU DQ28 DNU DNU DNU DNU DQ11 DQ20 DNU DQ29 DNU DNU DNU DNU DQ12 DQ30 DNU DQ21 DNU DNU DNU DNU DQ13 DQ22 DNU DQ31 /DOFF /DOFF DNU DNU DNU DNU DQ14 DQ23 DNU DQ32 DNU DNU DNU DQ15 DNU DNU DNU DQ16 DNU DNU DNU DNU DQ33 DQ24 DNU DNU DQ25 DQ34 DNU DNU
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 20 of 23
R1Q5A3636B/R1Q5A3618B
Bit # 99 100 101 102 103 104
Ball ID 3P 2N 2P 1P 3R 4R
Signal names x18 x36 DQ17 DNU DNU DNU SA SA DQ26 DQ35 DNU DNU SA SA
Signal names Bit # 105 106 107 108 109 Ball ID 4P 5P 5N 5R x18 SA SA SA SA INTERNAL x36 SA SA SA SA INTERNAL
Notes: In boundary scan mode, 1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z). 3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K (except EXTEST, SAMPLE-Z). 4. ZQ must be driven to VDDQ supply to ensure consistent results.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 21 of 23
R1Q5A3636B/R1Q5A3618B
ID Register
Part R1Q5A3636B R1Q5A3618B Revision number (31:29) 000 000 Type number (28:12) 0 0MMM 0WW0 10Q0 B0S0 0 0010 0110 1000 1000 0 0010 0100 1000 1000 010:36Mb, 10: x 18, 0: DDR 0: 2-word burst 0: Common I/O Vendor JEDEC code (11:1) 0100 0100 011 0100 0100 011 001:18Mb 00: x 9, Start bit (0) 1 1
Notes: 1. Type number MMM :Density WW :Organization Q :QDR/DDR B :Burst lengths S :I/O
011:72Mb, 11: x 36, 1: QDR, 1: 4-word burst, 1: Separate I/O,
01: x 8
TAP Controller State Diagram Package Dimensions
1 Test Logic Reset 0 Run Test/Idle 0 1 1 Select DR Scan 0 Capture DR 0 Shift DR 1 Exit1 DR 0 Pause DR 0 1 Exit2 DR 1 Update DR 1 0 1 0 1 0 0 1 1 Select IR Scan 0 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 0 1 0 0 1
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK.
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 22 of 23
R1Q5A3636B/R1Q5A3618B
Package Dimensions
R1Q5A3636B/R1Q5A3618B (PLBG0165FB-A)
JEITA Package Code P-LBGA165-15x17-1.00 RENESAS Code PLBG0165FB-A Previous Code BP-165A MASS[Typ.] 0.7g
D A B
INDEX
y1 S S
A
y
S e
R P N M L K J H G F E D C B A
e
A1
E
Reference Symbol
Dimension in Millimeters
Min 14.90 16.90
Nom 15.00 17.00
Max 15.10 17.10
D E v w A A1 e b x
1 2 3 4 5 6 7 8 9 10 11
1.34 0.27 0.45
1.40 0.32 1.00 0.50
1.46 0.37 0.55 0.20 0.15 0.25
φb
y
φ× M S A B φ0.07 M S
y1 SD SE ZD ZE
REJ03C0344-0003 Rev.0.03 Apr.11, 2008 page 23 of 23
Revision History
R1Q5A3636B/R1Q5A3618B Data Sheet
Contents of Modification Description
Rev. 0.01 0.02
Date Jan.31, 2008 Mar.17,2008
Page Initial issue P7 DLL Constraints 2.the lower end of the frequency at which the DLL can operate is 119MHz P13 AC characteristics Average clock cycle time is enlarged tKHKH(-33)(max) 8.40ns, tKHKH(-40)(max) 8.40ns, tKHKH(-50)(max) 8.40ns, tKHKH(-60)(max) 8.40ns P2 Ordering Infomatuon: Adding Part Number and Marking Name 1.Part Number (9) R: 1stGeneration,A: 2ndGeneration,B: 3rdGeneration (10:11) BG: Package type=BGA (12:13) 60: Cycle time=6.0 ns,50 : Cycle time=5.0 ns,40: Cycle time=4.0 ns 33: Cycle time=3.3 ns (14) R: Temperature range= 0°C ∼70°C,I: Temperature range= -40°C ∼85°C (15) B: Pb-free,T: Tape&Reel,S: Pb-free and Tape&Reel None: Standard (Pb and Tray) (16) 0 ∼9 , A ∼Z:Renesas internal use 2.Marking Name Marking Name(0:14) =Part Number (0:14) ------------Pb Marking Name(0:16) =Part Number (0:14)+Bx------------Pb-free (x=0 ∼9 , A ∼Z) (Example) R1Q5A3618BBG-60R ------------Pb R1Q5A3618BBG-60RB0 ------------Pb-free
0.03
Apr.11,2008
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