R1RW0404D

R1RW0404D Series 4M High Speed SRAM (1-Mword × 4-bit) REJ03C0115-0100Z Rev. 1.00 Mar.12.2004 Description The R1RW0404D is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The R1RW0404D is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features • Single supply: 3.3 V ± 0.3 V • Access time: 12 ns (max) • Completely static memory  No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible  All inputs and outputs • Operating current: 100 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current : 5 mA (max) : 0.8 mA (max) (L-version) • Data retention current: 0.4 mA (max) (L-version) • Data retention voltage: 2 V (min) (L-version) • Center VCC and VSS type pin out Rev.1.00, Mar.12.2004, page 1 of 11 R1RW0404D Series Ordering Information Type No. R1RW0404DGE-2PR R1RW0404DGE-2LR Access time 12 ns 12 ns Package 400-mil 32-pin plastic SOJ (32P0K) Pin Arrangement 32-pin SOJ A0 A1 A2 A3 A4 CS# I/O1 VCC VSS I/O2 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE# I/O4 VSS VCC I/O3 A14 A13 A12 A11 A10 NC Pin Description Pin name A0 to A19 I/O1 to I/O4 CS# OE# WE# VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Power supply Ground No connection Rev.1.00, Mar.12.2004, page 2 of 11 R1RW0404D Series Block Diagram (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 A1 (MSB) I/O1 . . . I/O4 VCC Row decoder 1024-row × 64-column × 16-block × 4-bit (4,194,304 bits) VSS CS Column I/O Input data control Column decoder CS WE# CS# A8 A9 A19 A17 A18 A15 A0 A2 A4 A16 (LSB) (MSB) OE# CS Rev.1.00, Mar.12.2004, page 3 of 11 R1RW0404D Series Operation Table CS# H L L L L OE# × H L H L WE# × H H L L Mode Standby Output disable Read Write Write VCC current ISB, ISB1 ICC ICC ICC ICC I/O High-Z High-Z DOUT DIN DIN Ref. cycle   Read cycle (1) to (3) Write cycle (1) Write cycle (2) Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Supply voltage relative to VSS Voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value −0.5 to +4.6 −0.5* to VCC + 0.5* 1 2 Unit V V W °C °C °C 1.0 0 to +70 −55 to +125 −10 to +85 Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Input voltage Notes: 1. 2. 3. 4. Symbol VCC* VSS* VIH VIL 3 4 Min 3.0 0 2.0 −0.5* 1 Typ 3.3 0   Max 3.6 0 VCC + 0.5* 0.8 2 Unit V V V V VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Rev.1.00, Mar.12.2004, page 4 of 11 R1RW0404D Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) Parameter Input leakage current Output leakage current Operation power supply current Symbol IILII IILOI ICC Min    Max 2 2 100 Unit µA µA mA Test conditions VIN = VSS to VCC VIN = VSS to VCC Min cycle CS# = VIL, lOUT = 0 mA Other inputs = VIH/VIL Min cycle, CS# = VIH, Other inputs = VIH/VIL f = 0 MHz VCC ≥ CS# ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V IOL = 8 mA IOH = −4 mA Standby power supply current ISB ISB1   40 5 mA mA * Output voltage Note: VOL VOH  2.4 1 0.8* 0.4  1 V V 1. This characteristics is guaranteed only for L-version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance* Note: 1 1 Symbol CIN CI/O Min   Max 6 8 Unit pF pF Test conditions VIN = 0 V VI/O = 0 V Input/output capacitance* 1. This parameter is sampled and not 100% tested. Rev.1.00, Mar.12.2004, page 5 of 11 R1RW0404D Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) 1.5 V 3.3 V 319Ω DOUT 30 pF 353 Ω 5 pF DOUT Zo=50 Ω RL=50 Ω Output load (A) Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Read Cycle R1RW0404D -2 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ Min 12    3 3 0   Max  12 12 6    6 6 Unit ns ns ns ns ns ns ns ns ns 1 1 1 1 Notes Rev.1.00, Mar.12.2004, page 6 of 11 R1RW0404D Series Write Cycle R1RW0404D -2 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Symbol tWC tAW tCW tWP tAS tWR tDW tDH tOW tOHZ tWHZ Min 12 8 8 8 0 0 6 0 3   Max          6 6 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 1 9 8 6 7 Notes Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS# transition low. 3. WE# and/or CS# must be high during address transition time. 4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, output remains a high impedance state. 6. tAS is measured from the latest address transition to the later of CS# or WE# going low. 7. tWR is measured from the earlier of CS# or WE# going high to the first address transition. 8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest transition among CS# going low and WE# going low. A write ends at the earliest transition among CS# going high and WE# going high. tWP is measured from the beginning of write to the end of write. 9. tCW is measured from the later of CS# going low to the end of write. Rev.1.00, Mar.12.2004, page 7 of 11 R1RW0404D Series Timing Waveforms Read Timing Waveform (1) (WE# = VIH) tRC Address Valid address tAA tACS tOH tCHZ CS# tOE OE# tOLZ tCLZ DOUT High impedance Valid data tOHZ Read Timing Waveform (2) (WE# = VIH, CS# = VIL, OE# = VIL) tRC Address tOH DOUT Valid address tAA tOH Valid data Rev.1.00, Mar.12.2004, page 8 of 11 R1RW0404D Series Read Timing Waveform (3) (WE# = VIH, CS# = VIL, OE# = VIL)* tRC CS# tACS tCLZ DOUT High impedance Valid data High impedance tCHZ 2 Write Timing Waveform (1) (WE# Controlled) tWC Address Valid address tAW OE# tCW CS#*3 tAS WE#*3 tOHZ DOUT High impedance*5 tDW DIN *4 tDH *4 tWP tWR Valid data Rev.1.00, Mar.12.2004, page 9 of 11 R1RW0404D Series Write Timing Waveform (2) (CS# Controlled) tWC Address Valid address tCW CS# *3 tAW tWP WE# *3 tAS tWHZ DOUT tOW High impedance*5 tDW DIN *4 tDH *4 tWR Valid data Rev.1.00, Mar.12.2004, page 10 of 11 R1RW0404D Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. Parameter VCC for data retention Symbol VDR Min 2.0 Max  Unit V Test conditions VCC ≥ CS# ≥ VCC − 0.2 V (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V VCC = 3 V, VCC ≥ CS# ≥ VCC − 0.2 V (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V See retention waveform Data retention current ICCDR  400 µA Chip deselect to data retention time Operation recovery time tCDR tR 0 5   ns ms Low VCC Data Retention Timing Waveform t CDR V CC 3.0 V Data retention mode tR V DR 2.0 V CS# 0V VCC ≥ CS# ≥ VCC − 0.2 V Rev.1.00, Mar.12.2004, page 11 of 11 Revision History Rev. Date R1RW0404D Series Data Sheet Contents of Modification Page Description Initial issue Deletion of Preliminary   0.01 1.00 Oct. 01, 2003 Mar.12.2004 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. 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