R1RW0416DSB-2LR

R1RW0416D Series 4M High Speed SRAM (256-kword × 16-bit) REJ03C0107-0100Z Rev. 1.00 Mar.12.2004 Description The R1RW0416D is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The R1RW0416D is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting. Features • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 12 ns (max) • Completely static memory  No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible  All inputs and outputs • Operating current: 130 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current : 5 mA (max) : 0.8 mA (max) (L-version) • Data retention current: 0.4 mA (max) (L-version) • Data retention voltage: 2.0 V (min) (L-version) • Center VCC and VSS type pin out Rev.1.00, Mar.12.2004, page 1 of 14 R1RW0416D Series Ordering Information Type No. R1RW0416DGE-2PR R1RW0416DGE-2LR R1RW0416DSB-2PR R1RW0416DSB-2LR Access time 12 ns 12 ns 12 ns 12 ns 400-mil 44-pin plastic TSOPII (44P3W-H) Package 400-mil 44-pin plastic SOJ (44P0K) Pin Arrangement 44-pin SOJ A0 A1 A2 A3 A4 CS# I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE# UB# LB# I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 A0 A1 A2 A3 A4 CS# I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-pin TSOP 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE# UB# LB# I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 (Top View) (Top View) Rev.1.00, Mar.12.2004, page 2 of 14 R1RW0416D Series Pin Description Pin name A0 to A17 I/O1 to I/O16 CS# OE# WE# UB# LB# VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Upper byte select Lower byte select Power supply Ground No connection Rev.1.00, Mar.12.2004, page 3 of 14 R1RW0416D Series Block Diagram (LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 (MSB) A1 I/O1 . . . I/O8 I/O9 . . . I/O16 WE# CS# LB# UB# VCC Row decoder Memory matrix 1024 rows × 32 columns × 8 blocks × 16 bit (4,194,304 bits) VSS CS Column I/O Input data control Column decoder CS (LSB) A8 A9 A17 A15 A16 A0 A2 A4 (MSB) OE# CS Rev.1.00, Mar.12.2004, page 4 of 14 R1RW0416D Series Operation Table CS# OE# WE# LB# UB# Mode H L L L L L L L L L × H L L L L × × × × × H H H H H L L L L × × L L H H L L H H × × L H L H L H L H Standby Output disable Read VCC current ISB, ISB1 ICC ICC I/O1−I/O8 High-Z High-Z Output Output High-Z High-Z Input Input High-Z High-Z I/O9−I/O16 High-Z High-Z Output High-Z Output High-Z Input High-Z Input High-Z Ref. cycle   Read cycle Read cycle Read cycle  Write cycle Write cycle Write cycle  Lower byte read ICC Upper byte read ICC  Write ICC ICC Lower byte write ICC Upper byte write ICC  ICC Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Supply voltage relative to VSS Voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value −0.5 to +4.6 −0.5* to VCC + 0.5* 1 2 Unit V V W °C °C °C 1.0 0 to +70 −55 to +125 −10 to +85 Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Symbol VCC* VSS* Input voltage Notes: 1. 2. 3. 4. VIH VIL 3 4 Min 3.0 0 2.0 −0.5* 1 Typ 3.3 0   Max 3.6 0 VCC + 0.5* 0.8 2 Unit V V V V VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Rev.1.00, Mar.12.2004, page 5 of 14 R1RW0416D Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) Parameter Input leakage current Output leakage current Operating power supply current Symbol |ILI| |ILO| ICC Min    Max 2 2 130 Unit µA µA mA Test conditions VIN = VSS to VCC VIN = VSS to VCC Min cycle CS# = VIL, IOUT = 0 mA Other inputs = VIH/VIL Min cycle, CS# = VIH, Other inputs = VIH/VIL f = 0 MHz VCC ≥ CS# ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V IOL = 8 mA IOH = −4 mA Standby power supply current ISB ISB1   40 5 mA mA * Output voltage Note: VOL VOH  2.4 1 0.8* 0.4  1 mA V V 1. This characteristics is guaranteed only for L-version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance* Note: 1 1 Symbol CIN CI/O Min   Max 6 8 Unit pF pF Test conditions VIN = 0 V VI/O = 0 V Input/output capacitance* 1. This parameter is sampled and not 100% tested. Rev.1.00, Mar.12.2004, page 6 of 14 R1RW0416D Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) 1.5 V RL = 50 Ω DOUT Zo = 50 Ω 30 pF DOUT 353 Ω 3.3 V 319 Ω 5 pF Output load (A) Output load (B) (for tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, and tOW) Read Cycle R1RW0416D -2 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Byte select to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Byte select to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Byte deselect to output in high-Z Symbol tRC tAA tACS tOE tBA tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ Min 12     3 3 0 0    Max  12 12 6 6     6 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 Notes Rev.1.00, Mar.12.2004, page 7 of 14 R1RW0416D Series Write Cycle R1RW0416D -2 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Byte select to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 12 8 8 8 8 0 0 6 0 3   Max           6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 5 6 8 7 Notes Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or after the WE# transition, output remains a high impedance state. 3. WE# and/or CS# must be high during address transition time. 4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going low. 6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address transition. 7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A write begins at the latest transition among CS# going low, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB# going high. 8. tCW is measured from the later of CS# going low to the end of write. Rev.1.00, Mar.12.2004, page 8 of 14 R1RW0416D Series Timing Waveforms Read Timing Waveform (1) (WE# = VIH) t RC Address tAA tACS CS# tOE OE# tBA LB#, UB# tBLZ *1 tOLZ *1 tCLZ *1 High impedance *4 *4 tBHZ *1 tOH tOHZ *1 tCHZ *1 Valid address DOUT Valid data Rev.1.00, Mar.12.2004, page 9 of 14 R1RW0416D Series Read Timing Waveform (2) (WE# = VIH, LB# = VIL, UB# = VIL) tRC Address Valid address tAA tACS tOH tCHZ*1 CS# tOE OE# tOLZ*1 tCLZ *1 DOUT High impedance *4 Valid data *4 tOHZ*1 Rev.1.00, Mar.12.2004, page 10 of 14 R1RW0416D Series Write Timing Waveform (1) (WE# Controlled) tWC Address tAW tAS WE#*3 tCW CS#*3 tWP Valid address tWR OE# tBW LB#, UB# tWHZ tOHZ DOUT *2 High impedance tOLZ tOW tDW tDH Valid data DIN Rev.1.00, Mar.12.2004, page 11 of 14 R1RW0416D Series Write Timing Waveform (2) (CS# Controlled) tWC Address Valid address tAW tAS tWP tWR WE# *3 tCW CS# *3 OE# tBW LB#, UB# tWHZ tOHZ High impedance * DOUT *2 tDW tDH Valid data 4 tOLZ tOW DIN Rev.1.00, Mar.12.2004, page 12 of 14 R1RW0416D Series Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH) tWC Address tAW tWP WE#*3 tCW CS#*3 tAS UB# (LB#) tBW LB# (UB#) tDW DIN-UB (DIN-LB) tDH tBW Valid address tWR Valid data tDW tDH DIN-LB (DIN-UB) Valid data DOUT High impedance Rev.1.00, Mar.12.2004, page 13 of 14 R1RW0416D Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. Parameter VCC for data retention Symbol VDR Min 2.0 Max  Unit V Test conditions VCC ≥ CS# ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V VCC = 3 V VCC ≥ CS# ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V See retention waveform Data retention current ICCDR  400 µA Chip deselect to data retention time Operation recovery time tCDR tR 0 5   ns ms Low VCC Data Retention Timing Waveform t CDR V CC 3.0 V Data retention mode tR V DR 2.0 V CS# 0V VCC ≥ CS# ≥ VCC – 0.2 V Rev.1.00, Mar.12.2004, page 14 of 14 Revision History Rev. Date R1RW0416D Series Data Sheet Contents of Modification Page Description Initial issue Deletion of Preliminary   0.01 1.00 Sep. 30, 2003 Mar.12.2004 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. 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