R1WV6416RSA-5SI#B0

R1WV6416R Series 64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit) REJ03C0368-0100 Rev.1.00 2009.05.07 Description The R1WV6416R Series is a family of low voltage 64-Mbit static RAMs organized as 4,194,304-word by 16-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1WV6416R Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. The R1WV6416R Series is provided in 48-pin thin small outline package [TSOP (I): 12mm x 20mm with pin pitch of 0.5mm], 52-pin micro thin small outline package [µTSOP (II): 10.79mm x 10.49mm with pin pitch of 0.4mm] and 48-ball fine pitch ball grid array [f-BGA] package. It gives the best solution for compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • • • • • • • • Single 2.7~3.6V power supply Small stand-by current: 8 µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1#, CS2, LB# and UB# Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Type No. R1WV6416RSA-5S% R1WV6416RSA-7S% R1WV6416RSD-5S% R1WV6416RSD-7S% R1WV6416RBG-5S% R1WV6416RBG-7S% Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns % R I 350 mil 52-pin plastic μ-TSOP (II) (normal-bend type) (52PTG) f-BGA 0.75mm pitch 48-ball % - Temperature version; see table below Temperature Range 0 ~ +70 °C -40 ~ +85 °C REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 1 of 16 Package 12mm x 20mm 48-pin plastic TSOP (I) (normal-bend type) (48P3R) R1WV6416R Series Pin Arrangement A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 Vss A11 5 48 LB# A10 6 47 DQ15/A-1 A9 7 46 DQ7 A8 8 45 DQ14 A19 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 A21 16 37 DQ3 A20 17 36 DQ10 A18 18 35 DQ2 A17 19 34 DQ9 A7 20 33 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 Vss A2 25 28 NC A1 26 27 A0 52-pin μTSOP (II) 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B DQ15 UB# A3 A4 CS1# DQ0 C DQ13 DQ14 A5 A6 DQ1 DQ2 D Vss DQ12 A17 A7 DQ3 Vcc E Vcc DQ11 A21 A16 DQ4 Vss F DQ10 DQ9 A14 A15 DQ6 DQ5 G DQ8 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 48-pin f-BGA (TOP VIEW) A15 1 48 A16 A14 2 47 BYTE# A13 3 46 Vss A12 4 45 DQ15/A-1 A11 5 44 DQ7 A10 6 43 DQ14 A9 7 42 DQ6 A8 8 41 DQ13 A19 9 40 DQ5 A20 10 39 DQ12 WE# 11 38 DQ4 CS2 12 37 Vcc A21 13 36 DQ11 UB# 14 35 DQ3 LB# 15 34 DQ10 A18 16 33 DQ2 A17 17 32 DQ9 A7 18 31 DQ1 A6 19 30 DQ8 A5 20 29 DQ0 A4 21 28 OE# A3 22 27 Vss A2 23 26 CS1# A1 24 25 A0 REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 2 of 16 48-pin TSOP (I) R1WV6416R Series Pin Description Pin name Vcc Vss A0 to A21 A-1 to A21 DQ0 to DQ15 CS1# CS2 WE# OE# LB# UB# BYTE# NC Function Power supply Ground Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte enable Upper byte enable Byte control mode enable Non connection Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 3 of 16 R1WV6416R Series Block Diagram A0 A1 MEMORY ARRAY ADDRESS ROW BUFFER DECODER 2M-word x16-bit or 4M-word x 8-bit DQ DQ0 DQ1 BUFFER A21 DQ7 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ8 DQ9 COLUMN DECODER DQ BUFFER CLOCK CS2 DQ15 / A -1 GENERATOR CS1# LB# Vcc X8 / x16 UB# CONTROL Vss BYTE# WE# OE# 32Mb SRAM #1 32Mb SRAM #2 Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 4 of 16 R1WV6416R Series Operation Table CS1# CS2 BYTE# LB# UB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation H X X X X X X High-Z High-Z High-Z Stand-by X L X X X X X High-Z High-Z High-Z Stand-by X X H H H X X High-Z High-Z High-Z Stand-by L H H L H L X Din High-Z High-Z Write in lower byte L H H L H H L Dout High-Z High-Z Read in lower byte L H H L H H H High-Z High-Z High-Z Output disable L H H H L L X High-Z Din Din Write in upper byte L H H H L H L High-Z Dout Dout Read in upper byte L H H H L H H High-Z High-Z High-Z Output disable L H H L L L X Din Din Din Word write L H H L L H L Dout Dout Dout Word read L H H L L H H High-Z High-Z High-Z Output disable L H L L L L X Din High-Z A-1 Byte write L H L L L H L Dout High-Z A-1 Byte read L H L L L H H High-Z High-Z A-1 Output disable Note1. H: VIH L:VIL X: VIH or VIL 2. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. 3. When apply BYTE# =“L”, please assign LB#=UB#=“L”. Absolute Maximum Ratings Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Symbol Vcc VT PT Topr*3 unit V V W °C °C °C R ver. Value -0.5 to +4.6 -0.5*1 to Vcc+0.3*2 0.7 0 to +70 -40 to +85 -65 to 150 0 to +70 I ver. -40 to +85 °C R ver. I ver. Tstg Tbias*3 Note 1. –2.0V in case of AC (Pulse width ≤30ns) 2. Maximum voltage is +4.6V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 5 of 16 °C R1WV6416R Series Recommended Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range Symbol Min. Typ. Max. Unit Vcc Vss VIH VIL 2.7 0 2.4 -0.2 3.0 0 - 3.6 0 0.4 V V V V 0 - +70 °C 1 2 °C 2 R ver. Vcc+0.2 Ta I ver. -40 +85 Note 1. –2.0V in case of AC (Pulse width ≤ 30ns) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. Note DC Characteristics Parameter Input leakage current Output leakage current Symbol Min. Typ. Max. Unit | ILI | - - 1 μA | ILO | - - 1 μA ICC1 - 45*1 60 mA ICC2 - 5*1 10 mA ISB - 0.1*1 0.3 mA - 8*1 24 μA - 14*2 48 μA - - 100 μA - - 160 μA VOH 2.4 - - V VOL - - 0.4 V Average operating current Standby current Standby current ISB1 Output high voltage Output low voltage Test conditions*3 Vin = Vss to Vcc BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# =VIH or CS2 =VIL or OE# =VIH or WE# =VIL or LB# = UB# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1μs, duty =100%, II/O = 0mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS2 =VIL Vin ≥ 0V ~+25°C BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ~+40°C (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or ~+70°C (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, ~+85°C CS2 ≥ VCC-0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOH = -0.5mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOL = 2mA Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested. 3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 6 of 16 R1WV6416R Series Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Typ. Input capacitance C in Input / output capacitance C I/O Note1.This parameter is sampled and not 100% tested. Max. 20 20 Unit pF pF Test conditions Vin =0V V I/O =0V AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) 1.4V RL = 500 ohm DQ CL = 30 pF Note1. Ambient temperature range depends on R/I-version. Please see table on page 1. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 7 of 16 Note 1 1 R1WV6416R Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 8 of 16 R1WV6416R**-5S Min. 55 10 10 10 5 5 0 0 0 0 Max. 55 55 55 25 55 20 20 20 20 R1WV6416R**-7S Min. 70 10 10 10 5 5 0 0 0 0 Max. 70 70 70 35 70 25 25 25 25 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2,3 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 1,2,3 R1WV6416R Series Write Cycle Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ R1WV6416R**-5S Min. 55 50 50 40 50 0 0 25 0 5 0 0 Max. 20 20 R1WV6416R**-7S Min. 70 65 65 55 65 0 0 35 0 5 0 0 Max. 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note 5 4 6 7 2 1,2 1,2 Note1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 9 of 16 R1WV6416R Series BYTE# Timing Conditions Parameter Byte setup time Byte recovery time Symbol tBS tBR R1WV6416R**-5S Min. 5 5 Max. - R1WV6416R**-7S Min. 5 5 BYTE# Timing Waveforms CS1# CS2 tBS BYTE# REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 10 of 16 tBR Max. - Unit ms ms Note R1WV6416R Series Timing Waveforms Read Cycle*1 tRC A0~21 (Word Mode) A -1~21 tBA LB#,UB# tBLZ tBHZ tACS1 CS1# tCHZ1 tCLZ1 CS2 tACS2 tCHZ2 tCLZ2 WE# tOH tAA (Byte Mode) VIH WE# = “H” level VIL tOE OE# tOLZ DQ0~15 High impedance (Word Mode) DQ0~7 (Byte Mode) Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 11 of 16 tOHZ Valid Data R1WV6416R Series Write Cycle (1)*1 (WE# CLOCK) tWC A0~21 (Word Mode) A -1~21 tOH (Byte Mode) tBW LB#,UB# tCW CS1# tCW CS2 tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ tOW DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 12 of 16 Valid Data tDW tDH R1WV6416R Series Write Cycle (2)*1 (CS1#, CS2 CLOCK) tWC A0~21 (Word Mode) A -1~21 tAW (Byte Mode) tBW LB#,UB# tAS tCW tWR tAS tCW tWR CS1# CS2 tWP WE# OE# OE# = “H” level VIH VIL tDW tDH DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 13 of 16 Valid Data R1WV6416R Series Write Cycle (3)*1 (LB#, UB# CLOCK) tWC A0~21 (Word Mode) A -1~21 tAW (Byte Mode) tAS tBW tWR LB#,UB# tCW CS1# tCW CS2 tWP WE# OE# OE# = “H” level VIH VIL tDW tDH DQ0~15 (Word Mode) DQ0~7 (Byte Mode) Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 14 of 16 Valid Data R1WV6416R Series Low Vcc Data Retention Characteristics Parameter VCC for data retention Data retention current Chip select to data retention time Operation recovery time Symbol VDR Min. Typ Max. Unit 2.0 - 3.6 V - 8*1 24 μA - 14*2 48 μA - - 100 μA - - 160 μA tCDR 0 - - ns tR 5 - - ms ICCDR Test conditions*3,4 Vin ≥ 0V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Vin ≥ 0V ~+25°C BYTE# ≥ Vcc -0.2V or BYTE# ≤0.2V ~+40°C (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or ~+70°C (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, ~+85°C CS2 ≥ VCC-0.2V See retention waveform. Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested. 3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. 4. CS2 also controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 15 of 16 R1WV6416R Series Low Vcc Data Retention Timing Waveforms*1 (1) CS1# Controlled Vcc 2.7V tCDR 2.7V tR VDR 2.2V 2.2V CS1# ≥ Vcc - 0.2V CS1# (2) CS2 Controlled Vcc 2.7V tCDR CS2 2.7V tR VDR 0.6V 0.6V 0V ≤ CS2 ≤ 0.2V (3) LB#, UB# Controlled Vcc 2.7V tCDR VDR 2.2V LB#, UB# LB#, UB# ≥ Vcc - 0.2V Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0100, Rev.1.00, 2009.05.07 Page 16 of 16 2.7V tR 2.2V Revision History Rev. Date Page 0.01 1.00 Mar.24, 2008 May 07, 2009 5 6 R1WV6416R Data Sheet Contents pf Revision Description Initial issue: Preliminary Data Sheet Finalized Operation Table corrected Error corrected: ISB Test condition CS2=VIH->VIL Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. “Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.