R2A20118ASP

Preliminary Datasheet R2A20118ASP Critical Conduction Mode Interleaved PFC Control IC Description The R2A20118A controls a boost converter to provide an active power factor correction. The R2A20118A is based on R2A20117, and additional functions are OVP2 and Brownout. R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 The R2A20118A adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Interleaving function improves ripple current on input or output capacitor by 180 degrees phase shift. The feedback loop short detection, two modes overvoltage protection and OVP2, overcurrent protection, overcurrent timer latch protection, and ZCD open detection are built in the R2A20118A, and can constitute a power supply system of high reliability with few external parts. Features  Absolute Maximum Ratings  Supply voltage Vcc: 24 V  Operating junction temperature Tjopr: –40 to +150°C  Electrical Characteristics  VREF output voltage VREF: 5.0 V  1.5%  UVLO operation start voltage Vuvlh: 10.5 V  0.7 V  UVLO operation shutdown voltage Vuvll: 9.3 V  0.5 V  UVLO hysteresis voltage Hysuvl: 1.2 V  0.5 V  Functions  Boost converter control with critical conduction mode  Interleaving control  Brownout function  Two mode overvoltage protection and OVP2 Mode1: Dynamic OVP corresponding to a voltage rise by dynamic load change Mode2: Static OVP corresponding to overvoltage in stable. OVP2: OVP2 sense the PFC output voltage by independenced pin.  Feedback loop short detection  Slave ZCD signal open detection  RAMP charge current selectable function  Master and Slave independenced overcurrent protection  Overcurrent timer latch protection at abnormal operation  280 s restart timer  Soft start function for the reference voltage of Error Amp  Package: Pb-free SOP-20 Ordering Information Part No. R2A20118ASPW0 Package Name FP-20DAV Package Code PRSP0020DD-B Package Abbreviation SP Taping Abbreviation (Quantity) W (2,000 pcs/reel) R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 1 of 9 R2A20118ASP Preliminary Pin Arrangement ZCD-M ZCD-S BO VREF SS NC RT RAMP RAMP-GAIN COMP 1 2 3 4 5 6 7 8 9 10 (Top view) 20 19 18 17 16 15 14 13 12 11 VCC GD-M GND GD-S OCP-M OCP-S NC TL OVP2 FB Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name ZCD-M ZCD-S BO VREF SS NC RT RAMP RAMP-GAIN COMP FB OVP2 TL NC OCP-S OCP-M GD-S GND GD-M VCC Input/Output Input Input Input Output Output — Input/Output Input/Output Input Output Input Input Output — Input Input Output — Output Input Function Master converter zero current detection input terminal Slave converter zero current detection input terminal Brownout input terminal Reference voltage output terminal Soft start time setting terminal Open terminal Oscillator frequency setting terminal Ramp waveform setting terminal RAMP charge current selection terminal Error amplifier output terminal Error amplifier input terminal Over voltage detection terminal Timer latch time setting terminal Open terminal Slave converter overcurrent detection terminal Master converter overcurrent detection terminal Slave converter Power MOSFET drive terminal Ground Master converter Power MOSFET drive terminal Supply voltage terminal R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 2 of 9 R2A20118ASP Preliminary Block Diagram 10 μA 10 μA VREF VCC VREF: 5 V ZCD COMP1 UVLO ON: 10.5 V OFF: 9.3 V ZCD-M Clamp –0.1 V ~ 4.5 V Vzcd_lo = 1.3 V 250 mVhys – + ZCD COMP2 GD-M ZCD-S Clamp VREF –0.1 V ~ 4.5 V 3.2 μA TL COMP – + VREF GD-S TL 3.2 V + – LATCH Stop GD SQ R Logic 5 μA OCP COMP1 OCP-M + OCP-M 5 μA 6.4 μA – OCP COMP2 Vcc reset Hi: ON OCP-S VREF 1.4 V OCP-S Stop GD (BOUT) GD Disable COMP Discharge + – 0.3 V OVP2 BO + – 7.5 μA Hi: ON OVP2 OVP BLOCK FB – Ibo, Iramp Tstart SW COMP RT Vac_lo = 3.2 V 390 mVhys VREF + ErrorAmp + – RAMP AMP – + 2.5 V FB RAMP-GAIN 10 μA VREF 80 μA 0 to 240 μA Hi: ON + – 2.275 V (design spec) VREF 10 μA UVL BOUT FBLOW SS RAMP Iramp 0.9 V (design spec) Hi: ON GND COMP 4.3 V R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 3 of 9 R2A20118ASP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Supply voltage GD terminal peak current GD terminal DC current ZCD terminal current BO terminal current RT terminal current Vref terminal current Vref terminal capacitor COMP terminal current Terminal voltage Vref terminal voltage OCP terminal voltage Power dissipation Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. Symbol VCC Ipk-gd Idc-gd Izcd Ibom Irt Iref Cref min Cref max Icomp Vt-group1 Vt-group2 Vt-ref Vt-ocp Pt Tj-opr Tstg Ratings –0.3 to 24 –300 +1200 –15 +60 +3 –3 200 –200 –5 1000 1 1 –0.3 to Vcc –0.3 to Vref –0.3 to Vref + 0.3 *–1 to Vref 1 –40 to +150 –55 to +150 Unit V mA mA mA A A mA pF F mA V V V V W °C °C Notes 3 4 5 6 7 Rated voltages are with reference to the GND terminal. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. This is the rated voltage for the following pins: NC 5. This is the rated voltage for the following pins: FB, OVP2, RT, TL, RAMP-GAIN, SS, RAMP 6. Minus value is peak voltage. Do not impress the DC voltage of the minus. 7. ja = 120°C/W This value is a thing mounting on 40  40 (thickness: 1.6 mm) [mm2], a glass epoxy board of wiring density 10%. R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 4 of 9 R2A20118ASP Preliminary Electrical Characteristics (Ta = 25°C, VCC = 12 V, RT = 33 k, BO = 5 V, OCP = TL = OVP2 = GND, CRAMP = 820 pF, FB = COMP, RAMP-GAIN = OPEN) Item Supply UVLO turn-on threshold UVLO turn-off threshold UVLO hysteresis Standby current Operating current Brownout VREF BO threshold voltage BO pin hysteresis current Output voltage Line regulation Load regulation Temperature stability Error amplifier Feedback voltage Input bias current Open loop gain Upper clamp voltage Low voltage Source current Sink current Transconductance RAMP RAMP charge current 1 RAMP charge current 2 RAMP discharge current Low voltage RAMP gain control Threshold voltage Input bias current AC detect low threshold voltage AC detect hysteresis Symbol Vuvlh Vuvll Hysuvl Istby Icc Vbo Ibo Vref Vref-line Vref-load dVref Vfb Ifb Av Vclamp-comp Vl-comp Isrc-comp Isnk-comp gm Ic-ramp1 Ic-ramp2 Id-ramp Vl-ramp Vth-ramp_gain Iramp_gain Vac-lo Hys-ac Min 9.8 8.8 0.7 — — 1.33 6.7 4.925 — — — 2.452 –0.5 — 4.0 — — — 120 72 288 7 — 1.5 –14 2.9 350 Typ 10.5 9.3 1.2 85 4.2 1.40 7.5 5.00 5 5 80 2.49 –0.3 60 4.3 0.1 –120 330 200 80 320 15 17 2.5 –10 3.2 390 Max 11.2 9.8 1.7 170 6.3 1.47 8.3 5.075 20 20 — 2.528 –0.1 — — 0.3 — — 290 88 352 29 200 3.5 –6 3.5 430 Unit V V V A mA V A V mV mV ppm/°C V A dB V V A A s A A mA mV V A V mV BO = 1 V Isource = –1 mA Isource = –1 mA Vcc = 10 V to 24 V Isource = –1 mA to –5 mA Ta = –40 to 125°C * FB-COMP short Measured pin: FB 1 FB = 3 V * * 1 1 Test Conditions VCC = 8.9 V FB: Open FB = 2.0 V COMP: Open FB = 3.0 V COMP: Open FB = 1.5 V COMP = 2.5 V FB = 3.5 V COMP = 2.5 V FB = 2.45V  2.55 V COMP = 2.5 V RAMP = 0 V to 3 V RAMP-GAIN = GND RAMP = 0 V to 3 V FB = 3 V RAMP = 1 V FB = 3 V Isink = 100 A Measured pin RAMP-GAIN RAMP-GAIN = 3.5 V Measured pin BO Measured pin BO Note: *1 Design spec. R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 5 of 9 R2A20118ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, RT = 33 k, BO = 5 V, OCP = TL = OVP2 = GND, CRAMP = 820 pF, FB = COMP, RAMP-GAIN = OPEN) Item Slave control Gate drive Phase delay On time ratio Master gate drive rise time Symbol Phase Ton-ratio tr-gdm Min 160 0 — Typ 180 — 20 Max 200 5 100 Unit deg % ns ** ** 1, 1, 2 2 Test Conditions CL = 100 pF 90% 10% tr Slave gate drive rise time tr-gds — 20 100 ns CL = 100 pF 90% 10% tr 90% tf 10% Master gate drive fall time tf-gdm — 5 30 ns CL = 100 pF Slave gate drive fall time tf-gds — 5 30 ns CL = 100 pF 90% tf 10% Master gate drive low voltage Master gate drive high voltage Slave gate drive low voltage Slave gate drive high voltage Over current protection Over voltage protection Dynamic OVP threshold voltage Static OVP threshold voltage Static OVP hysteresis FB Low detect threshold voltage FB Low detect hysteresis OVP2 threshold voltage OVP2 pin input bias current OCP threshold voltage Vol1-gdm Vol2-gdm Voh-gdm Vol1-gds Vol2-gds Voh-gds Vocp — — 11.5 — — 11.5 0.27 0.02 0.01 11.9 0.02 0.01 11.9 0.30 0.1 0.2 — 0.1 0.2 — 0.33 V V V V V V V Isink = 2 mA Isink = 1 mA, VCC = 5 V Isource = –2 mA * Isink = 2 mA Isink = 1 mA, VCC = 5 V Isource = –2 mA * 1 1 Vdovp Vsovp1 Hys-sovp1 Vfblow Hysfblow Vovp2 Iovp2 VFB 1.035 VFB 1.075 50 0.45 0.16 2.670 –0.5 VFB 1.050 VFB 1.090 100 0.50 0.20 2.725 –0.3 VFB 1.065 VFB 1.105 150 0.55 0.24 2.780 –0.1 V V mV V V V A COMP = 2.5 V COMP = 2.5 V COMP = 2.5 V COMP = 2.5 V COMP = 2.5 V Measured pin: OVP2 Measured pin: OVP2 1 OVP2 = 3 V * Notes: *1 Design spec. *2 Tperiod (25 μs) Ton-m (17 μs) GD-M Tdelay GD-S Tdelay × 360 [deg] Tperiod Ton-s × 100 [%] Ton-m Ton-s Phase = Ton-ratio = 1 – R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 6 of 9 R2A20118ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, RT = 33 k, BO = 5 V, OCP = TL = OVP2 = GND, CRAMP = 820 pF, FB = COMP, RAMP-GAIN = OPEN) Item Zero current detector Upper clamp voltage Lower clamp voltage ZCD low threshold voltage ZCD hysteresis Input bias current ZCD open detector Soft start Timer latch for overcurrent Slave ZCD open detect delay time Charge current Charge current Discharge current Threshold voltage Restart Restart time delay Symbol Vzcdh Vzcdl Vzcd-lo Hyszcd Izcd tzcds Ic-ss Ic-tl Id-tl Vtl Tstart Min 4.0 –0.5 0.9 130 –14 — –14 –4.8 1.2 2.88 210 Typ 4.5 –0.1 1.3 250 –10 100 –10 –3.2 3.2 3.2 280 Max 5.0 0.4 1.6 360 –6 — –6 –1.2 4.8 3.52 350 Unit V V V mV A ms A A A V s ZCD-M = 10 k ZCD-S = 10 k * 2 Test Conditions Isource = –3 mA Isink = 3 mA * * 1 1 1.2 V < Vzcd < 2.5 V ZCD-S: Open 1 Gate drive 10 kHz * SS = 2 V TL = 2 V OCP-M = 0.5 V TL = 2 V Notes: *1 Design spec. *2 Tstart (280 μs) [A period without ZCD-M trigger] Vzcd-lo (1.3 V: provide 250 mV hysteresis) ZCD-M GD-M Restart pulse width: 1 μs (Design spec) R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 7 of 9 R2A20118ASP Preliminary System Diagram T1 230 μ D1 3M 3M PFC OUT (390 Vdc, 300 W) 470 μ (450 V) 0.04 GND 2μ Q1 From GD-M + VRB1 VRB2 T2 230 μ D2 Q2 From GD-S 0.04 47 k 47 k AUX VCC ZCD-M GD-M ZCD-S GD-S To Q2 gate 1μ To Q1 gate TL 0.1 μ OCP-M 200 1000 p OCP-S VREF OVP2 0.1 μ 200 1000 p 3M BO R2A20118ASP FB 2.2 μ 68 k RT 33 k RAMP-GAIN SS RAMP 470 p 1μ GND COMP 1μ 820 k 51 k 0.1 μ R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 8 of 9 R2A20118ASP Preliminary Package Dimensions JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B Previous Code FP-20DAV MASS[Typ.] 0.31g *1 D 11 F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E Index mark *2 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 10 bp x M L1 c Reference Dimension in Millimeters Symbol θ y A1 L Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 A Page 9 of 9 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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