R2A20124AFP_11

Preliminary Datasheet R2A20124AFP/R2A20124ASP Synchronous Phase Shift Full-Bridge Control IC Series Description R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 The R2A20124AFP/R2A20124ASP controls a full-bridge phase shift circuit and secondary synchronous rectification. The R2A20124AFP/R2A20124ASP has adjustable delay time functions which make ZVS of primary side and make loss of body diode of primary switching device minimal. The R2A20124AFP/R2A20124ASP is based on HA16163/R2A20121. And RAMP slope compensation circuit is builtin as an additional function. Also its output driver circuits are improved to enlarge gate drive output voltage swing from VREF to VCC. In addition R2A20124AFP has ON/OFF function of synchronous rectification and includes amplifier which detect input current signal. Features  Maximum ratings  Supply voltage Vcc: 20 V  Operating junction temperature Tj-opr: –40 to +125°C  Electrical characteristics  VFB feedback voltage VFB(–): 1.25 V  2.0%  UVLO (Under Voltage Lockout) operation start voltage VH: 8.4 V  0.7 V  UVLO operation shutdown voltage VL: 8.0 V  0.6 V  UVLO hysteresis voltage dVUVL: 0.4 V  0.1 V  Output voltage swing of OUT-A, B, C, D, and E for gate drive: GND to VCC  Functions R2A20124AFP/R2A20124ASP  Full-bridge phase-shift switching circuit with adjustable delay times  Pulse by pulse current limit  Synchronization I/O for the oscillator  Ramp sloping adjustor  Error amplifier built-in  Soft start function R2A20124AFP  Synchronous rectification on/off control  Remote on/off control  Amplified output of current sense input voltage: CS  Package lineup  Pb-free LQFP-40: R2A20124AFP  Pb-free SOP-20: R2A20124ASP Ordering Information Part No. R2A20124AFP-W0 R2A20124AFP-W5 R2A20124AFP-U0 R2A20124AFP-U5 R2A20124ASP-W0 R2A20124ASP-W5 R2A20124ASP-U0 R2A20124ASP-U5 Package Name FP-40EV Package Code PLQP0040JB-C Taping Spec. 2000 pcs./one taping product 2000 pcs./one taping product — — 2000 pcs./one taping product 2000 pcs./one taping product — — FP-20DAV PRSP0020DD-B R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 1 of 12 R2A20124AFP/R2A20124ASP Preliminary Modified Points from R2A20121SP     The swing level of the maximum output voltage is changed from VREF to VCC. Ramp sloping compensation circuit is added. Synchronous rectification control is possible to turned off at light load. (only R2A20124AFP) On/off control terminal for Remote is added. (only R2A20124AFP) Illustrative Circuit VIN DC 12 V DC 12 V DC 12 V DC 12 V DC 12 V Vbias (DC 12 V) VCC OUT OUT -A -B SEC-CONT(∗1) REMOTE(∗1) VREF CS RAMP RAMP -SLP OUT OUT -C -D OUT OUT -E -F COMP R2A20124AFP/ASP FB(–) CSDELAY -1 SS OUT(∗1) DELAY -2 DELAY -3 PGND SGND RT SYNC Note: ∗1. Only R2A20124AFP R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 2 of 12 R2A20124AFP/R2A20124ASP Preliminary Pin Arrangement R2A20124AFP RAMP-SLP SYNC SGND PGND N.C. N.C. N.C. N.C. N.C. RT R2A20124ASP RAMP N.C. CS CS-OUT N.C. COMP FB(–) SS N.C. N.C. 30 29 28 27 26 25 24 23 22 21 31 20 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 11 10 OUT-A OUT-B OUT-C OUT-D N.C. N.C. OUT-E OUT-F N.C. N.C. SYNC RAMP-SLP RAMP CS COMP FB(–) SS DELAY-1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT GND OUT-A OUT-B OUT-C OUT-D OUT-E OUT-F VCC VREF REMOTE DELAY-1 DELAY-2 DELAY-3 VREF N.C. N.C. SEC-CONT VCC N.C. DELAY-2 DELAY-3 N.C.: Non-connection (Top view) Outline: LQFP-40 (PLQP0040JB-C) (Top view) Outline: SOP-20 (PRSP0020DD-B) R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 3 of 12 R2A20124AFP/R2A20124ASP Preliminary Pin Functions LQFP-40 Pin No. 1 2 4 5 6 7 9 13 14 17 18 19 20 22 23 — 24 27 29 31 33 34 36 37 38 3, 8, 10 to 12, 15, 16, 21, 25, 26, 28, 30, 32, 35, 39, 40 SOP-20 Pin No. 8 9 10 — — 11 12 13 14 15 16 17 18 — — 19 20 1 2 3 4 — 5 6 7 — Pin Name DELAY-1 DELAY-2 DELAY-3 SEC-CONT REMOTE VREF VCC OUT-F OUT-E OUT-D OUT-C OUT-B OUT-A PGND SGND GND RT SYNC RAMP-SLP RAMP CS CS-OUT COMP FB(–) SS N.C. Input/Output Input/Output Input/Output Input/Output Input Input Output Input Output Output Output Output Output Output — — — Input/Output Input/Output Input/Output Input Input Output Output Input Output — Pin Function Delay time adjustor for the full-bridge control signal (OUT-A and B) Delay time adjustor for the full-bridge control signal (OUT-C and D) Delay time adjustor for the secondary control signal (OUT-E and F) Synchronous rectification on/off control Remote on/off control 5 V/20 mA output IC power supply input Secondary control signal Secondary control signal Full-bridge control signal Full-bridge control signal Full-bridge control signal Full-bridge control signal Ground level for the output signal Ground level for the small signal Ground Timing resistor for the oscillator Synchronization I/O for the oscillator Ramp sloping adjustor Ramp waveform set Current sense signal input for OCP Current sense information amplifier output Error amplifier output Error amplifier negative input Timing capacitor for soft start Open R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 4 of 12 R2A20124AFP/R2A20124ASP Preliminary Block Diagram R2A20124AFP VCC VREF 40 μA REMOTE ON: 1.32 V OFF: 1.23 V VREF RT H L UVLO 5V GENERATOR VREF H GOOD L VREF CIRCUIT BIAS START-UP COUNTER 32 CLOCK OSCILLATOR RES OUT-A VREF GOOD VCC SYNC SYNC I/O Q DELAY-1 VREF GOOD VCC OUT-B DELAY Control Circuit FB(–) ERROR VREF AMP 500 μA VCC 1.25 V OUT-C COMPARATOR COMP VCC 1.135 V RAMP VREF RAMP-SLP RES Phase Shift Control Logic CLAMP CIRCUIT VREF Zero Delay DELAY-2 OUT-D DELAY-3 VCC DELAY Control Circuit OUT-E Synchronous Rectification Control Logic 4V 10 μA SS VREF GOOD VCC OUT-F ×3.0 CS-OUT 1.15 V CS 1.4 V PULSE BY PULSE RES heavy load SEC-CONT 2.5 kΩ 10 μA 185 kΩ SGND PGND R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 5 of 12 R2A20124AFP/R2A20124ASP R2A20124ASP VCC Preliminary H L UVLO 5V GENERATOR VREF H GOOD L VREF VREF RT START-UP COUNTER 32 CLOCK VREF GOOD CIRCUIT BIAS VCC OUT-A RES SYNC I/O Q VCC VREF GOOD ERROR VREF AMP 500 μA DELAY Control Circuit OUT-B DELAY-1 OSCILLATOR SYNC FB(–) VCC OUT-C 1.25 V DELAY-2 COMPARATOR COMP 1.135 V RAMP VREF RAMP-SLP RES Phase Shift Control Logic CLAMP CIRCUIT VREF DELAY Control Circuit 4V 10 μA SS VREF GOOD VCC OUT-D Zero Delay DELAY-3 VCC OUT-E Synchronous Rectification Control Logic VCC OUT-F PULSE BY PULSE CS 1.4 V RES GND R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 6 of 12 R2A20124AFP/R2A20124ASP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power supply voltage Peak output current DC output current VREF output current COMP sink current DELAY set current RT set current RAMP-SLP set current VREF terminal voltage Terminal group 1 voltage Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. 6. Symbol Vcc Ipk-out Idc-out Iref-out Isink-comp Iset-delay Iset-rt Iset-ramp-slp Vter-ref Vter-1 Tj-opr Tstg Ratings 20 200 50 –20 2 0.3 0.3 0.3 –0.3 to +6 –0.3 to (Vref + 0.3) –40 to +125 –55 to +150 Unit V mA mA mA mA mA mA mA V V °C °C Note 1 2, 3 3, 4 3 3 3 3 3 1, 5 1, 6 7 Rated voltages are with reference to the GND or SGND pin. The Rating shows the transient current when driving a capacitive load. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Total current of OUT-A, Out-B, OUT-C, OUT-D, OUT-E, and OUT-F must be not exceed 90 mA. VREF pin voltage must not exceed VCC pin voltage. Terminal group 1 is defined the pins; REMOTE, RAMP-SLP, SEC-CONT, CS, RAMP, COMP, CS-OUT, FB(–), SS, RT, SYNC, and DELAY-1 to 3 7. Theramal resistance ja R2A20124AFP (40-pin); 85.3°C/W Board condition; Glass epoxy 50 mm  50 mm  1.6 mm, 10% wiring density. R2A20124ASP (20-pin); 120°C/W Board condition; Glass epoxy 40 mm  40 mm  1.6 mm, 10% wiring density. R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 7 of 12 R2A20124AFP/R2A20124ASP Preliminary Electrical Characteristics (Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.) Item SUPPLY: R2A20124AFP/ASP Start threshold Shutdown threshold UVLO hysteresis Start-up current Operating current VREF: R2A20124AFP/ASP Output voltage Line regulation Load regulation Temperature stability OSCILLATOR: R2A20124AFP/ASP Oscillator frequency Switching frequency Line stability Temperature stability RT voltage SYNC: R2A20124AFP/ASP Input threshold Output high Output low Minimum input pulse Output pulse width REMOTE: R2A20124AFP On threshold voltage Off threshold voltage REMOTE hysteresis Input bias current FB(–) input voltage FB(–) input current Open-loop DC gain Unity gain bandwidth Output source current Output sink current Output high voltage Output low voltage Output clamp voltage * 3 Symbol VH VL dVUVL Is Icc Vref Vref-line Vref-load dVref/dTa fosc fsw fsw-line dfsw/dTa VRT VTH-SYNC VOH-SYNC VOL-SYNC TI-MIN TO-SYNC VON-REMOTE VOFF-REMOTE dVREMOTE IREMOTE VFB(–) IFB(–) Av BW ISOURCE ISINK VOH-EO VOL-EO VCLAMP-EO Min 7.7 7.4 0.3 — — 4.9 — — — — 85 –1.5 — 2.5 2.5 3.5 — 50 — 1.12 1.04 60 –100 1.225 –2.0 — — –650 2.0 3.7 — –0.16 Typ 8.4 8.0 0.4 90 8 5.0 0 6 80*1 200*1 100 0 0.1*1 2.7 2.85 4.0 0.10 — 3.0*1 1.32 1.23 90 –50 1.250 0 80*1 2* 1 Max 9.1 8.6 0.5 150 11.5 5.1 10 20 — — 115 1.5 — 2.9 3.2 — 0.18 — — 1.52 1.42 120 — 1.275 2.0 — — –390 — — 0.4 0.0 Unit V V V A mA V mV mV ppm/°C kHz kHz % %/°C V V V V ns s V V mV A V A dB MHz A mA V V V Test Conditions Vcc = 7.5 V No load on VREF pin Vcc= 10 V to 16 V Iref= –1 mA to –20 mA Ta = –40°C to 105°C Measured on OUT-A, -B Vcc = 10 V to 16 V Ta = –40°C to 105°C RSYNC = 33 k to GND *2 RSYNC = 33 k to VREF REMOTE = 2 V FB(–) and COMP are shorted FB(–) = 1.25 V ERROR AMPLIFIER: R2A20124AFP/ASP –500 6.5 3.9 0.1 –0.07 FB(–) = 0.75 V, COMP = 2 V FB(–) = 1.75 V, COMP = 2 V FB(–) = 0.75 V, COMP; open FB(–) = 1.75 V, COMP; open FB(–) = 0.75 V, COMP; open, SS = 1 V Notes: 1. Design specification (reference data) 2. R2A20124AFP: SGND and PGND 3. VCLAMP-EO = VCOMP – SS voltage (1 V) R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 8 of 12 R2A20124AFP/R2A20124ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.) Item RAMP offset voltage RAMP source current RAMP sink current Minimum phase shift Maximum phase shift Delay to OUT-C, -D *2 RAMP discharge time *1 RAMP-SLP voltage DELAY: R2A20124AFP/ASP DELAY-1, -2 *3 DELAY-3 *3 DELAY2-1, -2 *1*3 DELAY2-3 * * 13 Symbol VRAMP Isource-RAMP ISINK-RAMP Dmin Dmax Tpd Tdis VRAMP-SLP TD1, 2 TD3 TD2_1, _2 TD2_3 VD1, 2, 3 ISS VOH-SS Min 1.035 –220 3 — — — — 2.1 70 45 140 110 1.9 –14 3.9 Typ 1.135 –185 10 0*1*4 97.0* * 100 80 2.3 100 65 220 170 2.0 –10 4.0 14 Max 1.235 –150 — — — 200 120 2.5 130 85 300 230 2.1 –6 4.1 Unit V A mA % % ns ns V ns ns ns ns V A V Test Conditions PHASE MODULATOR: R2A20124AFP/ASP RAMP = 0.15 V, COMP; open RAMP = 0.15 V, COMP = 0 V RAMP = 0 V, COMP = 0 V RAMP = 0 V, COMP = 2.1 V COMP = 1.6 V FB(–) = 0.75 V, COMP; open Delay set R = 51 k Delay set R = 51 k Delay set R = 180 k Delay set R = 180 k Delay set R = 51 k SS = 1 V Terminal voltage SOFT START: R2A20124AFP/ASP Source current SS high voltage Notes: 1. Design specification (reference data) 2. Tpd is defined as; 1V RAMP 50% 0V OUT-C/D VCC 0V Tpd 50% 3. TD1, TD2, and TD3 are defined as; TD1 OUT-A OUT-B For primary control OUT-C TD2 OUT-D OUT-E For secondary control OUT-F TD3 TD3 TD2 50% TD1 4. Maximum/Minimum phase shift is defined as; T2 D= × 2 × 100 (%) T1 OUT-A T2 OUT-D T1 OUT-B T2 OUT-C T1 R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 9 of 12 R2A20124AFP/R2A20124ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.) Item Pulse-by-pulse current limit threshold Delay to OUT pins *1 CS sink current OUTPUT: R2A20124AFP/ASP High voltage Low voltage Rise time Fall time Timing offset *2 Tranceconductance Forced synchronous rectification on voltage Forced synchronous rectification off voltage Input bias current-1 Input bias current-2 Current hysteresis VOH-OUT VOL-OUT tr tf TD4 gm Von-sec-cont Voff-sec-cont ISEC-CONT1 ISEC-CONT2 dISEC-CONT 11.5 — — — — 15 4.6 — 5 10 5 11.9 0.05 30 30 20 20 — — 10 20 10 — 0.2 100 100 140 25 — 0.4 20 40 20 V V ns ns ns s V V A A A CS = 0.4 V CS = 1 V CS = 0 V CS = 0 V, SEC-CONT = 2.1 V CS = 1 V, SEC-CONT = 2.1 V IOUT = –2 mA IOUT = 2 mA COUT = 100 pF COUT = 100 pF Symbol VCS-PP Tpd-cs ISINK-CS Min 1.26 — 2 Typ 1.4 100 5 Max 1.54 200 — Unit V ns mA Test Conditions SEC-CONT = 0.3 V (AFP) CS = 0 V to 1.57 V, SEC-CONT = 0.3 V (AFP) CS = 0.15 V, COMP = 0 V OVER CURRENT PROTECTION: R2A20124AFP/ASP POWER INFORMATION AMPLIFIER: R2A20124AFP SECONDARY CONTROL: R2A20124AFP Notes: 1. Tpd-cs is defined as; 1.57 V CS 0 50% 50% Tpd-cs OUT-C/D 2. TD4 is defined as; 50% OUT-D OUT-E TD4 OUT-C OUT-F 50% 50% 50% TD4 R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 10 of 12 R2A20124AFP/R2A20124ASP Preliminary Timing Diagram Note: All voltage, current, time shown in the diagram is typical value. • Full Bridge and Secondary Control: R2A20124AFP/ASP TD1 OUT-A TD1 OUT-B TD2 OUT-C TD2 OUT-D TD3 OUT-E TD3 OUT-F • Full Bridge and Secondary Control: R2A20124AFP (SEC-CONT > 4.6 V) TD1 OUT-A TD1 OUT-B TD2 OUT-C TD2 OUT-D OUT-E OUT-F Low-fixed Low-fixed VIN OUT-A DRIVE MA MC DRIVE OUT-C OUT-B DRIVE MB MD DRIVE OUT-D DRIVE RAMP ME MF DRIVE OUT-E External Power Stage OUT-F R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 Page 11 of 12 R2A20124AFP/R2A20124ASP Preliminary Package Dimensions JEITA Package Code P-LQFP40-7x7-0.65 RENESAS Code PLQP0040JB-C Previous Code FP-40EV MASS[Typ.] 0.2g HD *1 D 21 30 31 20 bp NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 HE E 40 11 Terminal cross section ( Ni/Pd/Au plating ) c Reference Dimension in Millimeters Symbol ZE 1 ZD Index mark 10 F θ A1 L L1 Detail F e *3 bp y x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 7.0 7.0 1.40 8.8 9.0 9.2 8.8 9.0 9.2 1.70 0.08 0.13 0.22 0.17 0.22 0.27 0.10 0.15 0.20 0° 0.65 0.13 0.10 0.575 0.575 0.40 0.50 0.60 1.0 8° Min A A2 JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B Previous Code FP-20DAV MASS[Typ.] 0.31g *1 D 11 c F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E Index mark *2 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 10 bp x M L1 c Reference Dimension in Millimeters Symbol θ y A1 L Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 R03DS0031EJ0300 Rev.3.00 Mar 11, 2011 A Page 12 of 12 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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