R2A20135SP#W5

Preliminary Data Sheet R2A20133DSP R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Critical Conduction Mode PFC Control IC Description The R2A20133D controls a boost converter to provide an active power factor correction. The R2A20133D adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Because the zero current is detected by using the GND current, the ZCD Auxiliary winding is unnecessary. The feedback loop open detection, two mode overvoltage protection, overcurrent protection are built in the R2A20133D, and can constitute a power supply system of high reliability with few external parts. Features • Absolute Maximum Ratings ⎯ Supply voltage Vcc: 24 V ⎯ Junction temperature Tj: –40 to +150°C • Electrical characteristics ⎯ UVLO operation start voltage VH: 9.5 V ± 0.7 V ⎯ UVLO operation shutdown voltage VL: 8.5 V ± 0.4 V ⎯ UVLO hysteresis voltage Hysuvl: 1.0 V ± 0.4 V • Functions ⎯ Boost converter control with critical conduction mode ⎯ Two mode overvoltage protection and OVP2 Mode 1: Dynamic OVP corresponding to a voltage rise by load change Mode 2: Static OVP corresponding to overvoltage in stable. OVP2: OVP2 senses the PFC output voltage by independence pin. ⎯ Feedback loop, open detection ⎯ Overcurrent protection ⎯ Dynamic UVP corresponding to a voltage fall by load change ⎯ Frequency limiter, adjustable ⎯ Zero Current Detect (ZCD) delay time, adjustable ⎯ CS pin's open detection ⎯ Package lineup: Pb-free SOP-8 (JEDEC) Ordering Information Part No. R2A20133DSP#W5 Package Name — R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Package Code PRSP0008DJ-A Package Abbreviation SP Taping Abbreviation (Quantity) W (2,500 pcs/reel) Page 1 of 13 R2A20133DSP Preliminary Pin Arrangement FB 1 8 VCC RT 2 7 OUT COMP 3 6 GND OVP2 4 5 CS (Top view) Pin Functions Pin No. 1 2 3 Pin Name FB RT COMP Error amplifier input terminal Max-ON time, ZCD-delay and Frequency limiter adjustment terminal Error amplifier output terminal 4 5 6 7 8 OVP2 CS GND OUT VCC Over voltage detection terminal Zero current detection and overcurrent detection input terminal Ground Power MOSFET drive terminal Supply voltage terminal R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Function Page 2 of 13 R2A20133DSP Preliminary Block Diagram CS open 72.5mV comparator VCC – + VREF UVLO VREF: 5.02V 8 ON: 9.5V OFF: 8.5V ZCD comparator 42μA + – CS 60k 3mV OCP comparator – + 5 5p OUT 7 GND 6 LOGIC BLOCK –0.6V GD Disable (OVP & FB_LOW) OVP & FB_LOW BLOCK PWM comparator VREF COMP Discharge FB OVP2 – + RT OVP2 4 ErrorAmp 2 – + 1V FB 1 2.51V (Vfb) 4.1V 10p COMP 3 Dynamic OVP + – VFB × 1.04V Ramp Control Dynamic UVP + – R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 VFB × 0.92V Page 3 of 13 R2A20133DSP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Supply Voltage OUT terminal peak current OUT terminal DC current COMP terminal current RT terminal current Terminal voltage CS terminal voltage Power dissipation Operating ambient temperature Junction temperature Storage temperature Symbol VCC Ratings –0.3 to +24 Unit V Note Ipk-snk-out Ipk-src-out +0.9 –0.5 A 3 Idc-snk-out Idc-src-out Icomp +100 –50 mA +1 –1 –50 to –2 –0.3 to VCC –0.3 to 5.3 –5 to +0.3 0.68 –40 to +125 –40 to +150 –55 to +150 mA Irt Vt-group1 Vt-group2 Vcs Pt Ta-opr Tj Tstg μA V V W °C °C °C 4 5 6 7 Notes: 1. 2. 3. 4. Rated voltages are with reference to the GND terminal. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. This is the rated voltage for the following pins: OUT 5. This is the rated voltage for the following pins: FB, COMP, OVP2, RT 6. θja = 120°C/W This value is a thing mounting on 40 × 40 × 1.6 [mm], a glass epoxy board of wiring density 10%. 7. Stresses exceeding the absolute maximum ratings may damage the device. These are stress ratings only. Functional operation above the recommended operating ambient temperature range is not implied. Extended exposure to stresses above the absolute maximum ratings may affect device reliability. R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 4 of 13 R2A20133DSP Preliminary Electrical Characteristics (Ta = 25°C, VCC = 12 V, CS = 0.04 V, FB = 2 V, COMP: Open, OVP2 = 1 V, RRT = 200 kΩ) Item Supply Error amplifier RT Min Typ Max Unit UVLO turn-on threshold Vuvlh Symbol 8.8 9.5 10.2 V UVLO turn-off threshold Vuvll 8.1 8.5 8.9 V UVLO hysteresis Hysuvl 0.6 1.0 1.4 V Standby current Istby — 100 200 μA mA Test Conditions VCC = Vuvlh – 0.2 V Operating current Icc — 1.8 2.6 Feedback voltage Vfb 2.472 2.510 2.548 V Temperature stability dVfb — ±80 — ppm/°C Input bias current Ifb –0.40 –0.15 –0.05 μA Measured pin: FB Open loop gain Av — 65 — dB *1 Upper clamp voltage Vclamp-comp 3.75 4.10 4.35 V FB = 2.45 V COMP: Open Low voltage Vl-comp — 0.1 0.3 V FB = 3.0 V COMP: Open Source current1 Isrc-comp1 –13.5 –10 –6 μA FB = 1.7 V COMP = 2.5 V Source current2 Isrc-comp2 Isrc-comp1 ×3.3 Isrc-comp1 ×3.0 Isrc-comp1 ×2.7 μA FB = 1.5 V COMP = 2.5 V Sink current Isnk-comp 6 10 13.5 μA FB = 3.5 V COMP = 2.5 V Transconductance gm 25 46 75 μS FB = 2.45V ↔ 2.55 V COMP = 2.5 V RAMP offset voltage Voff_ramp — 1.0 — V *1 RAMP amplitude dVramp 2.90 3.1 3.3 V *2 RT voltage V-rt 2.5 2.6 2.7 V ZCD delay time Zcd-delay — 0.87 — μs RRT = 200 kΩ *1 Maximum frequency fmax — 500 — kHz RRT = 200 kΩ *1 mV Zero ZCD threshold voltage Vzcd 1 3 6 current detector Input bias current Ics –58 –42 –25 μA CS open detect threshold voltage Vcs-open 45 72.5 130 mV Restart Restart time delay Tstart 75 150 330 μs FB-COMP short Ta = –40 to +125°C *1 Vcs = 0 V FB = 2.0 V COMP = 2.5 V Notes: *1 Design spec *2 dVramp = Vclamp_comp – Voff_ramp R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 5 of 13 R2A20133DSP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, CS = 0.04 V, FB = 2 V, COMP: Open, OVP2 = 1 V, RRT = 200 kΩ) Item Out Rise time Symbol tr-out Min Typ Max Unit — 35 100 ns Test Conditions CL = 1000 pF 90% 10% Fall time tf-out — 35 100 ns CL = 1000 pF tr 90% tf Out low voltage Over 10% Vol1-out — 0.08 0.2 V Isink = 20 mA Vol2-out — 0.05 0.7 V VCC = 5 V, Isink = 10 mA Out high voltage Voh-out 11.5 11.8 — V Isource = –20 mA OCP threshold voltage Vocp –0.63 –0.6 –0.57 V Dynamic OVP threshold voltage Vdovp — Vfb× 1.040 — V Measure FB *1 Dynamic UVP threshold voltage Vduvp — Vfb× 0.920 — V *1 Static OVP threshold voltage Vsovp Vfb× 1.075 Vfb× 1.090 Vfb× 1.105 V Static OVP hysteresis Hys-sovp 50 100 150 mV FB low detect threshold voltage Vfblow 0.25 0.3 0.35 V FB low detect hysteresis Hysfblow 0.16 0.20 0.24 V OVP2 high threshold voltage Vovp2-high Vfb× 1.18 Vfb× 1.20 Vfb× 1.22 V OVP2 low threshold voltage Vovp2-low 0.1 0.2 0.3 V OVP2 source current Isrc-ovp2 –0.40 –0.15 –0.05 μA current protection Over & Under voltage protection Note: Measure OVP2 *1 Design spec R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 6 of 13 R2A20133DSP Preliminary Waveforms 1. Start-up 9.5V (Vuvlh) VCC 5.02V 3.6V VREF (Internal signal) VREF GOOD (Internal signal) FB 0.5V (Vfblow + Hysfblow) COMP 1.0V (Voff_ramp) OUT 2. Shut-down 8.5V (Vuvll) VCC OUT Normal operation R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 7 of 13 R2A20133DSP Preliminary 3. Gate Drive Output COMP RAMP+1V (Internal signal) RAMP (Internal signal) IL 0V CS OUT Enlargement around Zero-current detection COMP RAMP+1V (Internal signal) RAMP (Internal signal) IL 0A 0V CS 0.87μs (adjustable) OUT R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 8 of 13 R2A20133DSP Preliminary 4. Overvoltage Protection (SOVP) Vfb × 1.09V (Vsovp) 100mV (Hys-sovp) FB SOVP_ON (Internal signal) COMP OUT 5. FB Low Detection FB 0.3V (Vfblow) 0.5V (Vfblow + Hysfblow) FB_LOW (Internal signal) COMP OUT R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 9 of 13 R2A20133DSP Preliminary 6. Overcurrent Protection (OCP) COMP RAMP+1V (Internal signal) RAMP (Internal signal) IL 0V CS –0.6V OUT 7. Frequency Limiter IL 0A ZCD_pulse (Internal signal) ZCD_mask (Internal signal) Mask Mask Mask 1.13μs ZCD_delay 0.87μs (adjustable) OUT Tmin = Zcd_delay + Zcd_mask = 1/fmax R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 10 of 13 R2A20133DSP Preliminary 8. Overvoltage Protection 2 (OVP2) Vfb × 1.2V (Vovp2-high) OVP2 OVP2_HIGH (Internal signal) OUT 9. OVP2 Low Detection OVP2 0.2V (Vovp2-low) OVP2_LOW (Internal signal) COMP OUT R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 11 of 13 R2A20133DSP Preliminary System Diagram D1 L1 PFC OUT (390V dc) Q1 1.0μ 220μ (450V) 6M 6M VRB1 VRB2 + From OUT GND 0.05 (5W) AUX VCC 8 1μ OUT 7 To Q1 gate GND CS 6 5 180 1000p R2A20133D OVP2 4 RT FB 2 1 200k COMP 3 200k 0.022μ 0.047μ R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Page 12 of 13 R2A20133DSP Preliminary Package Dimensions JEITA Package Code P-SOP8-3.94x4.93-1.27 RENESAS Code PRSP0008DJ-A *1 Previous Code — MASS[Typ.] 0.073g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 8 5 c *2 E HE bp Terminal cross section Reference Symbol (Ni/Pd/Au plating) Index mark 1 Z 4 *3 e bp x M A L1 θ S A1 L y S R03DS0052EJ0401 Rev.4.01 Jan 08, 2016 Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 4.80 4.93 4.98 3.81 3.94 3.99 1.47 0.10 0.15 0.25 1.73 0.35 0.41 0.49 0.19 0° 5.84 0.20 5.99 1.27 0.25 8° 6.20 0.25 0.10 0.41 0.56 0.64 1.03 0.89 Page 13 of 13 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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