R2A20169NP#W5

Datasheet R2A20168NP/SA/SP 8-bit 8ch D/A Converter with Buffer Amplifiers R03DS0019EJ0200 Rev.2.00 Jul 03, 2013 Description The R2A20168 is an integrated circuit semiconductor of CMOS structure with 8 channels of built in D/A unnecessary and enabling configuration of a system with few component parts. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area. Features · Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB · Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD ) · Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V ) · Very small size package line-up: QFN-16(pin pitch: 0.5mm), TSSOP-16(pin pitch 0.65mm) Application · Conversion from digital data to analog control data for home-use and industrial equipment. · Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor. · Blurring correction control or various control of the interchangeable lens of digital still camera. · Automatic adjustment by combination with microcomputer and EEPROM. (substitution of half fixed resistance) Block Diagram Number for SOP/TSSOP package Number for QFN package DI 14 12 12-bit shift register CLK 13 11 D0 D1 D2 D3 D4 D5 D6 D7 9 11 DO D8 D9 D10 D11 10 12 LD Channel decoder Vcc 9 7 1 2 3 4 5 6 7 8 8 Power on reset 8 1 GND 16 14 8 8–bit latch 8-bit latch 8-bit upper segment R-2R 8-bit upper segment R-2R 6 13 16 1 2 3 4 5 8 15 8 15 2 3 4 5 6 7 10 1 VrefU Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 VrefL R03DS0019EJ0200 Rev.2.00 Jul 03, 2013 Page 1 of 9 Datasheet R2A20168NP/SA/SP Pin Arrangement 13 Ao1 14 GND VrefL 1 16 GND Ao2 2 15 Ao1 12 DI Ao3 3 11 CLK Ao4 4 10 LD Ao5 5 9 DO Ao8 8 Ao7 5 Ao6 4 Vcc 7 Ao5 3 VrefU 6 Ao4 2 R2A20168SA/SP (Top view) Outline: PWQN0016KB-A [NP] Ao6 6 Ao7 7 VrefU 8 R2A20168SA/SP R2A20168NP Ao3 1 15 VrefL 16 Ao2 R2A20168NP (Top view) 14 DI 13 CLK 12 LD 11 DO 10 Ao8 9 Vcc Outline: PTSP0016JB-A [SA] PRSP0016DH-B [SP] Pin Description Pin No. [TSSO P [QFN] /SOP] Symbol 12 14 DI 11 13 CLK 10 12 LD 9 11 Do 13 16 1 2 3 4 5 8 7 14 6 15 15 2 3 4 5 6 7 10 9 16 8 1 Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 Vcc GND VrefU VrefL R03DS0019EJ0200 Rev.2.00 Jul 03, 2013 Function Serial data input terminal. ( Input serial data with a 12-bit data length ) Serial clock input terminal (Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.) Load terminal (When High level is input to LD terminal, value in 12-bit shift register is loaded into decoder and 8-bit latch.) Serial data output terminal (Data is sequentially output from the MSB bit.) 8-bit resolution D/A converter output terminals (After power on, all channels are reset and DAC data 00h is output.) Power supply terminal GND terminal D/A converter upper reference voltage input terminal D/A converter lower reference voltage input terminal Page 2 of 9 Datasheet R2A20168NP/SA/SP Absolute Maximum Ratings Item (Ta= +25deg unless otherwise noted) Symbol Conditions Ratings Unit Supply voltage Vcc -0.3 to +6.5 V D/A converter upper reference voltage VrefU -0.3 to +6.5 V D/A converter lower reference voltage VrefL -0.3 to +6.5 V Buffer amplifier output current IAO -2.0 to +2.0 mA Input voltage Vin -0.3 to Vcc+0.3 VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted ) Item Symbol Test conditions Limits Unit Min Typ Max 2.7 5.0 5.5 V Supply voltage Vcc Supply current Icc CLK =1MHz, Vcc =5V, IAO =0µA - 0.4 1.2 mA Input leak current IILK VIN = 0 to Vcc -10 - 10 µA Input low voltage VIL - - 0.2Vcc V 4.0V < Vcc Input high voltage VIH 0.55Vcc - - V Vcc £ 4.0V 0.8Vcc - - V Output low voltage VOL 4.0V < Vcc, IOL = 2.0mA - - 0.4 V Vcc < 4.0V, IOL = 1.5mA - - 0.4 V Output high voltage VOH IOH = -400µA Vcc – 0.4 - - V Supply voltage rise time *1 trVcc Vcc = 0 to 2.7V 100 - - µs VccPOR Vcc = 0 to 2.7V - 1.5 1.9 V tPOR Vcc < 0.1V 1 - - ms Internal reset operating voltage *1 Power supply restart interval (Power supply OFF à ON) *1 *1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR). trVcc Vcc tPOR (equivalent to trVcc) VccPOR GND Internal Reset signal < 0.1V GND Resetting period R03DS0019EJ0200 Rev.2.00 Jul 03, 2013 Resetting period Page 3 of 9 R2A20168NP/SA/SP Datasheet « Analog Part » ( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted ) Limits Item Symbol Current dissipation IrefU D/A converter upper reference voltage range *2 VrefU D/A converter lower reference voltage range *2 VrefL Buffer amplifier output voltage range VAO Buffer amplifier output drive range IAO Differential nonlinearity SDL Nonlinearity SL Zero code error SZERO Full scale error SFULL Test conditions Unit Min Typ Max - 1.0 2.0 Vcc ³ 4.5V 3.5 - Vcc Vcc < 4.5V 0.7Vcc - Vcc Vcc ³ 4.5V GND - Vcc-3.5 Vcc