R2A20178NP#W0

Datasheet R2A20169NP/SA/SP 8-bit 12ch D/A Converter with Buffer Amplifiers R03DS0020EJ0300 Rev.3.00 Jul 25, 2013 Description The R2A20169 is an integrated circuit semiconductor of CMOS structure with 12 channels of built in D/A unnecessary and enabling configuration of a system with few component parts. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area. Features · Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB · Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD ) · Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V ) · High output current capacity: +/-1mA or Higher · Very small size package line-up: QFN-20 (pin pitch: 0.5mm), TSSOP-20 (pin pitch 0.65mm) Application · Conversion from digital data to analog control data for home-use and industrial equipment. Block Diagram Number for TSSOP/SOP package Number for QFN package Ao12 Vcc Ao11 GND Ao2 Ao1 DI CLK LD DO 20 19 18 17 16 15 14 13 12 11 18 17 16 15 14 13 12 11 10 9 D/A D/A Power on reset 8-bit latch 8-bit latch 12-bit shift register D0 1 2 3 4 5 6 7 8-bit upper segment R-2R D/A converter 8 9 10 11 D/A Channel decoder 8 8-bit latch 8-bit latch 12 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit upper segment R-2R D/A converter D/A D/A D/A D/A D/A D/A D/A 19 20 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 VrefL Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 Ao9 Ao10 VrefU R03DS0020EJ0300 Rev.3.00 Jul 25, 2013 Page 1 of 9 Datasheet R2A20169NP/SA/SP Pin Arrangement R2A20169SP/SA (Top view) 16 Ao1 17 Ao2 18 GND 19 VrefL 20 Ao3 R2A20169NP (Top view) R2A20169NP Ao5 2 Ao6 3 Ao7 4 14 CLK 13 LD 12 Do Ao11 10 Vcc 9 VrefU 8 11 Ao12 Ao10 7 Ao5 4 Ao6 5 Ao7 6 Ao8 7 Ao9 8 Ao8 5 Ao9 6 Ao4 3 Outline: PWQN0020KB-A [NP] 19 Ao2 R2A20169SP/SA 15 DI Ao4 1 20 GND VrefL 1 Ao3 2 18 Ao1 17 DI 16 CLK 15 LD 14 Do 13 Ao12 Ao10 9 12 Ao11 VrefU 10 11 Vcc Outline: PRSP0020DD-B[SP] PTSP0020JB-A [SA] Pin Description Pin No. Pin Name [QFN] [TSSOP /SOP] 15 17 DI 12 14 Do 14 16 CLK 13 15 LD 16 18 Ao1 17 19 Ao2 20 2 Ao3 1 3 Ao4 2 4 Ao5 3 5 Ao6 4 6 Ao7 5 7 Ao8 6 8 Ao9 7 9 Ao10 10 12 Ao11 11 13 Ao12 Function Serial data input terminal. (Input serial data with a 12-bit data length.) Serial data output terminal (Data is sequentially output from the MSB bit.) Serial clock input terminal (Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.) Load terminal (When High level is input to LD terminal, value in 12-bit shift register is loaded into decoder and 8-bit latch.) 8-bit resolution D/A converter output terminals (After power-on, all channels are reset and DAC data 00h is output.) 9 11 Vcc Power supply terminal 18 20 GND GND terminal 8 10 VrefU D/A converter upper reference voltage input terminal 19 1 VrefL D/A converter lower reference voltage input terminal R03DS0020EJ0300 Rev.3.00 Jul 25, 2013 Page 2 of 9 Datasheet R2A20169NP/SA/SP Absolute Maximum Ratings (Ta= +25deg unless otherwise noted) Item Symbol Conditions Ratings Unit Supply voltage Vcc -0.3 to +6.5 V D/A converter upper reference voltage VrefU -0.3 to +6.5 V D/A converter lower reference voltage VrefL -0.3 to +6.5 V Buffer amplifier output current IAO -2.0 to +2.0 mA Continuous Input voltage Vin -0.3 to Vcc+0.3 VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted ) Limits Item Symbol Test conditions Unit Min Typ Max 2.7 5.0 5.5 V Supply voltage Vcc Supply current Icc CLK = 1MHz, Vcc =5V, IAO =0µA - 0.6 1.8 mA Input leak current IILK VIN = 0 to Vcc -10 - 10 µA Input low voltage VIL - - 0.2Vcc V 4.0V < Vcc 0.5Vcc - - V Input high voltage VIH Vcc < 4.0V 0.8Vcc - - V 4.0V < Vcc, IOL =2.0 mA - - 0.4 V Vcc < 4.0V, IOL =1.5 mA - - 0.4 V Output low voltage VOL Output high voltage VOH IOH = -400 µA Vcc – 0.4 - - V Supply voltage rise time *1 trVcc Vcc = 0 ® 2.7V 100 - - µs VccPOR Vcc = 0 ® 2.7V - 1.5 1.9 V tPOR Vcc < 0.1V 1 - - ms Internal reset operating voltage *1 Power supply restart interval (Power supply OFF à ON) *1 *1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR). trVcc Vcc tPOR (equivalent to trVcc) VccPOR GND Internal Reset signal < 0.1V GND Resetting period R03DS0020EJ0300 Rev.3.00 Jul 25, 2013 Resetting period Page 3 of 9 Datasheet R2A20169NP/SA/SP « Analog Part » ( Vcc,VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL=0V, Ta= -30 to +85deg, unless otherwise noted ) Limits Item Symbol Current dissipation IrefU D/A converter upper reference voltage range *2 VrefU D/A converter lower reference voltage range *2 VrefL Buffer amplifier output voltage range VAO Buffer amplifier output drive range IAO Differential nonlinearity SDL Nonlinearity SL Zero code error SZERO Full scale error SFULL Test conditions Unit Min Typ Max - 1.5 3.0 Vcc ³ 4.5V 3.5 - Vcc Vcc < 4.5V 0.7Vcc - Vcc Vcc ³ 4.5V GND - Vcc-3.5 Vcc < 4.5V GND - 0.3Vcc IAO = +/- 100 µA 0.1 - Vcc – 0.1 V IAO = +/- 500 µA 0.2 - Vcc – 0.2 V Upper side saturation voltage = 0.3V, Lower side saturation voltage = 0.2V -1.0 - 1.0 mA -0.7 - 0.7 LSB -1.0 - 1.0 LSB -2.0 - 2.0 LSB -2.0 - 2.0 LSB VrefU=5V, VrefL=0V, IAO=0µA, Data condition: at maximum current mA V V VrefU = 4.79V, VrefL = 0.95V, Vcc = 5.5V (15mV/LSB), Without load (IAO =0µA) Output capacitive load Co - - 0.1 µF Buffer amplifier output impedance Ro - 5.0 - ohm *2 : The output does not necessary be the value with the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). R03DS0020EJ0300 Rev.3.00 Jul 25, 2013 Page 4 of 9 Datasheet R2A20169NP/SA/SP AC Characteristics ( Vcc, VrefU = +5V +/-10%, Vcc >VrefU, GND=VrefL = 0V, Ta = -30 to +85deg, unless otherwise noted ) Item Test conditions Symbol Limits Min Typ Max Unit Clock frequency fCLK - 1.0 10 MHz Clock low pulse width tCKL 40 - - ns Clock high pulse width tCKH 40 - - ns Clock rise time tCR - - 200 ns Clock fall time tCF - - 200 ns Data setup time tDCH 4 - - ns Data hold time tCHD 30 - - ns LD setup time tCHL 40 - - ns LD hold time tLDC 40 - - ns LD high pulse width tLDH Data output delay time tDO CL < 100 pF D/A output settling time tLDD Ta=25deg, CL