R2J20602NP-G3

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. R2J20602NP Integrated Driver – MOS FET (DrMOS) REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Description The R2J20602NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the package standard “Integrated Driver – MOS FET (DrMOS)” proposed by Intel Corporation. Features             Built-in power MOS FET suitable for applications with 12 V input and low output voltage Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers VIN operating-voltage range: 16 V max High-frequency operation (above 1 MHz) possible Large average output current (Max. 40 A) Achieve low power dissipation (About 4.4 W at 1 MHz, 25 A) Controllable driver: Remote on/off Built-in Schottky diode for bootstrapping Low-side drive voltage can be independently set Small package: QFN56 (8 mm  8 mm  0.95 mm) Terminal Pb-free/Halogen-free Outline VCIN BOOT GH VIN 56 Driver Tab Reg5V VSWH Low-side MOS Tab PWM 43 28 High-side MOS Tab 1 14 15 DISBL# MOS FET Driver CGND VLDRV GL PGND 42 29 (Bottom view) QFN56 package 8 mm × 8 mm REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 1 of 14 R2J20602NP Block Diagram VCIN Reg5V BOOT GH Driver chip UVL DISBL# 2 µA CGND 5 V Gen. SBD VIN High-side MOS FET Level shifter VSWH VCIN PWM Input logic (TTL level) (3 state in) Overlap protection Low-side MOS FET PGND CGND VLDRV GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input “L” “Open” “H” Driver Chip Status Shutdown (GL, GH = “L”) Shutdown (GL, GH = “L”) Enable (GL, GH = “Active”) 2. Output signal from the UVL block "H" UVL Output Logic Level "L" VL VH VCIN For activation For shutdown REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 2 of 14 R2J20602NP Pin Arrangement VLDRV 3 CGND 14 13 12 11 10 9 8 7 6 5 4 2 VIN VIN VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND PGND PGND CGND 1 56 55 BOOT VCIN VIN VIN VIN VIN VIN VIN VIN GH NC 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 PWM DISBL# Reg5V NC GL CGND VSWH VSWH VSWH VSWH VSWH VSWH VSWH VSWH VIN CGND 54 53 52 51 50 49 48 VSWH 47 46 45 44 43 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND VSWH VSWH (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name CGND NC VLDRV VCIN BOOT GH VIN VSWH PGND GL Reg5V DISBL# PWM Pin No. 1, 6, 51, Tab 2, 53 3 4 5 7 8 to 20, Tab 21, 40 to 50, Tab 22 to 39 52 54 55 56 Description Control signal ground No connect Low side gate supply voltage Control input voltage (+12 V input) Bootstrap voltage pin High side gate signal Input voltage Phase output/Switch output Power ground Low side gate signal +5 V logic power supply output Signal disable PWM drive logic input Remarks Should be connected to PGND externally For 5 V to 12 V gate drive voltage for Low side gate driver Driver Vcc input To be supplied +5 V through internal SBD Pin for Monitor Pin for Monitor Disabled when DISBL# is “L” REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 3 of 14 VSWH R2J20602NP Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage Low side driver voltage Switch node voltage BOOT voltage DISBL# voltage PWM voltage Reg5V current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. 6. Symbol Pt(25) Pt(110) Iout VIN (DC) VIN (AC) VCIN (DC) VCIN (AC) VLDRV (DC) VLDRV (AC) VSWH (DC) VSWH (AC) VBOOT (DC) VBOOT (AC) Vdisble Vpwm Ireg5V Tj-opr Tstg Rating 25 8 40 –0.3 to +16 20 –0.3 to +16 20 –0.3 to +16 20 16 20 22 25 –0.3 to VCIN –0.3 to +5.5 –0.3 to +0.3 –10 to +0.1 –40 to +150 –55 to +150 Units W W A V V V V V V V V mA °C °C Note 1 1 2 2, 6 2 2, 6 2 2, 6 2 2, 6 2 2, 6 2 2, 4 2, 5 3 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode). This rating is when UVL (Under Voltage Lock out) is effective (lock out mode). The specification values indicated “AC” are limited within 100 ns. Safe Operating Area 45 40 Condition VOUT = 1.3 V VIN = 12 V VLDRV = 5 V VCIN = 12 V L = 0.45 µH fPWM = 1 MHz Average Output Current (A) 35 30 25 20 15 10 5 0 0 20 40 60 80 100 120 140 160 PCB Temperature (°C) REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 4 of 14 R2J20602NP Electrical Characteristics (Ta = 25C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified) Supply Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN bias current VLDRV bias current PWM Input PWM rising threshold PWM falling threshold PWM input resistance Tri-state shutdown window Shutdown hold-off time Output voltage Line regulation Load regulation Disable threshold Enable threshold Input current Note: Symbol VH VL dUVL ICIN ILDRV VH-PWM VL-PWM RIN-PWM VIN-SD tHOLD-OFF Vreg Vreg-line Vreg-load VDISBL VENBL IDISBL Min 7.0 6.6 — 10.5 35.5 3.7 0.9 12.5 VL-PWM — 4.95 –10 –10 0.9 1.9 0.5 Typ 7.4 7.0 0.4 *1 14.0 44.0 4.0 1.2 25 — 240 *1 5.2 0 0 1.2 2.4 2.0 Max 7.8 7.4 — 18.5 52.5 4.3 1.5 37.5 VH-PWM — 5.45 10 10 1.5 2.9 5.0 Units V V V mA mA V V k V ns V mV mV V V A Test Conditions VH – VL fPWM = 1 MHz, ton-PWM = 125 ns fPWM = 1 MHz, ton-PWM = 125 ns 4V–1V IPWM (VPWM = 4 V) – IPWM (VPWM = 1 V) 5V Regulator DISBL# Input VCIN = 12 V to 16 V Ireg = 0 to 10 mA DISBL# = 1 V 1. Reference values for design. Not 100% tested in production. REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 5 of 14 R2J20602NP Typical Application +12 V +5 V to 12 V +12 V VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP PWM CGND GH PGND GL VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP PWM PWM1 CGND GH PGND GL PWM control circuit PWM2 PWM3 PWM4 +1.3 V VCIN VLDRV BOOT DISBL# VIN Signal Power GND GND Reg5V VSWH R2J20602NP PWM CGND GH PGND GL VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP PWM CGND GH PGND GL REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 6 of 14 R2J20602NP Test Circuit VB VLDRV VCIN A A A IIN ILDRV ICIN V VIN VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP 5 V pulse PWM CGND GH PGND GL Electric load IO Averaging Average Output Voltage V VO circuit Note: PIN = IIN × VIN + ILDRV × VLDRV + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 7 of 14 R2J20602NP Typical Data Power Loss vs. Output Current 12 11 10 9 8 7 6 5 4 3 2 1 0 VIN = 12 V VCIN = 12 V VLDRV = 5 V VOUT = 1.3 V fPWM = 1 MHz L = 0.45 µH Power Loss vs. Input Voltage 1.3 VCIN = 12 V VLDRV = 5 V VOUT = 1.3 V 1.2 fPWM = 1 MHz L = 0.45 µH Iout = 25 A Normalized Power Loss @ VIN = 12 V Power Loss (W) 1.1 1.0 0.9 0 5 10 15 20 25 30 35 40 0.8 5 6 7 8 9 10 11 12 13 14 15 16 Input Voltage (V) Output Current (A) Power Loss vs. Output Voltage 1.5 1.4 Normalized Power Loss @ VOUT = 1.3 V VIN = 12 V VCIN = 12 V VLDRV = 5 V fPWM = 1 MHz L = 0.45 µH Iout = 25 A Power Loss vs. Switching Frequency 1.4 VIN = 12 V VLDRV = 5 V L = 0.45 µH 1.3 VCIN = 12 V Normalized Power Loss @ fpwm = 1 MHz 1.2 VOUT = 1.3 V 1.1 Iout = 25 A 1.0 0.9 0.8 0.7 0.6 1.3 1.2 1.1 1.0 0.9 0.8 0.8 1.6 2.4 3.2 4.0 4.8 0.5 250 500 750 1000 1250 1500 Output Voltage Vout (V) Switching Frequency (kHz) REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 8 of 14 R2J20602NP Typical Data (cont.) Power Loss vs. Output Inductance 1.20 1.15 Normalized Power Loss @ L = 0.45 µH Power Loss vs. VLDRV 1.6 VIN = 12 V 1.5 VCIN = 12 V Normalized Power Loss @ VLDRV = 5 V 1.10 1.05 1.00 0.95 VIN = 12 V VCIN = 12 V 0.90 VLDRV = 5 V VOUT = 1.3 V 0.85 fPWM = 1 MHz Iout = 25 A VOUT = 1.3 V fPWM = 1 MHz 1.4 L = 0.45 µH Iout = 25 A 1.3 1.2 1.1 1.0 0.9 0.8 0.80 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (µH) 5 6 7 8 9 10 11 12 13 14 15 16 VLDRV (V) Average ILDRV vs. Switching Frequency 250 VIN = 12 V VCIN = 12 V VOUT = 1.3 V 200 L = 0.45 µH Iout = 0 A Average ICIN vs. Switching Frequency 30 VIN = 12 V VCIN = 12 V 25 VOUT = 1.3 V L = 0.45 µH Iout = 0 A Average ILDRV (mA) Average ICIN (mA) VLDRV = 5 V VLDRV = 12 V VLDRV = 16 V 20 15 10 5 0 250 VLDRV = 5 V VLDRV = 12 V VLDRV = 16 V 150 100 50 0 250 500 750 1000 1250 1500 500 750 1000 1250 1500 Switching Frequency (kHz) Switching Frequency (kHz) REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 9 of 14 R2J20602NP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. Driver The driver has two types of power-supply voltage input pin, VCIN and VLDRV. VCIN supplies the operating voltage to the internal logic circuit. The low-side driving voltage is applied to VLDRV, so setting of the gate-driving voltage for the low-side MOS FET is independent of the voltage on VCIN. The VLDRV setting voltage is from 5 V to 16 V. The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 7.4 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 7.0 V or less. The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and the 5 V regulator is not disabled. VCIN L H H H VLDRV >5V >5V >5V >5V DISBL#  L H Open Reg5V 0 5V 5V 5V Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. The built-in 5 V regulator is a series regulator with temperature compensation. The voltage output by this regulator determines the operating voltage of the internal logic and gate-voltage swing for the high-side MOS FET. A ceramic capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V pin. The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (Reg5V + 3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 10 of 14 R2J20602NP The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 4.0 V or more is required to make the circuit return to normal operation. 240 ns(tHOLD-OFF) 240 ns(tHOLD-OFF) PWM 4.0 V 1.2 V GH GL 240 ns(tHOLD-OFF) 240 ns(tHOLD-OFF) PWM 4.0 V 1.2 V GH GL Figure 1 For the high-side driver, the BOOT pin is the power-supply voltage pin and voltage VSWH provides a standard for operation of the high-side driving circuit. Consequently, the difference between the voltage on the BOOT and VSWH pins becomes the gate swing for the high-side MOS FET. Connect a bootstrap capacitor between the BOOT pin and the VSWH pin. Since the Schottky barrier diode (SBD) is connected between the BOOT and Reg5V pins, this bootstrap capacitor is charged up to 5 V. When the high-side MOS FET is turned on, voltage VSWH becomes equal to VIN, so VBOOT is boosted to VSWH + 5 V. The GH and GL pins are the gate-monitor pins for each MOS FET. MOS FETs The MOS FETs incorporated in R2J20602NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 11 of 14 R2J20602NP PCB Layout Example Figure 2 shows an example of a PCB layout for the R2J20602NP in application. The several ceramic capacitors (e.g. 10 F) close to VIN and PGND can be expected to decrease switching noise and improve efficiency. In that case, all sections of the GND pattern must be connected with other PCB layers via low impedances. Moreover, the wide VSWH pattern can be expected to have the effect of dissipating heat from the low-side MOS FET. When R2J20602NP is mounted on small circuit boards, such as those for point-of-load (POL) applications, heating of the device can be alleviated by adding thermal via-holes under the VIN and VSWH pads. 10 µF Vin 10 µF 10 µF GND 10 µF GND BOOT 1 µF VCIN 1 µF VLDRV Reg. 5 V VSWH GND PWM DISBL# 1 µF 0.1 µF GND To inductor To BOOT Via hole Figure 2 R2J20602NP PCB Layout Example (Top View) REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 12 of 14 R2J20602NP Footprint Example (Unit: mm) 4.30 3.60 3.10 0.45 0.90 3.10 56 1 3.10 3.10 3.60 0.85 0.50 0.5 Figure 3 Footprint Example REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 13 of 14 4.30 0.3 R2J20602NP Package Dimensions JEITA Package Code P-HVQFN56-8x8-0.50 RENESAS Code PVQN0056KA-A Previous Code — MASS[Typ.] 0.2g HD D 42 43 29 28 28 29 42 43 3.0 HE e 0.0 0.3 1.0 E Lp C 4 0. 3.0 Reference Symbol Dimension in Millimeters 1 Index mark 14 ZD ZE 56 15 15 14 1 b b1 56 y Min Nom Max D 7.95 8.00 8.05 E 7.95 8.00 8.05 A2 A 0.95 A1 0.005 b 0.20 0.25 0.30 b1 0.23 e 0.50 Lp 0.40 0.50 0.60 x y 0.05 y1 t HD 8.10 8.20 8.30 HE 8.10 8.20 8.30 ZD 0.75 ZE 0.75 c 0.17 0.22 0.27 c1 0.20 3.0 0.0 0.4 1.0 c1 c Ordering Information Part Name R2J20602NP#G3 Quantity 2500 pcs Shipping Container Taping Reel REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 14 of 14 A1 A 3.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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