R2J20651NPG3

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. R2J20651NP Integrated Driver – MOS FET (DrMOS) REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Description The R2J20651NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Features                Compliant with Intel 6  6 DrMOS specification Built-in power MOS FET suitable for applications with 5 V/12 V input Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers Capable of both 3.3 V and 5 V PWM signal VIN operating-voltage range: 16 V max High-frequency operation (above 1 MHz) possible Large average output current (Max. 35 A) Achieve low power dissipation Controllable driver: Remote on/off Low-side MOS FET disabled function for DCM operation Built-in thermal warning Built-in Schottky diode for bootstrapping Small package: QFN40 (6 mm  6 mm  0.95 mm) Terminal Pb-free/Halogen-free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN BOOT GH VIN 40 THWN Driver Pad High-side MOS Pad 1 10 11 DISBL# MOS FET Driver LSDBL# Low-side MOS Pad PWM 31 CGND VDRV GL PGND 30 (Bottom view) 21 20 VSWH REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 1 of 17 R2J20651NP Block Diagram Driver chip BOOT GH VIN VCIN SBD UVL THWN THWN High-side MOS FET Level shifter 0.5 μA CGND DISBL# VCIN CGND 150 k LSDBL# VCIN Overlap protection VSWH PWM Input logic (TTL level) (3 state in) Low-side MOS FET CGND PGND VDRV GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input "L" "Open" "H" Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 2. Truth table for the LSDBL# pin. LSDBL# Input "L" "Open" "H" "L" "Active" "Active" GL Status 3. Output signal from the UVL block "H" UVL Output Logic Level "L" VL VH VCIN For active For shutdown 4. Output signal from the THWN block "H" THWN Output Logic Level "L" Normal operating Thermal warning TL TH TIC (°C) REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 2 of 17 R2J20651NP Pin Arrangement VSWH CGND BOOT VDRV 3 10 9 8 7 6 5 4 VCIN 2 VIN VIN VIN GH VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND LSDBL# 1 40 39 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PWM DISBL# THWN CGND GL VSWH VSWH VSWH VSWH VSWH VIN CGND 38 37 36 35 VSWH 34 33 32 31 PGND PGND PGND PGND PGND PGND PGND PGND VSWH (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name LSDBL# VCIN VDRV BOOT CGND GH VIN VSWH PGND GL THWN DISBL# PWM Pin No. 1 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 39 40 Description Low-side gate disable Control input voltage (+5 V input) Gate supply voltage (+5 V input) Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning Signal disable PWM drive logic input Remarks When asserted "L" signal, Low-side gate disable Driver Vcc input 5 V gate drive To be supplied +5 V through internal SBD Should be connected to PGND externally Pin for Monitor Pin for Monitor Thermal warning when over 130°C Disabled when DISBL# is "L" Capable of both 3.3 V and 5 V logic input REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 3 of 17 VSWH R2J20651NP Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. Symbol Pt(25) Pt(110) Iout VIN (DC) VIN (AC) VCIN & VDRV VSWH (DC) VSWH (AC) VBOOT (DC) VBOOT (AC) Vpwm, Vdisble, Vlsdbl, Vthwn Tj-opr Tstg Rating 25 8 35 –0.3 to +16 20 –0.3 to +6 16 25 22 25 –0.3 to VCIN + 0.3 –40 to +150 –55 to +150 Units W A V V V V V °C °C Note 1 2 2, 3 2 2 2, 3 2 2, 3 2, 4 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. The specification values indicated "AC" are limited within 100 ns. VCIN + 0.3 V < 6 V Safe Operating Area 45 Average Output Current (A) 40 35 30 25 20 15 10 5 0 0 25 50 75 100 125 150 175 PCB Temperature (°C) Condition VOUT = 1.3 V VIN = 12 V VCIN = 5 V VDRV = 5 V L = 0.45 μH Fsw = 1 MHz Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Symbol VIN VCIN & VDRV Rating 4.5 to 14 4.5 to 5.5 Units V V Note REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 4 of 17 R2J20651NP Electrical Characteristics (Ta = 25C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified) Supply Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM input PWM rising threshold PWM falling threshold PWM input resistance Tri-state shutdown window Shutdown hold-off time Disable threshold Enable threshold Input current Low-side activation threshold Low-side disable threshold Input current Warning temperature Temperature hysteresis THWN on resistance THWN leakage current Note: Symbol VH VL dUVL ICIN ICIN-DISBL VH-PWM VL-PWM RIN-PWM VIN-SD tHOLD-OFF * VDISBL VENBL IDISBL VLSDBLH VLSDBLL ILSDBL TTHWN *1 THYS *1 RTHWN *1 ILEAK 1 Min 3.1 2.7 — — — 1.7 0.9 42 VL-PWM — 0.9 1.9 — 1.9 0.9 –54 110 — 1.0 — Typ 3.5 3.0 0.5 29 — 2.1 1.2 70 — 240 1.2 2.4 0.5 2.4 1.2 –27 130 15 2.5 0.001 Max 3.9 3.3 — — 50 2.5 1.5 98 VH-PWM — 1.5 2.9 2.0 2.9 1.5 –13.5 — — 4.0 1.0 Units V V V mA A V V k V ns V V A V V A °C °C k A Test Conditions VH – VL fPWM = 1 MHz, Ton_pwm = 120 ns DISBL# = 0 V, PWM = 0 V, LSDBL# = Open PWM = 1 V DISBL# input LSDBL# input Thermal warning DISBL# = 1 V LSDBL# = 1 V Driver IC temperature THWN = 1 V THWN = 5 V 1. Reference values for design. Not 100% tested in production. REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 5 of 17 R2J20651NP Pin Connection +5 V 0.1 μF 1.0 μF CGND VIN (4.5 V~14 V) 0~10 Ω Low Side Disable Signal INPUT CGND 10 11 10 μF × 4 9 8 7 6 5 4 3 2 1 BOOT LSDBL# CGND VDRV VSWH VCIN VIN GH 40 39 38 PWM DISBL# THWN PWM INPUT 12 PGND 13 14 VIN 15 VSWH 16 PGND 17 18 19 20 VIN PAD CGND PAD CGND 37 DISBL# INPUT 51 kΩ R2J20651NP VSWH PAD GL 36 VSWH 35 34 33 +5 V VSWH PGND 32 31 0.45 μF Vout 21 22 23 24 25 26 27 28 29 30 PGND PGND Power GND Signal GND REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 6 of 17 R2J20651NP Typical Application (1) 12 V Input Power +12 V +5 V VCIN THWN DISBL# LSDBL# VDRV BOOT GH VIN R2J20651 NP VSWH PGND PWM CGND GL VCIN THWN DISBL# LSDBL# VDRV BOOT GH VIN R2J20651 NP VSWH PGND PWM CGND PWM1 GL +1.3 V PWM Control Circuit PWM2 PWM3 VCIN PWM4 THWN DISBL# LSDBL# PGND PWM CGND GL VIN VDRV BOOT GH R2J20651 NP VSWH Power GND Signal GND VCIN THWN DISBL# LSDBL# VDRV BOOT GH VIN R2J20651 NP VSWH PGND PWM CGND GL REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 7 of 17 R2J20651NP (2) 5 V Input Power +5 V VCIN THWN DISBL# LSDBL# VDRV BOOT GH VIN R2J20651 NP VSWH PGND PWM CGND GL VCIN THWN DISBL# LSDBL# VDRV BOOT GH VIN R2J20651 NP VSWH PGND PWM CGND PWM1 GL +1.5 V PWM Control Circuit PWM2 PWM3 VCIN PWM4 THWN DISBL# LSDBL# PGND PWM CGND GL VIN VDRV BOOT GH R2J20651 NP VSWH Power GND Signal GND VCIN THWN DISBL# LSDBL# VDRV BOOT GH VIN R2J20651 NP VSWH PGND PWM CGND GL REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 8 of 17 R2J20651NP Test Circuit Vinput A IIN V VIN Vcont A ICIN VCIN V VCIN VDRV 6.2 Ω BOOT VIN 0.1 μF DISBL# LSDBL# R2J20651 NP VSWH THWN 5V pulse fPWM PWM CGND GH GL PGND Electric load IO Note: PIN = IIN × VIN + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C Average Output Voltage Averaging V VO circuit REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 9 of 17 R2J20651NP Typical Data Power Loss vs. Output Current 10 9 VCIN = 5 V 8 VOUT = 1.3 V Power Loss (W) VIN = 12 V Power Loss vs. Input Voltage 1.5 VCIN = 5 V 1.4 VOUT = 1.3 V Normalized Power Loss @ VIN = 12 V fPWM = 600 kHz 7 L = 0.45 μH fPWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 1.2 1.1 1.0 0.9 0.8 4 6 8 10 12 14 16 Output Current (A) Input Voltage (V) Power Loss vs. Output Voltage 1.5 VIN = 12 V Power Loss vs. Switching Frequency 1.5 VIN = 12 V 1.4 VCIN = 5 V Normalized Power Loss @ VOUT = 1.3 V Normalized Power Loss @ fPWM = 600 kHz fPWM = 600 kHz L = 0.45 μH 1.3 IOUT = 25 A 1.4 VCIN = 5 V VOUT = 1.3 V L = 0.45 μH 1.3 IOUT = 25 A 1.2 1.1 1.0 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Output Voltage (V) 1.2 1.1 1.0 0.9 0.8 250 500 750 1000 1250 Switching Frequency (kHz) REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 10 of 17 R2J20651NP Typical Data (cont.) Power Loss vs. Output Inductance 1.5 VIN = 12 V Power Loss vs. VCIN 1.5 1.4 Normalized Power Loss @ VCIN = 5 V VIN = 12 V VOUT = 1.3 V fPWM = 600 kHz L = 0.45 μH IOUT = 25 A 1.4 VCIN = 5 V Normalized Power Loss @ L = 0.45 μH VOUT = 1.3 V fPWM = 600 kHz 1.3 IOUT = 25 A 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 VCIN (V) 1.2 1.1 1.0 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (μH) 5.5 6.0 Average ICIN vs. Switching Frequency 50 VIN = 12 V VCIN = 5 V 40 VOUT = 1.3 V L = 0.45 μH IOUT = 0 A Average ICIN (mA) 30 20 10 0 250 500 750 1000 1250 Switching Frequency (kHz) REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 11 of 17 R2J20651NP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 3.5 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.0 V or less. The signal on pin DISBL# also enables or disables the circuit. Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL#  L H Open Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the low-side gate disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 1 shows the typical high-side and low-side gate switching and inductor current (IL) during Continuous Conduction Mode (CCM) and low-side gate disabled when asserting low-side disable signal. This pin is internally pulled up to VCIN with 150 k resistor. When low-side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 1.1 Typical Signals During CCM REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 12 of 17 R2J20651NP DCM Operation (LSDBL# = "L") IL 0A GH GL Figure 1.2 Typical Signals During Low-Side Disable Operation The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 2.1 V or more is required to make the circuit return to normal operation. 240 ns (tHOLD-OFF) 240 ns (tHOLD-OFF) 2.1 V PWM 1.2 V GH GL 240 ns (tHOLD-OFF) 240 ns (tHOLD-OFF) 2.1 V PWM 1.2 V GH GL Figure 2 REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 13 of 17 R2J20651NP THWN This thermal warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex. 51 k) to THWN for systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 130°C, thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. Thermal warning "H" THWN output Logic Level "L" Normal operating 115 130 TIC (°C) Figure 3 MOS FETs The MOS FETs incorporated in R2J20651NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the lowside MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 14 of 17 R2J20651NP PCB Layout Example Figure 4 shows an example of the PCB layout for the R2J20651NP. Placing several ceramic capacitors (e.g. 10 F) between VIN and PGND can be expected to the decreasing switching noise and improvement of efficiency. In that case, it is necessary to connect each GND pattern with low impedance by using other PCB layers. Moreover, by taking the wide VSWH pattern, the effect of letting the heat from the low side MOS FET can be expected. When R2J20651NP is mounted on a small substrate like POL module, the temperature rising of the device could be eased if the thermal via-hole is added under the pad of VIN and VSWH. 10 μF Vin 10 μF 10 μF 10 μF GND 0.1 μF GND GND Rboot 1 μF VCIN VSWH To Inductor GND PWM DISBL# Via Hole Figure 4 R2J20651NP PCB Layout Example (Top View) REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 15 of 17 R2J20651NP Footprint Example (Unit: mm) 0.20 6.20 0.20 2.3 0.1 0.1 2.3 2.3 C0.4 6.20 0.6 0.3 13–R0.2 C0.1 2.15 2.15 0.6 0.50 40–0.30 Figure 5 Footprint Example REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 16 of 17 2.3 0.20 0.20 R2J20651NP Package Dimensions JEITA Package Code P-HVQFN40-p-0606-0.50 RENESAS Code PVQN0040KC-A Previous Code — MASS[Typ.] — HD D 2.2 0.2 0.2 B INDEX 1pin 40 4-C0.50 40 1pin B 2.2 C0.3 E /2 1.95 A 2.2 0.7 0.2 Reference Symbol HD/2 D /2 HE E 1.95 HE/2 t S AB e y1 S X4 f S AB b 2.2 X4 20° 20° L1 x S AB S A A2 0.69 A1 c2 Lp yS Ordering Information Part Name R2J20651NP#G3 Quantity 2500 pcs Shipping Container Taping Reel REJ03G1743-0400 Rev.4.00 Mar 12, 2010 Page 17 of 17 2.05 ZD ZE 4(0 .1 39 ) 1.95 2-A section CAV No. Die No. Dimension in Millimeters 1.95 2.05 Min Nom Max D 5.95 6.00 6.05 5.95 6.00 6.05 E A2 0.87 0.89 0.91 f — — 0.20 A 0.865 0.91 0.95 A1 0.005 0.02 0.04 b 0.17 0.22 0.27 b1 0.16 0.20 0.24 — 0.50 — e Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 t — — 0.20 HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — ZE — 0.75 — L1 0.06 0.10 0.14 c1 0.17 0.20 0.23 c2 0.17 0.22 0.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. 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