R2J20653ANP

Preliminary R2J20653ANP Integrated Driver – MOS FET (DrMOS) REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Description The R2J20653ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose. Features • • • • • • • • • • • • • • • Compliant with Intel 6 × 6 DrMOS specification Built-in power MOS FET suitable for Notebook, Desktop, Server application Low-side MOS FET with built-in SBD for lower loss and reduced ringing Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers High-frequency operation (above 1 MHz) possible VIN operating-voltage range: 27 V max Large average output current (Max. 35 A) Achieve low power dissipation Controllable driver: Remote on/off Low-side MOS FET disabled function for DCM operation Double thermal protection: Thermal warning & Thermal shutdown Built-in bootstrapping switch Small package: QFN40 (6 mm × 6 mm × 0.95 mm) Terminal Pb-free/Halogen-free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN BOOT GH VIN 40 THWN Driver Pad High-side MOS Pad 1 10 11 DISBL# MOS FET Driver LSDBL# Low-side MOS Pad PWM 31 CGND VDRV GL PGND 30 (Bottom view) 21 20 VSWH REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 1 of 12 R2J20653ANP Preliminary Block Diagram Driver Chip VCIN VDRV BOOT GH THWN DISBL# THWN THDN Boot SW VIN High Side MOS FET 2 μA CGND UVL VCIN Level Shifter 25 k CGND 150 k LSDBL# VCIN VSWH PWM Input Logic (TTL Level) (3 state in) Overlap Protection. & Logic VDRV Low Side MOS FET 20 μA PGND CGND GL Notes: 1. Truth table for the DISBL# pin. DISBL# Input "L" "Open" "H" Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active") 2. Truth table for the LSDBL# pin. LSDBL# Input "L" "Open" "H" "L" "Active" "Active" GL Status 3. Output signal from the UVL block UVL output Logic Level "H" For shutdown "L" VL VH VCIN For active 4. Output signal from the THWN block "H" Thermal Warning Logic Level "L" Normal operating Thermal Warning TIC(°C) TwarnL TwarnH 5. Truth table for the THDN block Driver IC Temp. < 150°C (< 135°C on cancellation) > 150°C Driver Chip Status Enable (GL, GH = "Active") Shutdown (GL, GH = "L") REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 2 of 12 R2J20653ANP Preliminary Pin Arrangement LSDBL# 1 40 39 VSWH CGND BOOT 4 VDRV 3 10 9 8 7 6 5 VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND VCIN 2 VIN VIN VIN GH 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PWM DISBL# THWN CGND GL VSWH VSWH VSWH VSWH VSWH VIN CGND 38 37 36 35 VSWH 34 33 32 31 PGND PGND PGND PGND PGND PGND PGND PGND VSWH (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name LSDBL# VCIN VDRV BOOT CGND GH VIN VSWH PGND GL THWN DISBL# Pin No. 1 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 39 Description Low-side gate disable Control input voltage (+5 V input) Gate supply voltage (+5 V input) Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning Signal disable Remarks When asserted "L" signal, Low-side gate disable Driver Vcc input 5 V gate drive To be supplied +5 V through internal switch Should be connected to PGND externally Pin for monitor Pin for monitor Thermal warning when over 115°C Disabled when DISBL# is "L" This pin is pulled low when internal IC over the thermal shutdown level, 150°C. 5 V logic input PWM 40 PWM drive logic input REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 3 of 12 VSWH R2J20653ANP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage THWN current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. Symbol Pt(25) Pt(110) Iout VIN (DC) VIN (AC) VCIN & VDRV VSWH (DC) VSWH (AC) VBOOT (DC) VBOOT (AC) Vpwm, Vdisble, Vlsdbl, Vthwn Ithwn Tj-opr Tstg Rating 25 8 35 –0.3 to +27 30 –0.3 to +6 27 30 32 36 –0.3 to VCIN + 0.3 0 to 1.0 –40 to +150 –55 to +150 Units W A V V V V V mA °C °C Note 1 2 2, 4 2 2 2, 4 2 2, 4 2, 5 Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110°C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow. The specification values indicated "AC" are limited within 100 ns. VCIN + 0.3 V < 6 V Safe Operating Area 45 Average Output Current (A) 40 35 30 25 20 15 10 5 0 0 25 50 75 100 125 150 175 PCB Temperature (°C) Condition VOUT = 1.3 V VIN = 12 V VCIN = 5 V VDRV = 5 V L = 0.45 μH Fsw = 1 MHz Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Symbol VIN VCIN & VDRV Rating 4.5 to 22 4.5 to 5.5 Units V V Note REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 4 of 12 R2J20653ANP Preliminary Electrical Characteristics (Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified) Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM input PWM rising threshold PWM falling threshold PWM input resistance Tri-state shutdown window Shutdown hold-off time DISBL# input Disable threshold Enable threshold Input current THDN on resistance LSDBL# input Thermal warning Low-side activation threshold Low-side disable threshold Input current Warning temperature Temperature hysteresis THWN on resistance THWN leakage current Thermal shutdown Shutdown temperature Temperature hysteresis Symbol VH VL dUVL ICIN ICIN-DISBL VH-PWM VL-PWM RIN-PWM VIN-SD tHOLD-OFF *1 VDISBL VENBL IDISBL RTHDN * VLSDBLH VLSDBLL ILSDBL TTHWN *1 THYS *1 RTHWN *1 ILEAK Tstdn *1 TDHYS *1 1 Min 4.1 3.6 — — — 3.0 0.9 10 VL-PWM — 0.9 1.9 — 0.2 1.9 0.9 –56 95 — 0.2 — 130 — Typ 4.3 3.8 0.5 33 — 3.4 1.2 20 — 100 1.2 2.4 2.0 0.5 2.4 1.2 –27 115 15 0.5 0.001 150 15 Max 4.5 4.0 — — 2 3.8 1.5 40 VH-PWM — 1.5 2.9 5.0 1.0 2.9 1.5 –14 135 — 1.0 1.0 — — Units V V V mA mA V V kΩ V ns V V μA kΩ V V μA °C °C kΩ μA °C °C Test Conditions VH – VL fPWM = 1 MHz, Ton_pwm = 120 ns DISBL# = 0 V, PWM = 0 V, LSDBL# = Open PWM = 1 V DISBL# = 1 V THDN = 0.2 V LSDBL# = 1 V Driver IC temperature THWN = 0.2 V THWN = 5 V Driver IC temperature Note: 1. Reference values for design. Not 100% tested in production. REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 5 of 12 R2J20653ANP Preliminary Typical Application 4.5 to 22 V +5 V VCIN THWN VDRV BOOT GH VIN DISBL# R2J20653A NP LSDBL# PWM CGND VSWH PGND GL VCIN THWN VDRV BOOT GH VIN DISBL# R2J20653A NP LSDBL# PWM CGND PWM1 VSWH PGND GL +1.3 V PWM Control Circuit PWM2 PWM3 VCIN PWM4 THWN DISBL# R2J20653A VIN VDRV BOOT GH NP LSDBL# PWM CGND VSWH Power GND Signal GND PGND GL VCIN THWN VDRV BOOT GH VIN DISBL# R2J20653A NP LSDBL# PWM CGND VSWH PGND GL REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 6 of 12 R2J20653ANP Preliminary Pin Connection +5 V 0.1 μF 1.0 μF CGND VIN (4.5 V~22 V) 0~10 Ω Low Side Disable Signal INPUT CGND 10 11 10 μF × 4 9 8 7 6 5 4 3 2 1 BOOT CGND VDRV VCIN VIN LSDBL# VSWH GH 40 39 38 PWM DISBL# THWN PWM INPUT 12 PGND 13 14 VIN 15 VSWH 16 PGND 17 18 19 20 VIN PAD CGND PAD CGND 37 10 kΩ 10 kΩ +5 V R2J20653ANP VSWH PAD GL 36 VSWH 35 34 33 +5 V Thermal Shutdown VSWH PGND 32 31 Thermal Warning 0.45 μH Vout 21 22 23 24 25 26 27 28 29 30 PGND PGND Power GND Signal GND REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 7 of 12 R2J20653ANP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The signal on pin DISBL# also enables or disables the circuit. Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL# ∗ L H Open Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is connected to the DISBL# pin. The detailed function is described in THDN section. PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the low-side gate disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 1 shows the typical high-side and low-side gate switching and inductor current (IL) during Continuous Conduction Mode (CCM) and low-side gate disabled when asserting low-side disable signal. This pin is internally pulled up to VCIN with 150 kΩ resistor. When low-side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 1.1 Typical Signals during CCM REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 8 of 12 R2J20653ANP DCM Operation (LSDBL# = "L") IL 0A Preliminary GH GL Figure 1.2 Typical Signals during Low-Side Disable Operation The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.4 V or more is required to make the circuit return to normal operation. 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL 100 ns (tHOLD-OFF) 100 ns (tHOLD-OFF) 3.4 V PWM 1.2 V GH GL Figure 2 REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 9 of 12 R2J20653ANP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 100 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. VCIN M1 20 k PWM Pin Input Logic 20 k Tri-state detection signal To internal control DISBL# Figure 3 Equivalent Circuit for the PWM-pin Input THWN & THDN This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function. This thermal warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex. 51 kΩ) to THWN for systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 115°C, thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. Thermal warning "H" THWN output Logic Level "L" Normal operating 100 115 TIC (°C) Figure 4 THWN Trigger Temperature REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 10 of 12 R2J20653ANP THDN is an internal thermal shutdown signal when driver IC becomes over 150°C. Preliminary This function makes high-side MOS FET and low-side MOS FET turn off for the device protection from abnormal high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system controller. Figure 5 shows the example of two types of DISBL# connection with the system controller signal. Driver IC Temp. < 150°C (< 135°C on cancellation) > 150°C Driver Chip Status Enable (GL, GH = "Active") Shutdown (GL, GH = "L") 5V 10 k DISBL# 2 μA To Internal Logic 10 k DISBL# 2 μA To Internal Logic To shutdown signal Thermal Shutdown Detection ON/OFF signal Thermal Shutdown Detection Figure 5.1 THDN Signal to the System Controller Figure 5.2 ON/OFF Signal from the System Controller MOS FETs The MOS FETs incorporated in R2J20653ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 11 of 12 R2J20653ANP Preliminary Package Dimensions JEITA Package Code P-HVQFN40-p-0606-0.50 RENESAS Code PVQN0040KC-A Previous Code — MASS[Typ.] — HD D 2.2 0.2 0.2 B INDEX 1pin 40 4-C0.50 40 1pin B 2.2 C0.3 E /2 1.95 A 2.2 0.7 0.2 Reference Symbol HD/2 D /2 HE E 1.95 HE/2 t S AB e y1 S X4 f S AB b 2.2 X4 20° 20° L1 x S AB S A A2 0.69 A1 c2 Lp yS Ordering Information Part Name R2J20653ANP#G3 Quantity 2500 pcs Shipping Container Taping Reel REJ03G1849-0100 Rev.1.00 Dec 07, 2009 Page 12 of 12 2.05 ZD ZE 4(0 .1 39 ) 1.95 2-A section CAV No. Die No. Dimension in Millimeters 1.95 2.05 Min Nom Max D 5.95 6.00 6.05 5.95 6.00 6.05 E A2 0.87 0.89 0.91 f — — 0.20 A 0.865 0.91 0.95 A1 0.005 0.02 0.04 b 0.17 0.22 0.27 b1 0.16 0.20 0.24 — 0.50 — e Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 t — — 0.20 HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — ZE — 0.75 — L1 0.06 0.10 0.14 c1 0.17 0.20 0.23 c2 0.17 0.22 0.27 Sales Strategic Planning Div. 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