R2J20655NPG0

Preliminary Datasheet R2J20655NP Integrated Driver - MOS FET (DrMOS) Description R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 The R2J20655NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose. Features                Based on Intel 6  6 DrMOS Specification. Built-in power MOS FET suitable for Desktop, Server application. Low-side MOS FET with built-in SBD for lower loss and reduced ringing. Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers High-frequency operation (above 1 MHz) possible VIN operating-voltage range: 27 Vmax Large average output current (Max.35 A) Achieve low power dissipation Controllable driver: Remote on/off Low side MOS FET disabled function for DCM operation Double thermal protection: Thermal Warning & Thermal Shutdown Built-in bootstrapping Switch Small package: QFN40 (6 mm  6 mm  0.95 mm) Pb-free/Halogen-Free Outline Integrated Driver-MOS FET (DrMOS) QFN40 package 6 mm × 6 mm VCIN Reg5V BOOT GH VIN 40 THWN Driver Pad High-side MOS Pad 1 10 11 DISBL# MOS FET Driver LSDBL# Low-side MOS Pad PWM 31 CGND GL PGND 30 (Bottom view) 21 20 VSWH R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 1 of 17 R2J20655NP Preliminary Block Diagram Driver Chip VCIN Reg5V BOOT GH THWN DISBL# THWN THDN UVL Boot SW VIN High Side MOS FET Reg5V 2 μA CGND Supervisor Level Shifter 20 k CGND Reg5V 160 k LSDBL# VSWH Overlap Protection. & Logic Reg5V Reg5V Low Side MOS FET PWM Input Logic (TTL Level) (3 state in) 35 k PGND CGND GL Notes: 1. Truth table for the DISBL# pin DISBL# Input Driver Chip Status "L" Shutdown (GL, GH = "L") "Open" Shutdown (GL, GH = "L") "H" Enable (GL, GH = "Active") 3. Output signal from the UVL block UVL output Logic Level "H" For shutdown "L" VL VH VCIN For active 2. Truth table for the LSDBL# pin LSDBL# Input GL Status "L" "Open" "H" "L" "Active" "Active" 4. Output signal from the THWN block "H" Thermal Warning Logic Level "L" Thermal Warning TIC(°C) TwarnL TwarnH Normal operating 5. Truth table for the THDN block Driver IC Temp. Driver Chip Status < 150°C Enable (GL, GH = "Active") > 150°C Shutdown (GL, GH = "L") (latch-off) R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 2 of 17 R2J20655NP Preliminary Pin Arrangement Reg5V 2 VSWH CGND BOOT 10 9 8 7 6 5 4 VCIN 3 VIN VIN VIN GH VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND LSDBL# 1 40 39 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PWM DISBL# THWN CGND GL VSWH VSWH VSWH VSWH VSWH VIN CGND 38 37 36 35 VSWH 34 33 32 31 PGND PGND PGND PGND PGND PGND PGND PGND VSWH (Top view) Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name LSDBL# Reg5V VCIN BOOT CGND GH VIN VSWH PGND GL THWN DISBL# Pin No. 1 2 3 4 5, 37, Pad 6 8 to 14, Pad 7, 15, 29 to 35, Pad 16 to 28 36 38 39 Description Low-side gate disable +5 V logic power supply output Control input voltage Bootstrap voltage pin Control signal ground High-side gate signal Input voltage Phase output/Switch output Power ground Low-side gate signal Thermal warning Signal disable Remarks When asserted "L" signal, Low-side gate disable Driver Vcc input To be supplied +5 V through internal switch Should be connected to PGND externally Pin for monitor Pin for monitor Thermal warning when over 115°C Disabled when DISBL# is "L". This Pin is pulled low when internal IC over the thermal shutdown level, 150°C. Capable of both 3.3 V and 5 V logic input PWM 40 PWM drive logic input R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 VSWH Page 3 of 17 R2J20655NP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Switch node voltage BOOT voltage Supply voltage PWM voltage Symbol Pt(25) Pt(110) Iout VIN(DC) VIN(AC) VSWH(DC) VSWH(AC) VBOOT(DC) VBOOT(AC) VCIN Vpwm Rating 25 8 35 –0.3 to +27 30 27 30 32 36 –0.3 to +27 –0.3 to +5.5 @UVL OFF –0.3 to +0.3 @UVL ON –0.3 to Reg5V + 0.3 –0.3 to VCIN + 0.3 –0.3 to +6 –20 to +0.1 0 to 1.0 –40 to +150 –55 to +150 Units W A V V V V V Note 1 2 2, 4, 6 2 2, 4, 6 2 2, 4, 6 2 2, 4 2, 5 2, 7, 8 2 2, 7 3 3 Other I/O voltage Reg5V voltage Reg5V current THWN/THDN current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. 5. 6. 7. 8. Vdisbl, Vlsdbl Vreg5V Ireg5V Ithwn, Idisbl Tj-opr Tstg V V mA mA °C °C Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. Rated voltages are relative to voltages on the CGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode). This rating is when UVL (Under Voltage Lock out) is effective (lock out mode). The specification values indicated "AC" are limited within 10 ns. This rating is when the external power-source is applied to Reg5V pin. Reg5V + 0.3 V < 6 V Safe Operating Area 45 Average Output Current (A) 40 35 30 25 20 15 10 5 0 0 VOUT = 1.3 V VIN = 12 V VCIN = 5 V L = 0.45 μH Fsw = 1 MHz 25 50 75 100 125 PCB Temperature (°C) 150 175 R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 4 of 17 R2J20655NP Preliminary Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Symbol VIN VCIN Rating 4.5 to 22 4.5 to 5.5 or 8 to 22 Units V V Note When the usage of VCIN = 4.5 V to 5.5 V, VCIN should be connected to Reg5V (Refer to "Pin Connection") Electrical Characteristics (Ta = 25°C, VCIN = 12 V, VSWH = 0 V, unless otherwise specified) Supply Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM input PWM input high level PWM input low level PWM input resistance PWM input tri-state range Shutdown hold-off time Enable level Disable level Input current THDN on resistance Low-side activation level Low-side disable level Input current Warning temperature Temperature hysteresis THWN on resistance THWN leakage current Shutdown temperature Output voltage Line regulation Load regulation Note: Symbol VH VL dUVL ICIN ICIN-DISBL VH-PWM VL-PWM RIN-PWM VIN-tri tHOLD-OFF * VENBL VDISBL IDISBL 1 RTHDN * VLSDBLH VLSDBLL ILSDBL TTHWN *1 THYS *1 RTHWN *1 ILEAK 1 Tstdn * Vreg Vreg-line Vreg-load 1 Min 7.0 6.6 — — — 2.6 — 6.5 1.4 — 2.0 — — 0.2 2.0 — –52 100 — 0.2 — 130 4.95 –10 –10 Typ 7.4 7.0 0.4 49 — — — 12.5 — 150 — — 2.0 0.5 — — –26 115 15 0.5 — 150 5.2 0 0 Max 7.8 7.4 — — 800 — 0.8 25 2.0 — — 0.8 5.0 1.0 — 0.8 –12 130 — 1.0 1.0 — 5.45 10 10 Units V V V mA A V V k V ns V V A k V V A °C °C k A °C V mV mV Test Conditions VH – VL fPWM = 1 MHz, Ton_pwm = 120 ns DISBL# = 0 V, PWM = LSDBL# = Open 3.3 V/5.0 V PWM interface PWM = 1 V 3.3 V/5.0 V PWM interface DISBL# input DISBL# = 1 V DISBL# = 0.2 V LSDBL# input Thermal warning LSDBL# = 1 V Driver IC temperature THWN = 0.2 V THWN = 5 V Driver IC temperature Thermal shutdown 5V regulator VCIN = 12 V to 16 V Ireg = 0 to 10 mA 1. Reference values for design. Not 100% tested in production. R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 5 of 17 R2J20655NP Preliminary Typical Application (1) Desktop/Server Application +12 V VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH VSWH PGND GL +5 V VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH PWM1 VSWH PGND GL PWM Control Circuit PWM2 +1.3 V PWM3 PWM4 VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH VSWH Power GND Signal GND PGND GL VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH VSWH PGND GL R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 6 of 17 R2J20655NP Preliminary Typical Application (cont.) (2) Notebook Application +19 V +5 V VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH VSWH PGND GL VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH PWM1 VSWH PGND GL PWM Control Circuit PWM2 +1.1 V PWM3 VCIN THWN DISBL# Reg5V BOOT VIN R2J20655NP PWM CGND LSDBL# GH VSWH Power GND Signal GND PGND GL R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 7 of 17 R2J20655NP Preliminary Pin Connection (1) Single 12 V Application 0.1 μF 0 to 10 Ω 1.0 μF CGND VIN 12 V 1.0 μF Low Side Disable Signal INPUT CGND 10 μF × 4 11 12 10 9 8 VIN 7 VSWH 6 GH 5 CGND 4 BOOT 3 VCIN 2 Reg5V 1 LSDBL# PWM 40 PWM INPUT Thermal Shutdown PGND 13 14 VIN 15 VSWH 16 PGND 17 18 19 VIN PAD CGND PAD DISBL# 39 THWN 38 CGND 37 10 kΩ R2J20655NP VSWH PAD VSWH GL 36 VSWH 35 34 33 10 kΩ VCIN VCIN Thermal Warning 32 PGND 20 31 21 22 23 24 25 26 27 28 29 30 Power GND Signal GND 0.45 μH Vout PGND PGND (2) VCIN 5 V Application 0.1 μF 0 to 10 Ω VIN 12 V 1.0 μF Low Side Disable Signal INPUT 5.0 V External Power Supply 10 μF × 4 11 12 CGND 10 9 8 VIN 7 VSWH 6 GH 5 CGND 4 BOOT 3 VCIN 2 Reg5V 1 LSDBL# PWM 40 PWM INPUT Thermal Shutdown PGND 13 14 VIN 15 VSWH 16 PGND 17 18 19 VIN PAD CGND PAD DISBL# 39 THWN 38 CGND 37 10 kΩ R2J20655NP VSWH PAD VSWH GL 36 VSWH 35 34 33 10 kΩ 5V 5V Thermal Warning 32 PGND 20 31 21 22 23 24 25 26 27 28 29 30 Power GND Signal GND 0.45 μH Vout PGND PGND R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 8 of 17 R2J20655NP Preliminary Test Circuit Vinput A IIN V VIN Vcont A ICIN VCIN V VCIN DISBL# BOOT VIN R2J20655NP Reg5V LSDBL# VSWH 5 V pulse PWM CGND GH GL PGND Electric load IO Note: PIN = IIN × VIN + ICIN × VCIN POUT = IO × VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN – POUT Ta = 27°C Average Output Voltage Averaging V VO circuit R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 9 of 17 R2J20655NP Preliminary Typical Data Power Loss vs. Output Current 9 VIN = 12 V Power Loss vs. Input Voltage 1.7 VCIN = Reg5V = 5 V 8 VCIN = Reg5V = 5 V VOUT = 1.3 V L = 0.45 μH 1.6 VOUT = 1.3 V Normalized Power Loss @ VIN = 12 V 7 fPWM = 600 kHz Power Loss (W) 1.5 L = 0.45 μH 1.4 1.3 1.2 1.1 1.0 0.9 fPWM = 600 kHz IOUT = 25 A 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 0.8 4 6 8 10 12 14 16 18 20 22 Output Current (A) Input Voltage (V) Power Loss vs. Output Voltage 1.7 VIN = 12 V Power Loss vs. Switching Frequency 1.7 VIN = 12 V 1.6 VCIN = Reg5V = 5 V Normalized Power Loss @ VOUT = 1.3 V Normalized Power Loss @ fPWM = 600 kHz 1.6 VCIN = Reg5V = 5 V VOUT = 1.3 V 1.5 L = 0.45 μH 1.4 1.3 1.2 1.1 1.0 0.9 fPWM = 600 kHz 1.5 L = 0.45 μH IOUT = 25 A IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 0.8 250 500 750 1000 1250 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Output Voltage (V) Switching Frequency (kHz) R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 10 of 17 R2J20655NP Preliminary Typical Data (cont.) Power Loss vs. Output Inductance 1.7 VIN = 12 V Power Loss vs. VCIN 1.7 VIN = 12 V 1.6 VCIN = Reg5V = 5 V VOUT = 1.3 V 1.6 VOUT = 1.3 V Normalized Power Loss @ L = 0.45 μH Normalized Power Loss @ VCIN = Reg5V = 5 V 1.5 fPWM = 600 kHz IOUT = 25 A 1.5 L = 0.45 μH 1.4 1.3 1.2 1.1 1.0 0.9 0.8 4.5 fPWM = 600 kHz IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (μH) 5.0 5.5 6.0 VCIN = Reg5V (V) Average ICIN vs. Switching Frequency 70 60 VIN = 12 V VCIN = Reg5V = 5 V VOUT = 1.3 V L = 0.45 μH IOUT = 0 A Average ICIN (mA) 50 40 30 20 10 250 500 750 1000 1250 Switching Frequency (kHz) R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 11 of 17 R2J20655NP Preliminary Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, lowside MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & DISBL# The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the built-in 5 V regulator is disabled as long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input is driven to 7.0 V or less. The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V pin. The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is more than 4.3 V (typ.), the driver state becomes active (figure 1.1). Supervisor circuit has hysteresis and its shutdown level of Supervisor is 3.8 V (typ.). Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5 V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V. The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit , the built-in 5 V regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and the 5 V regulator is not disabled. Voltages from –0.3 V to VCIN+0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. VCIN L H H H DISBL#  L H Open REG5V 0 Active Active Active Driver State Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L) 12 V VCIN VCIN > 7.4 V VCIN 5V IN OUT OUT Reg5V IN Reg5V External 5 V UVL & 5 V Regulator To Internal Logic Supervisor UVL & 5 V Regulator To Internal Logic Supervisor Figure 1.1 Typical 12 V Input Application (Activate Built-in 5 V Regulator) Figure 1.2 External 5 V Application R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 12 of 17 R2J20655NP PWM & LSDBL# Preliminary The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM L H GH L H GL H L The LSDBL# pin is the Low Side Gate Disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. Figure 2 shows the Typical high side and low side gate switching and Inductor current (IL) during "Continuous Conduction Mode (CCM)" and low side gate disabled when asserting LSDBL# signal. This pin is internally pulled up to Reg5V with 160 k resistor. When low side disable function is not used, keep this pin open or pulled up to VCIN. CCM Operation (LSDBL# = "H" or Open mode) IL GH GL Figure 2.1 Typical Signals during CCM DCM Operation (LSDBL# = "L") IL 0A GH GL Figure 2.2 Typical Signals during DCM R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 13 of 17 R2J20655NP Preliminary The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tristate function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 150ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 2.6 V or more is required to make the circuit return to normal operation. 150 ns (tHOLD-OFF) 150 ns (tHOLD-OFF) 2.0 V PWM 1.4 V GH GL 150 ns (tHOLD-OFF) 150 ns (tHOLD-OFF) 2.0 V PWM 1.4 V GH GL Figure 3 PWM Shutdown-Hold Time Signal R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 14 of 17 R2J20655NP Preliminary The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is asserted high signal, M1 becomes ON and shifts to normal operation. Reg5V M1 25 k PWM Pin Input Logic 12.5 k Tri-state detection signal To internal control Figure 4 Equivalent Circuit for the PWM-pin Input THWN & THDN This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function. This Thermal Warning feature is the indication of the high temperature status. THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems with the thermal warning implementation. When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates. This signal is only indication for the system controller and does not disable DrMOS operation. When thermal warning function is not used, keep this pin open. Thermal warning "H" THWN output Logic Level "L" Normal operating 100 115 TIC (°C) Figure 5 THWN Trigger Temperature R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 15 of 17 R2J20655NP THDN is an internal thermal shutdown signal when driver IC becomes over 150°C. Preliminary This function makes High Side MOS FET and Low Side MOS FET turn off for the device protection from abnormal high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes under UVL level (or under supervisor shutdown level). Figure 6 shows the example of two types of DISBL# connection with the system controller signal. Driver IC Temp. < 150°C > 150°C Driver Chip Status Enable (GL, GH = "Active") Shutdown (GL, GH = "L") 5V 10 k DISBL# 2 μA To Internal Logic 10 k DISBL# 2 μA To Internal Logic To shutdown signal Thermal Shutdown Detection ON/OFF signal Thermal Shutdown Detection Figure 6.1 THDN Signal to the System Controller Figure 6.2 ON/OFF Signal from the System Controller MOS FET The MOS FETs incorporated in R2J20655NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the lowside MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 Page 16 of 17 R2J20655NP Preliminary Package Dimensions JEITA Package Code P-HVQFN40-p-0606-0.50 RENESAS Code PVQN0040KE-A Previous Code — MASS[Typ.] — HD D 2.2 0.2 0.2 B INDEX 1pin 40 4-C0.50 40 1pin B 2.2 C0.3 E /2 1.95 A 2.2 0.7 0.2 Reference Symbol HD/2 D /2 HE E 1.95 HE/2 t S AB e y1 S X4 f S AB b 2.2 X4 20° 20° L1 x S AB S A A2 0.69 A1 c2 Lp yS Ordering Information Part Name R2J20655NP#G0 Quantity 2500 pcs Shipping Container Taping Reel R07DS0200EJ0100 Rev.1.00 Jan 25, 2011 2.05 ZD ZE 4(0 .1 39 ) 1.95 2-A section CAV No. Die No. Dimension in Millimeters 1.95 2.05 Min Nom Max D 5.95 6.00 6.05 5.95 6.00 6.05 E A2 0.87 0.89 0.91 f — — 0.20 A 0.865 0.91 0.95 A1 0.005 0.02 0.04 b 0.17 0.22 0.27 b1 0.16 0.20 0.24 — 0.50 — e Lp 0.40 0.50 0.60 x — — 0.05 y — — 0.05 y1 — — 0.20 t — — 0.20 HD 6.15 6.20 6.25 HE 6.15 6.20 6.25 ZD — 0.75 — ZE — 0.75 — L1 0.06 0.10 0.14 c1 0.17 0.20 0.23 c2 0.17 0.22 0.27 Page 17 of 17 Notice 1. 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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com © 2011 Renesas Electronics Corporation. All rights reserved. Colophon 1.0