R2J20701NP

R2J20701NP Peak Current Mode Synchronous Buck Controller with Power MOS FETs REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Description This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET, low-side MOS FET, and PWM controller in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver circuit, making this device suitable for large-current high-efficiency buck converters. In a simple peak-current mode topology, stable operation is obtained in a closed power loop, and a fast converter is easily realized with the addition of simple components. Furthermore, the same topology can be applied to realize converters for parallel synchronized operation with current sharing, and two-phase operation. The package also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Features • • • • • • • • • • • • • • Three chips in one package for high-efficiency and space saving Large average output current (35 A) Wide input voltage range: 8 to 14 V 0.6 V reference voltage accurate to within 1% Wide programmable switching frequency: 200 kHz to 1 MHz Fast response by peak-current-mode topology. Simple current sharing (up to five modules in parallel) Two-phase operation in parallel operation Built-in SBD for boot strapping On/off control Hiccup operation under over load condition Tracking function Thin small package: 56-pin QFN (8 mm × 8 mm) Pb-free Applications • • • • Network equipment Telecommunications equipment Servers POL modules Typical Characteristic Curve 95 Efficiency (%) 90 85 80 75 0 5 10 15 20 25 30 35 VIN = 12 V VOUT = 1.8 V L = 440 nH CO = 600 µF Frequency = 500 kHz No airflow Ta = 27°C Iout (A) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 1 of 27 R2J20701NP Application Circuit Example VIN (8 V to 14 V) ON/OFF SYNC REG5 BOOT IREF CT REG5 DRV5 VCIN VIN VOUT (1.8 V) TRK-SS FB RAMP Ishare SW Controller Chip EO SGND CS REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 2 of 27 PGND ON/OFF REG5 DRV5 BOOT VCIN R2J20701NP SBD VIN Supervisor UVLO Reference current generator ON/OFF REG GOOD Idh Block Diagram IREF 5 V (4%) Regulator 5.25 V (4%) Regulator 8 V to 14 V CT OSC Max. Duty RES 50 ns RES REG GOOD REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 3 of 27 Active current sensing Pulse generator Max. Duty ON/OFF PWM OCP R S Idh 18500 Q Q SYNC 55 ns Blanking (Bi-lateral) VOUT EO Gate drive logic circuit SW REG5 Error Amp. REG5 DRV5 0.6 V (1%) TRK-SS ON/OFF REG GOOD OCP Current sense comparator 1.5 V OCP hiccup control (1024 pulses blank) PGND VOUT 50 k 0.1 V 50 k OCP comparator 490 µA FB SGND Ishare RAMP CS R2J20701NP Pin Arrangement SGND BOOT Ishare 2 REG5 VCIN IREF VIN VIN VIN VIN VIN SW EO 14 13 12 11 10 9 8 7 6 5 4 3 FB 1 56 55 54 VIN 15 VIN 16 VIN 17 VIN VIN 18 VIN 19 VIN 20 SW 21 PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 TRK-SS CT RAMP CS SGND DRV5 ON/OFF SYNC SW SW SW SW SW SW SGND 53 52 51 50 49 48 SW 47 46 45 44 43 SW PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND (Top view) Package: 56-pin QFN (8 mm × 8 mm, 0.5-mm pin pitch) Note: All die-pads (three pads in total) should be soldered to PCB. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 4 of 27 PGND SW SW R2J20701NP Pin Description Pin Name VIN SW PGND SGND VCIN BOOT REG5 ON/OFF IREF CT SYNC TRK-SS FB EO Ishare RAMP CS DRV5 Pin No. 10 to 20 9, 21, 40 to 48 22 to 39 6, 52 7 8 5 50 4 55 49 56 1 3 2 54 53 51 Description Input voltage for the buck converter. Switching node. Connect a choke coil between the SW pin and dc output node of the converter. Ground of the power stage. Ground of the IC chip. Input voltage for the control circuit. Bootstrap voltage pin. A bootstrap capacitor should be connected between the BOOT and SW pin. +5 V logic power-supply output. Signal disable pin. Reference current generator for the IC. Timing capacitor pin for the oscillator. This pin has a select function for operation in slave mode. I/O pin for synchronous operation. Start-up timing control input. Feedback voltage input for the closed loop. Error amplifier output pin. For current-sharing bus. RAMP signal input pin for peak current mode PWM control. Current output pin of active current sensing circuit. +5.25 V generator output for driving power MOS FETs. Remarks Should be externally connected to SGND. Should be externally connected to PGND. Should be externally connected to VIN. To be supplied +5 V through the internal SBD. Requires decoupling from the GND plane by a capacitance 0.1 µF. Disabled when ON/OFF pin is in the low state. Should be connected via 27 kΩ to the SGND pin. If the pin voltage is 4 V, the IC operates in slave mode. Requires connection to an RC circuit for loop compensation. Simply connect the Ishare pins of all devices to get balanced current. Appropriate resistance is required between CS and the GND plane. Requires decoupling from the GND plane by a capacitance from 0.1 µF to 1.0 µF. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 5 of 27 R2J20701NP Absolute Maximum Ratings (Ta = 25°C) Item Power dissipation Average output current Input voltage Switch node voltage BOOT pin voltage ON/OFF pin voltage SYNC pin voltage Voltage on other pins REG5 current Ishare current TRK-SS dc current IREF current EO sink current Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. Symbol Pt(25) Pt(100) Iout Vin (dc), Vcin (dc) Vin (ac), Vcin (ac) Vsw (dc) Vsw (ac) Vboot (dc) Vboot (ac) Von/off Vsync Vic Ireg5 Ishare Itrk Iref Ieo Tj-opr Tstg Rating 25 8 35 –0.3 to +16 20 16 20 22 25 –0.3 to VIN –0.3 to +5.5 –0.3 to (REG5 + 0.3) –10 to 0 –500 to 0 0 to 1 –120 to 0 0 to 2 –40 to +150 –55 to +150 Unit W A V V V V V V mA µA mA µA mA °C °C Note 1 1 2 2, 4 2 2, 4 2 2, 4 2 2 2 3 3 3 3 3 Pt(25) represents a PCB temperature of 25°C, and Pt(100) represents 100°C. Rated voltages are relative to voltages on the SGND and PGND pins. For rated current, (+) indicates inflow to the chip and (–) indicates outflow. Ratings for which “ac” is indicated are limited to within 100 ns. Safe Operating Area 40 35 30 25 20 15 10 5 0 0 Average Output Current (A) VIN = 12 V VOUT = 1.3 V 25 50 75 100 125 150 175 PCB Temperature (°C) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 6 of 27 R2J20701NP Electrical Characteristics (Ta = 25°C, VIN = VCIN = 12 V, unless otherwise specified) Supply Item VIN start threshold VIN shutdown threshold UVLO hysteresis Input bias current Input shutdown current 5-V regulator 5.25-V regulator Remote On/off Reference current generator Oscillator Output voltage Line regulation Load regulation Output voltage Disable threshold Enable threshold Input current IREF pin voltage Symbol VH VL dUVL Iin Isd Vreg Vreg-line Vreg-load Vdrv Voff Von Ion/off VIref Min 6.8 6.45 — 36 3.0 4.8 –5 –8 5.04 1.0 2.0 0.5 2.6 Typ 7.2 6.85 0.35 *1 73 4.5 5.0 0 –3 5.25 1.3 2.5 2.0 2.7 Max 7.6 7.25 — 110 6.0 5.2 +5 +2 5.46 1.6 3.0 5.0 2.8 Unit V V V mA mA V mV mV V V V µA V Von/off = 1 V Riref = 27 kΩ Test Conditions CT = 68 pF, Duty cycle = 50% On/off = 0 V VIN = 10 to 16 V Ireg = 0 to 10 mA CT oscillating frequency SW switching frequency CT higher trip voltage CT lower trip voltage CT source current CT sink current CT threshold for twophase operation CT threshold for synchronous operation SYNC frequency SYNC high voltage SYNC low voltage SYNC input threshold Feedback voltage Input bias current Output source current Output sink transient current Voltage gain Band width Resistance connected to the Ishare pin Fct Fsw Vhct Vlct Ict-src Ict-snk Vct-two Vct-one Fsync Vh-sync Vl-sync Vsync Vfb Ifb Io-src Io-snk Av BW Rshare — 418 — — –170 150 3.6 0.8 418 4.0 0 1.0 594 –0.1 150 5.0 — — 70 930 *1 465 3 *1 2 *1 –160 160 4.0 1.0 465 5.0 — 2.0 600 0 200 10.6 80 *1 15 *1 100 — 512 — — –150 170 4.4 1.2 512 — 1.0 3.0 606 +0.1 250 19.0 — — 130 kHz kHz V V µA µA V V kHz V V V mV µA µA mA dB MHz kΩ CT = 68 pF CT = 68 pF CT = 68 pF CT = 68 pF CT = 1.5 V CT = 3.5 V SYNC and pulse generator Error amplifier CT = 68 pF Rsync = 51 kΩ to GND Rsync = 51 kΩ to REG5 CT = 0 V or 5 V TRK-SS = 1 V FB = 0.6 V EO = 4 V, FB = 0 V EO = 1 V, FB = 1 V EO = 0 V. Ishare = 1 V Note: 1. These are reference values for design and have not been 100% tested in production. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 7 of 27 R2J20701NP (Ta = 25°C, VIN = VCIN = 12 V, unless otherwise specified) Current sense Item CS current ratio Leading edge blanking time CS comparator delay to output OCP comparator threshold on CS pin Hiccup interval RAMP offset voltage CS offset current Note: Symbol Idh/Ics TLD Td-cs Vocp Tocp Vramp-dc Ics-dc Min — — — 1.43 1.98 77 — Typ 18500 *1 55 * 50 * 1.5 2.20 92 490 * 1 1 Max — — — 1.57 2.42 107 — Unit — ns ns V ms mV µA Test Conditions 1 CT = 68 pF CS = 0 V 1. These are reference values for design and have not been 100% tested in production. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 8 of 27 R2J20701NP Description of Operation Peak Current Control The control IC operates in a current-programmed control mode, in which the output of the converter is controlled by the choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active current-sensing circuit (ACS), the output current of which is 1/18500 (54 ppm) of the MOS FET current. The ACS current is then converted to a certain voltage by the external resistor on the CS pin. The CS voltage is fed to the RAMP pin by an external connection, then compared with the current-control signal which is determined from the error amplifier output voltage (EO) via an NPN transistor and resistor network. To start with, the RES pulse from the pulse generator resets a latch, then the high-side MOS FET is turned on. The latch output (Q bar) is toggled when the voltage on RAMP reaches the level of the current-control signal on EO, the high-side MOS FET is turned off, and the low-side MOS FET is turned off after a certain dead-time interval. The IC remains in this state until the arrival of the next RES pulse. Since current information is used in the control loop, loop compensation design for the converter is simple and easy. Maximum Duty-Cycle Limitation If the current-sense comparator output is not toggled 50-ns prior to the arrival of the next RES pulse, an internal maximum duty pulse is generated and forces toggling of the SR latch. So, the duty cycle of the high-side MOS FET is limited by the maximum duty period. The maximum duty period of the high-side MOS FET depends on its switching frequency. Maximum duty period = 1 – 50 ns × Fsw OCP Hiccup Operation Once the voltage of CS exceeds 1.5 V, OCP hiccup circuit disables switching operation of the IC and MOS FETs. Internal circuitry also pulls the TRK-SS pin down to SGND. The IC is turned off for a period of 1024 RES pulses; after this has elapsed, switching operation of the IC is restarted from the soft-start state. UVLO and On/off Control When VIN (=Vcin) is below the start-up voltage, that is, is in the UVLO condition, functioning of the IC is disabled. The oscillator is turned off, both high- and low-side MOS FETs are turned off, and the TRK-SS pin is pulled down. Furthermore, if the ON/OFF pin is in the low state or left open, functioning of the IC is disabled and both MOS FETs are turned off. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 9 of 27 R2J20701NP Oscillator and Pulse Generator The frequency of oscillation is set by the value of the external capacitor connected to the CT pin. This frequency is twice as high as the actual switching frequency. The frequencies are determined by the following equations: Oscillator frequency; Fct = 160 µA / {2 × (CT(F) + 18 pF) × 1 V} Switching frequency; Fsw = 0.5 × Fct (Hz) (in Hz) When the chip is operating in standalone mode or as the master chip for parallel operation, it requires a capacitor on the CT pin. In this case, the SYNC pin outputs a synchronization signal with a frequency of Fsw. In operation as a slave chip, the CT pin must be connected to SGND or REG5, after which it acts as an input pin for the synchronized operation by external clock. The internal circuit is synchronized its rising edge when CT4.4 V. In two-phase operation in parallel configuration, the CT pin should be at a voltage over 4.4 V. Mode Item CT pin SYNC pin Synchronizing trigger Standalone Has a cap. Output mode — Master Has a cap. Output mode — Slave –0° < 0.8 V Input mode Rising Slave –180° > 4.4 V Input mode Falling The internal RES pulse and maximum duty-cycle-control pulses are produced from the signal at half the oscillator frequency in standalone and master operating modes. In slave mode, internal pulses are produced from the externally supplied input signal on the SYNC pin. Current Sharing It is easy to obtain balanced-current operation in a parallel configuration due to the application of peak current control. To obtain current-sharing operation, simply tie the buffered error-amplifier outputs of all of the devices (Ishare pins) together. No more than five devices can operate in parallel. Soft Start Both simple soft starting and tracking start-up can be realized with the setup of the TRK-SS pin provided for soft-starts. The error amplifier has three inputs, two of which are designed to give priority to low-level non-inverting inputs for the amplifier. All that is required to realize soft-start operation is to simply attach an RC charging circuit to the TRK-SS pin. The soft-start period is determined by the following equation, with C and R as the values for the RC charging circuit attached to the TRK-SS pin. Tss = –C · R · Ln (1 – 0.6 V / REG5) (s) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 10 of 27 R2J20701NP Application Example Start-up Settings Case 1) Standalone or master chip in parallel operation With the RC network on the TRK-SS pin, the voltage on the pin should ramp up slowly. ON/OFF R REG5 TRK-SS C Vout 0.6 V TRK-SS TSS = − CR × Ln (1 − 0.6 V / 5 V) (s) Case 2) Coincident tracking The TRS-SS signal for channel two is the voltage from Vout1 after division by a resistor network. Vout1 must be greater than Vout2. Cross-talk is not generated between the channels. R REG5 Channel 1 TRK-SS SW FB R1 Vout1 (nominal) = 0.6 V × (R1 + R2) / R2 From Vout1 R2 Vout1 C R3 REG5 Channel 2 TRK-SS SW FB R3 Vout2 (nominal) = 0.6 V × (R3 + R4) / R4 R4 Vout2 R4 Vout1 Output voltage Vout2 Time REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 11 of 27 R2J20701NP Case 3) Retiometric tracking The TRS-SS of channel two is tied to TRK-SS of channel 1. No cross talk is observed between the channels. R REG5 Channel 1 TRK-SS SW FB R1 Vout1 (nominal) = 0.6 V × (R1 + R2) / R2 R2 Vout1 C R REG5 Channel 1 TRK-SS SW FB R3 Vout2 (nominal) = 0.6 V × (R3 + R4) / R4 R4 Vout2 C Vout1 Output voltage Vout2 Time REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 12 of 27 R2J20701NP Case 4) Current sharing or two-phase operation In the case of master–slave operation, the TRK-SS pin on the master device should be attached to an RC network for soft starts. TRK-SS pins of slave devices should be tied to the master’s TRK-SS pin. The error amplifiers on the slave devices can be disabled by pulling up the corresponding FB pins to REG5, and the slave devices do not require loop-compensation networks. R REG5 Channel 1 (Master) SW TRK-SS Ishare FB CT Vout1 R1 Vout (nominal) = 0.6 V × (R1 + R2) / R2 C R2 REG5 Channel 2 (Slave) SW TRK-SS Ishare CT FB R C To SGND (for current sharing and synchronized operation) To REG5 (for current sharing and two-phase operation) Choice of The Resistance of CS Pin The CS pin is a current-output pin. A current 1/18500 of that of the high-side MOS FET flows through this pin, which also has a dc current offset of 490 µA. The converter’s maximum current is determined by the voltage on the CS pin, i.e. 1.5 V, and by the value of the external resistor attached to this pin. The resistance is determined as shown below. Specification: L = 360 nH, Vin = 12 V, Vout = 1.8 V, Fsw = 500 kHz, Iout(max) = 25 A Current through the choke coil is ILpp = (Vin – Vout) × Vout / (L × Vin × Fsw) = 8.5 A (p-p) Peak choke current is the current when Io is at its maximum, i.e. Ilmax = Io(max) + 0.5 × ILpp = 25A + 4.25A = 29.25 A Maximum CS pin output current is; Icsmax = Ilmax / 18500 + Ics-dc = 29.25 A / 18500 + 490 µA = 2.071 mA The ideal resistance for attachment to the CS pin is RCS = Vcl / Icsmax =1.5 V / 2.071 mA = 724 Ω Therefore choose 750 Ω as the value of the resistor for attachment to the CS pin. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 13 of 27 R2J20701NP Output Voltage Setting The error amplifier of the device has an accurate 0.6 V reference voltage. Feedback thus leads to a voltage of about 0.6 V on the FB pin once the converter system has stabilized, so the output voltage is Vout = 0.6 V × (R1 + R2) / R2 R REG5 Vout TRK-SS SW FB R1 C CT R2 Loop Compensation Peak-current control makes design in terms of phase margins easier than is the case with voltage control. This is because of differences between the characteristics of the PWM modulator and power stage in the two methods. Figures 1 and 2 show the behavior of the PWM modulator and power stage in the cases of voltage control and peak current control, respectively. Gain (dB) −40 dB/dec Gain (dB) −20 dB/dec freq. (Hz) 0 Phase (deg) −180 freq. (Hz) 0 Phase (deg) −90 −180 freq. (Hz) freq. (Hz) Figure 1 Bode Plot of Modulator + Power Stage (Voltage Mode) Figure 2 Bode Plot of Modulator + Power Stage (Peak Curent Mode) Feed-forward current to the modulator in the case of peak-current control means that the system is single pole, so we see a –20 dB/decade cutoff and phase margin of 90° in the Bode plot. In voltage control, the system configures a twopole pole system. That is why rather complicated loop compensation of the error amplifier is required, such as type-III compensation. The design of effective compensation is thus much simpler in the case of peak-current control (refer to figure 3). REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 14 of 27 R2J20701NP Rf Cf EO R1 FB Vout R2 0.6 V reference 50 kΩ Amplifier output: to current-sense comparator 50 kΩ Figure 3 Error Amplifier Compensation Design example Specification: L = 360 nH, Co = 600 µF, Fsw = 500 kHz, Vin = 12 V, Vout = 1.8 V, R1 = 2 kΩ, R2 = 1 kΩ, RCS = 750 Ω 1. Flat-band gain of error amplifier The flat-band gain is; Af = Rf / (R1 // R2) / 2 × {R2 / (R1 + R2)} Hence, Rf = 2 × Af × R1 ……(1) In the Bode plot, the total gain should be less than 1 (0 dB) at the switching frequency. The total gain at Fsw (= Asw) depends on the flat-band gain, so Af should be expressed as follows. Af = Asw × 2 π × Fsw × Co × RCS / Nt ……(2) Here, Nt = Idh / Ics = 18500 In the typical way, the value chosen for Asw is in the range from 0.1 to 0.5, since this produces a stable control loop. The transient response will be faster if a larger Asw is adopted ,but the system might be unstable. We choose 0.2 for Asw in the example below. Af = 0.2 × 2 π × 500 kHz × 600 µF × 750 Ω / 18500 = 15.283 Rf = 2 × 15.283 × 2 kΩ = 61.132 kΩ Therefore, we select a value of 62 kΩ for Rf. 2. Selecting the Cf value to determine the frequency of the zero The frequency of the zero established by Cf and Rf is about ten times the frequency of the pole for the power stage and modulator. We must start with the dc gain of the power stage and modulator. A0 = 2 × Nt / RCS × L × Vin × Fsw SQRT {Vin2 − 8 × L × Vin × Fsw × (VCS0 × Nt / RCS) } ……(3) Here VCS0 is the peak ac voltage on the CS pin when the load current is zero, thus VCS0 = 0.5 × RCS × (Vin – Vout) × Vout / (L × Vin × Fsw) / 18500 ……(4) = 0.5 × 750 Ω × (12 V – 1.8 V) × 1.8 V / (360 nH × 12 V × 500 kHz) / 18500 = 0.172 V REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 15 of 27 R2J20701NP Equation (3) A0 = 2 × Nt / RCS × L × Vin × Fsw SQRT {Vin2 − 8 × L × Vin × Fsw × (VCS0 × Nt / RCS) } ……(3) = 2 × 18500 / 750 Ω × 360 nH × 12 V × 500 kHz SQRT {12 V2 − 8 × 360 nH × 12 V × 500 kHz × (0.172 V × 18500 / 750 Ω) } 106.56 SQRT {70.687} = = 12.674 The frequency of the pole established by the power stage and modulator is F0 = Nt / (2 π × Co × RCS × A0) ……(5) Thus, F0 = 18500 / (2 π × 600 µF × 750 Ω × 12.674) = 516 Hz Therefore, the frequency of the zero established by Cf and Rf is Fzero = 10 × F0 = 5.16 kHz Cf = (2 π × Fzero × Rf)–1 = (2 π × 5.16 kHz × 62 kΩ)–1 = 497 pF Therefore, we select the value 510 pF for Cf. Basically, the transient response is faster when Cf is smaller, but too small a value will make the system-loop unstable. Gain (dB) −20 dB/dec Open loop converter −40 dB/dec W/ error amp. compensation BW/Af A0 Af −20 dB/dec Error amp. unity gain frequency BW F0 Power stage and modulator Fzero Asw Fsw Freq. (Hz) Figure 4 REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 16 of 27 R2J20701NP Study of Vout Accuracy The nominal output voltage is calculated as Vout = VFB × (R1 + R2) / R2 ……(6) Here, the typical feedback voltage is 0.6 V. R REG5 Vout TRK-SS SW FB R1 C CT R2 The accuracy of Vout is strongly dependent on the variation of VFB, R1 and R2. VFB has a variation of 1% and resistance intrinsically has a certain variation. When we take the variation in resistance into account, equation (6) is extended to produce equation (7). Vout = R1 × K1 + R2 × K2 R2 × K2 R1 × K1 / K2 + R2 R2 × VFB × VFB ……(7) = Here, K1 and K2 are coefficients. Both are 1.00 in the ideal case. By equation (6), R1 is chosen as R1 = Vout (typical) VFB (typical) −1 × R2 ……(8) Substituting this expression for R1 into equation (7) yields the following. Vout = VFB × Vout (typical) VFB (typical) −1 × K1 K2 ……(9) +1 Therefore, variation in Vout is expressed as Vout Vout (typical) VFB Vout (typical) Vout (typical) VFB (typical) K1 K2 = × −1 × +1 −1 × 100 (%) …… (10) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 17 of 27 R2J20701NP The accuracy of Vout can be estimated by using equation (10). For example, if Vout (typical) = 1.8 V, resistance variation is 1% (i.e. K1, K2 = 1.01 and 0.99), and VFB = 594 mV to 606 mV: Vout Vout (typical) VFB Vout (typical) × Vout (typical) VFB (typical) −1 × K1 K2 −1 × 100 (%) …… (10) = +1 = 606 mV 1.8 V × 1.8 V 600 mV −1 × 1.01 0.99 +1 −1 × 100 (%) = 2.36% or = 594 mV 1.8 V × 1.8 V 600 mV −1 × 0.99 1.01 +1 −1 × 100 (%) = −2.31% Therefore, the output accuracy will be ±2.3% under the above conditions. Figure 5 shows the relationship between the accuracy of the resistance and the accuracy of the output voltage. The resistor value must have an accuracy of 0.5% if the variation in output voltage from the system is to be kept within two percent across the voltage range from 0.6 to 3.3 V. 3 2 Vout accuracy (%) 1 0 −1 −2 −3 0.5 1.0 1.5 R = ±0.5% R = ±1% 2.0 Vout (typical) 2.5 3.0 3.5 Figure 5 Vout Accuracy vs. Vout Set Voltage REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 18 of 27 R2J20701NP Current Sharing Simply tie the Ishare pins together SYNC Device 1 Ishare CT REG5 VOUT SYNC Device 2 Ishare CT REG5 Device N (up to 5) SYNC Ishare CT REG5 External Synchronization Simply tie the CT pin to GND External clock 5V 0V SYNC Ishare CT REG5 VOUT External clock; Frequency range: 200 kHz to 1 MHz Minimum pulse width: 100 ns Maximum pulse duty cycle: 90% REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 19 of 27 R2J20701NP Current Sharing and Synchronization Tie the Ishare and SYNC pins together Device 1 (Master) SYNC Ishare CT REG5 VOUT SYNC Device 2 Ishare CT REG5 Device N (up to 5) SYNC Ishare CT REG5 Two-Phase Operation Tie the Ishare and SYNC pins together. IL1 VOUT CT REG5 IL2 SYNC Ishare CT REG5 Device 1 (Master) SYNC Ishare Device 2 (Slave) 2.4 kΩ IL1 IL2 REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 20 of 27 R2J20701NP Timing Chart Peak Current Control Max. Duty (Internal signal) RES (Internal signal) 50 ns (typ.) TLD 50 ns (typ.) EO (EO-Vbe) / 2 (Internal signal) RAMP 0V VIN SW 0V The high-side MOS FET is turned off by the max. duty signal. To obtain stable operation, settings should be such that the level on the switching node is high for at least 80 ns. Note: Propagation delay is ignored. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 21 of 27 R2J20701NP Oscillator and Pulse Generator 1. Standalone operation or operation as the master chip in a parallel configuration with other chips. 3V CT 2V 5V SYNC 0V Max. Duty (Internal signal) 50 ns (typ.) RES (Internal signal) Note: Propagation delay is ignored. Frequency of oscillation for CT: Fct = 160 µA 2 × (CT(F) + 18 pF) × 1 V (Hz) Switching frequency Fsw = 0.5 × Fct (Hz) Frequency setting range (for Fsw): 200 kHz to 1 MHz (i.e. 400 kHz to 2 MHz for Fct) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 22 of 27 R2J20701NP 2. Operation as a slave chip (simple synchronous operation) 0.8 V CT 0V 5V SYNC (Input) 0V Should be pulled down to or below 0.8 V. Max. Duty (Internal signal) 50 ns (typ.) RES (Internal signal) SYNC frequency range: 200 kHz to 1 MHz Note: Propagation delay is ignored. 3. Operation as a slave chip in a parallel configuration (two-phase operation) 5V CT 4.4 V 5V SYNC (Input) 0V Should be pulled up to at least 4.4 V. Max. Duty (Internal signal) 50 ns (typ.) RES (Internal signal) SYNC frequency range: 200 kHz to 1 MHz Note: Propagation delay is ignored. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 23 of 27 R2J20701NP Hiccup Operation when the Over-Current Limit (OCL) is Reached TRK-SS Detected OCL 1.5 V CS 1024 pulses skipped 0V 1024 pulses skipped Normal operation Note: Propagation delay is ignored. REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 24 of 27 R2J20701NP Main Characteristics VH vs. Temperature 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 VL vs. Temperature VH (V) VL (V) 7.3 7.2 7.1 7.0 6.9 6.8 6.7 –50 –25 0 25 50 75 100 125 150 6.9 6.8 6.7 6.6 6.5 6.4 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) Vreg vs. Temperature 5.10 610 608 606 5.05 604 Vfb vs. Temperature Vfb (mV) 0 25 50 75 100 125 150 Vreg (V) 602 600 598 596 5.00 4.95 594 592 4.90 –50 –25 590 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 25 of 27 R2J20701NP Fsync vs. Temperature 500 CT = 68 pF Von vs. Temperature 2.70 2.65 2.60 490 480 Fsync (kHz) 470 460 450 440 430 –50 –25 Von (V) 0 25 50 75 100 125 150 2.55 2.50 2.45 2.40 2.35 2.30 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) Voff vs. Temperature 1.45 1.40 1.35 1000 2000 Fsync vs. CT Voff (V) 1.30 1.25 1.20 1.15 1.10 1.05 –50 –25 0 25 50 75 100 125 150 Fsync (kHz) 100 10 100 CT (pF) 500 Temperature (°C) REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 26 of 27 R2J20701NP Package Dimensions JEITA Package Code — RENESAS Code PWQN0056KB-A Previous Code — MASS[Typ.] 0.17g D 42 43 29 28 A B 1.00 29 28 3.40 0.55 2.05 1.00 42 43 1.00 1.00 2.00 0.65 3.35 E C0.4 2× t C 56× Lp 56 1 C t 15 14 15 14 e 56× b 1 56 ×M C A B 3.25 3.60 Reference Dimension in Millimeters Symbol y1 C y C A1 c A C 42 3.60 3.25 43 29 28 0.45 0.80 3.25 56 3.60 1 e 14 15 0.30 Standard Foot Print D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 Min Nom Max 7.90 8.00 8.10 7.90 8.00 8.10 2× 3.60 3.25 0.85 0.50 0.80 0 0.05 0.18 0.23 0.28 0.50 0.30 0.40 0.50 0.10 0.08 0.10 0.15 0.70 0.20 REJ03G1459-0400 Rev.4.00 Jun 30, 2008 Page 27 of 27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. 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