User's Manual
16
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
H8S/2456, H8S/2456R, H8S/2454 Group
User’s Manual: Hardware
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2456
H8S/2456R
H8S/2454
R4F2456
R4S2456
R4F2456R
R4S2456R
R4F2454
R4S2454
All information contained in these materials, including products and product
specifications, represents information on the product at the time of publication and is
subject to change by Renesas Electronics Corp. without notice. Please review the
latest information published by Renesas Electronics Corp. through various means,
including the Renesas Electronics Corp. website (http://www.renesas.com).
www.renesas.com
Rev.5.00 Sep 2012
Page ii of xxx
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No
license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The
recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property
damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas
Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any
application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred
by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas
Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas
Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation
of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by
you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility
of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.
Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws
and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose
manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use
Renesas Electronics products or technology described in this document for any purpose relating to military applications or use
by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas
Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this
document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of
unauthorized use of Renesas Electronics products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document
or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
(Note 2)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
(2012.4)
Page iii of xxx
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may
occur due to the false recognition of the pin state as an input signal. Unused pins should
be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Page iv of xxx
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions
and electrical characteristics of the MCU. It is intended for users designing application systems
incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is
necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control
functions, peripheral functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These
notes occur within the body of the text, at the end of each section, and in the Usage Notes
section.
The revision history summarizes the locations of revisions and additions. It does not list all
revisions. Refer to the text of the manual for details.
The following documents apply to the H8S/2456, H8S/2456R, H8S/2454 Group. Make sure to
refer to the latest versions of these documents. The newest versions of the documents listed
may be obtained from the Renesas Electronics Web site.
Document Type
Contents
Document Title
Document No.
Data Sheet
Hardware overview and
electrical characteristics
⎯
⎯
User’s manual for
Hardware
Hardware specifications (pin
assignments, memory maps,
peripheral function
specifications, electrical
characteristics, timing charts)
and operation description
H8S/2456, H8S/2456R, This User’s
H8S/2454 Group User’s manual
manual for Hardware
User’s manual for
Software
Note: Refer to the application
notes for details on using
peripheral functions.
H8S/2600 Series
Application Note
Description of CPU instruction
set
Available from Renesas Electronics
Web site.
REJ09B0139
H8S/2000 Series
Software Manual
Renesas Technical Information on using peripheral
Update
functions and application
examples
Page v of xxx
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
(2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Page vi of xxx
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
(1)
[Table of Bits]
Bit
(2)
(3)
(4)
(5)
Bit Name
−
−
Initial Value R/W
Description
0
0
R
R
Reserved
These bits are always read as 0.
13 to 11
ASID2 to
ASID0
All 0
R/W
Address Identifier
These bits enable or disable the pin function.
10
−
0
R
Reserved
This bit is always read as 0.
9
−
1
R
Reserved
This bit is always read as 1.
−
0
15
14
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W: The bit or field is readable and writable.
R/(W): The bit or field is readable and writable.
However, writing is only performed to flag clearing.
The bit or field is readable.
R:
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
The bit or field is writable.
W:
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Page vii of xxx
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations specific to this product
Abbreviation
Description
BSC
Bus controller
CPG
INT
SCI
TMR
TPU
WDT
Clock pulse generator
Interrupt controller
Serial communication interface
8-bit timer
16-bit timer pulse unit
Watchdog timer
• Abbreviations other than those listed above
Abbreviation
Description
ACIA
Asynchronous communications interface adapter
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
UART
VCO
Bits per second
Cyclic redundancy check
Direct memory access
Direct memory access controller
Global System for Mobile Communications
High impedance
⎯
Input/output
Infrared Data Association
Least significant bit
Most significant bit
No connection
Phase-locked loop
Pulse width modulation
Special function register
Subscriber Identity Module
Universal asynchronous receiver/transmitter
Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Page viii of xxx
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Features.................................................................................................................................. 1
1.1.1 Applications.............................................................................................................. 1
1.1.2 Overview of Specifications....................................................................................... 1
List of Products...................................................................................................................... 9
Block Diagrams ................................................................................................................... 13
Pin Description .................................................................................................................... 15
1.4.1 Pin Assignments ..................................................................................................... 15
1.4.2 Pin Assignments in Each Operating Mode ............................................................. 18
1.4.3 Pin Functions .......................................................................................................... 33
Section 2 CPU......................................................................................................45
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features................................................................................................................................ 45
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 46
2.1.2 Differences from H8/300 CPU ............................................................................... 47
2.1.3 Differences from H8/300H CPU ............................................................................ 48
CPU Operating Modes......................................................................................................... 49
2.2.1 Normal Mode.......................................................................................................... 49
2.2.2 Advanced Mode...................................................................................................... 51
Address Space...................................................................................................................... 53
Registers .............................................................................................................................. 54
2.4.1 General Registers.................................................................................................... 55
2.4.2 Program Counter (PC) ............................................................................................ 56
2.4.3 Extended Register (EXR) ....................................................................................... 56
2.4.4 Condition-Code Register (CCR)............................................................................. 57
2.4.5 Multiply-Accumulate Register (MAC)................................................................... 58
2.4.6 Initial Values of CPU Internal Registers................................................................. 58
Data Formats........................................................................................................................ 59
2.5.1 General Register Data Formats............................................................................... 59
2.5.2 Memory Data Formats ............................................................................................ 61
Instruction Set ...................................................................................................................... 62
2.6.1 Table of Instructions Classified by Function .......................................................... 63
2.6.2 Basic Instruction Formats ....................................................................................... 72
Addressing Modes and Effective Address Calculation........................................................ 74
2.7.1 Register Direct—Rn ............................................................................................... 74
2.7.2 Register Indirect—@ERn....................................................................................... 74
Page ix of xxx
2.8
2.9
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 75
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 75
2.7.5 Absolute Address—@aa:8/@aa:16/@aa:24/@aa:32.............................................. 75
2.7.6 Immediate—#xx:8/#xx:16/#xx:32.......................................................................... 76
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 76
2.7.8 Memory Indirect—@@aa:8 ................................................................................... 77
2.7.9 Effective Address Calculation ................................................................................ 78
Processing States.................................................................................................................. 80
Usage Note........................................................................................................................... 82
2.9.1 Usage Notes on Bit-wise Operation Instructions .................................................... 82
Section 3 MCU Operating Modes .......................................................................83
3.1
3.2
3.3
3.4
Operating Mode Selection ................................................................................................... 83
Register Descriptions ........................................................................................................... 84
3.2.1 Mode Control Register (MDCR) ............................................................................ 84
3.2.2 System Control Register (SYSCR)......................................................................... 85
Operating Mode Descriptions .............................................................................................. 87
3.3.1 Mode 1.................................................................................................................... 87
3.3.2 Mode 2.................................................................................................................... 87
3.3.3 Mode 3.................................................................................................................... 87
3.3.4 Mode 4.................................................................................................................... 88
3.3.5 Mode 7.................................................................................................................... 88
3.3.6 Pin Functions .......................................................................................................... 89
Memory Map in Each Operating Mode ............................................................................... 90
Section 4 Exception Handling ............................................................................. 97
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Exception Handling Types and Priority............................................................................... 97
Exception Sources and Exception Vector Table .................................................................. 98
Reset .................................................................................................................................. 100
4.3.1 Reset Exception Handling .................................................................................... 100
4.3.2 Interrupts after Reset............................................................................................. 102
4.3.3 On-Chip Peripheral Functions after Reset Release............................................... 102
Trace Exception Handling ................................................................................................. 103
Interrupt Exception Handling ............................................................................................ 104
Trap Instruction Exception Handling................................................................................. 105
Illegal Instruction Exception Handling .............................................................................. 106
Stack Status after Exception Handling............................................................................... 107
Usage Note......................................................................................................................... 108
Page x of xxx
Section 5 Interrupt Controller ............................................................................109
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Features.............................................................................................................................. 109
Input/Output Pins............................................................................................................... 111
Register Descriptions ......................................................................................................... 112
5.3.1 Interrupt Control Register (INTCR) ..................................................................... 113
5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN)............................................. 114
5.3.3 IRQ Enable Register (IER) ................................................................................... 116
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 118
5.3.5 IRQ Status Register (ISR)..................................................................................... 124
5.3.6 IRQ Pin Select Register (ITSR)............................................................................ 125
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 128
Interrupt Sources................................................................................................................ 129
5.4.1 External Interrupts ................................................................................................ 129
5.4.2 Internal Interrupts ................................................................................................. 130
Interrupt Exception Handling Vector Table....................................................................... 131
Interrupt Control Modes and Interrupt Operation .............................................................. 138
5.6.1 Interrupt Control Mode 0...................................................................................... 139
5.6.2 Interrupt Control Mode 2...................................................................................... 141
5.6.3 Interrupt Exception Handling Sequence ............................................................... 143
5.6.4 Interrupt Response Times ..................................................................................... 145
5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 146
Usage Notes ....................................................................................................................... 147
5.7.1 Conflict between Interrupt Generation and Disabling .......................................... 147
5.7.2 Instructions that Disable Interrupts....................................................................... 148
5.7.3 Times when Interrupts are Disabled ..................................................................... 148
5.7.4 Interrupts during Execution of EEPMOV Instruction .......................................... 148
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................. 148
5.7.6 IRQ Status Register (ISR)..................................................................................... 149
Section 6 Bus Controller (BSC).........................................................................151
6.1
6.2
6.3
Features.............................................................................................................................. 151
Input/Output Pins............................................................................................................... 154
Register Descriptions ......................................................................................................... 157
6.3.1 Bus Width Control Register (ABWCR)................................................................ 158
6.3.2 Access State Control Register (ASTCR) .............................................................. 158
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ........................................... 159
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................. 165
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 167
Page xi of xxx
6.3.6
6.4
6.5
6.6
6.7
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 169
6.3.7 Bus Control Register (BCR) ................................................................................. 170
6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 172
6.3.9 DRAM Control Register (DRAMCR) .................................................................. 173
6.3.10 DRAM Access Control Register (DRACCR)....................................................... 181
6.3.11 Refresh Control Register (REFCR) ...................................................................... 184
6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 187
6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 187
Bus Control........................................................................................................................ 188
6.4.1 Area Division........................................................................................................ 188
6.4.2 Bus Specifications ................................................................................................ 189
6.4.3 Memory Interfaces................................................................................................ 191
6.4.4 Chip Select Signals ............................................................................................... 193
Basic Bus Interface ............................................................................................................ 194
6.5.1 Data Size and Data Alignment.............................................................................. 194
6.5.2 Valid Strobes ........................................................................................................ 196
6.5.3 Basic Timing......................................................................................................... 197
6.5.4 Wait Control ......................................................................................................... 205
6.5.5 Read Strobe (RD) Timing..................................................................................... 206
6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 208
Address/Data Multiplexed I/O Interface............................................................................ 209
6.6.1 Setting Address/Data Multiplexed I/O Space ....................................................... 209
6.6.2 Address/Data Multiplexing................................................................................... 209
6.6.3 Data Bus ............................................................................................................... 210
6.6.4 Address Hold Signal ............................................................................................. 210
6.6.5 Basic Timing......................................................................................................... 210
6.6.6 Wait Control ......................................................................................................... 219
6.6.7 Read Strobe (RD) Timing..................................................................................... 220
6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 221
DRAM Interface ................................................................................................................ 223
6.7.1 Setting DRAM Space............................................................................................ 223
6.7.2 Address Multiplexing ........................................................................................... 224
6.7.3 Data Bus ............................................................................................................... 225
6.7.4 Pins Used for DRAM Interface............................................................................. 226
6.7.5 Basic Timing......................................................................................................... 227
6.7.6 Column Address Output Cycle Control ................................................................ 229
6.7.7 Row Address Output State Control....................................................................... 230
6.7.8 Precharge State Control ........................................................................................ 232
6.7.9 Wait Control ......................................................................................................... 233
Page xii of xxx
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.7.10 Byte Access Control ............................................................................................. 236
6.7.11 Burst Operation..................................................................................................... 238
6.7.12 Refresh Control..................................................................................................... 244
6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 252
Synchronous DRAM Interface........................................................................................... 255
6.8.1 Setting Continuous Synchronous DRAM Space................................................... 255
6.8.2 Address Multiplexing ........................................................................................... 256
6.8.3 Data Bus ............................................................................................................... 257
6.8.4 Pins Used for Synchronous DRAM Interface....................................................... 257
6.8.5 Synchronous DRAM Clock .................................................................................. 259
6.8.6 Basic Timing......................................................................................................... 259
6.8.7 CAS Latency Control............................................................................................ 261
6.8.8 Row Address Output State Control....................................................................... 263
6.8.9 Precharge State Count........................................................................................... 264
6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 266
6.8.11 Byte Access Control ............................................................................................. 267
6.8.12 Burst Operation..................................................................................................... 270
6.8.13 Refresh Control..................................................................................................... 274
6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 281
6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous
DRAM Interface ................................................................................................... 282
Burst ROM Interface.......................................................................................................... 287
6.9.1 Basic Timing......................................................................................................... 287
6.9.2 Wait Control ......................................................................................................... 289
6.9.3 Write Access......................................................................................................... 289
Idle Cycle........................................................................................................................... 290
6.10.1 Operation .............................................................................................................. 290
6.10.2 Pin States in Idle Cycle......................................................................................... 309
Write Data Buffer Function ............................................................................................... 310
Bus Release........................................................................................................................ 311
6.12.1 Operation .............................................................................................................. 311
6.12.2 Pin States in External Bus Released State ............................................................ 312
6.12.3 Transition Timing ................................................................................................. 313
Bus Arbitration .................................................................................................................. 315
6.13.1 Operation .............................................................................................................. 315
6.13.2 Bus Transfer Timing............................................................................................. 316
Bus Controller Operation in Reset ..................................................................................... 318
Usage Notes ....................................................................................................................... 318
6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 318
6.15.2 External Bus Release Function and Software Standby ......................................... 318
Page xiii of xxx
6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 318
6.15.4 BREQO Output Timing ........................................................................................ 319
6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 319
Section 7 DMA Controller (DMAC).................................................................321
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Features.............................................................................................................................. 321
Input/Output Pins............................................................................................................... 323
Register Descriptions ......................................................................................................... 324
7.3.1 Memory Address Registers (MARA and MARB)................................................ 326
7.3.2 I/O Address Registers (IOARA and IOARB)....................................................... 327
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 328
7.3.4 DMA Control Registers (DMACRA and DMACRB) .......................................... 329
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 337
7.3.6 DMA Write Enable Register (DMAWER)........................................................... 348
7.3.7 DMA Terminal Control Register (DMATCR) ..................................................... 350
Activation Sources............................................................................................................. 351
7.4.1 Activation by Internal Interrupt Request .............................................................. 352
7.4.2 Activation by External Request ............................................................................ 353
7.4.3 Activation by Auto-Request ................................................................................. 353
Operation ........................................................................................................................... 353
7.5.1 Transfer Modes..................................................................................................... 353
7.5.2 Sequential Mode ................................................................................................... 356
7.5.3 Idle Mode.............................................................................................................. 358
7.5.4 Repeat Mode......................................................................................................... 361
7.5.5 Single Address Mode............................................................................................ 365
7.5.6 Normal Mode........................................................................................................ 368
7.5.7 Block Transfer Mode ............................................................................................ 371
7.5.8 Basic Bus Cycles .................................................................................................. 377
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles................................................ 378
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 387
7.5.11 Write Data Buffer Function .................................................................................. 394
7.5.12 Multi-Channel Operation...................................................................................... 395
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and
EXDMAC............................................................................................................. 397
7.5.14 DMAC and NMI Interrupts .................................................................................. 398
7.5.15 Forced Termination of DMAC Operation ............................................................ 399
7.5.16 Clearing Full Address Mode................................................................................. 400
Interrupt Sources................................................................................................................ 401
Usage Notes ....................................................................................................................... 402
Page xiv of xxx
Section 8 EXDMA Controller (EXDMAC) ......................................................407
8.1
8.2
8.3
8.4
8.5
8.6
Features.............................................................................................................................. 407
Input/Output Pins............................................................................................................... 409
Register Descriptions ......................................................................................................... 410
8.3.1 EXDMA Source Address Register (EDSAR)....................................................... 411
8.3.2 EXDMA Destination Address Register (EDDAR)............................................... 411
8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 412
8.3.4 EXDMA Mode Control Register (EDMDR) ........................................................ 414
8.3.5 EXDMA Address Control Register (EDACR) ..................................................... 419
Operation ........................................................................................................................... 423
8.4.1 Transfer Modes..................................................................................................... 423
8.4.2 Address Modes ..................................................................................................... 424
8.4.3 EXDMA Transfer Requests.................................................................................. 428
8.4.4 Bus Modes ............................................................................................................ 429
8.4.5 Transfer Modes..................................................................................................... 431
8.4.6 Repeat Area Function ........................................................................................... 434
8.4.7 Registers during EXDMA Transfer Operation ..................................................... 437
8.4.8 Channel Priority Order.......................................................................................... 441
8.4.9 EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 445
8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 452
8.4.11 Examples of Operation Timing in Each Mode ..................................................... 457
8.4.12 Ending EXDMA Transfer..................................................................................... 471
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 472
Interrupt Sources................................................................................................................ 473
Usage Notes ....................................................................................................................... 475
Section 9 Data Transfer Controller (DTC) ........................................................477
9.1
9.2
9.3
9.4
Features.............................................................................................................................. 477
Register Descriptions ......................................................................................................... 479
9.2.1 DTC Mode Register A (MRA) ............................................................................. 479
9.2.2 DTC Mode Register B (MRB).............................................................................. 481
9.2.3 DTC Source Address Register (SAR)................................................................... 482
9.2.4 DTC Destination Address Register (DAR)........................................................... 482
9.2.5 DTC Transfer Count Register A (CRA) ............................................................... 482
9.2.6 DTC Transfer Count Register B (CRB)................................................................ 482
9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 483
9.2.8 DTC Vector Register (DTVECR)......................................................................... 483
9.2.9 DTC Control Register (DTCCR) .......................................................................... 484
Activation Sources............................................................................................................. 485
Location of Register Information and DTC Vector Table ................................................. 487
Page xv of xxx
9.5
9.6
9.7
9.8
Operation ........................................................................................................................... 491
9.5.1 Normal Mode........................................................................................................ 494
9.5.2 Repeat Mode......................................................................................................... 495
9.5.3 Block Transfer Mode ............................................................................................ 496
9.5.4 Chain Transfer ...................................................................................................... 497
9.5.5 Interrupt Sources................................................................................................... 498
9.5.6 Operation Timing.................................................................................................. 498
9.5.7 Number of DTC Execution States ........................................................................ 499
Procedures for Using DTC................................................................................................. 501
9.6.1 Activation by Interrupt.......................................................................................... 501
9.6.2 Activation by Software ......................................................................................... 501
Examples of Use of the DTC ............................................................................................. 502
9.7.1 Normal Mode........................................................................................................ 502
9.7.2 Chain Transfer ...................................................................................................... 503
9.7.3 Chain Transfer when Counter = 0......................................................................... 504
9.7.4 Software Activation .............................................................................................. 506
Usage Notes ....................................................................................................................... 507
9.8.1 Module Stop Function Setting .............................................................................. 507
9.8.2 On-Chip RAM ...................................................................................................... 507
9.8.3 DTCE Bit Setting.................................................................................................. 507
9.8.4 DMAC Transfer End Interrupt.............................................................................. 507
9.8.5 Chain Transfer ...................................................................................................... 507
Section 10 I/O Ports........................................................................................... 509
10.1 Port 1.................................................................................................................................. 523
10.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 523
10.1.2 Port 1 Data Register (P1DR)................................................................................. 524
10.1.3 Port 1 Register (PORT1)....................................................................................... 524
10.1.4 Port 1 Open Drain Control Register (P1ODR) ..................................................... 525
10.1.5 Pin Functions ........................................................................................................ 526
10.2 Port 2.................................................................................................................................. 549
10.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 549
10.2.2 Port 2 Data Register (P2DR)................................................................................. 550
10.2.3 Port 2 Register (PORT2)....................................................................................... 550
10.2.4 Port 2 Open Drain Control Register (P2ODR) ..................................................... 551
10.2.5 Pin Functions ........................................................................................................ 552
10.3 Port 3.................................................................................................................................. 563
10.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 563
10.3.2 Port 3 Data Register (P3DR)................................................................................. 564
10.3.3 Port 3 Register (PORT3)....................................................................................... 564
Page xvi of xxx
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.3.4 Port 3 Open Drain Control Register (P3ODR) ..................................................... 565
10.3.5 Pin Functions ........................................................................................................ 566
Port 4.................................................................................................................................. 570
10.4.1 Port 4 Register (PORT4)....................................................................................... 570
10.4.2 Pin Functions ........................................................................................................ 570
Port 5.................................................................................................................................. 572
10.5.1 Port 5 Data Direction Register (P5DDR).............................................................. 572
10.5.2 Port 5 Data Register (P5DR)................................................................................. 572
10.5.3 Port 5 Register (PORT5)....................................................................................... 573
10.5.4 Port 5 Open Drain Control Register (P5ODR) ..................................................... 573
10.5.5 Pin Functions ........................................................................................................ 574
Port 6.................................................................................................................................. 582
10.6.1 Port 6 Data Direction Register (P6DDR).............................................................. 582
10.6.2 Port 6 Data Register (P6DR)................................................................................. 583
10.6.3 Port 6 Register (PORT6)....................................................................................... 583
10.6.4 Port 6 Open Drain Control Register (P6ODR) ..................................................... 584
10.6.5 Pin Functions ........................................................................................................ 584
Port 8.................................................................................................................................. 588
10.7.1 Port 8 Data Direction Register (P8DDR).............................................................. 588
10.7.2 Port 8 Data Register (P8DR)................................................................................. 589
10.7.3 Port 8 Register (PORT8)....................................................................................... 589
10.7.4 Port 8 Open Drain Control Register (P8ODR) ..................................................... 590
10.7.5 Pin Functions ........................................................................................................ 590
Port 9.................................................................................................................................. 600
10.8.1 Port 9 Register (PORT9)....................................................................................... 600
10.8.2 Pin Functions ........................................................................................................ 601
Port A................................................................................................................................. 603
10.9.1 Port A Data Direction Register (PADDR)............................................................ 604
10.9.2 Port A Data Register (PADR)............................................................................... 606
10.9.3 Port A Register (PORTA)..................................................................................... 606
10.9.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................. 607
10.9.5 Port A Open Drain Control Register (PAODR).................................................... 607
10.9.6 Pin Functions ........................................................................................................ 608
10.9.7 Port A Input Pull-Up MOS States......................................................................... 617
Port B ................................................................................................................................. 618
10.10.1 Port B Data Direction Register (PBDDR) ............................................................ 618
10.10.2 Port B Data Register (PBDR) ............................................................................... 619
10.10.3 Port B Register (PORTB) ..................................................................................... 619
10.10.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 620
10.10.5 Port B Open Drain Control Register (PBODR) .................................................... 620
Page xvii of xxx
10.11
10.12
10.13
10.14
10.15
10.16
10.10.6 Pin Functions ........................................................................................................ 621
10.10.7 Port B Input Pull-Up MOS States......................................................................... 629
Port C ................................................................................................................................. 630
10.11.1 Port C Data Direction Register (PCDDR) ............................................................ 630
10.11.2 Port C Data Register (PCDR) ............................................................................... 631
10.11.3 Port C Register (PORTC) ..................................................................................... 631
10.11.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................. 632
10.11.5 Port C Open Drain Control Register (PCODR) .................................................... 632
10.11.6 Pin Functions ........................................................................................................ 633
10.11.7 Port C Input Pull-Up MOS States......................................................................... 641
Port D................................................................................................................................. 642
10.12.1 Port D Data Direction Register (PDDDR)............................................................ 642
10.12.2 Port D Data Register (PDDR)............................................................................... 643
10.12.3 Port D Register (PORTD)..................................................................................... 643
10.12.4 Port D Pull-Up MOS Control Register (PDPCR) ................................................. 644
10.12.5 Port D Open Drain Control Register (PDODR).................................................... 644
10.12.6 Pin Functions ........................................................................................................ 645
10.12.7 Port D Input Pull-Up MOS States......................................................................... 646
Port E ................................................................................................................................. 647
10.13.1 Port E Data Direction Register (PEDDR)............................................................. 647
10.13.2 Port E Data Register (PEDR)................................................................................ 648
10.13.3 Port E Register (PORTE)...................................................................................... 648
10.13.4 Port E Pull-Up MOS Control Register (PEPCR).................................................. 649
10.13.5 Port E Open Drain Control Register (PEODR) .................................................... 649
10.13.6 Pin Functions ........................................................................................................ 650
10.13.7 Port E Input Pull-Up MOS States ......................................................................... 651
Port F ................................................................................................................................. 652
10.14.1 Port F Data Direction Register (PFDDR) ............................................................. 653
10.14.2 Port F Data Register (PFDR) ................................................................................ 655
10.14.3 Port F Register (PORTF) ...................................................................................... 655
10.14.4 Port F Open Drain Control Register (PFODR) ..................................................... 656
10.14.5 Pin Functions ........................................................................................................ 656
Port G................................................................................................................................. 668
10.15.1 Port G Data Direction Register (PGDDR)............................................................ 669
10.15.2 Port G Data Register (PGDR)............................................................................... 670
10.15.3 Port G Register (PORTG)..................................................................................... 670
10.15.4 Port G Open Drain Control Register (PGODR).................................................... 671
10.15.5 Pin Functions ........................................................................................................ 671
Port H................................................................................................................................. 675
10.16.1 Port H Data Direction Register (PHDDR)............................................................ 675
Page xviii of xxx
10.16.2 Port H Data Register (PHDR)............................................................................... 677
10.16.3 Port H Register (PORTH)..................................................................................... 677
10.16.4 Port H Open Drain Control Register (PHODR).................................................... 678
10.16.5 Pin Functions ........................................................................................................ 679
10.17 Port J .................................................................................................................................. 682
10.17.1 Port J Data Direction Register (PJDDR)............................................................... 682
10.17.2 Port J Data Register (PJDR) ................................................................................. 682
10.17.3 Port J Register (PORTJ) ....................................................................................... 683
10.17.4 Port J Open Drain Control Register (PJODR) ...................................................... 683
10.17.5 Pin Functions ........................................................................................................ 684
10.18 Port Function Control Registers......................................................................................... 685
10.18.1 Port Function Control Register 0 (PFCR0)........................................................... 685
10.18.2 Port Function Control Register 1 (PFCR1)........................................................... 686
10.18.3 Port Function Control Register 2 (PFCR2)........................................................... 687
10.18.4 Port Function Control Register 3 (PFCR3)........................................................... 688
10.18.5 Port Function Control Register 4 (PFCR4)........................................................... 690
10.18.6 Port Function Control Register 5 (PFCR5)........................................................... 692
Section 11 16-Bit Timer Pulse Unit (TPU) .......................................................693
11.1 Features.............................................................................................................................. 693
11.2 Input/Output Pins............................................................................................................... 700
11.3 Register Descriptions ......................................................................................................... 703
11.3.1 Timer Control Register (TCR).............................................................................. 708
11.3.2 Timer Mode Register (TMDR)............................................................................. 713
11.3.3 Timer I/O Control Register (TIOR)...................................................................... 715
11.3.4 Timer Interrupt Enable Register (TIER)............................................................... 732
11.3.5 Timer Status Register (TSR)................................................................................. 734
11.3.6 Timer Counter (TCNT)......................................................................................... 737
11.3.7 Timer General Register (TGR) ............................................................................. 737
11.3.8 Timer Start Register (TSTR) ................................................................................ 737
11.3.9 Timer Synchronous Register (TSYR)................................................................... 738
11.3.10 Timer Start Register B (TSTRB) .......................................................................... 739
11.3.11 Timer Synchronous Register B (TSYRB) ............................................................ 740
11.4 Operation ........................................................................................................................... 741
11.4.1 Basic Functions..................................................................................................... 741
11.4.2 Synchronous Operation......................................................................................... 749
11.4.3 Buffer Operation................................................................................................... 752
11.4.4 Cascaded Operation .............................................................................................. 756
11.4.5 PWM Modes......................................................................................................... 758
11.4.6 Phase Counting Mode........................................................................................... 764
Page xix of xxx
11.5
11.6
11.7
11.8
11.9
Interrupt Sources................................................................................................................ 772
DTC Activation.................................................................................................................. 776
DMAC Activation.............................................................................................................. 776
A/D Converter Activation.................................................................................................. 776
Operation Timing............................................................................................................... 777
11.9.1 Input/Output Timing ............................................................................................. 777
11.9.2 Interrupt Signal Timing ........................................................................................ 782
11.10 Usage Notes ....................................................................................................................... 786
11.10.1 Module Stop Function Setting .............................................................................. 786
11.10.2 Input Clock Restrictions ....................................................................................... 786
11.10.3 Caution on Cycle Setting ...................................................................................... 787
11.10.4 Contention between TCNT Write and Clear Operations ...................................... 787
11.10.5 Contention between TCNT Write and Increment Operations............................... 788
11.10.6 Contention between TGR Write and Compare Match .......................................... 789
11.10.7 Contention between Buffer Register Write and Compare Match ......................... 790
11.10.8 Contention between TGR Read and Input Capture............................................... 791
11.10.9 Contention between TGR Write and Input Capture.............................................. 792
11.10.10
Contention between Buffer Register Write and Input Capture ..................... 793
11.10.11
Contention between Overflow/Underflow and Counter Clearing................. 794
11.10.12
Contention between TCNT Write and Overflow/Underflow........................ 795
11.10.13
Multiplexing of I/O Pins ............................................................................... 795
11.10.14
Interrupts and Module Stop State.................................................................. 795
Section 12 Programmable Pulse Generator (PPG) ............................................ 797
12.1 Features.............................................................................................................................. 797
12.2 Input/Output Pins............................................................................................................... 799
12.3 Register Descriptions ......................................................................................................... 800
12.3.1 Next Data Enable Registers H and L (NDERH, NDERL).................................... 801
12.3.2 Output Data Registers H and L (PODRH, PODRL)............................................. 802
12.3.3 Next Data Registers H and L (NDRH, NDRL)..................................................... 803
12.3.4 PPG Output Control Register (PCR) .................................................................... 806
12.3.5 PPG Output Mode Register (PMR) ...................................................................... 807
12.4 Operation ........................................................................................................................... 809
12.4.1 Output Timing ...................................................................................................... 810
12.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 811
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 812
12.4.4 Non-Overlapping Pulse Output............................................................................. 813
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 815
12.4.6 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output) .................. 816
Page xx of xxx
12.4.7 Inverted Pulse Output ........................................................................................... 818
12.4.8 Pulse Output Triggered by Input Capture ............................................................. 819
12.5 Usage Notes ....................................................................................................................... 820
12.5.1 Module Stop Function Setting .............................................................................. 820
12.5.2 Operation of Pulse Output Pins............................................................................. 820
Section 13 8-Bit Timers (TMR).........................................................................821
13.1 Features.............................................................................................................................. 821
13.2 Input/Output Pins............................................................................................................... 823
13.3 Register Descriptions ......................................................................................................... 824
13.3.1 Timer Counter (TCNT)......................................................................................... 825
13.3.2 Time Constant Register A (TCORA).................................................................... 825
13.3.3 Time Constant Register B (TCORB) .................................................................... 825
13.3.4 Timer Control Register (TCR).............................................................................. 826
13.3.5 Timer Counter Control Register (TCCR) ............................................................. 827
13.3.6 Timer Control/Status Register (TCSR)................................................................. 829
13.4 Operation ........................................................................................................................... 833
13.4.1 Pulse Output.......................................................................................................... 833
13.4.2 Reset Input ............................................................................................................ 834
13.5 Operation Timing............................................................................................................... 835
13.5.1 TCNT Incrementation Timing .............................................................................. 835
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 836
13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 836
13.5.4 Timing of Compare Match Clear.......................................................................... 837
13.5.5 Timing of TCNT External Reset........................................................................... 837
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 838
13.6 Operation with Cascaded Connection................................................................................ 839
13.6.1 16-Bit Counter Mode ............................................................................................ 839
13.6.2 Compare Match Count Mode................................................................................ 839
13.7 Interrupt Sources................................................................................................................ 840
13.7.1 Interrupt Sources and DTC Activation ................................................................. 840
13.7.2 A/D Converter Activation..................................................................................... 840
13.8 Usage Notes ....................................................................................................................... 841
13.8.1 Contention between TCNT Write and Clear......................................................... 841
13.8.2 Contention between TCNT Write and Increment ................................................. 842
13.8.3 Contention between TCOR Write and Compare Match ....................................... 843
13.8.4 Contention between Compare Matches A and B .................................................. 844
13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 844
13.8.6 Mode Setting with Cascaded Connection ............................................................. 846
13.8.7 Module Stop Function Setting .............................................................................. 846
Page xxi of xxx
13.8.8 Interrupts in Module Stop State ............................................................................ 846
Section 14 Watchdog Timer (WDT) ................................................................. 847
14.1 Features.............................................................................................................................. 847
14.2 Input/Output Pin ................................................................................................................ 848
14.3 Register Descriptions ......................................................................................................... 849
14.3.1 Timer Counter (TCNT)......................................................................................... 849
14.3.2 Timer Control/Status Register (TCSR)................................................................. 849
14.3.3 Reset Control/Status Register (RSTCSR)............................................................. 851
14.4 Operation ........................................................................................................................... 852
14.4.1 Watchdog Timer Mode......................................................................................... 852
14.4.2 Interval Timer Mode............................................................................................. 854
14.5 Interrupt Source ................................................................................................................. 854
14.6 Usage Notes ....................................................................................................................... 855
14.6.1 Notes on Register Access ..................................................................................... 855
14.6.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 857
14.6.3 Changing Value of CKS2 to CKS0 ...................................................................... 857
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 857
14.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 858
14.6.6 System Reset by WDTOVF Signal....................................................................... 858
Section 15 Serial Communication Interface (SCI, IrDA) ................................. 859
15.1 Features.............................................................................................................................. 859
15.2 Input/Output Pins............................................................................................................... 862
15.3 Register Descriptions ......................................................................................................... 863
15.3.1 Receive Shift Register (RSR) ............................................................................... 864
15.3.2 Receive Data Register (RDR)............................................................................... 864
15.3.3 Transmit Data Register (TDR).............................................................................. 865
15.3.4 Transmit Shift Register (TSR) .............................................................................. 865
15.3.5 Serial Mode Register (SMR) ................................................................................ 865
15.3.6 Serial Control Register (SCR) .............................................................................. 869
15.3.7 Serial Status Register (SSR) ................................................................................. 874
15.3.8 Smart Card Mode Register (SCMR)..................................................................... 882
15.3.9 Bit Rate Register (BRR) ....................................................................................... 883
15.3.10 IrDA Control Register (IrCR)............................................................................... 891
15.3.11 SCI_2 Serial Extension Mode Register (SEMR) .................................................. 892
15.4 Operation in Asynchronous Mode ..................................................................................... 894
15.4.1 Data Transfer Format............................................................................................ 894
15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode..................................................................................................................... 896
Page xxii of xxx
15.5
15.6
15.7
15.8
15.9
15.10
15.4.3 Clock..................................................................................................................... 897
15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 898
15.4.5 Data Transmission (Asynchronous Mode) ........................................................... 899
15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 901
Multiprocessor Communication Function.......................................................................... 905
15.5.1 Multiprocessor Serial Data Transmission ............................................................. 906
15.5.2 Multiprocessor Serial Data Reception .................................................................. 908
Operation in Clocked Synchronous Mode ......................................................................... 912
15.6.1 Clock..................................................................................................................... 912
15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 913
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 914
15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 917
15.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................. 919
Operation in Smart Card Interface Mode........................................................................... 921
15.7.1 Pin Connection Example ...................................................................................... 921
15.7.2 Data Format (Except for Block Transfer Mode)................................................... 922
15.7.3 Block Transfer Mode ............................................................................................ 923
15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 924
15.7.5 Initialization.......................................................................................................... 926
15.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 927
15.7.7 Serial Data Reception (Except for Block Transfer Mode).................................... 930
15.7.8 Clock Output Control............................................................................................ 933
IrDA Operation .................................................................................................................. 935
Interrupt Sources................................................................................................................ 938
15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 938
15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 940
Usage Notes ....................................................................................................................... 942
15.10.1 Module Stop Function Setting .............................................................................. 942
15.10.2 Break Detection and Processing ........................................................................... 942
15.10.3 Mark State and Break Sending ............................................................................. 942
15.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 942
15.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 943
15.10.6 Restrictions on Use of DMAC or DTC................................................................. 943
15.10.7 Operation in Case of Mode Transition.................................................................. 944
Section 16 USB Function Module (USB)..........................................................949
16.1 Features.............................................................................................................................. 949
16.2 Input/Output Pins............................................................................................................... 950
Page xxiii of xxx
16.3 Register Descriptions ......................................................................................................... 951
16.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 952
16.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 954
16.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 955
16.3.4 Interrupt Enable Register 0 (IER0) ....................................................................... 956
16.3.5 Interrupt Enable Register 1 (IER1) ....................................................................... 957
16.3.6 Interrupt Enable Register 2 (IER2) ....................................................................... 958
16.3.7 Interrupt Select Register 0 (ISR0)......................................................................... 959
16.3.8 Interrupt Select Register 1 (ISR1)......................................................................... 960
16.3.9 Interrupt Select Register 2 (ISR2)......................................................................... 961
16.3.10 EP0i Data Register (EPDR0i)............................................................................... 961
16.3.11 EP0o Data Register (EPDR0o) ............................................................................. 962
16.3.12 EP0s Data Register (EPDR0s) .............................................................................. 962
16.3.13 EP1 Data Register (EPDR1) ................................................................................. 963
16.3.14 EP2 Data Register (EPDR2) ................................................................................. 963
16.3.15 EP3 Data Register (EPDR3) ................................................................................. 964
16.3.16 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 964
16.3.17 EP1 Receive Data Size Register (EPSZ1) ............................................................ 964
16.3.18 Data Status Register 0 (DASTS0)......................................................................... 965
16.3.19 Data Status Register 1 (DASTS1)......................................................................... 966
16.3.20 Trigger Register 0 (TRG0) ................................................................................... 967
16.3.21 Trigger Register 1 (TRG1) ................................................................................... 968
16.3.22 FIFO Clear Register 0 (FCLR0) ........................................................................... 969
16.3.23 FIFO Clear Register 1 (FCLR1) ........................................................................... 970
16.3.24 Endpoint Stall Register 0 (EPSTL0)..................................................................... 971
16.3.25 Endpoint Stall Register 1 (EPSTL1)..................................................................... 972
16.3.26 Stall Status Register 1 (STLSR1) ......................................................................... 973
16.3.27 DMA Transfer Setting Register (DMAR) ............................................................ 974
16.3.28 Configuration Value Register (CVR) ................................................................... 977
16.3.29 Control Register (CTLR) ...................................................................................... 977
16.3.30 Endpoint Information Register (EPIR) ................................................................. 979
16.3.31 Transceiver Test Register 0 (TRNTREG0) .......................................................... 983
16.3.32 Transceiver Test Register 1 (TRNTREG1) .......................................................... 984
16.4 Interrupt Sources................................................................................................................ 986
16.5 Operation ........................................................................................................................... 988
16.5.1 Initial Settings....................................................................................................... 988
16.5.2 Cable Connection.................................................................................................. 989
16.5.3 Cable Disconnection ............................................................................................. 990
16.5.4 Suspend and Resume Operations.......................................................................... 991
16.5.5 Control Transfer.................................................................................................... 998
Page xxiv of xxx
16.6
16.7
16.8
16.9
16.10
16.5.6 EP1 Bulk-Out Transfer ....................................................................................... 1004
16.5.7 EP2 Bulk-In Transfer.......................................................................................... 1005
16.5.8 EP3 Interrupt-In Transfer.................................................................................... 1007
Processing of USB Standard Commands and Class/ Vendor Commands........................ 1008
16.6.1 Processing of Commands Transmitted by Control Transfer............................... 1008
Stall Operations................................................................................................................ 1009
16.7.1 Overview ............................................................................................................ 1009
16.7.2 Forcible Stall by Application .............................................................................. 1009
16.7.3 Automatic Stall by USB Function Module ......................................................... 1011
DMA Transfer.................................................................................................................. 1012
16.8.1 Overview ............................................................................................................ 1012
16.8.2 Setting for the On-chip DMAC........................................................................... 1012
16.8.3 DMA Transfer for Endpoints 1 and 4 ................................................................. 1013
16.8.4 DMA Transfer for Endpoints 2........................................................................... 1014
Example of USB External Circuitry ................................................................................ 1015
Usage Notes ..................................................................................................................... 1017
16.10.1 Receiving Setup Data.......................................................................................... 1017
16.10.2 Clearing the FIFO ............................................................................................... 1017
16.10.3 Overreading and Overwriting the Data Registers ............................................... 1017
16.10.4 Assigning Interrupt Sources to EP0.................................................................... 1018
16.10.5 Clearing the FIFO When DMA Transfer is Enabled .......................................... 1018
16.10.6 Notes on TR Interrupt ......................................................................................... 1018
16.10.7 Module Stop Function Setting ............................................................................ 1019
Section 17 I2C Bus Interface 2 (IIC2) ..............................................................1021
17.1 Features............................................................................................................................ 1021
17.2 Input/Output Pins............................................................................................................. 1023
17.3 Register Descriptions ....................................................................................................... 1024
17.3.1 I2C Bus Control Register A (ICCRA) ................................................................. 1026
17.3.2 I2C Bus Control Register B (ICCRB) ................................................................. 1028
17.3.3 I2C Bus Mode Register (ICMR).......................................................................... 1029
17.3.4 I2C Bus Interrupt Enable Register (ICIER)......................................................... 1031
17.3.5 I2C Bus Status Register (ICSR)........................................................................... 1033
17.3.6 Slave Address Register (SAR)............................................................................ 1035
17.3.7 I2C Bus Transmit Data Register (ICDRT) .......................................................... 1036
17.3.8 I2C Bus Receive Data Register (ICDRR)............................................................ 1036
17.3.9 I2C Bus Shift Register (ICDRS).......................................................................... 1036
17.4 Operation ......................................................................................................................... 1037
17.4.1 I2C Bus Format.................................................................................................... 1037
17.4.2 Master Transmit Operation................................................................................. 1038
Page xxv of xxx
17.4.3 Master Receive Operation .................................................................................. 1040
17.4.4 Slave Transmit Operation ................................................................................... 1043
17.4.5 Slave Receive Operation..................................................................................... 1046
17.4.6 Noise Canceler.................................................................................................... 1048
17.4.7 Example of Use................................................................................................... 1048
17.5 Interrupt Request.............................................................................................................. 1053
17.6 Bit Synchronous Circuit................................................................................................... 1054
17.7 Usage Notes ..................................................................................................................... 1055
Section 18 A/D Converter ...............................................................................1059
18.1 Features............................................................................................................................ 1059
18.2 Input/Output Pins............................................................................................................. 1062
18.3 Register Descriptions ....................................................................................................... 1064
18.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................ 1065
18.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0).......................................... 1067
18.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1).......................................... 1069
18.3.4 A/D Control Register (ADCR_0) Unit 0 ............................................................ 1072
18.3.5 A/D Control Register (ADCR_1) Unit 1 ............................................................ 1074
18.4 Operation ......................................................................................................................... 1076
18.4.1 Single Mode........................................................................................................ 1076
18.4.2 Scan Mode .......................................................................................................... 1078
18.4.3 Input Sampling and A/D Conversion Time ........................................................ 1082
18.4.4 External Trigger Input Timing............................................................................ 1084
18.5 Interrupt Source ............................................................................................................... 1085
18.6 A/D Conversion Accuracy Definitions ............................................................................ 1086
18.7 Usage Notes ..................................................................................................................... 1088
18.7.1 Module Stop Function Setting ............................................................................ 1088
18.7.2 A/D Input Hold Function in Software Standby Mode ........................................ 1088
18.7.3 Restarting the A/D Converter ............................................................................. 1088
18.7.4 Permissible Signal Source Impedance ................................................................ 1089
18.7.5 Influences on Absolute Accuracy ....................................................................... 1089
18.7.6 Setting Range of Analog Power Supply and Other Pins..................................... 1090
18.7.7 Notes on Board Design ....................................................................................... 1090
18.7.8 Notes on Noise Countermeasures ....................................................................... 1091
18.7.9 Concurrent Operation of Two A/D Converters................................................... 1092
18.7.10 Notes on Start of A/D Conversion by Conversion Start Trigger from TPU
(Units 0 and 1) .................................................................................................... 1093
Section 19 D/A Converter ...............................................................................1095
19.1 Features............................................................................................................................ 1095
Page xxvi of xxx
19.2 Input/Output Pins............................................................................................................. 1097
19.3 Register Descriptions ....................................................................................................... 1097
19.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)........................................... 1097
19.3.2 D/A Control Register 23 (DACR23) .................................................................. 1098
19.4 Operation ......................................................................................................................... 1100
19.5 Usage Notes ..................................................................................................................... 1102
19.5.1 Module Stop Function Setting ............................................................................ 1102
19.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1102
Section 20 Synchronous Serial Communication Unit (SSU) ..........................1103
20.1 Features............................................................................................................................ 1103
20.2 Input/Output Pins............................................................................................................. 1105
20.3 Register Descriptions ....................................................................................................... 1106
20.3.1 SS Control Register H (SSCRH) ........................................................................ 1107
20.3.2 SS Control Register L (SSCRL) ......................................................................... 1109
20.3.3 SS Mode Register (SSMR) ................................................................................. 1110
20.3.4 SS Enable Register (SSER) ................................................................................ 1111
20.3.5 SS Status Register (SSSR).................................................................................. 1112
20.3.6 SS Control Register 2 (SSCR2) .......................................................................... 1114
20.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................. 1116
20.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................. 1117
20.3.9 SS Shift Register (SSTRSR)............................................................................... 1117
20.4 Operation ......................................................................................................................... 1118
20.4.1 Transfer Clock .................................................................................................... 1118
20.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1118
20.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1119
20.4.4 Communication Modes and Pin Functions ......................................................... 1120
20.4.5 SSU Mode........................................................................................................... 1122
20.4.6 SCS Pin Control and Conflict Error.................................................................... 1133
20.4.7 Clock Synchronous Communication Mode ........................................................ 1134
20.5 Interrupt Requests ............................................................................................................ 1141
20.6 Usage Note....................................................................................................................... 1142
20.6.1 Module Stop Function Setting ............................................................................ 1142
Section 21 RAM ..............................................................................................1143
Section 22 Flash Memory ................................................................................1145
22.1 Memory Map ................................................................................................................... 1147
22.2 Register Descriptions ....................................................................................................... 1148
22.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 1149
Page xxvii of xxx
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10
22.11
22.12
22.2.2 Flash Memory Data Block Protect Register (FLMDBPR) ................................. 1150
22.2.3 Flash Memory Status Register (FLMSTR)......................................................... 1151
On-Board Programming Mode ........................................................................................ 1152
22.3.1 User Programming Mode.................................................................................... 1153
22.3.2 EW0 Mode.......................................................................................................... 1154
Software Commands........................................................................................................ 1155
22.4.1 Read Array.......................................................................................................... 1156
22.4.2 Read Status Register ........................................................................................... 1156
22.4.3 Clear Status Register........................................................................................... 1156
22.4.4 Program .............................................................................................................. 1156
22.4.5 Block Erase......................................................................................................... 1158
22.4.6 Block Blank Check ............................................................................................. 1160
Status Register ................................................................................................................. 1161
22.5.1 Sequencer Status (FMRDY Bit) ......................................................................... 1162
22.5.2 Erase Status (FMERSF Bit) ................................................................................ 1162
22.5.3 Programming Status (FMPRSF Bit) ................................................................... 1162
Full Status Check ............................................................................................................. 1163
Notes on User Programming Mode ................................................................................. 1165
22.7.1 Prohibited Interrupts (EW0 Mode) ..................................................................... 1165
22.7.2 Access Method.................................................................................................... 1165
22.7.3 Programming (EW0 Mode) ................................................................................ 1165
22.7.4 Writing Commands or Data ................................................................................ 1165
22.7.5 Software Standby Mode...................................................................................... 1165
Boot Mode ....................................................................................................................... 1165
SCI Boot Mode ................................................................................................................ 1166
USB Boot Mode............................................................................................................... 1167
Serial Communication Interface Specification for Boot Mode........................................ 1171
Programmer Mode ........................................................................................................... 1200
Section 23 Clock Pulse Generator................................................................... 1201
23.1 Register Descriptions ....................................................................................................... 1202
23.1.1 System Clock Control Register (SCKCR) .......................................................... 1202
23.1.2 PLL Control Register (PLLCR).......................................................................... 1204
23.1.3 USB PLL Control Register (USPLLCR) ............................................................ 1205
23.2 Oscillator.......................................................................................................................... 1206
23.2.1 Connecting a Crystal Resonator.......................................................................... 1206
23.2.2 External Clock Input........................................................................................... 1207
23.3 System-Clock PLL Circuit and Divider........................................................................... 1209
23.4 PLL Circuit for the USB Module..................................................................................... 1210
23.5 Usage Notes ..................................................................................................................... 1211
Page xxviii of xxx
23.5.1 Notes on Clock Pulse Generator ......................................................................... 1211
23.5.2 Notes on Resonator............................................................................................. 1211
23.5.3 Notes on Board Design ....................................................................................... 1212
Section 24 Power-Down Modes ......................................................................1213
24.1 Register Descriptions ....................................................................................................... 1217
24.1.1 Standby Control Register (SBYCR) ................................................................... 1217
24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 1219
24.1.3 Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL) ........................................................................ 1220
24.1.4 RAM Module Stop Control Registers H and L
(RMMSTPCRH, RMMSTPCRL)....................................................................... 1221
24.2 Operation ......................................................................................................................... 1223
24.2.1 Clock Division Mode.......................................................................................... 1223
24.2.2 Sleep Mode ......................................................................................................... 1224
24.2.3 Software Standby Mode...................................................................................... 1225
24.2.4 Hardware Standby Mode .................................................................................... 1228
24.2.5 Module Stop Function ........................................................................................ 1231
24.2.6 All Module Clocks Stop Mode ........................................................................... 1232
24.3 φ Clock Output Control.................................................................................................... 1233
24.4 SDRAMφ Clock Output Control ..................................................................................... 1234
24.5 Usage Notes ..................................................................................................................... 1235
24.5.1 I/O Port Status..................................................................................................... 1235
24.5.2 Current Dissipation during Oscillation Stabilization Standby Period................. 1235
24.5.3 EXDMAC, DMAC, and DTC Module Stop....................................................... 1235
24.5.4 On-Chip Peripheral Module Interrupts ............................................................... 1235
24.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR...................................... 1235
24.5.6 Notes on Clock Division Mode........................................................................... 1236
Section 25 List of Registers .............................................................................1237
25.1 Register Addresses (Address Order)................................................................................ 1238
25.2 Register Bits..................................................................................................................... 1254
25.3 Register States in Each Operating Mode ......................................................................... 1274
Section 26 Electrical Characteristics ...............................................................1289
26.1 Electrical Characteristics for H8S/2456 Group and H8S/2456R Group .......................... 1289
26.1.1 Absolute Maximum Ratings ............................................................................... 1289
26.1.2 DC Characteristics .............................................................................................. 1290
26.1.3 AC Characteristics .............................................................................................. 1294
26.1.4 A/D Conversion Characteristics ......................................................................... 1302
Page xxix of xxx
26.1.5 D/A Conversion Characteristics ......................................................................... 1303
26.1.6 USB Characteristics............................................................................................ 1303
26.1.7 Flash Memory Characteristics ............................................................................ 1304
26.2 Electrical Characteristics for H8S/2454 Group................................................................ 1306
26.2.1 Absolute Maximum Ratings ............................................................................... 1306
26.2.2 DC Characteristics .............................................................................................. 1307
26.2.3 AC Characteristics .............................................................................................. 1311
26.2.4 A/D Conversion Characteristics ......................................................................... 1319
26.2.5 D/A Conversion Characteristics ......................................................................... 1320
26.2.6 USB Characteristics............................................................................................ 1320
26.2.7 Flash Memory Characteristics ............................................................................ 1321
26.3 Timing Charts .................................................................................................................. 1323
26.3.1 Clock Timing ...................................................................................................... 1323
26.3.2 Control Signal Timing ........................................................................................ 1325
26.3.3 Bus Timing ......................................................................................................... 1326
26.3.4 DMAC and EXDMAC Timing........................................................................... 1344
26.3.5 USB Characteristics............................................................................................ 1350
26.3.6 Timing of On-Chip Peripheral Modules ............................................................. 1351
Appendix
A.
B.
C.
.......................................................................................................1359
Port States in Each Processing State ................................................................................ 1359
Package Dimensions ........................................................................................................ 1378
Treatment of Unused Pins................................................................................................ 1382
Main Revisions and Additions in this Edition................................................... 1385
Index
Page xxx of xxx
.......................................................................................................1401
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Section 1 Overview
1.1
Features
The H8S/2456 Group, H8S/2454 Group, and H8S/2456R Group are CISC (Complex Instruction
Set Computer) microprocessors that integrate an H8S/2600 CPU core which has an internal 16-bit
architecture and is upward-compatible with Renesas-original H8/300, H8/300H, and H8S CPUs.
The on-chip peripheral functions provided for enabling system configuration at a low cost are the
DMA controller, EXDMA controller*, data transfer controller, serial communication interface, I2C
bus interface 2, synchronous serial communication unit, USB function module, A/D converter,
D/A converter, and various timers. On-chip ROM is flash memory whose size is 256 Kbytes and
128 Kbytes.
Note: * Not supported by the H8S/2454 Group.
1.1.1
Applications
Application field examples: PC peripheral equipment, office automation equipment, consumer
equipment, etc.
1.1.2
Overview of Specifications
The specifications of this LSI are summarized in table 1.1.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Table 1.1
Overview of Specifications
Type
Module/
Function
Description
Memory
ROM
•
Flash memory version
⎯ User ROM: 256 Kbytes and 128 Kbytes
⎯ Data flash: 8 Kbytes
•
CPU
ROM-less version
RAM
RAM size: 64 Kbytes and 48 Kbytes
CPU
•
16-bit high-speed H8S/2600 CPU (CISC type)
Upward-compatible with H8/300, H8/300H, and H8S CPUs on
an object level
•
General register mode (Sixteen 16-bit general registers)
•
Eight addressing modes
•
Address space: 16 Mbytes
(program: 16 Mbytes, data: 16 Mbytes)
•
Number of basic instructions
69 types (arithmetic and logic, multiply and divide, bitmanipulation, and multiply-and-accumulate instructions)
•
Minimum instruction execution time (ns)
30.3 ns when system clock φ = 33 MHz and Vcc = 3.0 to 3.6 V
(ADD instruction)
Operating mode
Page 2 of 1408
•
Multiplier is included (16 × 16 → 32 bits)
•
Multiply-and-accumulate instructions are supported (16 × 16 +
32 → 32 bits)
Advanced mode
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Type
CPU
Interrupts
(sources)
Module/
Function
MCU operating
mode
Interrupt
controller
Section 1 Overview
Description
•
Mode 1:
Expanded mode with on-chip ROM disabled,
16-bit bus (MD2 and MD1 pins are low and MD0
pin is high)
•
Mode 2:
Expanded mode with on-chip ROM disabled,
8-bit bus (MD2 pin is low, MD1 pin is high, and
MD0 pin is low)
•
Mode 3:
Boot mode (MD2 pin is low and MD1 and MD0 pins
are high)
•
Mode 4:
Expanded mode with on-chip ROM enabled,
8-bit bus (MD2 pin is high and MD1 and MD0 pins
are low)
•
Mode 7:
Single-chip mode (MD2, MD1, and MD0 pins are
high)
•
Power-down modes (a power-down mode is entered when the
SLEEP instruction is executed)
•
External interrupt pins
H8S/2456 Group, H8S/2456R Group:
29 pins (NMI, IRQ15-A to IRQ0-A, IRQ15-B to IRQ0-13B)
H8S/2454 Group:
17 pins (NMI, IRQ7-A to IRQ0-A, IRQ7-B to IRQ0-B)
•
Internal interrupt sources
H8S/2456 Group, H8S/2456R Group: 101 sources
H8S/2454 Group: 99 sources
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
•
Two interrupt control modes (specified by the interrupt control
register)
•
Eight priority levels can be set (specified by the interrupt
priority registers)
•
Independent vector addresses
Page 3 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Type
DMA
Module/
Function
DMA controller
(DMAC)
Description
•
DMA transfer is possible on four channels
•
Three activation sources (auto-request, on-chip module
interrupt, and external request)
•
Byte or word can be set as the transfer unit
•
Short address mode or full address mode can be selected
•
16-Mbyte address space can be specified directly
EXDMA controller •
(EXDMAC)
•
DMA transfer is possible on two channels
Two activation sources (auto-request and external request)
•
Two transfer modes (normal mode and block transfer mode)
•
Dual address mode or single address mode can be selected
•
16-Mbyte address space can be specified directly
• Repeat area can be set
Note: EXDMAC is supported only by the H8S/2456 Group and
H8S/2456R Group.
Data transfer
controller (DTC)
External
bus
extension
Bus controller
(BSC)
•
Transfer is possible on any number of channels
•
An interrupt source can trigger data transfer (chain transfer is
possible)
•
Three transfer modes (normal mode, repeat mode, and block
transfer mode)
•
Byte or word can be set as the transfer unit
•
Activation by software is possible
•
External address space: 16 Mbytes
•
Manages the external address space divided into eight areas
Chip select signals (CS0 to CS7) can be output
8-bit access or 16-bit access can be selected
2-state access or 3-state access can be selected
Program wait states can be inserted
•
External memory interfaces (burst ROM, DRAM, synchronous
DRAM*, address/data multiplexed I/O)
•
Bus arbitration function (bus arbitration of the bus masters
CPU, DTC, DMAC, and EXDMAC)
Note * Supported only by the H8S/2456R Group.
Page 4 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Type
Clock
Module/
Function
Clock pulse
generator (CPG)
Section 1 Overview
Description
•
This LSI has a single on-chip clock pulse generator circuit
•
Consists of an oscillator, a system-clock PLL circuit, a divider,
and a PLL circuit for the USB, and the system clock frequency
can be changed
System clock (φ) cycle: 8 to 33 MHz
•
Six power-down modes
Divided clock mode, sleep mode, module stop function, all
module clock stop mode, software standby mode, and
hardware standby mode
A/D
converter
A/D converter
(ADC)
•
Two units
•
10-bit resolution
•
Number of input channels
H8S/2456 Group and H8S/2456R Group: 16 channels
⎯ Unit 0: 8 channels
⎯ Unit 1: 8 channels
H8S/2454 Group: 10 channels
⎯ Unit 0: 8 channels
⎯ Unit 1: 2 channels
D/A
converter
D/A converter
(DAC)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
•
Sample and hold functionality
•
Conversion time: 4.0 μs per channel (when A/D conversion
clock is set to 10 MHz)
•
Two kinds of operating modes (single mode and scan mode)
•
Three types of A/D conversion start (software, trigger by timer
(TPU or TMR), or external trigger)
•
Resolution (8 bits) × Number of output channels (2 channels)
•
Conversion time: Maximum 10 μs (with 20-pF load)
•
Output voltage: 0 V to Vref
Page 5 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Type
Timer
Module/
Function
16-bit timer
pulse unit (TPU)
Description
•
16-bit timer × 12 channels (general pulse timer unit)
•
Eight counter input clocks can be selected for each channel
•
Maximum 16-pulse input/output (when external expanded
mode is set)
•
Maximum 32-pulse input/output (when single-chip mode is
set)
•
Counter clear operation, simultaneous write to multiple timer
counters (TCNT), simultaneous clearing by compare match
and input capture, register simultaneous input/output possible
by counter synchronous operation, and maximum of 15-phase
PWM output by combination with synchronous operation
•
Buffer operation, phase counting mode (two-phase encoder
input), and cascaded operation settable for channels
•
Input capture function
•
Output compare function (waveform output at compare match)
8-bit timer (TMR) •
Programmable
pulse generator
(PPG)
8-bit timer × 2 channels (operation as a 16-bit timer is also
possible)
•
Selection of seven clock sources: Six internal clock signals or
an external clock input
•
Pulse output with an arbitrary duty cycle or PWM output
•
16-bit pulse output
•
Pulse outputs are divided into four groups
Non-overlap mode is available
Inverted output can be specified
Watchdog
timer
Serial
interface
Page 6 of 1408
Watchdog timer
(WDT)
Serial
communication
interface (SCI)
•
Can operate together with the data transfer controller (DTC)
and DMA controller (DMAC)
•
8-bit timer × 1 channel (eight counter input clocks can be
selected)
•
Switchable between watchdog timer mode and interval timer
mode
•
Five channels (asynchronous or clocked synchronous serial
communication mode)
•
Full-duplex communication capability
•
Choice of any bit rate and choice of LSB-first or MSB-first
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Type
Module/
Function
Smart
Card/SIM
Highfunction
communications
Section 1 Overview
Description
SCI supports Smart Card (SIM) interface
I2C bus interface
2 (IIC2)
Synchronous
serial
communication
unit (SSU)
USB function
module
I/O ports
•
Four channels
•
Continuous transmission/reception
•
Start and stop conditions generated automatically in master
mode
•
Selection of acknowledge output levels when receiving
•
Automatic loading of acknowledge bit when transmitting
•
Bit synchronization/wait function
•
One channel
•
Master mode or slave mode can be selected
•
Standard mode or bidirectional mode can be selected
•
Full-duplex communication capability
•
Consecutive serial communication capability
•
The protocol block conforming to USB2.0 and transceiver
process USB protocol automatically.
•
Transfer speed: Supports full-speed (12 Mbps)
•
Power mode: Self power mode or bus power mode can be
selected
H8S/2456 Group, H8S/2456R Group:
•
Input-only pins: 18
•
Input/output pins: 94
•
Pull-up resistor pins: 40
•
Open-drain pins: 94
H8S/2454 Group:
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
•
Input-only pins: 11
•
Input/output pins: 79
•
Pull-up resistor pins: 40
•
Open-drain pins: 79
Page 7 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Type
Module/
Function
Package
Description
H8S/2456 Group, H8S/2456R Group:
•
144-pin QFP package (PLQP0144KA-A)
(code: FP-144LV, body size: 20 × 20 mm, pin pitch: 0.50 mm)
•
145-pin TLP package (PTLG0145JB-A)
(code: body size: 9 × 9 mm, pin pitch: 0.65 mm)
H8S/2454 Group:
•
120-pin QFP package (PLQP0120LA-A)
(code: FP-120BV, body size: 14 × 14 mm, pin pitch: 0.40 mm)
•
120-pin QFP package (PLQP0120KA-A)
(body size: 16 × 16 mm, pin pitch: 0.50 mm)
•
Operating frequency/
power supply voltage
Pb-free package
• Operating frequency: 8 to 33 MHz
• Power supply voltage: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V
• Supply current: 45 mA typ. (VCC = 3.3 V, AVCC = 3.3 V,
φ = 33 MHz)
Operating environment
temperature (°C)
Page 8 of 1408
−20°C to +75°C (regular specifications)
−40°C to +85°C (wide-range specifications)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
1.2
Section 1 Overview
List of Products
Table 1.2 lists the products and figure 1.1 shows how to read the product type name.
Table 1.2
Product Code Lineup
Flash
RAM
Operating
Guaranteed
Product Type
Type Code
Memory Size
Size
Voltage
Temperature Range Package Code
H8S/2456R
R4F24569NVRFQV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568NVRFQV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565NVRFQV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562NVRFQV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561NVRFQV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24569DVRFQV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568NVRFQV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565NVRFQV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562NVRFQV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561NVRFQV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24569NVRLPV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568NVRLPV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565NVRLPV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562NVRLPV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561NVRLPV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24569DVRLPV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568DVRLPV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565DVRLPV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562DVRLPV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561DVRLPV
⎯
48 Kbytes 3.0 to 3.6 V
Group
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
−20°C to +75°C
PLQP0144KA-A
−40°C to +85°C
−20°C to +75°C
PTLG0145JB-A
−40°C to +85°C
Page 9 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Flash
RAM
Operating
Guaranteed
Product Type
Type Code
Memory Size
Size
Voltage
Temperature Range Package Code
H8S/2456
R4F24569NVFQV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568NVFQV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565NVFQV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562NVFQV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561NVFQV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24569DVFQV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568NVFQV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565NVFQV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562NVFQV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561NVFQV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24569NVLPV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568NVLPV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
Group
Page 10 of 1408
R4F24565NVLPV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562NVLPV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561NVLPV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24569DVLPV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24568DVLPV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24565DVLPV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24562DVLPV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24561DVLPV
⎯
48 Kbytes 3.0 to 3.6 V
−20°C to +75°C
PLQP0144KA-A
−40°C to +85°C
−20°C to +75°C
PTLG0145JB-A
−40°C to +85°C
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Flash
RAM
Operating
Guaranteed
Product Type
Type Code
Memory Size
Size
Voltage
Temperature Range Package Code
H8S/2454
R4F24549NVFPV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24548NVFPV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24545NVFPV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24542NVFPV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24541NVFPV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24549DVFPV
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24548NVFPV
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24545NVFPV
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24542NVFPV
⎯
64 Kbytes 3.0 to 3.6 V
R4S24541NVFPV
⎯
48 Kbytes 3.0 to 3.6 V
R4F24549NVFAU
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24548NVFAU
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24545NVFAU
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24542NVLFAU
⎯
64 Kbytes 3.0 to 3.6 V
R4S24541NVFAU
⎯
48 Kbytes 3.0 to 3.6 V
R4F24549DVFAU
256 Kbytes
64 Kbytes 3.0 to 3.6 V
R4F24548DVFAU
256 Kbytes
48 Kbytes 3.0 to 3.6 V
R4F24545DVFAU
128 Kbytes
48 Kbytes 3.0 to 3.6 V
R4S24542DVFAU
⎯
64 Kbytes 3.0 to 3.6 V
R4S24541DVFAU
⎯
48 Kbytes 3.0 to 3.6 V
Group
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
−20°C to +75°C
PLQP0120LA-A
−40°C to +85°C
−20°C to +75°C
PLQP0120KA-A
−40°C to +85°C
Page 11 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Product type name
R
4
F
2456
9
N
V
R
FQ
V
Indicates treatment of outer leads
V: Sn-2Bi
U: Sn
Indicates the package
FQ: PLQP0144KA-A
LP: PTLG0145JB-A
FP: PLQP0120LA-A
FA: PLQP0120KA-A
Indicates the product group
R: H8S/2456R group
None: H8S/2456 group or H8S/2454 group
Indicates the operating voltage
V: 3.0 to 3.6 V
None: 4.5 to 5.5 V
Indicates the guaranteed temperature range
N: -20 to +75 °C
D: -40 to +85 °C
Indicates memory size classification:
On-chip memory size
9: ROM 256 Kbytes, RAM 64 Kbytes
8: ROM 256 Kbytes, RAM 48 Kbytes
5: ROM 128 Kbytes, RAM 48 Kbytes
2:
, RAM 64 Kbytes
1:
, RAM 48 Kbytes
Indicates "product original type number":
H8S/2456
Indicates the ROM device type:
F: On-chip ROM
S: ROM-less
Indicates the product classification:
Microprocessor
Indicates "Renesas semiconductor"
Figure 1.1 Meaning of Product Type Name
Page 12 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Port A
Port B
Peripheral address bus
Bus controller
Peripheral data bus
Internal data bus
Internal address bus
Port C
PE7/D7/AD7
PE6/D6/AD6
PE5/D5/AD5
PE4/D4/AD4
PE3/D3/AD3
PE2/D2/AD2
PE1/D1/AD1
PE0/D0/AD0
Port F
DMAC
ROM
(flash memory)
PB7/A15/TIOCB8/TCLKH
PB6/A14/TIOCA8
PB5/A13/TIOCB7/TCLKG
PB4/A12/TIOCA7
PB3/A11/TIOCD6/TCLKF
PB2/A10/TIOCC6/TCLKE
PB1/A9/TIOCB6
PB0/A8/TIOCA6
PC7/A7/TIOCB11
PC6/A6/TIOCA11
PC5/A5/TIOCB10
PC4/A4/TIOCA10
PC3/A3/TIOCD9
PC2/A2/TIOCC9
PC1/A1/TIOCB9
PC0/A0/TIOCA9
P35/OE-B/CKE-B*/SCK1/SCL0
P34/SCK0/SCK4-A/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
WDT
RAM
SCI × 5 channels
IIC2 × 4 channels
TPU × 12 channels
(two units)
8-bit D/A converter
(2 channels)
10-bit A/D converter
(total of 16 channels for two units)
PPG
SSU
TMR × 2 channels
Port 5
Port G
EXDMAC
P53/IRQ3-A/ADTRG0-A
P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2
P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3
P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3
Port 2
Port 4
Port 9
Port H
Port J
P97/AN15_1
P96/AN14_1
P95/AN13_1/DA3
P94/AN12_1/DA2
P93/AN11_1
P92/AN10_1
P91/AN9_1
P90/AN8_1
PH3/CS7/OE-A/CKE-A*/IRQ7-B
PH2/CS6/IRQ6-B
PH1/CS5/RAS5/SDRAMφ*
PH0/CS4/RAS4/WE*
PJ2
PJ1
PJ0
Vref
AVcc
AVss
Port 1
P47/AN7_0
P46/AN6_0
P45/AN5_0
P44/AN4_0
P43/AN3_0
P42/AN2_0
P41/AN1_0
P40/AN0_0
USB
P20/IRQ8-B/PO0-A/TIOCA3-A/PUPD+
P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A/VBUS
P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1
P27/IRQ15-B/PO7/TIOCB5/SCL2
P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3
P84/IRQ4-B/EDACK2
P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3
P82/IRQ2-B/ETEND2
P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3
P80/IRQ0-B/EDREQ2
DTC
Interrupt controller
PA7/A23/IRQ7-A/SSO0-B
PA6/A22/IRQ6-A/SSI0-B
PA5/A21/IRQ5-A/SSCK0-B
PA4/A20/IRQ4-A/SCS0-B
PA3/A19/SCK4-B
PA2/A18/RxD4-B
PA1/A17/TxD4-B
PA0/A16
P10/PO8/TIOCA0
P11/PO9/TIOCB0
P12/PO10/TIOCC0/TCLKA
P13/PO11/TIOCD0/TCLKB
P14/PO12/TIOCA1/SSO0-A
P15/PO13/TIOCB1/TCLKC/SSI0-A
P16/PO14/TIOCA2/EDRAK2/SSCK0-A
P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A
P65/IRQ13-A/DACK1/TMO1-A
P64/IRQ12-A/DACK0/TMO0-A
P63/IRQ11-A/TEND1/TMCI1-A
P62/IRQ10-A/TEND0/TMCI0-A
P61/IRQ9-A/DREQ1/TMRI1-A
P60/IRQ8-A/DREQ0/TMRI0-A
H8S/2600 CPU
Clock
pulse
PLL
Port 6
PG6/BREQ-A
PG5/BACK-A
PG4/BREQO-A
PG3/CS3/RAS3/CAS*
PG2/CS2/RAS2/RAS*
PG1/CS1
PG0/CS0
Port E
System
clock
PLL
Port 8
PF7/φ
PF6/AS/AH
PF5/RD
PF4/HWR
PF3/LWR/SSO0-C
PF2/LCAS/DQML*/IRQ15-A/SSI0-C
PF1/UCAS/DQMU*/IRQ14-A/SSCK0-C
PF0/WAIT-A/ADTRG0-B/SCS0-C
Port D
Port 3
MD2
MD1
MD0
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
USD+
USD-
PD7/D15/AD15
PD6/D14/AD14
PD5/D13/AD13
PD4/D12/AD12
PD3/D11/AD11
PD2/D10/AD10
PD1/D9/AD9
PD0/D8/AD8
Block Diagrams
DrVcc
DrVss
Vcc
Vcc
Vcc
Vcc
PLLVcc
PLLVss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VCL
1.3
Section 1 Overview
Note: ∗ Not available in the H8S/2456 Group.
Figure 1.2 Block Diagram of H8S/2456 Group and H8S/2456R Group
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 13 of 1408
Port G
P85/PO5-B/TIOCB4-B/TMO1-B/SCK3
P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3
P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3
Port A
PG6/BREQ-A
PG5/BACK-A
PG4/BREQO-A/CS4
PG3/CS3/RAS3
PG2/CS2/RAS2
PG1/CS1
PG0/CS0
Port B
DMAC
ROM
(flash memory)
Periheral address bus
DTC
PA7/A23/CS7/IRQ7-A/SSO0-B
PA6/A22/IRQ6-A/SSI0-B
PA5/A21/IRQ5-A/SSCK0-B
PA4/A20/IRQ4-A/SCS0-B
PA3/A19/SCK4-B
PA2/A18/RxD4-B
PA1/A17/TxD4-B
PA0/A16
PB7/A15/TIOCB8/TCLKH
PB6/A14/TIOCA8
PB5/A13/TIOCB7/TCLKG
PB4/A12/TIOCA7
PB3/A11/TIOCD6/TCLKF
PB2/A10/TIOCC6/TCLKE
PB1/A9/TIOCB6
PB0/A8/TIOCA6
Port C
Port F
Interrupt controller
Bus controller
Internal data bus
H8S/2600 CPU
Clock
pulse
PLL
Peripheral data bus
PE7/D7/AD7
PE6/D6/AD6
PE5/D5/AD5
PE4/D4/AD4
PE3/D3/AD3
PE2/D2/AD2
PE1/D1/AD1
PE0/D0/AD0
Port E
Internal address bus
Port D
System
clock
PLL
Port 8
PF7/φ
PF6/AS/AH
PF5/RD
PF4/HWR
PF3/LWR/SSO0-C
PF2/CS6/LCAS/SSI0-C
PF1/CS5/UCAS/SSCK0-C
PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C
PD7/D15/AD15
PD6/D14/AD14
PD5/D13/AD13
PD4/D12/AD12
PD3/D11/AD11
PD2/D10/AD10
PD1/D9/AD9
PD0/D8/AD8
DrVCC
DrVSS
VCC
VCC
VCC
VCC
PLLVCC
PLLVSS
VSS
VSS
VSS
VSS
VSS
VSS
VCL
MD2
MD1
MD0
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
USD+
USD-
PC7/A7/TIOCB11
PC6/A6/TIOCA11
PC5/A5/TIOCB10
PC4/A4/TIOCA10
PC3/A3/TIOCD9
PC2/A2/TIOCC9
PC1/A1/TIOCB9
PC0/A0/TIOCA9
Port 3
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
P35/OE-B/SCK1/SCL0
P34/SCK0/SCK4-A/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
WDT
SCI × 5 channels
RAM
IIC2 × 4 channels
TPU × 12 channels
(two units)
8-bit D/A converter
(2 channel)
PPG
Port 5
10-bit A/D converter
(total of 10 channels for two units)
SSU
P20/PO0-A/TIOCA3-A/TMRI0-A/PUPD+
P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A/VBUS
P26/PO6/TIOCA5/SDA2/ADTRG1
P27/PO7/TIOCB5/SCL2
Port 4
Port 9
P95/AN13_1/DA3
P94/AN12_1/DA2
P10/DREQ0/PO8/TIOCA0
P11/DREQ1/PO9/TIOCB0
P12/TEND0/PO10/TIOCC0/TCLKA
P13/TEND1/PO11/TIOCD0/TCLKB
P14/DACK0/PO12/TIOCA1/SSO0-A
P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
P16/PO14/TIOCA2/SSCK0-A
P17/PO15/TIOCB2/TCLKD/SCS0-A
Vref
AVCC
AVSS
Port 2
P47/IRQ7-B/AN7_0
P46/IRQ6-B/AN6_0
P45/IRQ5-B/AN5_0
P44/IRQ4-B/AN4_0
P43/IRQ3-B/AN3_0
P42/IRQ2-B/AN2_0
P41/IRQ1-B/AN1_0
P40/IRQ0-B/AN0_0
USB
TMR × 2 channels
Port 1
P53/IRQ3-A/ADTRG0-A
P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2
P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3
P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3
Figure 1.3 Block Diagram of H8S/2454 Group
Page 14 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Pin Description
1.4.1
Pin Assignments
H8S/2456 Group,
H8S/2456R Group
PLQP0144KA-A
FP-144LV
(Top view)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
MD2
Vss
P80/IRQ0-B/EDREQ2
Vcc
PC0/A0/TIOCA9
PC1/A1/TIOCB9
PC2/A2/TIOCC9
PC3/A3/TIOCD9
PC4/A4/TIOCA10
Vss
PC5/A5/TIOCB10
PC6/A6/TIOCA11
PC7/A7/TIOCB11
PB0/A8/TIOCA6
PB1/A9/TIOCB6
PB2/A10/TIOCC6/TCLKE
PB3/A11/TIOCD6/TCLKF
Vss
PB4/A12/TIOCA7
PB5/A13/TIOCB7/TCLKG
PB6/A14/TIOCA8
PB7/A15/TIOCB8/TCLKH
PA0/A16
PA1/A17/TxD4-B
Vss
PA2/A18/RxD4-B
PA3/A19/SCK4-B
PA4/A20/IRQ4-A/SCS0-B
PA5/A21/IRQ5-A/SSCK0-B
PA6/A22/IRQ6-A/SSI0-B
PA7/A23/IRQ7-A/SSO0-B
EMLE*2
P81/IRQ1-B/PO1-B/TIOCB3-B/TMRI1-B/TxD3/EDREQ3
P82/IRQ2-B/ETEND2
PH0/CS4/RAS4/WE*1
PH1/CS5/RAS5/SDRAMφ*1
PG2/CS2/RAS2/RAS*1
PG3/CS3/RAS3/CAS*1
AVcc
Vref
P40/AN0_0
P41/AN1_0
P42/AN2_0
P43/AN3_0
P44/AN4_0
P45/AN5_0
P46/AN6_0
P47/AN7_0
P90/AN8_1
P91/AN9_1
P92/AN10_1
P93/AN11_1
P94/AN12_1/DA2
P95/AN13_1/DA3
P96/AN14_1
P97/AN15_1
AVss
PG4/BREQO-A/ETCK*4
PG5/BACK-A/ETMS*4
PG6/BREQ-A/ETDI*4
P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3
P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3
P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2
P53/IRQ3-A/ADTRG0-A/ETRST*4
P35/OE-B/CKE-B*1/SCK1/SCL0
P34/SCK0/SCK4-A/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PG1/CS1
PG0/CS0
P65/IRQ13-A/DACK1/TMO1-A
P64/IRQ12-A/DACK0/TMO0-A
P63/IRQ11-A/TEND1/TMCI1-A
STBY
Vss
PJ1
PJ0
Vcc
Vcc
EXTAL
XTAL
Vss
PF7/φ
PLLVss
RES
PLLVcc
PF6/AS/AH
PF5/RD
PF4/HWR
PF3/LWR/SSO0-C
PF2/LCAS/DQML*1/IRQ15-A/SSI0-C
PF1/UCAS/DQMU*1/IRQ14-A/SSCK0-C
PF0/WAIT-A/ADTRG0-B/SCS0-C
P62/IRQ10-A/TEND0/TMCI0-A
P61/IRQ9-A/DREQ1/TMRI1-A
P60/IRQ8-A/DREQ0/TMRI0-A
PD7/D15/AD15
PD6/D14/AD14
PD5/D13/AD13
PD4/D12/AD12
PD3/D11/AD11
PD2/D10/AD10
PD1/D9/AD9
PD0/D8/AD8
1.4
Section 1 Overview
Vcc
PE7/D7/AD7
Vss
PE6/D6/AD6
PE5/D5/AD5
PE4/D4/AD4
PE3/D3/AD3
PE2/D2/AD2
PE1/D1/AD1
PE0/D0/AD0
PJ2
P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/EDACK3
P84/IRQ4-B/EDACK2
P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/ETEND3
P27/IRQ15-B/PO7/TIOCB5/SCL2
P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1
P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A/VBUS
DrVss
USDUSD+
DrVcc
P20/IRQ8-B/PO0-A/TIOCA3-A/PUPD+
Vss
P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A
P16/PO14/TIOCA2/EDRAK2/SSCK0-A
P15/PO13/TIOCB1/TCLKC/SSI0-A
P14/PO12/TIOCA1/SSO0-A
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
VCL*3
NMI
WDTOVF/ETDO*4
PH3/CS7/OE-A/CKE-A*1/IRQ7-B
PH2/CS6/IRQ6-B
41
0.1 μF
(recommended value)
Notes: 1. Not available in the H8S/2456 Group.
2. Emulator enable pin. In normal operating mode, this pin should be fixed low.
Driving this pin high in the flash-memory version enables the on-chip emulation function.
When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins.
3. The VCL pin should be connected to an external capacitor.
4. This pin is dedicated to the on-chip emulator. This pin is enabled when the EMLE pin is high.
Figure 1.4 Pin Assignments for H8S/2456 Group and H8S/2456R Group (1)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 15 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
1
2
3
4
5
6
7
8
9
10
11
12
13
A
Vss
MD1
MD0
P32
P35
P50
AVss
P94
P90
P44
P40
PG2
PG3
B
MD2
Vcc
P31
P34
P51
PG4
P93
P47
P45
P42
AVcc
Vref
PG1
C
PC0
P80
PC1
P30
P33
P52
PG5
P92
P46
P43
P41
PG0
P65
D
PC4
PC2
PC3
P53
PG6
P97
P96
P95
P91
P63
PJ0
P64
STBY
E
PC7
Vss
PC5
PB0
NC
Vss
Vcc
PJ1
Vcc
F
PB3
PC6
PB1
Vss
PF7
Vss
XTAL EXTAL
G
PB6
PB2
PA0
PB4
PF6
RES
PF5
PLLVss
H
Vss
PB7
PA3
PB5
PF2
PF4
PF1
PLLVcc
J
PA5
PA2
PA7
PA1
P62
PF0
P60
PF3
K
EMLE
PA6
P82
PA4
P15
P16
P27
P83
PE0
PE4
PD7
PD6
P61
L
PH0
P81
VCL
P12
P17
P20
DrVcc
P26
PJ2
PE3
PD4
PD2
PD5
M
PH1
PH3
WDTOVF
P11
P13
USD+ DrVss
P85
PE2
PE6
Vss
PD3
PD0
N
NMI
PH2
P10
P14
Vss
USD-
P84
PE1
PE5
PE7
Vcc
PD1
H8S/2456 Group,
H8S/2456R Group
PTLG0145JB-A
(Perspective top view)
P25
Note: Connect NC to VSS or leave it open.
The VCL pin must be connected to an external capacitor (recommended value: 0.1 μF).
Figure 1.5 Pin Assignments for H8S/2456 Group and H8S/2456R Group (2)
Page 16 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PG1/CS1
PG0/CS0
STBY
VSS
P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3
P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3
VCC
VCC
EXTAL
XTAL
VSS
PF7/φ
PLLVSS
RES
PLLVCC
PF6/AS/AH
PF5/RD
PF4/HWR
PF3/LWR/SSO0-C
PF2/CS6/LCAS/SSI0-C
PF1/CS5/UCAS/SSCK0-C
PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C
PD7/D15/AD15
PD6/D14/AD14
PD5/D13/AD13
PD4/D12/AD12
PD3/D11/AD11
PD2/D10/AD10
PD1/D9/AD9
PD0/D8/AD8
Section 1 Overview
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
H8S/2454 Group
PLQ0120LA-A
PLQP0120KA-A
FP-120BV
(Top view)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VCC
PE7/D7/AD7
VSS
PE6/D6/AD6
PE5/D5/AD5
PE4/D4/AD4
PE3/D3/AD3
PE2/D2/AD2
PE1/D1/AD1
PE0/D0/AD0
P85/PO5-B/TIOCB4-B/TMO1-B/SCK3
P27/PO7/TIOCB5/SCL2
P26/PO6/TIOCA5/SDA2/ADTRG1
P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A/VBUS
DrVss
USDUSD+
DrVcc
P20/PO0-A/TIOCA3-A/TMRI0-A/PUPD+
P17/PO15/TIOCB2/TCLKD/SCS0-A
P16/PO14/TIOCA2/SSCK0-A
P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
P14/DACK0/PO12/TIOCA1/SSO0-A
P13/TEND1/PO11/TIOCD0/TCLKB
P12/TEND0/PO10/TIOCC0/TCLKA
P11/DREQ1/PO9/TIOCB0
P10/DREQ0/PO8/TIOCA0
VCL*2
NMI
WDTOVF/ETDO*3
MD2
VCC
PC0/A0/TIOCA9
PC1/A1/TIOCB9
PC2/A2/TIOCC9
PC3/A3/TIOCD9
PC4/A4/TIOCA10
VSS
PC5/A5/TIOCB10
PC6/A6/TIOCA11
PC7/A7/TIOCB11
PB0/A8/TIOCA6
PB1/A9/TIOCB6
PB2/A10/TIOCC6/TCLKE
PB3/A11/TIOCD6/TCLKF
PB4/A12/TIOCA7
VSS
PB5/A13/TIOCB7/TCLKG
PB6/A14/TIOCA8
PB7/A15/TIOCB8/TCLKH
PA0/A16
VSS
PA1/A17/TxD4-B
PA2/A18/RxD4-B
PA3/A19/SCK4-B
PA4/A20/IRQ4-A/SCS0-B
PA5/A21/IRQ5-A/SSCK0-B
PA6/A22/IRQ6-A/SSI0-B
PA7/A23/CS7/IRQ7-A/SSO0-B
EMLE*1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PG2/CS2/RAS2
PG3/CS3/RAS3
AVCC
Vref
P40/IRQ0-B/AN0_0
P41/IRQ1-B/AN1_0
P42/IRQ2-B/AN2_0
P43/IRQ3-B/AN3_0
P44/IRQ4-B/AN4_0
P45/IRQ5-B/AN5_0
P46/IRQ6-B/AN6_0
P47/IRQ7-B/AN7_0
P94/AN12_1/DA2
P95/AN13_1/DA3
AVSS
PG4/BREQO-A/CS4/ETCK*3
PG5/BACK-A/ETMS*3
PG6/BREQ-A/ETDI*3
P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3
P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3
P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2
P53/IRQ3-A/ADTRG0-A/ETRST*3
P35/OE-B/SCK1/SCL0
P34/SCK0/SCK4-A/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
MD0
MD1
33
0.1 μF
(recommended value)
Notes: 1. Emulator enable pin. In normal operating mode, this pin should be fixed low.
Driving this pin high in the flash-memory version enables the on-chip emulation function.
When the on-chip emulation function is in use, pins P53, PG4, PG5, PG6, and WDTOVF are used exclusively as the on-chip emulator pins.
2. The VCL pin should be connected to an external capacitor.
3. This pin is dedicated to the on-chip emulator. This pin is enabled when the EMLE pin is high.
Figure 1.6 Pin Assignments for H8S/2454 Group
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 17 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
1.4.2
Pin Assignments in Each Operating Mode
Table 1.3
Pin Assignments in Each Operating Mode of H8S/2456 Group and H8S/2456R
Group
Pin No.
Pin Name
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash
Memory
Programmer
Mode
1
B1
MD2
MD2
MD2
MD2
MD2
Vss
2
A1
Vss
Vss
Vss
Vss
Vss
Vss
3
C2
P80/IRQ0-B/
EDREQ2
P80/IRQ0-B/
EDREQ2
P80/IRQ0-B/
EDREQ2
P80/IRQ0-B/
EDREQ2
P80/IRQ0-B/ NC
EDREQ2
4
B2
Vcc
Vcc
Vcc
Vcc
Vcc
5
C1
A0
A0
PC0/A0
PC0/A0
PC0/TIOCA9 A0
6
C3
A1
A1
PC1/A1
PC1/A1
PC1/TIOCB9 A1
7
D2
A2
A2
PC2/A2
PC2/A2
PC2/
TIOCC9
A2
8
D3
A3
A3
PC3/A3
PC3/A3
PC3/
TIOCD9
A3
9
D1
A4
A4
PC4/A4
PC4/A4
PC4/
TIOCA10
A4
10
E2
Vss
Vss
Vss
Vss
Vss
Vss
11
E3
A5
A5
PC5/A5
PC5/A5
PC5/
TIOCB10
A5
12
F2
A6
A6
PC6/A6
PC6/A6
PC6/
TIOCA11
A6
13
E1
A7
A7
PC7/A7
PC7/A7
PC7/
TIOCB11
A7
14
E4
A8
A8
PB0/A8
PB0/A8
PB0/TIOCA6 A8
15
F3
A9
A9
PB1/A9
PB1/A9
PB1/TIOCB6 A9
16
G2
A10
A10
PB2/A10
PB2/A10
PB2/
TIOCC6/
TCLKE
A10
17
F1
A11
A11
PB3/A11
PB3/A11
PB3/
TIOCD6/
TCLKF
A11
Mode 3, 7
Page 18 of 1408
Vcc
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash
Memory
Programmer
Mode
18
F4
Vss
Vss
Vss
Vss
Vss
Vss
19
G4
A12
A12
PB4/A12
PB4/A12
PB4/TIOCA7 A12
20
H4
A13
A13
PB5/A13
PB5/A13
PB5/
TIOCB7/
TCLKG
21
G1
A14
A14
PB6/A14
PB6/A14
PB6/TIOCA8 A14
22
H2
A15
A15
PB7/A15
PB7/A15
PB7/
TIOCB8/
TCLKH
A15
23
G3
A16
A16
PA0/A16
PA0/A16
PA0
A16
24
J4
A17
A17
PA1/A17/
TxD4_B
PA1/A17/
TxD4_B
PA1/TxD4_B A17
25
H1
Vss
Vss
Vss
Vss
Vss
26
J2
A18
A18
PA2/A18/
RxD4-B
PA2/A18/
RxD4-B
PA2/RxD4-B A18
27
H3
A19
A19
PA3/A19/
SCK4-B
PA3/A19/
SCK4-B
PA3/SCK4-B NC
28
K4
A20/IRQ4-A
A20/IRQ4-A
PA4/A20/
IRQ4-A/
SCS0-B
PA4/A20/
IRQ4-A/
SCS0-B
PA4/IRQ4-A/ NC
SCS0-B
29
J1
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/
IRQ5-A/
SSCK0-B
NC
30
K2
PA6/A22/
IRQ6-A/
SSI0-B
PA6/A22/
IRQ6-A/
SSI0-B
PA6/A22/
IRQ6-A/
SSI0-B
PA6/A22/
IRQ6-A/
SSI0-B
PA6/
IRQ6-A/
SSI0-B
NC
31
J3
PA7/A23/
IRQ7-A/
SSO0-B
PA7/A23/
IRQ7-A/
SSO0-B
PA7/A23/
IRQ7-A/
SSO0-B
PA7/A23/
IRQ7-A/
SSO0-B
PA7/
IRQ7-A/
SSO0-B
NC
32
K1
EMLE
EMLE
EMLE
EMLE
EMLE
Vss
33
L2
P81/IRQ1-B/
PO1-B/
TIOCB3-B/
TMRI1-B/
TxD3/
EDREQ3
P81/IRQ1-B/
PO1-B/
TIOCB3-B/
TMRI1-B/
TxD3/
EDREQ3
P81/IRQ1-B/
PO1-B/
TIOCB3-B/
TMRI1-B/
TxD3/
EDREQ3
P81/IRQ1-B/
PO1-B/
TIOCB3-B/
TMRI1-B/
TxD3/
EDREQ3
P81/IRQ1-B/ NC
PO1-B/
TIOCB3-B/
TMRI1-B/
TxD3/
EDREQ3
Mode 3, 7
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
A13
Vss
Page 19 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
34
K3
P82/IRQ2-B/
ETEND2
P82/IRQ2-B/
ETEND2
P82/IRQ2-B/
ETEND2
P82/IRQ2-B/
ETEND2
P82/
IRQ2-B
NC
35
L1
PH0/CS4/
RAS4/WE*
PH0/CS4/
RAS4/WE*
PH0/CS4/
RAS4/WE*
PH0/CS4/
RAS4/WE*
PH0
NC
36
M1
PH1/CS5/
RAS5/
SDRAMφ*
PH1/CS5/
RAS5/
SDRAMφ*
PH1/CS5/
RAS5/
SDRAMφ*
PH1/CS5/
RAS5/
SDRAMφ*
PH1/
SDRAMφ*
NC
37
N2
PH2/CS6/
IRQ6-B
PH2/CS6/
IRQ6-B
PH2/CS6/
IRQ6-B
PH2/CS6/
IRQ6-B
PH2/
IRQ6-B
NC
38
M2
PH3/CS7/
OE-A/
CKE-A*/
IRQ7-B
PH3/CS7/
OE-A/
CKE-A*/
IRQ7-B
PH3/CS7/
OE-A/
CKE-A*/
IRQ7-B
PH3/CS7/
OE-A/
CKE-A*/
IRQ7-B
PH3/IRQ7-B NC
39
M3
WDTOVF
WDTOVF
WDTOVF
WDTOVF
WDTOVF
NC
40
N1
NMI
NMI
NMI
NMI
NMI
Vcc
41
L3
VCL
VCL
VCL
VCL
VCL
VCL
42
N3
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
NC
43
M4
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
NC
44
L4
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
OE
45
M5
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
CE
46
N4
P14/PO12/
TIOCA1/
SSO0-A
P14/PO12/
TIOCA1/
SSO0-A
P14/PO12/
TIOCA1/
SSO0-A
P14/PO12/
TIOCA1/
SSO0-A
P14/PO12/
TIOCA1/
SSO0-A
WE
47
K5
P15/PO13/
TIOCB1/
TCLKC/
SSI0-A
P15/PO13/
TIOCB1/
TCLKC/
SSI0-A
P15/PO13/
TIOCB1/
TCLKC/
SSI0-A
P15/PO13/
TIOCB1/
TCLKC/
SSI0-A
P15/PO13/
TIOCB1/
TCLKC/
SSI0-A
NC
48
K6
P16/PO14/
TIOCA2/
EDRAK2/
SSCK0-A
P16/PO14/
TIOCA2/
EDRAK2/
SSCK0-A
P16/PO14/
TIOCA2/
EDRAK2/
SSCK0-A
P16/PO14/
TIOCA2/
EDRAK2/
SSCK0-A
P16/PO14/
TIOCA2/
SSCK0-A
NC
Page 20 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
49
L5
P17/PO15/
TIOCB2/
TCLKD/
EDRAK3/
SCS0-A
P17/PO15/
TIOCB2/
TCLKD/
EDRAK3/
SCS0-A
P17/PO15/
TIOCB2/
TCLKD/
EDRAK3/
SCS0-A
P17/PO15/
TIOCB2/
TCLKD/
EDRAK3/
SCS0-A
P17/PO15/
TIOCB2/
TCLKD/
SCS0-A
NC
50
N5
Vss
Vss
Vss
Vss
Vss
Vss
51
L6
P20/IRQ8-B/
PO0-A/
TIOCA3-A/
PUPD+
P20/IRQ8-B/
PO0-A/
TIOCA3-A/
PUPD+
P20/IRQ8-B/
PO0-A/
TIOCA3-A/
PUPD+
P20/IRQ8-B/
PO0-A/
TIOCA3-A/
PUPD+
P20/IRQ8-B/ NC
PO0-A/
TIOCA3-A/
PUPD+
52
L7
DrVcc
DrVcc
DrVcc
DrVcc
DrVcc
53
M6
USD+
USD+
USD+
USD+
USD+
NC
54
N6
USD-
USD-
USD-
USD-
USD-
NC
55
M7
DrVss
DrVss
DrVss
DrVss
DrVss
Vss
56
N7
P25/WAIT-B/
IRQ13-B/
PO5-A/
TIOCB4-A/
VBUS
P25/WAIT-B/
IRQ13-B/
PO5-A/
TIOCB4-A/
VBUS
P25/WAIT-B/
IRQ13-B/
PO5-A/
TIOCB4-A/
VBUS
P25/WAIT-B/
IRQ13-B/
PO5-A/
TIOCB4-A/
VBUS
P25/
IRQ13-B/
PO5-A/
TIOCB4-A/
VBUS
NC
57
L8
P26/
IRQ14-B/
PO6/
TIOCA5/
SDA2/
ADTRG1
P26/
IRQ14-B/
PO6/
TIOCA5/
SDA2/
ADTRG1
P26/
IRQ14-B/
PO6/
TIOCA5/
SDA2/
ADTRG1
P26/
IRQ14-B/
PO6/
TIOCA5/
SDA2/
ADTRG1
P26/
IRQ14-B/
PO6/
TIOCA5/
SDA2/
ADTRG1
NC
58
K7
P27/
IRQ15-B/
PO7/
TIOCB5/
SCL2
P27/
IRQ15-B/
PO7/
TIOCB5/
SCL2
P27/
IRQ15-B/
PO7/
TIOCB5/
SCL2
P27/
IRQ15-B/
PO7/
TIOCB5/
SCL2
P27/
IRQ15-B/
PO7/
TIOCB5/
SCL2
NC
59
K8
P83/IRQ3-B/
PO3-B/
TIOCD3-B/
TMCI1-B/
RxD3/
ETEND3
P83/IRQ3-B/
PO3-B/
TIOCD3-B/
TMCI1-B/
RxD3/
ETEND3
P83/IRQ3-B/
PO3-B/
TIOCD3-B/
TMCI1-B/
RxD3/
ETEND3
P83/IRQ3-B/
PO3-B/
TIOCD3-B/
TMCI1-B/
RxD3/
ETEND3
P83/IRQ3-B/ NC
PO3-B/
TIOCD3-B/
TMCI1-B/
RxD3
60
N8
P84/IRQ4-B/
EDACK2
P84/IRQ4-B/
EDACK2
P84/IRQ4-B/
EDACK2
P84/IRQ4-B/
EDACK2
P84/IRQ4-B
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Vcc
NC
Page 21 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
61
M8
P85/IRQ5-B/
PO5-B/
TIOCB4-B/
TMO1-B/
SCK3/
EDACK3
P85/IRQ5-B/
PO5-B/
TIOCB4-B/
TMO1-B/
SCK3/
EDACK3
P85/IRQ5-B/
PO5-B/
TIOCB4-B/
TMO1-B/
SCK3/
EDACK3
P85/IRQ5-B/
PO5-B/
TIOCB4-B/
TMO1-B/
SCK3/
EDACK3
P85/IRQ5-B/ NC
PO5-B/
TIOCB4-B/
TMO1-B/
SCK3
62
L9
PJ2
PJ2
PJ2
PJ2
PJ2
Vss
63
K9
PE0/D0/AD0
PE0/D0/AD0
PE0/D0/AD0
PE0/D0/AD0
PE0
NC
64
N9
PE1/D1/AD1
PE1/D1/AD1
PE1/D1/AD1
PE1/D1/AD1
PE1
NC
65
M9
PE2/D2/AD2
PE2/D2/AD2
PE2/D2/AD2
PE2/D2/AD2
PE2
NC
66
L10
PE3/D3/AD3
PE3/D3/AD3
PE3/D3/AD3
PE3/D3/AD3
PE3
NC
67
K10
PE4/D4/AD4
PE4/D4/AD4
PE4/D4/AD4
PE4/D4/AD4
PE4
NC
68
N10
PE5/D5/AD5
PE5/D5/AD5
PE5/D5/AD5
PE5/D5/AD5
PE5
NC
69
M10
PE6/D6/AD6
PE6/D6/AD6
PE6/D6/AD6
PE6/D6/AD6
PE6
NC
70
M11
Vss
Vss
Vss
Vss
Vss
Vss
71
N11
PE7/D7/AD7
PE7/D7/AD7
PE7/D7/AD7
PE7/D7/AD7
PE7
NC
72
N12
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
73
M13
D8/AD8
D8/AD8
D8/AD8
D8/AD8
PD0
I/O0
74
N13
D9/AD9
D9/AD9
D9/AD9
D9/AD9
PD1
I/O1
75
L12
D10/AD10
D10/AD10
D10/AD10
D10/AD10
PD2
I/O2
76
M12
D11/AD11
D11/AD11
D11/AD11
D11/AD11
PD3
I/O3
77
L11
D12/AD12
D12/AD12
D12/AD12
D12/AD12
PD4
I/O4
78
L13
D13/AD13
D13/AD13
D13/AD13
D13/AD13
PD5
I/O5
79
K12
D14/AD14
D14/AD14
D14/AD14
D14/AD14
PD6
I/O6
80
K11
D15/AD15
D15/AD15
D15/AD15
D15/AD15
PD7
I/O7
81
J12
P60/IRQ8-A/
DREQ0/
TMRI0-A
P60/IRQ8-A/
DREQ0/
TMRI0-A
P60/IRQ8-A/
DREQ0/
TMRI0-A
P60/IRQ8-A/
DREQ0/
TMRI0-A
P60/IRQ8-A/ NC
DREQ0/
TMRI0-A
82
K13
P61/IRQ9-A/
DREQ1/
TMRI1-A
P61/IRQ9-A/
DREQ1/
TMRI1-A
P61/IRQ9-A/
DREQ1/
TMRI1-A
P61/IRQ9-A/
DREQ1/
TMRI1-A
P61/IRQ9-A/ NC
DREQ1/
TMRI1-A
Page 22 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
83
J10
P62/
IRQ10-A/
TEND0/
TMCI0-A
P62/
IRQ10-A/
TEND0/
TMCI0-A
P62/
IRQ10-A/
TEND0/
TMCI0-A
P62/
IRQ10-A/
TEND0/
TMCI0-A
P62/
IRQ10-A/
TEND0/
TMCI0-A
NC
84
J11
PF0/WAIT-A/ PF0/WAIT-A/ PF0/WAIT-A/ PF0/WAIT-A/
ADTRG0-B/ ADTRG0-B/ ADTRG0-B/ ADTRG0-B/
SCS0-C
SCS0-C
SCS0-C
SCS0-C
PF0/
ADTRG0-B/
SCS0-C
NC
85
H12
PF1/UCAS/
DQMU*1/
IRQ14-A/
SSCK0-C
PF1/UCAS/
DQMU*1/
IRQ14-A/
SSCK0-C
PF1/UCAS/
DQMU*1/
IRQ14-A/
SSCK0-C
PF1/UCAS/
DQMU*1/
IRQ14-A/
SSCK0-C
PF1/
IRQ14-A/
SSCK0-C
NC
86
H10
PF2/LCAS/
DQML*1/
IRQ15-A/
SSI0-C
PF2/LCAS/
DQML*1/
IRQ15-A/
SSI0-C
PF2/LCAS/
DQML*1/
IRQ15-A/
SSI0-C
PF2/LCAS/
DQML*1/
IRQ15-A/
SSI0-C
PF2/
IRQ15-A/
SSI0-C
NC
87
J13
PF3/LWR/
SSO0-C
PF3/LWR/
SSO0-C
PF3/LWR/
SSO0-C
PF3/LWR/
SSO0-C
PF3/
SSO0-C
NC
88
H11
HWR
HWR
HWR
HWR
PF4
NC
89
G12
RD
RD
RD
RD
PF5
NC
90
G10
PF6/AS/AH
PF6/AS/AH
PF6/AS/AH
PF6/AS/AH
PF6
NC
91
H13
PLLVcc
PLLVcc
PLLVcc
PLLVcc
PLLVcc
Vcc
92
G11
RES
RES
RES
RES
RES
RES
93
G13
PLLVss
PLLVss
PLLVss
PLLVss
PLLVss
Vss
94
F10
PF7/φ
PF7/φ
PF7/φ
PF7/φ
PF7/φ
NC
95
F11
Vss
Vss
Vss
Vss
Vss
Vss
96
F12
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
97
F13
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
98
E11
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
99
E13
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
100
D11
PJ0
PJ0
PJ0
PJ0
PJ0
NC
101
E12
PJ1
PJ1
PJ1
PJ1
PJ1
NC
102
E10
Vss
Vss
Vss
Vss
Vss
Vss
103
D13
STBY
STBY
STBY
STBY
STBY
Vcc
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 23 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
104
D10
P63/
IRQ11-A/
TEND1/
TMCI1-A
P63/
IRQ11-A/
TEND1/
TMCI1-A
P63/
IRQ11-A/
TEND1/
TMCI1-A
P63/
IRQ11-A/
TEND1/
TMCI1-A
P63/
IRQ11-A/
TEND1/
TMCI1-A
NC
105
D12
P64/
IRQ12-A/
DACK0/
TMO0-A
P64/
IRQ12-A/
DACK0/
TMO0-A
P64/
IRQ12-A/
DACK0/
TMO0-A
P64/
IRQ12-A/
DACK0/
TMO0-A
P64/
IRQ12-A/
DACK0/
TMO0-A
NC
106
C13
P65/
IRQ13-A/
DACK1/
TMO1-A
P65/
IRQ13-A/
DACK1/
TMO1-A
P65/
IRQ13-A/
DACK1/
TMO1-A
P65/
IRQ13-A/
DACK1/
TMO1-A
P65/
IRQ13-A/
DACK1/
TMO1-A
NC
107
C12
PG0/CS0
PG0/CS0
PG0/CS0
PG0/CS0
PG0
NC
108
B13
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
PG1
NC
109
A12
PG2/CS2/
RAS2/RAS*
PG2/CS2/
RAS2/RAS*
PG2/CS2/
RAS2/RAS*
PG2/CS2/
RAS2/RAS*
PG2
NC
110
A13
PG3/CS3/
RAS3/CAS*
PG3/CS3/
RAS3/CAS*
PG3/CS3/
RAS3/CAS*
PG3/CS3/
RAS3/CAS*
PG3
NC
111
B11
AVcc
AVcc
AVcc
AVcc
AVcc
Vcc
112
B12
Vref
Vref
Vref
Vref
Vref
Vcc
113
A11
P40/AN0_0
P40/AN0_0
P40/AN0_0
P40/AN0_0
P40/AN0_0
NC
114
C11
P41/AN1_0
P41/AN1_0
P41/AN1_0
P41/AN1_0
P41/AN1_0
NC
115
B10
P42/AN2_0
P42/AN2_0
P42/AN2_0
P42/AN2_0
P42/AN2_0
NC
116
C10
P43/AN3_0
P43/AN3_0
P43/AN3_0
P43/AN3_0
P43/AN3_0
Vss
117
A10
P44/AN4_0
P44/AN4_0
P44/AN4_0
P44/AN4_0
P44/AN4_0
Vcc
118
B9
P45/AN5_0
P45/AN5_0
P45/AN5_0
P45/AN5_0
P45/AN5_0
Vss
119
C9
P46/AN6_0
P46/AN6_0
P46/AN6_0
P46/AN6_0
P46/AN6_0
NC
120
B8
P47/AN7_0
P47/AN7_0
P47/AN7_0
P47/AN7_0
P47/AN7_0
NC
121
A9
P90/AN8_1
P90/AN8_1
P90/AN8_1
P90/AN8_1
P90/AN8_1
NC
122
D9
P91/AN9_1
P91/AN9_1
P91/AN9_1
P91/AN9_1
P91/AN9_1
NC
123
C8
P92/AN10_1
P92/AN10_1
P92/AN10_1
P92/AN10_1
P92/AN10_1 NC
124
B7
P93/AN11_1
P93/AN11_1
P93/AN11_1
P93/AN11_1
P93/AN11_1 NC
125
A8
P94/
AN12_1/
DA2
P94/
AN12_1/
DA2
P94/
AN12_1/
DA2
P94/
AN12_1/
DA2
P94/
AN12_1/
DA2
Page 24 of 1408
NC
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
126
D8
P95/
AN13_1/
DA3
P95/
AN13_1/
DA3
P95/
AN13_1/
DA3
P95/
AN13_1/
DA3
P95/
AN13_1/
DA3
NC
127
D7
P96/AN14_1
P96/AN14_1
P96/AN14_1
P96/AN14_1
P96/AN14_1
NC
128
D6
P97/AN15_1
P97/AN15_1
P97/AN15_1
P97/AN15_1
P97/AN15_1
NC
129
A7
AVss
AVss
AVss
AVss
AVss
Vss
130
B6
PG4/
BREQO-A
PG4/
BREQO-A
PG4/
BREQO-A
PG4/
BREQO-A
PG4
NC
131
C7
PG5/
BACK-A
PG5/
BACK-A/
PG5/
BACK-A
PG5/
BACK-A
PG5
NC
132
D5
PG6/BREQ-A PG6/BREQ-A PG6/BREQ-A PG6/BREQ-A PG6
NC
133
A6
P50/
BREQO-B/
IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/
SDA3
P50/
BREQO-B/
IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/
SDA3
P50/
BREQO-B/
IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/
SDA3
P50/
BREQO-B/
IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/
SDA3
P50/IRQ0-A/ Vss
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/
SDA3
134
B5
P51/BREQ-B/
IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/
SCL3
P51/BREQ-B/
IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/
SCL3
P51/BREQ-B/
IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/
SCL3
P51/BREQ-B/
IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/
SCL3
P51/IRQ1-A/ Vss
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
135
C6
P52/BACK-B/
IRQ2-A/
PO4-B/
TIOCA4-B/
TMO0-B/
SCK2
P52/BACK-B/
IRQ2-A/
PO4-B/
TIOCA4-B/
TMO0-B/
SCK2
P52/BACK-B/
IRQ2-A/
PO4-B/
TIOCA4-B/
TMO0-B/
SCK2
P52/BACK-B/
IRQ2-A/
PO4-B/
TIOCA4-B/
TMO0-B/
SCK2
P52/IRQ2-A/ Vcc
PO4-B/
TIOCA4-B/
TMO0-B/
SCK2
136
D4
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/ NC
ADTRG0-A
137
A5
P35/OE-B/
CKE-B*1/
SCK1/SCL0
P35/OE-B/
CKE-B*1/
SCK1/SCL0
P35/OE-B/
CKE-B*1/
SCK1/SCL0
P35/OE-B/
CKE-B*1/
SCK1/SCL0
P35/SCK1/
SCL0
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
NC
Page 25 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0144KA-A PTLG0145JB-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
138
B4
P34/SCK0/
SCK4-A/
SDA0
P34/SCK0/
SCK4-A/
SDA0
P34/SCK0/
SCK4-A/
SDA0
P34/SCK0/
SCK4-A/
SDA0
P34/SCK0/
SCK4-A/
SDA0
NC
139
C5
P33/RxD1/
SCL1
P33/RxD1/
SCL1
P33/RxD1/
SCL1
P33/RxD1/
SCL1
P33/RxD1/
SCL1
NC
140
A4
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
Vcc
IrRxD/SDA1
141
B3
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
NC
142
C4
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
NC
143
A3
MD0
MD0
MD0
MD0
MD0
Vss
144
A2
MD1
MD1
MD1
MD1
MD1
Vss
E5
NC
NC
NC
NC
NC
NC
⎯
Note: Not supported in the H8S/2456 Group.
Page 26 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Table 1.4
Section 1 Overview
Pin Assignments in Each Operating Mode of H8S/2454 Group
Pin No.
Pin Name
PLQP0120LA-A,
PLQP0120KA-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash
Memory
Programmer
Mode
1
MD2
MD2
MD2
MD2
MD2
Vss
2
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
3
A0
A0
PC0/A0
PC0/A0
PC0/TIOCA9
A0
4
A1
A1
PC1/A1
PC1/A1
PC1/TIOCB9
A1
5
A2
A2
PC2/A2
PC2/A2
PC2/TIOCC9
A2
6
A3
A3
PC3/A3
PC3/A3
PC3/TIOCD9
A3
Mode 3, 7
7
A4
A4
PC4/A4
PC4/A4
PC4/TIOCA10
A4
8
Vss
Vss
Vss
Vss
Vss
Vss
9
A5
A5
PC5/A5
PC5/A5
PC5/TIOCB10
A5
10
A6
A6
PC6/A6
PC6/A6
PC6/TIOCA11
A6
11
A7
A7
PC7/A7
PC7/A7
PC7/TIOCB11
A7
12
A8
A8
PB0/A8
PB0/A8
PB0/TIOCA6
A8
13
A9
A9
PB1/A9
PB1/A9
PB1/TIOCB6
A9
14
A10
A10
PB2/A10
PB2/A10
PB2/TIOCC6/
TCLKE
A10
15
A11
A11
PB3/A11
PB3/A11
PB3/TIOCD6/
TCLKF
A11
16
A12
A12
PB4/A12
PB4/A12
PB4/TIOCA7
A12
17
Vss
Vss
Vss
Vss
Vss
Vss
18
A13
A13
PB5/A13
PB5/A13
PB5/TIOCB7/
TCLKG
A13
19
A14
A14
PB6/A14
PB6/A14
PB6/TIOCA8
A14
20
A15
A15
PB7/A15
PB7/A15
PB7/TIOCB8/
TCLKH
A15
21
A16
A16
PA0/A16
PA0/A16
PA0
A16
22
Vss
Vss
Vss
Vss
Vss
Vss
23
A17
A17
PA1/A17/
TxD4-B
PA1/A17/
TxD4-B
PA1/TxD4-B
A17
24
A18
A18
PA2/A18/
RxD4-B
PA2/A18/
RxD4-B
PA2/RxD4-B
A18
25
A19
A19
PA3/A19/
SCK4-B
PA3/A19/
SCK4-B
PA3/SCK4-B
NC
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 27 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
Flash
Memory
Programmer
Mode
PLQP0120LA-A,
PLQP0120KA-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
26
A20/IRQ4-A
A20/IRQ4-A
PA4/A20/
IRQ4-A/
SCS0-B
PA4/A20/
IRQ4-A/
SCS0-B
PA4/IRQ4-A/
SCS0-B
NC
27
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/A21/
IRQ5-A/
SSCK0-B
PA5/IRQ5-A/
SSCK0-B
NC
28
PA6/A22/
IRQ6-A/SSI0-B
PA6/A22/
IRQ6-A/SSI0-B
PA6/A22/
IRQ6-A/SSI0-B
PA6/A22/
IRQ6-A/SSI0-B
PA6/IRQ6-A/
SSI0-B
NC
29
PA7/A23/CS7/
PA7/A23/CS7/
PA7/A23/CS7/
PA7/A23/CS7/
PA7/IRQ7-A/
IRQ7-A/SSO0-B IRQ7-A/SSO0-B IRQ7-A/SSO0-B IRQ7-A/SSO0-B SSO0-B
NC
30
EMLE
EMLE
EMLE
EMLE
EMLE
Vss
31
WDTOVF
WDTOVF
WDTOVF
WDTOVF
WDTOVF
NC
32
NMI
NMI
NMI
NMI
NMI
Vcc
33
VCL
VCL
VCL
VCL
VCL
VCL
34
P10/DREQ0/
PO8/TIOCA0
P10/DREQ0/
PO8/TIOCA0
P10/DREQ0/
PO8/TIOCA0
P10/DREQ0/
PO8/TIOCA0
P10/DREQ0/
PO8/TIOCA0
NC
35
P11/DREQ1/
PO9/TIOCB0
P11/DREQ1/
PO9/TIOCB0
P11/DREQ1/
PO9/TIOCB0
P11/DREQ1/
PO9/TIOCB0
P11/DREQ1/
PO9/TIOCB0
NC
36
P12/TEND0/
PO10/TIOCC0/
TCLKA
P12/TEND0/
PO10/TIOCC0/
TCLKA
P12/TEND0/
PO10/TIOCC0/
TCLKA
P12/TEND0/
PO10/TIOCC0/
TCLKA
P12/TEND0/
PO10/TIOCC0/
TCLKA
OE
37
P13/TEND1/
PO11/TIOCD0/
TCLKB
P13/TEND1/
PO11/TIOCD0/
TCLKB
P13/TEND1/
PO11/TIOCD0/
TCLKB
P13/TEND1/
PO11/TIOCD0/
TCLKB
P13/TEND1/
PO11/TIOCD0/
TCLKB
CE
38
P14/DACK0/
PO12/TIOCA1/
SSO0-A
P14/DACK0/
PO12/TIOCA1/
SSO0-A
P14/DACK0/
PO12/TIOCA1/
SSO0-A
P14/DACK0/
PO12/TIOCA1/
SSO0-A
P14/DACK0/
PO12/TIOCA1/
SSO0-A
WE
39
P15/DACK1/
PO13/TIOCB1/
TCLKC/SSI0-A
P15/DACK1/
PO13/TIOCB1/
TCLKC/SSI0-A
P15/DACK1/
PO13/TIOCB1/
TCLKC/SSI0-A
P15/DACK1/
PO13/TIOCB1/
TCLKC/SSI0-A
P15/DACK1/
PO13/TIOCB1/
TCLKC/SSI0-A
NC
40
P16/PO14/
TIOCA2/
SSCK0-A
P16/PO14/
TIOCA2/
SSCK0-A
P16/PO14/
TIOCA2/
SSCK0-A
P16/PO14/
TIOCA2/
SSCK0-A
P16/PO14/
TIOCA2/
SSCK0-A
NC
41
P17/PO15/
P17/PO15/
P17/PO15/
P17/PO15/
TIOCB2/
TIOCB2/
TIOCB2/
TIOCB2/
TCLKD/SCS0-A TCLKD/SCS0-A TCLKD/SCS0-A TCLKD/SCS0-A
P17/PO15/
TIOCB2/
TCLKD/SCS0-A
NC
Page 28 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
PLQP0120LA-A,
PLQP0120KA-A Mode 1
Mode 2
Mode 4
Flash
Memory
Programmer
Mode
EXPE = 1
EXPE = 0
42
P20/PO0-A/
TIOCA3-A/
TMRI0-A/
PUPD+
P20/PO0-A/
TIOCA3-A/
TMRI0-A/
PUPD+
P20/PO0-A/
TIOCA3-A/
TMRI0-A/
PUPD+
P20/PO0-A/
TIOCA3-A/
TMRI0-A/
PUPD+
P20/PO0-A/
TIOCA3-A/
TMRI0-A/
PUPD+
NC
43
DrVcc
DrVcc
DrVcc
DrVcc
DrVcc
Vcc
44
USD+
USD+
USD+
USD+
USD+
NC
45
USD-
USD-
USD-
USD-
USD-
NC
46
DrVss
DrVss
DrVss
DrVss
DrVss
DrVss
47
P25/WAIT-B/
P25/WAIT-B/
P25/WAIT-B/
P25/WAIT-B/
P25/
NC
PO5-A/
PO5-A/
PO5-A/
PO5-A/
PO5-A/
TIOCB4-A/
TIOCB4-A/
TIOCB4-A/
TIOCB4-A/
TIOCB4-A/
TMO1-A/VBUS
TMO1-A/VBUS
TMO1-A/VBUS
TMO1-A/VBUS
TMO1-A/VBUS
48
P26/PO6/
TIOCA5/SDA2/
ADTRG1
P26/PO6/
TIOCA5/SDA2/
ADTRG1
P26/PO6/
TIOCA5/SDA2/
ADTRG1
P26/PO6/
TIOCA5/SDA2/
ADTRG1
P26/PO6/
TIOCA5/SDA2/
ADTRG1
NC
49
P27/PO7/
TIOCB5/SCL2
P27/PO7/
TIOCB5/SCL2
P27/PO7/
TIOCB5/SCL2
P27/PO7/
TIOCB5/SCL2
P27/PO7/
TIOCB5/SCL2
NC
50
P85/PO5-B/
TIOCB4-B/
TMO1-B/SCK3
P85/PO5-B/
TIOCB4-B/
TMO1-B/SCK3
P85/PO5-B/
TIOCB4-B/
TMO1-B/SCK3
P85/PO5-B/
TIOCB4-B/
TMO1-B/SCK3
P85/PO5-B/
TIOCB4-B/
TMO1-B/SCK3
NC
51
PE0/D0/AD0
PE0/D0/AD0
PE0/D0/AD0
PE0/D0/AD0
PE0
NC
52
PE1/D1/AD1
PE1/D1/AD1
PE1/D1/AD1
PE1/D1/AD1
PE1
NC
53
PE2/D2/AD2
PE2/D2/AD2
PE2/D2/AD2
PE2/D2/AD2
PE2
NC
54
PE3/D3/AD3
PE3/D3/AD3
PE3/D3/AD3
PE3/D3/AD3
PE3
NC
55
PE4/D4/AD4
PE4/D4/AD4
PE4/D4/AD4
PE4/D4/AD4
PE4
NC
56
PE5/D5/AD5
PE5/D5/AD5
PE5/D5/AD5
PE5/D5/AD5
PE5
NC
57
PE6/D6/AD6
PE6/D6/AD6
PE6/D6/AD6
PE6/D6/AD6
PE6
NC
58
Vss
Vss
Vss
Vss
Vss
Vss
59
PE7/D7/AD7
PE7/D7/AD7
PE7/D7/AD7
PE7/D7/AD7
PE7
NC
60
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
61
D8/AD8
D8/AD8
D8/AD8
D8/AD8
PD0
I/O0
62
D9/AD9
D9/AD9
D9/AD9
D9/AD9
PD1
I/O1
63
D10/AD10
D10/AD10
D10/AD10
D10/AD10
PD2
I/O2
64
D11/AD11
D11/AD11
D11/AD11
D11/AD11
PD3
I/O3
65
D12/AD12
D12/AD12
D12/AD12
D12/AD12
PD4
I/O4
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 29 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
PLQP0120LA-A,
PLQP0120KA-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash
Memory
Programmer
Mode
66
D13/AD13
D13/AD13
D13/AD13
D13/AD13
PD5
I/O5
67
D14/AD14
D14/A14D
D14/AD14
D14/AD14
PD6
I/O6
68
D15/AD15
D15/AD15
D15/AD15
D15/AD15
PD7
I/O7
69
PF0/WAIT-A/
OE-A/
ADTRG0-B/
SCS0-C
PF0/WAIT-A/
OE-A/
ADTRG0-B/
SCS0-C
PF0/WAIT-A/
OE-A/
ADTRG0-B/
SCS0-C
PF0/WAIT-A/
OE-A/
ADTRG0-B/
SCS0-C
PF0/
ADTRG0-B/
SCS0-C
NC
70
PF1/CS5/UCAS/ PF1/CS5/UCAS/ PF1/CS5/UCAS/ PF1/CS5/UCAS/ PF1/SSCK0-C
SSCK0-C
SSCK0-C
SSCK0-C
SSCK0-C
NC
71
PF2/CS6/
LCAS/SSI0-C
PF2/CS6/
LCAS/SSI0-C
PF2/CS6/
LCAS/SSI0-C
PF2/CS6/
LCAS/SSI0-C
PF2/
SSI0-C
NC
72
PF3/LWR/
SSO0-C
PF3/LWR/
SSO0-C
PF3/LWR/
SSO0-C
PF3/LWR/
SSO0-C
PF3/
SSO0-C
NC
73
HWR
HWR
HWR
HWR
PF4
NC
74
RD
RD
RD
RD
PF5
NC
75
PF6/AS/AH
PF6/AS/AH
PF6/AS/AH
PF6/AS/AH
PF6
NC
76
PLLVcc
PLLVcc
PLLVcc
PLLVcc
PLLVcc
Vcc
Mode 3, 7
77
RES
RES
RES
RES
RES
RES
78
PLLVss
PLLVss
PLLVss
PLLVss
PLLVss
Vss
79
PF7/φ
PF7/φ
PF7/φ
PF7/φ
PF7/φ
NC
80
Vss
Vss
Vss
Vss
Vss
Vss
81
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
82
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
83
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
84
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
85
P83/PO3-B/
TIOCD3-B/
TMCI1-B/RxD3
P83/PO3-B/
TIOCD3-B/
TMCI1-B/RxD3
P83/PO3-B/
TIOCD3-B/
TMCI1-B/RxD3
P83/PO3-B/
TIOCD3-B/
TMCI1-B/RxD3
P83/PO3-B/
TIOCD3-B/
TMCI1-B/RxD3
NC
86
P81/PO1-B/
TIOCB3-B/
TMRI1-B/TxD3
P81/PO1-B/
TIOCB3-B/
TMRI1-B/TxD3
P81/PO1-B/
TIOCB3-B/
TMRI1-B/TxD3
P81/PO1-B/
TIOCB3-B/
TMRI1-B/TxD3
P81/PO1-B/
TIOCB3-B/
TMRI1-B/TxD3
NC
87
Vss
Vss
Vss
Vss
Vss
Vss
88
STBY
STBY
STBY
STBY
STBY
Vcc
89
PG0/CS0
PG0/CS0
PG0/CS0
PG0/CS0
PG0
NC
90
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
PG1
NC
Page 30 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
PLQP0120LA-A,
PLQP0120KA-A Mode 1
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Flash
Memory
Programmer
Mode
91
PG2/CS2/RAS2
PG2/CS2/RAS2
PG2/CS2/RAS2
PG2/CS2/RAS2
PG2
NC
92
PG3/CS3/RAS3
PG3/CS3/RAS3
PG3/CS3/RAS3
PG3/CS3/RAS3
PG3
NC
93
AVcc
AVcc
AVcc
AVcc
AVcc
Vcc
94
Vref
Vref
Vref
Vref
Vref
Vcc
95
P40/IRQ0-B/
AN0_0
P40/IRQ0-B/
AN0_0
P40/IRQ0-B/
AN0_0
P40/IRQ0-B/
AN0_0
P40/IRQ0-B/
AN0_0
NC
96
P41/IRQ1-B/
AN1_0
P41/IRQ1-B/
AN1_0
P41/IRQ1-B/
AN1_0
P41/IRQ1-B/
AN1_0
P41/IRQ1-B/
AN1_0
NC
97
P42/IRQ2-B/
AN2_0
P42/IRQ2-B/
AN2_0
P42/IRQ2-B/
AN2_0
P42/IRQ2-B/
AN2_0
P42/IRQ2-B/
AN2_0
NC
98
P43/IRQ3-B/
AN3_0
P43/IRQ3-B/
AN3_0
P43/IRQ3-B/
AN3_0
P43/IRQ3-B/
AN3_0
P43/IRQ3-B/
AN3_0
Vss
99
P44/IRQ4-B/
AN4_0
P44/IRQ4-B/
AN4_0
P44/IRQ4-B/
AN4_0
P44/IRQ4-B/
AN4_0
P44/IRQ4-B/
AN4_0
Vcc
100
P45/IRQ5-B/
AN5_0
P45/IRQ5-B/
AN5_0
P45/IRQ5-B/
AN5_0
P45/IRQ5-B/
AN5_0
P45/IRQ5-B/
AN5_0
Vss
101
P46/IRQ6-B/
AN6_0
P46/IRQ6-B/
AN6_0
P46/IRQ6-B/
AN6_0
P46/IRQ6-B/
AN6_0
P46/IRQ6-B/
AN6_0
NC
102
P47/IRQ7-B/
AN7_0
P47/IRQ7-B/
AN7_0
P47/IRQ7-B/
AN7_0
P47/IRQ7-B/
AN7_0
P47/IRQ7-B/
AN7_0
NC
103
P94/AN12_1/
DA2
P94/AN12_1/
DA2
P94/AN12_1/
DA2
P94/AN12_1/
DA2
P94/AN12_1/
DA2
NC
104
P95/AN13_1/
DA3
P95/AN13_1/
DA3
P95/AN13_1/
DA3
P95/AN13_1/
DA3
P95/AN13_1/
DA3
NC
105
AVss
AVss
AVss
AVss
AVss
Vss
106
PG4/BREQO-A/ PG4/BREQO-A/ PG4/BREQO-A/ PG4/BREQO-A/
CS4
CS4
CS4
CS4
PG4
NC
107
PG5/BACK-A
PG5/BACK-A
PG5/BACK-A
PG5/BACK-A
PG5
NC
108
PG6/BREQ-A
PG6/BREQ-A
PG6/BREQ-A
PG6/BREQ-A
PG6
NC
109
P50/BREQO-B/
IRQ0-A/PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
P50/BREQO-B/
IRQ0-A/PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
P50/BREQO-B/
IRQ0-A/PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
P50/BREQO-B/
IRQ0-A/PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
P50/IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
Vss
Mode 3, 7
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 31 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
Pin Name
Mode 3, 7
PLQP0120LA-A,
PLQP0120KA-A Mode 1
Mode 2
Mode 4
Flash
Memory
Programmer
Mode
EXPE = 1
EXPE = 0
110
P51/BREQ-B/
IRQ1-A/PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
P51/BREQ-B/
IRQ1-A/PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
P51/BREQ-B/
IRQ1-A/PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
P51/BREQ-B/
IRQ1-A/PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
P51/IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
Vss
111
P52/BACK-B/
IRQ2-A/PO4-B/
TIOCA4-B/
TMO0-B/SCK2
P52/BACK-B/
IRQ2-A/PO4-B/
TIOCA4-B/
TMO0-B/SCK2
P52/BACK-B/
IRQ2-A/PO4-B/
TIOCA4-B/
TMO0-B/SCK2
P52/BACK-B/
IRQ2-A/PO4-B/
TIOCA4-B/
TMO0-B/SCK2
P52/IRQ2-A/
PO4-B/
TIOCA4-B/
TMO0-B/SCK2
Vcc
112
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
P53/IRQ3-A/
ADTRG0-A
NC
113
P35/OE-B/
SCK1/SCL0
P35/OE-B/
SCK1/SCL0
P35/OE-B/
SCK1/SCL0
P35/OE-B/
SCK1/SCL0
P35/SCK1/
SCL0
NC
114
P34/SCK0/
SCK4-A/SDA0
P34/SCK0/
SCK4-A/SDA0
P34/SCK0/
SCK4-A/SDA0
P34/SCK0/
SCK4-A/SDA0
P34/SCK0/
SCK4-A/SDA0
NC
115
P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 NC
116
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
P32/RxD0/
IrRxD/SDA1
Vcc
117
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
NC
118
P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD
P30/TxD0/IrTxD
NC
119
MD0
MD0
MD0
MD0
MD0
Vss
120
MD1
MD1
MD1
MD1
MD1
Vss
Page 32 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
1.4.3
Section 1 Overview
Pin Functions
Table 1.5
Pin Functions
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Function
Power
supply
VCC
4, 72, 98,
99
B2, N12, E11,
E13
2, 60, 83,
84
Input
For connection to the power supply.
VCC pins should be connected to the
system power supply.
VSS
2, 10, 18,
25, 50, 70, 95,
102
A1, E2, F4, H1,
N5, M11, E10,
F11
8, 17, 22,
58, 80, 87
Input
For connection to ground. VSS pins
should be connected to the system
power supply (0 V).
PLLVCC
91
H13
76
Input
Power supply pin for the on-chip
PLL oscillator.
PLLVSS
93
G13
78
Input
Ground pin for the on-chip PLL
oscillator.
VCL
41
L3
33
Output This pin must not be connected to
the power supply and should be
connected to the VSS pin via a 0.1μF (recommended value) capacitor
(place it close to pin).
DrVCC
52
L7
43
Input
Power supply pin for the USB onchip transceiver. Pins should be
connected to the system power
supply.
DrVSS
55
M7
46
Input
Ground pin for the USB on-chip
transceiver.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 33 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Function
Clock
XTAL
96
F12
81
Input
For connection to a crystal
oscillator. See section 23, Clock
Pulse Generator, for typical
connection diagrams for a crystal
resonator and external clock input.
EXTAL
97
F13
82
Input
For connection to a crystal
oscillator. The EXTAL pin can also
input an external clock. See section
23, Clock Pulse Generator, for
typical connection diagrams for a
crystal resonator and external clock
input.
94
F10
79
Output Supplies the system clock to
external devices.
SDRAM
*1
36
M1
⎯
Output When a synchronous DRAM is
connected, this pin is connected to
the CLK pin of the synchronous
DRAM. For details, see section 6,
Bus Controller (BSC).
MD2
1
B1
1
Input
MD1
144
A2
120
These pins set the operating mode.
These pins should not be changed
during operation.
Operating
mode
control
System
control
MD0
143
A3
119
RES
92
G11
77
Input
Reset pin. When this pin is driven
low, the chip is reset.
STBY
103
D13
88
Input
When this pin is driven low, a
transition is made to hardware
standby mode.
EMLE
32
K1
30
Input
On-chip emulator enable pin. When
the on-chip emulator is used, this
pin should be fixed high. At this
time, pins P53, PG4 to PG6, and
WDTOVF are used exclusively by
the on-chip emulator. Therefore, the
corresponding pin functions of those
pins are not available. When the onchip emulator is not used, this pin
should be fixed low.
Page 34 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Address
bus
A23 to A0
31 to 26,
24 to 19,
17 to 11,
9 to 5
J3, K2, J1, K4,
H3, J2, J4, G3,
H2, G1, H4, G4,
F1, G2, F3, E4,
E1, F2, E3, D1,
D3, D2, C3, C1
29 to 23,
21 to 18,
16 to 9,
7 to 3
Output These pins output an address.
Data bus
D15 to D0
80 to 73,
71,
69 to 63
K11, K12, L13,
68 to 61,
L11, M12, L12,
59,
N13, M13, N11, 57 to 51
M11, N10, L9,
M10, N9, K10, L8
80 to 73,
71,
69 to 63
K11, K12, L13,
L11, M12, L12,
N13, M13, N11,
M10, N10, K10,
L10, M9, N9, K9
68 to 61,
59,
57 to 51
Input/ These pins output an address, and
output input or output data.
CS7 to
CS0
38 to 35,
110 to 107
M2, N2, M1, L1,
A13, A12, B13,
C12
29, 71, 70, 106,
92 to 89
Output Signals that select division areas 7
to 0 in the external address space
AS
90
G10
75
Output When this pin is low, it indicates that
address output on the address bus
is valid.
AH
90
G10
75
Output Signal for holding the address when
an address/data multiplexed I/O
space is being accessed.
RD
89
G12
74
Output When this pin is low, it indicates that
the external address space is being
read.
HWR
88
H11
73
Output Strobe signal indicating that an
external address space is to be
written to, and the upper half (D15
to D8) of the data bus is enabled.
Also functions as the write enable
signal for accessing the DRAM
space.
LWR
87
J13
72
Output Strobe signal indicating that an
external address space is to be
written to, and the lower half (D7 to
D0) of the data bus is enabled.
BREQ-A
132
D5
108
Input
BREQ-B
134
B5
110
AD15 to
Address/
AD0
data
multiplexed
bus
Bus
control
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Function
Input/ These pins constitute a bidirectional
output data bus. When an address/data
multiplexed I/O space is accessed,
an address is also output.
The external bus master requests
the bus to this LSI.
Page 35 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0120KA-A
I/O
Bus
control
BREQO-A 130
BREQO-B 133
B6
106
A6
109
Output External bus request signal when
the internal bus master accesses an
external space in the external bus
release state.
BACK-A
BACK-B
131
C7
107
135
C6
111
UCAS
85
H12
70
Output Upper column address strobe signal
for accessing the 16-bit DRAM
space. Also functions as the column
address strobe signal for accessing
the 8-bit DRAM space.
LCAS
86
H10
71
Output Lower column address strobe signal
for accessing the 16-bit DRAM
space.
DQMU*1
85
H12
⎯
Output Upper data mask enable signal for
accessing the 16-bit continuous
synchronous DRAM space. Also
functions as the data mask enable
signal for accessing the 8-bit
continuous synchronous DRAM
space.
DQML*1
86
H10
⎯
Output Lower-data mask enable signal for
accessing the 16-bit continuous
synchronous DRAM interface
space.
RAS2
109
A12
91
RAS3
110
A13
92
RAS4*2
35
L1
⎯
RAS5*2
36
M1
⎯
Output Row address strobe signal for the
DRAM when the DRAM interface is
set. Row address strobe signal
when areas 2 to 5 are set as the
continuous DRAM space.
RAS*1
109
A12
⎯
Output Row address strobe signal for the
synchronous DRAM when the
synchronous DRAM interface is set.
CAS*1
110
A13
⎯
Output Column address strobe signal for
the synchronous DRAM when the
synchronous DRAM interface is set.
WE*1
35
L1
⎯
Output Write enable signal for the
synchronous DRAM when the
synchronous DRAM interface is set.
Page 36 of 1408
PLQP0144KA-A PTLG0145JB-A
Function
Output Indicates the bus is released to the
external bus master.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
Bus
control
WAIT-A
84
J11
69
WAIT-B
56
N7
47
OE-A
38
M2
69
137
A5
113
OE-B
CKE-A*
38
M2
⎯
CKE-B*1
137
A5
⎯
NMI
40
N1
32
IRQ15-A
to
IRQ8-A*2
86, 85,
106 to 104,
83 to 81
H10, H12, C13, D12, ⎯
D10, J10, K13, J12
IRQ7-A to
IRQ0-A
31 to 28,
136 to 133
J3, K2, J1, K4, D4,
C6, B5, A6
29 to 26,
112 to 109
58 to 56
IRQ15-B
51
to
IRQ13-B*2
IRQ8-B*2
K7, L8, N7, L6
⎯
IRQ7-B to
IRQ0-B
38, 37,
61 to 59,
34, 33, 3
M2, N2, M8, N8, K8, 102 to 95
K3, L2, C2
DREQ1
82
K13, J12
35
1
Interrupts
DMA
controller
(DMAC)
EXDMA
controller
(EXDMAC)
*2
PLQP0120KA-A
I/O
Function
Input
Requests insertion of a wait state in
the bus cycles when accessing an
external 3-state address space.
Output Output enable signal when
accessing the DRAM space.
Output Clock enable signal when the
synchronous DRAM interface is set.
Input
Nonmaskable interrupt request pin.
This pin should be fixed high when
not used.
These pins request a maskable
interrupt.
The input pins of IRQn-A and IRQnB are selected by the IRQ pin select
register (ITSR) of the interrupt
controller.
(n = 0 to 15, m=0 to 8, 13 to 15 for
the H8S/2456R Group and
H8S/2456)
(n = 0 to 7 for the H8S/2454 Group)
Input
These signals request DMAC
activation.
DREQ0
81
TEND1
104
D10
37
TEND0
83
J10
36
DACK1
106
C13
39
DACK0
105
D12
38
EDREQ3
33
L2
⎯
Input
EDREQ2
3
C2
ETEND3
59
K8
⎯
ETEND2
34
K3
Output These signals indicate the end of
EXDMAC data transfer.
EDACK3
61
M8
⎯
EDACK2
60
N8
Output EXDMAC single address transfer
acknowledge signals.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
34
Output These signals indicate the end of
DMAC data transfer.
Output DMAC single address transfer
acknowledge signals.
These signals request EXDMAC
activation.
Page 37 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
EXDMA
controller
(EXDMAC)
*2
EDRAK3
49
L5
⎯
EDRAK2
48
K6
Output These signals notify an external
device of acceptance and start of
execution of a DMA transfer
request.
16-bit timer TCLKH
pulse
TCLKG
unit (TPU)
TCLKF
22
H2
20
Input
20
H4
18
17
F1
15
TCLKE
16
G2
14
TCLKD
49
L5
41
TCLKC
47
K5
39
TCLKB
45
M5
37
TCLKA
44
L4
36
TIOCA0
42
N3
34
TIOCB0
43
M4
35
TIOCC0
44
L4
36
TIOCD0
45
M5
37
TIOCA1
46
N4
38
TIOCB1
47
K5
39
TIOCA2
48
K6
40
TIOCB2
49
L5
41
TIOCA3-A
51
L6
42
TIOCA3-B
133
A6
109
TIOCB3-B
33
L2
86
TIOCC3-B
134
B5
110
TIOCD3-B
59
K8
85
Page 38 of 1408
Function
External clock input pins of the
timer.
Input/ TGRA_0 to TGRD_0 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_1 and TGRB_1 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_2 and TGRB_2 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_3 to TGRD_3 input capture
output input/output compare output/PWM
output pins.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
16-bit timer TIOCB4-A
pulse
TIOCA4-B
unit (TPU)
TIOCB4-B
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
56
N7
47
135
C6
111
Input/ TGRA_4 and TGRB_4 input capture
output input/output compare output/PWM
output pins.
61
M8
50
TIOCA5
57
L8
48
TIOCB5
58
K7
49
TIOCA6
14
E4
12
TIOCB6
15
F3
13
TIOCC6
16
G2
14
TIOCD6
17
F1
15
TIOCA7
19
G4
16
TIOCB7
20
H4
18
TIOCA8
21
G1
19
TIOCB8
22
H2
20
TIOCA9
5
C1
3
TIOCB9
6
C3
4
TIOCC9
7
D2
5
TIOCD9
8
D3
6
TIOCA10
9
D1
7
TIOCB10
11
E3
9
TIOCA11
12
F2
10
TIOCB11
13
E1
11
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Function
Input/ TGRA_5 and TGRB_5 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_6 to TGRD_6 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_7 and TGRB_7 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_8 and TGRB_8 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_9 to TGRD_9 input capture
output input/output compare output/PWM
output pins.
Input/ TGRA_10 and TGRB_10 input
output capture input/output compare
output/PWM output pins.
Input/ TGRA_11 and TGRB_11 input
output capture input/output compare
output/PWM output pins.
Page 39 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Programmable
pulse
generator
(PPG)
PO15 to
PO8
49 to 42
L5, K6, K5, N4,
M5, L4, M4, N3
41 to 34
Output Pulse output pins.
PO7
58
K7
49
PO6
57
L8
48
PO5-A
56
N7
47
PO0-A
51
L6
42
PO5-B
61
M8
50
PO4-B
135
C6
111
PO3-B
59
K8
85
PO2-B
134
B5
110
PO1-B
33
L2
86
8-bit timer
(TMR)
PO0-B
133
A6
109
TMO0-A*2
105
D12
46
TMO1-A
106
C13
47
TMO0-B
135
C6
111
TMO1-B
61
M8
50
TMCI0-A*2
83
J10
44
TMCI1-A*
104
D10
45
TMCI0-B
134
B5
110
2
Watchdog
timer
(WDT)
TMCI1-B
59
K8
85
TMRI0-A
81
J12
42
TMRI1-A*2
82
K13
43
TMRI0-B
133
A6
109
TMRI1-B
33
L2
86
WDTOVF
39
M3
31
Page 40 of 1408
Function
Output Waveform output pins with output
compare function.
Input
External event input pins.
Input
Counter reset input pins.
Output Counter overflow signal output pin
in watchdog timer mode.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Serial
communication
interface
(SCI)/
Smart Card
interface
(SCI_0
with IrDA
function)
TxD4-B
24
J4
23
Output Data output pins.
TxD3
33
L2
86
TxD2
133
A6
109
TxD1
141
B3
117
TxD0/
IrTxD
142
C4
118
RxD4-B
26
J2
24
RxD3
59
K8
85
RxD2
134
B5
110
RxD1
139
C5
115
RxD0/
IrRxD
140
A4
116
SCK4-A
138
B4
114
SCK4-B
27
H3
25
SCK3
61
M8
50
SCK2
135
C6
111
SCK1
137
A5
113
SCK0
138
B4
114
SCL3
134
B5
110
SCL2
58
K7
49
SCL1
139
C5
115
I2C bus
interface 2
(IIC2)
SCL0
137
A5
113
SDA3
133
A6
109
SDA2
57
L8
48
SDA1
140
A4
116
SDA0
138
B4
114
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Input
Function
Data input pins.
Input/ Clock input/output pins.
output
Input/ I2C clock input/output pins.
output
Input/ I2C data input/output pins.
output
Page 41 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Synchronous serial
communication
unit (SSU)
SSO0-A
46
N4
38
SSO0-B
31
J3
29
Input/ Data input/output pins.
output
SSO0-C
87
J13
72
SSI0-A
47
K5
39
SSI0-B
30
K2
28
SSI0-C
86
H10
71
SSCK0-A
48
K6
40
SSCK0-B
29
J1
27
SSCK0-C
85
H12
70
SCS0-A
49
L5
41
SCS0-B
28
K4
26
SCS0-C
84
J11
69
USD+
53
M6
44
USD-
54
N6
45
VBUS
56
N7
47
Input
Universal
serial
interface
(USB)
PUPD+
A/D
converter
D/A
converter
Function
Input/ Data input/output pins.
output
Input/ Clock input/output pins.
output
Input/ Chip select input/output pins.
output
Input/ USB data input/output pin.
output
USB cable
connection/disconnection detection
pin.
51
L6
42
output PULLUP control pin for D+signal.
2
AN15_1*
128
D6
⎯
Input
Analog input pins.
AN14_1*2
127
D7
AN13_1
126
D8
104
Input
Analog input pins.
AN12_1
125
A8
103
AN11_1 to 124 to 121
AN8_1*2
B7, C8, D9, A9
⎯
Input
Analog input pins.
AN7_0 to
AN0_0
120 to 113
B8, C9, B9, A10, 102 to 95
C10, B10, C11,
A11
Input
Analog input pins.
ADTRG0-A
136
D4
112
Input
ADTRG0-B
84
J11
69
Pin for input of an external trigger to
start A/D conversion.
ADTRG1
57
L8
48
DA3
126
D8
104
DA2
125
A8
103
Page 42 of 1408
Output Analog output pins.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Function
A/D
converter,
D/A
converter
AVCC
111
B11
93
Input
Analog power-supply pin for the A/D
converter and D/A converter. When
the A/D converter and D/A converter
are not used, this pin should be
connected to the system power
supply (VCC).
AVSS
129
A7
105
Input
Ground pin for the A/D converter
and D/A converter. This pin should
be connected to the system power
supply (VSS).
Vref
112
B12
94
Input
Reference voltage input pin for the
A/D converter and D/A converter.
When the A/D converter and D/A
converter are not used, this pin
should be connected to the system
power supply (VCC).
P17 to
P10
49 to 42
L5, K6, K5, N4,
M5, L4, M4, N3
41 to 34
Input/ 8-bit input/output pins.
output
P27 to P25 58 to 56
P20
51
K7, L8, N7, L6
49 to 47
42
Input/ 4-bit input/output pins.
output
P35 to
P30
137 to 142
A5, B4, C5, A4,
B3, C4
113 to 118
Input/ 6-bit input/output pins.
output
P47 to
P40
120 to 113
B8, C9, B9, A10, 102 to 95
C10, B10, C11,
A11
Input
P53 to
P50
136 to 133
D4, C6, B5, A6
112 to 109
Input/ 4-bit input/output pins.
output
P65 to
P60
106 to 104,
83 to 81
C13, D12, D10,
J10, K13, J12
⎯
Input/ 6-bit input/output pins.
output
P85
61
M8
50
P84*
60
N8
⎯
Input/ 6-bit input/output pins in the
output H8S/2456 Group and H8S/2456R
Group.
P83
59
K8
85
P82*
34
K3
⎯
P81
33
L2
86
P80*2
3
C2
⎯
I/O ports
2
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
8-bit input pins.
3-bit input/output pins in the
H8S/2454 Group.
Page 43 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 1 Overview
Pin No.
H8S/2454
H8S/2456, H8S/2456R
PLQP0120LA-A,
Type
I/O ports
Symbol
PLQP0144KA-A PTLG0145JB-A
PLQP0120KA-A
I/O
Function
P97* ,
P96*2
128 , 127
D6, D7
⎯
Input
P95, P94,
126, 125
D8, A8
104, 103
8-bit input/output pins in the
H8S/2456 Group and H8S/2456R
Group.
P93 to
P90*2
124 to 121
B7, C8, D9, A9
⎯
PA7 to
PA0
31 to 26,
24, 23
J3, K2, J1, K4,
H3, J2, J4, G3
29 to 23,
21
Input/ 8-bit input/output pins.
output
PB7 to
PB0
22 to 19,
17 to 14
H2, G1, H4, G4,
F1, G2, F3, E4
20 to 18,
16 to 12
Input/ 8-bit input/output pins.
output
PC7 to
PC0
13 to 11,
9 to 5
E1, F2, E3, D1,
D3, D2, C3, C1
11 to 9,
7 to 3
Input/ 8-bit input/output pins.
output
PD7 to
PD0
80 to 73
K11, K12, L13,
L11, M12, L12,
N13, M13
68 to 61
Input/ 8-bit input/output pins.
output
PE7 to
PE0
71,
69 to 63
N11, M10, N10,
K10, L10, M9,
N9, K9
59,
57 to 51
Input/ 8-bit input/output pins.
output
PF7 to
PF0
94,
90 to 84
F10, G10, G12,
H11, J13, H10,
H12, J11
79,
75 to 69
Input/ 8-bit input/output pins.
output
PG6 to
PG0
132 to 130,
110 to 107
D5, C7, B6, A13, 108 to 106,
A12, B13, C12
92 to 89
PH3 to
PH0*2
38 to 35
M2, N2, M1, L1
⎯
Input/ 4-bit input/output pins.
output
PJ2*2
⎯
Input
2
62
L9
2
PJ1*
101
E12
PJ0*2
100
D11
2-bit input/output pins in the
H8S/2454 Group.
Input/ 7-bit input/output pins.
output
3-bit input pins.
Notes: 1. Not supported by the H8S/2456 Group and H8S/2454 Group.
2. Not supported by the H8S/2454 Group.
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Section 2 CPU
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, see section 3, MCU Operating Modes.
2.1
Features
• Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H CPUs object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-nine basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Multiply-and-accumulate instruction
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
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Section 2 CPU
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• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 2 states
16 ÷ 8-bit register-register divide: 12 states
16 × 16-bit register-register multiply: 3 states
32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
Normal mode*
Advanced mode
Note: * Normal mode is not available in this LSI.
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
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Section 2 CPU
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
2*
12
MULXU.W Rs, ERd
2*
20
MULXS.B Rs, Rd
3*
13
MULXS.W Rs, ERd
3*
21
CLRMAC
CLRMAC
1*
Not supported
LDMAC
LDMAC ERs, MACH
1*
LDMAC ERs, MACL
1*
STMAC
STMAC MACH, ERd
1*
STMAC MACL, ERd
1*
MULXS
Note:
2.1.2
*
The number of execution states is incremented following a MAC instruction.
In addition, there are differences in address space, CCR and EXR register functions,
power-down modes, etc., depending on the model.
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-and-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
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• Higher speed
Basic instructions execute twice as fast.
Note: Normal mode is not available in this LSI.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
• Additional control register
One 8-bit and two 32-bit control registers have been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
A multiply-and-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
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2.2
Section 2 CPU
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When En is used as a 16-bit register it can contain any value, even when the corresponding
general register (Rn) is used as an address register. If the general register is referenced in the
register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a
carry or borrow occurs, however, the value in the corresponding extended register (En) will be
affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack
in interrupt control mode 0. For details, see section 4, Exception Handling.
Note: Normal mode is not available in this LSI.
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H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
EXR*1
SP
Reserved*1 *3
(SP*2
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
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2.2.2
Section 2 CPU
Advanced Mode
• Address Space
Linear access is provided to a 16-Mbyte maximum address space.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode the top area starting at H'00000000 is allocated to the exception vector table
in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in
the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception
Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
(Reserved for system use)
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address.
In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch
address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch
addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of
this range is also used for the exception vector table.
• Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.
EXR*1
SP
SP
Reserved*1 *3
Reserved
PC
(24 bits)
(SP*2
)
(a) Subroutine Branch
CCR
PC
(24 bits)
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.4 Stack Structure in Advanced Mode
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2.3
Section 2 CPU
Address Space
Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, see section 3, MCU Operating
Modes.
H'0000
H'00000000
64 kbytes
16 Mbytes
H'FFFF
Program area
H'00FFFFFF
Data area
Cannnot be
used in this LSI
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Note: * Normal mode cannot be used in this LSI.
Figure 2.5 Memory Map
Note:
Normal mode is not available in this LSI.
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2.4
Registers
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiplyaccumulate register (MAC).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
0
23
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
63
41
32
MACH
Sign extension
MAC
MACL
31
0
[Legend]
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*
H:
U:
N:
Z:
V:
C:
MAC:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register
Note: * UI cannot be used as an interrupt mask bit in this LSI.
Figure 2.6 CPU Registers
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2.4.1
Section 2 CPU
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
The usage of each register can be selected independently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
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Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3
Extended Register (EXR)
EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all interrupts
including NMI will be masked for three states after execution is completed.
Bit
Bit Name
Initial Value
R/W
Description
7
T
0
R/W
Trace Bit
When this bit is set to 1, a trace exception is
started each time an instruction is executed.
When this bit is cleared to 0, instructions are
executed in sequence.
6 to 3
⎯
All 1
⎯
Reserved
These bits are always read as 1.
2
I2
1
R/W
1
I1
1
R/W
0
I0
1
R/W
Page 56 of 1408
These bits designate the interrupt mask level (0
to 7). For details, see section 5, Interrupt
Controller.
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2.4.4
Section 2 CPU
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
Initial Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1.
NMI is accepted regardless of the I bit setting.
The I bit is set to 1 by hardware at the start of an
exception-handling sequence. For details, see
section 5, Interrupt Controller.
6
UI
Undefined
R/W
User Bit or Interrupt Mask Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC
instructions. This bit cannot be used as an
interrupt mask bit in this LSI.
5
H
Undefined
R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit
3, and cleared to 0 otherwise. When the ADD.W,
SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry
or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
4
U
Undefined
R/W
User Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC
instructions.
3
N
Undefined
R/W
Negative Flag
Stores the value of the most significant bit of
data as a sign bit.
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Bit
Bit Name
Initial Value
R/W
Description
2
Z
Undefined
R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined
R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
0
C
Undefined
R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a
carry
The carry flag is also used as a bit accumulator
by bit manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.6
Initial Values of CPU Internal Registers
When the reset exception handling loads the start address from the vector address, PC is
initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However,
the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is
undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a
reset.
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2.5
Section 2 CPU
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
Register Number
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Lower
0
Don't care
MSB
LSB
Figure 2.9 General Register Data Formats (1)
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Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
LSB
Legend:
ERn
En
Rn
RnH
RnL
MSB
LSB
: General register ER
: General register E
: General register R
: General register RH
: General register RL
: Most significant bit
: Least significant bit
Figure 2.9 General Register Data Formats (2)
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2.5.2
Section 2 CPU
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
LSB
Figure 2.10 Memory Data Formats
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2.6
Instruction Set
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
POP*1, PUSH*1
B/W/L
5
Arithmetic
operations
W/L
LDM, STM
MOVFPE*3, MOVTPE*3
L
ADD, SUB, CMP, NEG
B/W/L
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
B
23
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS*
B
MAC, LDMAC, STMAC, CLRMAC
⎯
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
B
14
Branch
Bcc*2, JMP, BSR, JSR, RTS
⎯
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
⎯
9
⎯
1
Total:
69
4
Block data transfer EEPMOV
[Legend]
B:
Byte
W:
Word
L:
Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
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2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
MAC
Multiply-accumulate register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
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Symbol
Description
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4
Section 2 CPU
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in two
general registers, or on immediate data and data in a general register.
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers:
either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or
32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4
Arithmetic Operations Instructions (2)
Instruction
Size*1
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers:
either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or
32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2
B
@ERd – 0, 1 → ( of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC
⎯
(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC
⎯
0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
L
Rs → MAC, MAC → Rd
Transfers data between a general register and a multiply-accumulate
register.
STMAC
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Table 2.5
Section 2 CPU
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → ( of )
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → ( of )
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
~ ( of ) → ( of )
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
~ ( of ) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ ( of ) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ [~ ( of )] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ ( of ) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ [~ ( of )] → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B: Byte
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Table 2.7
Section 2 CPU
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ ( of ) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ [~ ( of )] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BLD
B
( of ) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
~ ( of ) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → ( of )
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
~ C → ( of )
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B: Byte
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Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc
⎯
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
(high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
⎯
Branches unconditionally to a specified address.
BSR
⎯
Branches to a subroutine at a specified address.
JSR
⎯
Branches to a subroutine at a specified address.
RTS
⎯
Returns from a subroutine.
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Table 2.9
Section 2 CPU
System Control Instructions
Instruction
Size*
Function
TRAPA
⎯
Starts trap-instruction exception handling.
RTE
⎯
Returns from an exception-handling routine.
SLEEP
⎯
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the contents of a general register or memory, or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
NOP
⎯
PC + 2 → PC
Only increments the program counter.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
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Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
⎯
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
⎯
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2
Basic Instruction Formats
The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
•
Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
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(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
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2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address
modes are different in each instruction.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
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Section 2 CPU
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction code, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register indirect with post-increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For word or longword transfer instruction, the register value should
be even.
Register indirect with pre-decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For word or longword transfer instruction, the register value should be even.
2.7.5
Absolute Address—@aa:8/@aa:16/@aa:24/@aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
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Table 2.12 Absolute Address Access Ranges
Normal Mode*
Absolute Address
Data address
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
Note:
2.7.6
*
Advanced Mode
H'000000 to H'FFFFFF
24 bits (@aa:24)
Not available in this LSI.
Immediate—#xx:8/#xx:16/#xx:32
The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch
address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to
be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is −126 to +128 bytes (–63 to +64 words) or
−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting
value should be an even number.
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2.7.8
Section 2 CPU
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode the memory operand is a longword operand, the first byte of which is assumed to
be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For
further details, see section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
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2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: Normal mode is not available in this LSI.
Table 2.13 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct (Rn)
rm
Operand is general register contents.
rn
Register indirect (@ERn)
31
0
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
31
0
General register contents
op
r
31
disp
31
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
disp
31
0
31
24 23
0
Don't care
General register contents
r
• Register indirect with pre-decrement @-ERn
0
0
Sign extension
4
24 23
Don't care
1, 2, or 4
31
0
General register contents
31
24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
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1
2
4
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Table 2.13 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
23
Program-counter relative
0
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
0
23
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
31
op
abs
0
8 7
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
8 7
31
op
abs
H'000000
31
0
abs
0
31
24 23
Don't care
0
Memory contents
Note: * Normal mode is not available in this LSI.
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Page 79 of 1408
Section 2 CPU
2.8
H8S/2456, H8S/2456R, H8S/2454 Group
Processing States
The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset State
The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes
low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the RES signal changes from low to
high. For details, see section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, see section 4, Exception Handling.
• Program Execution State
In this state the CPU executes program instructions in sequence.
• Bus-Released State
In a product which has a bus master other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, see section 24, Power-Down Modes.
Page 80 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 2 CPU
End of bus request
Bus request
pt
ion
ha
ex
nd
ce
lin
pt
g
io n
ha
nd
lin
g
ce
En
d
or
ex
st
f
of
ue
d
En
Re
q
Exception
handling state
n
Bus-released state
Sleep mode
t
ues
q
t re
rrup
Inte
=0
BY
SS EEP tion
SL truc
ins
io
= 1 ruct
BY nst
SS EP i
E
SL
of
bu
s
re
Bu
qu
sr
es
eq
t
ue
st
Program execution state
External interrupt request
Software standby
mode
RES = High
Reset state*1
STBY = High,
RES = Low
Reset state
Hardware standby
mode*2
Power down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 24, Power-Down Modes.
Figure 2.13 State Transitions
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 81 of 1408
Section 2 CPU
2.9
Usage Note
2.9.1
Usage Notes on Bit-wise Operation Instructions
H8S/2456, H8S/2456R, H8S/2454 Group
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate
the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,
special care is necessary to use these instructions for the registers and the ports that include writeonly bit.
The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.
Page 82 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
The H8S/2456 Group, H8S/2454 Group, and H8S/2456R Group have five operating modes
(modes 1 to 4 and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0).
Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external
memory and peripheral devices. In an externally expanded mode, the external address space can
be designated as an 8-bit or 16-bit address space for each area by the bus controller at the
beginning of program execution. If a 16-bit address space is designated for any one area, the 16bit bus mode is selected. If an 8-bit address space is designated for all areas, the 8-bit bus mode is
selected.
Mode 7 is a single-chip activation expanded mode in which the CPU can switch to access an
external memory and peripheral devices at the beginning of program execution.
Mode 3 is a boot mode in which the flash memory can be programmed or erased. For details on
the boot mode, refer to section 22, Flash Memory.
The settings for pins MD2 to MD0 should not be changed during LSI operation.
Table 3.1
MCU Operating Modes
MCU
Operating
Mode
MD2
MD1
MD0
CPU
Operating
Mode
1*
0
0
1
Advanced
2*
0
1
0
Advanced
External Data Bus
On-Chip
ROM
Initial
Value
Max.
Value
Expanded mode with
on-chip ROM disabled
Disabled
16 bits
16 bits
Expanded mode with
on-chip ROM disabled
Disabled
8 bits
16 bits
Description
3
0
1
1
Advanced
Boot mode
Enabled
⎯
16 bits
4
1
0
0
Advanced
Expanded mode with
on-chip ROM enabled
Enabled
8 bits
16 bits
7
1
1
1
Advanced
Single-chip mode
Enabled
⎯
16 bits
Note:
*
Only modes 1 and 2 may be used in ROM-less versions.
R01UH0309EJ0500 Rev. 5.00
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Page 83 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to operating mode setting.
•
•
Mode control register (MDCR)
System control register (SYSCR)
3.2.1
Mode Control Register (MDCR)
MDCR monitors the current operating mode of this LSI.
Bit
Bit Name
Initial Value
R/W
Descriptions
7 to 3
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
2
MDS2
⎯*
R
Mode Select 2 to 0
1
MDS1
⎯*
R
0
MDS0
⎯*
R
These bits indicate the input levels at mode pins
MD2 to MD0 (the current operating mode). Bits
MDS2 to MDS0 correspond to pins MD2 to MD0,
respectively. These bits are read-only bits and so
they cannot be modified. The input levels of the
MD2 to MD0 pins are latched into these bits when
MDCR is read. These latches are canceled by a
reset.
Note:
*
Determined by the settings of pins MD2 to MD0.
Page 84 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
3.2.2
Section 3 MCU Operating Modes
System Control Register (SYSCR)
SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash
memory control registers, sets the external bus mode, and enables or disables on-chip RAM.
Bit
Bit Name
Initial Value
R/W
Descriptions
7, 6
⎯
All 1
R/W
Reserved
5
MACS
0
R/W
MAC Saturation Operation Control
The initial value should not be modified.
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction performs non-saturation operation
1: MAC instruction performs saturation operation
4
⎯
0
R/W
Reserved
3
FLSHE
0
R/W
Flash Memory Control Register Enable
The initial value should not be modified.
Controls CPU access to the flash memory control
registers (FLMCR1, FLMDBPR, and FLMSTR). If this
bit is set to 1, the flash memory control registers can
be read from and written to. If this bit is cleared to 0,
the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are retained. 0 should be written to this bit in
LSIs other than the flash memory version.
0: Flash memory control registers are not selected for
addresses H'FFFEB0 to H'FFFEB3
1: Flash memory control registers are selected for
addresses H'FFFEB0 to H'FFFEB3
2
⎯
0
⎯
Reserved
This bit is always read as 0 and cannot be modified.
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Section 3 MCU Operating Modes
Bit
Bit Name
Initial Value
R/W
Descriptions
1
EXPE
⎯
R/W
External Bus Mode Enable
Sets the external bus mode. In modes 1, 2, and 4,
this bit is fixed at 1 and cannot be modified. In modes
3 and 7, this bit can be read from and written to.
Writing 0 to this bit when its value is 1 should only be
carried out when an external bus cycle is not being
executed.
0: External address space is disabled
1: External address space is enabled
0
RAME
1
R/W
RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is canceled.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Page 86 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
3.3
Operating Mode Descriptions
3.3.1
Mode 1
Section 3 MCU Operating Modes
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H function as bus control signals.
The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. However,
if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits.
3.3.2
Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H function as bus control signals.
The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if
16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to
16 bits and port E functions as a data bus.
3.3.3
Mode 3
This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the
programming and erasure of the flash memory. Mode 3 is only available in the flash memory
version.
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Section 3 MCU Operating Modes
3.3.4
H8S/2456, H8S/2456R, H8S/2454 Group
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.
Ports A to C function as input ports immediately after a reset, but can be set to function as an
address bus depending on each port register setting. Port D functions as a data bus and parts of
ports F to H function as bus control signals. For details on function switching of ports A to C, see
section 10, I/O Ports.
The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if
16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to
16 bits and port E functions as a data bus.
In the flash memory version, user program mode is entered by clearing the CBIDB bit to 0 and
setting the FMCMDEN bit to 1 in FLMCR1.
3.3.5
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the LSI starts up in single-chip mode. External address spaces cannot be used in single-chip
mode.
The initial mode immediately after a reset is single-chip mode, with all I/O ports available for use
as input/output ports. However, setting the EXPE bit in SYSCR to 1 switches the mode to an
externally expanded mode in which the external address spaces are enabled. When an externally
expanded mode is selected, all areas are initially designated as a 16-bit access space. The functions
of pins in ports A to H are the same as those in an externally expanded mode with on-chip ROM
enabled.
In the flash memory version, user program mode is entered by clearing the CBIDB bit to 0 and
setting the FMCMDEN bit to 1 in FLMCR1.
Page 88 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
3.3.6
Section 3 MCU Operating Modes
Pin Functions
Table 3.2 shows the pin functions in each operating mode.
Table 3.2
Pin Functions in Each Operating Mode
Port
Mode 1
Mode 2
Mode 3
Mode 4
Mode 7
Port A
PA7 to PA5
P*/A
P*/A
P*/A
P*/A
P*/A
PA4 to PA0
A
A
Port B
A
A
P*/A
P*/A
P*/A
Port C
A
A
P*/A
P*/A
P*/A
Port D
D
D
P*/D
D
P*/D
Port E
P/D*
P*/D
P*/D
P*/D
P*/D
PF7, PF6
P/C*
P/C*
P*/C
P/C*
P*/C
PF5, PF4
C
C
C
PF3
P/C*
P/C*
P/C*
PF2 to PF0
P*/C
P*/C
P*/C
PG6 to PG1
P*/C
P*/C
PG0
P/C*
P/C*
PH3, PH2
P*/C
Port F
Port G
Port H
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
PH1 (H8S/2456R Group) P/C*
P/C*
P/C*
P/C*
P/C*
PH1 (H8S/2456 Group)
P*/C
P*/C
P*/C
P*/C
P*/C
PH0
P*/C
P*/C
P*/C
P*/C
P*/C
[Legend]
P:
I/O port
A:
Address bus output
D:
Data bus input/output
C:
Control signals, clock input/output
*:
Immediately after a reset
Note: Port H is not supported in the H8S/2454 Group.
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Page 89 of 1408
Section 3 MCU Operating Modes
3.4
H8S/2456, H8S/2456R, H8S/2454 Group
Memory Map in Each Operating Mode
Figures 3.1 to 3.5 show memory maps in each operating mode.
Page 90 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
RAM: 64 Kbytes/48 Kbytes
ROM: 256 Kbytes
RAM: 64 Kbytes/48 Kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
Mode 3
(Boot mode)
H'000000
H'000000
On-chip ROM
H'040000
Reserved area*4
H'080000
External address
space
External address space/
Reserved area*2*4
H'F00000
Data flash area 8 Kbytes
H'F02000
External address space/
Reserved area*2*4
H'FE8000
H'FEC000
H'FF0000
H'FFC000
H'FFD000
H'FE8000
Reserved area*4
Reserved area*4
On-chip RAM/External address space/
Reserved area*1*5
On-chip RAM/External address space*1
Reserved
area*4
External address space
H'FEC000
H'FF0000
On-chip RAM*3
H'FFC000
H'FFD000
H'FFFA00
H'FFFA00
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Notes: 1.
2.
3.
4.
5.
Internal I/O registers
Reserved area*4
External address space/
Reserved area*2*4
Internal I/O registers
Internal I/O registers
H'FFFF00
On-chip RAM/Reserved area*3*5
H'FFFF20
H'FFFFFF
External address space/
Reserved area*2*4
Internal I/O registers
This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
A reserved area should not be accessed.
Area from H'FEC000 to H'FEFFFF in the H8S/24568, H8S/24568R, and H8S/24548 Groups is reserved and
should not be accessed.
Figure 3.1 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version):
H8S/24569, H8S/24569R, H8S/24568, H8S/24568R, H8S/24549, and H8S/24548
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 91 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
ROM: 256 Kbytes
RAM: 64 Kbytes / 48 Kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
ROM: 256 Kbytes
RAM: 64 Kbytes / 48 Kbytes
Mode 7
(Single-chip activation expanded mode
with on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
On-chip ROM
H'040000
H'040000
Reserved area*4
Reserved area*4
H'080000
H'080000
External address space/
Reserved area*2*4
External address
space
H'F00000
H'F00000
Data flash area 8 Kbytes
Data flash area 8 Kbytes
H'F02000
H'F02000
External address space/
Reserved area*2*4
External address space
H'FE8000
H'FE8000
Reserved area*4
H'FEC000
H'FF0000
H'FFC000
H'FFD000
On-chip RAM/External address space/
Reserved area*1*5
On-chip RAM/
External address space*1
Reserved
area*4
Reserved area*4
H'FEC000
H'FF0000
H'FFC000
H'FFD000
External address space
H'FFFA00
H'FFFF00
H'FFFA00
H'FFFF00
External address space
H'FFFFFF
H'FFFF20
Internal I/O registers
On-chip RAM/
External address space*3
Reserved area*4
External address space/
Reserved area*2*4
Internal I/O registers
Internal I/O registers
H'FFFF20
On-chip RAM/External address space/
Reserved area*3*5
H'FFFFFF
External address space/
Reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area
when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area.
4. A reserved area should not be accessed.
5. Area from H'FEC000 to H'FEFFFF in the H8S/24568, H8S/24568R, and H8S/24548 Groups is reserved and
should not be accessed.
Figure 3.2 Memory Map in Each Operating Mode (ROM: 256-Kbyte Version):
H8S/24569, H8S/24569R, H8S/24568, H8S/24568R, H8S/24549, and H8S/24548
Page 92 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
RAM: 48 Kbytes
ROM: 128 Kbytes
RAM: 48 Kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
Mode 3
(Boot mode)
H'000000
On-chip ROM
H'020000
Reserved area*4
H'080000
External address
space
External address space/
Reserved area*2*4
H'F00000
Data flash area 8 Kbytes
H'F02000
External address space/
Reserved area*2*4
H'FE8000
H'FE8000
Reserved area*4
Reserved area*4
H'FF0000
H'FF0000
On-chip RAM/
External address space*1
H'FFC000
H'FFD000
Reserved area*4
External address space
On-chip RAM*3
H'FFC000
H'FFD000
H'FFFA00
H'FFFA00
Internal I/O registers
Internal I/O registers
H'FFFF00
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Notes: 1.
2.
3.
4.
Internal I/O registers
Reserved area*4
External address space/
Reserved area*2*4
H'FFFF20
H'FFFFFF
External address space/
Reserved area*2*4
Internal I/O registers
This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
A reserved area should not be accessed.
Figure 3.3 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version):
H8S/24565, H8S/24565R, and H8S/24545
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 93 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
ROM: 128 Kbytes
RAM: 48 Kbytes
Mode 4
(Expanded mode with
on-chip ROM enabled)
ROM: 128 Kbytes
RAM: 48 Kbytes
Mode 7
(Single-chip activation expanded mode
with on-chip ROM enabled)
H'000000
H'000000
On-chip ROM
H'020000
On-chip ROM
H'020000
Reserved area*4
Reserved area*4
H'080000
H'080000
External address space/
Reserved area*2*4
External address
space
H'F00000
H'F00000
Data flash area 8 Kbytes
Data flash area 8 Kbytes
H'F02000
H'F02000
External address space/
Reserved area*2*4
External address space
H'FE8000
H'FE8000
Reserved area*4
H'FF0000
Reserved area*4
H'FF0000
On-chip RAM/
External address space*1
H'FFC000
H'FFD000
Reserved area*4
On-chip RAM/
External address space*3
H'FFC000
H'FFD000
External address space
H'FFFA00
H'FFFF00
H'FFFA00
Internal I/O registers
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
H'FFFF20
Internal I/O registers
H'FFFFFF
Reserved area*4
External address space/
Reserved area*2*4
Internal I/O registers
External address space/
Reserved area*2*4
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0.
3. While EXPE = 1, this area is specified as the external address space when RAME = 0 and the on-chip RAM area
when RAME = 1. While EXPE = 0, this area is specified as the on-chip RAM area.
4. A reserved area should not be accessed.
Figure 3.4 Memory Map in Each Operating Mode (ROM: 128-Kbyte Version):
H8S/24565, H8S/24565R, and H8S/24545
Page 94 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 3 MCU Operating Modes
RAM: 64 Kbytes /48 Kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
H'000000
External address
space
H'FE8000
H'FEC000
H'FF0000
H'FFC000
H'FFD000
Reserved area*2
On-chip RAM/External address space/
Reserved area*1*3
On-chip RAM/External address space*1*3
Reserved area*2
External address space
H'FFFA00
Internal I/O registers
H'FFFF00
External address space
H'FFFF20
H'FFFFFF
Internal I/O registers
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. A reserved area should not be accessed.
3. Area from H'FEC000 to H'FEFFFF in the H8S/24561, H8S/24561R, and H8S/24541 Groups is
reserved and should not be accessed.
Figure 3.5 Memory Map in Each Operating Mode (ROM-Less Version):
H8S/24562, H8S/24562R, H8S/24561, H8S/24561R, H8S/24542, and H8S/24541
R01UH0309EJ0500 Rev. 5.00
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Page 95 of 1408
Section 3 MCU Operating Modes
Page 96 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 4 Exception Handling
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal
instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or
more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU
enters the reset state when the RES pin is low.
Illegal instruction
Starts when execution of an illegal instruction code is
detected.
Trace*1
Starts when execution of the currently executed instruction
or exception handling ends, if the trace (T) bit in the EXR is
set to 1.
Direct transition*2
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Interrupt
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued.*3
Trap instruction*4
Started by execution of a trap instruction (TRAPA)
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
4. Trap instruction exception handling requests are accepted at all times in program
execution state.
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Section 4 Exception Handling
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Table 4.2
Exception Handling Vector Table
Vector Address*1
Exception Source
Vector Number
Normal Mode*2
Advanced Mode
Power-on reset
Manual reset*3
0
H'0000 to H'0001
H'0000 to H'0003
1
H'0002 to H'0003
H'0004 to H'0007
Reserved for system use
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
Illegal instruction
4
H'0008 to H'0019
H'0010 to H'0013
Trace
5
H'000A to H'000B
H'0014 to H'0017
Interrupt (direct transition)*3
6
H'000C to H'000D
H'0018 to H'001B
Interrupt (NMI)
7
H'000E to H'000F
H'001C to H'001F
Trap instruction (#0)
8
H'0010 to H'0011
H'0020 to H'0023
(#1)
9
H'0012 to H'0013
H'0024 to H'0027
(#2)
10
H'0014 to H'0015
H'0028 to H'002B
(#3)
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
13
H'001A to H'001B
H'0034 to H'0037
14
H'001C to H'001D
H'0038 to H'003B
15
H'001E to H'001F
H'003C to H'003F
IRQ0
16
H'0020 to H'0021
H'0040 to H'0043
IRQ1
17
H'0022 to H'0023
H'0044 to H'0047
IRQ2
18
H'0024 to H'0025
H'0048 to H'004B
IRQ3
19
H'0026 to H'0027
H'004C to H'004F
IRQ4
20
H'0028 to H'0029
H'0050 to H'0053
IRQ5
21
H'002A to H'002B
H'0054 to H'0057
IRQ6
22
H'002C to H'002D
H'0058 to H'005B
Reserved for system use
External interrupt
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Section 4 Exception Handling
Vector Address*1
Vector Number
Normal Mode*2
Advanced Mode
IRQ7
IRQ8*5
23
H'002E to H'002F
H'005C to H'005F
24
H'0030 to H'0031
H'0060 to H'0063
IRQ9*
25
H'0032 to H'0033
H'0064 to H'0067
IRQ10*5
IRQ11*5
26
H'0034 to H'0035
H'0068 to H'006B
27
H'0036 to H'0037
H'006C to H'006F
IRQ12*5
IRQ13*5
28
H'0038 to H'0039
H'0070 to H'0073
29
H'003A to H'003B
H'0074 to H'0077
IRQ14*5
30
H'003C to H'003D
H'0078 to H'007B
IRQ15*
31
H'003E to H'003F
H'007C to H'007F
32
⎜
157
H'0040 to H'0041
⎜
H'013A to H'013B
H'0080 to H'0083
⎜
H'0274 to H'0277
Exception Source
External interrupt
5
External interrupt
Internal interrupt*
4
5
Notes: 1.
2.
3.
4.
Lower 16 bits of the address.
Not available in this LSI.
Not available in this LSI. It is reserved for system use.
For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
5. Reserved for system use in the H8S/2454 Group.
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Section 4 Exception Handling
4.3
H8S/2456, H8S/2456R, H8S/2454 Group
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 15 ms at
power-up. To reset this LSI during operation, hold the RES pin low for at least 2 ms. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI
can also be reset by overflow of the watchdog timer. For details see section 14, Watchdog Timer
(WDT). The interrupt control mode is 0 immediately after reset.
4.3.1
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
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Section 4 Exception Handling
Vector fetch
Prefetch of first
Internal
processing program instruction
(1)
(3)
φ
RES
Internal
address bus
(5)
Internal read
signal
Internal write
signal
Internal data
bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
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Section 4 Exception Handling
Internal
processing
Vector fetch
*
*
Prefetch of first
program instruction
*
φ
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
D15 to D0
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Seven program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
On-Chip Peripheral Functions after Reset Release
After reset release, MSTPCR is initialized to H'0FFF, EXMSTPCR is initialized to H'FFFF, and
all modules except the DMAC, EXDMAC, and DTC enter the module stop state.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when the module stop state is exited.
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4.4
Section 4 Exception Handling
Trace Exception Handling
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.3
Status of CCR and EXR after Trace Exception Handling
CCR
Interrupt Control Mode
I
0
2
UI
EXR
I2 to I0
T
Trace exception handling cannot be used.
1
⎯
⎯
0
[Legend]
1:
Set to 1
0:
Cleared to 0
⎯:
Retains value prior to execution
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Section 4 Exception Handling
4.5
H8S/2456, H8S/2456R, H8S/2454 Group
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, refer to section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
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4.6
Section 4 Exception Handling
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1
⎯
⎯
⎯
2
1
⎯
⎯
0
[Legend]
1:
Set to 1
0:
Cleared to 0
⎯:
Retains value prior to execution
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Section 4 Exception Handling
4.7
Illegal Instruction Exception Handling
Illegal instruction exception handling starts when the CPU executing an illegal instruction code is
detected. Illegal instruction exception handling can be executed at all times in the program
execution state.
The illegal instruction exception handling is as follows:
1. The values in the PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the exception is generated, the
start address of the exception service routine is loaded from the vector table to the PC, and
program execution starts from that address.
Table 4.5 shows the status of CCR and EXR after execution of illegal instruction exception
handling.
Table 4.5
Status of CCR and EXR after Illegal Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
T
I2 to I0
0
1
⎯
⎯
⎯
2
1
⎯
0
⎯
[Legend]
1:
Set to 1
0:
Cleared to 0
⎯:
Retains value prior to execution
Illegal instruction codes will not be searched for in the fields that do not affect instruction
definitions, such as the EA extension or register fields. Instruction codes for an instruction formed
with several words are detected independently, and combined instruction codes are not detected.
Undefined instruction codes must not be executed. The general register contents after execution of
an undefined instruction code or illegal instruction exception handling cannot be guaranteed. The
stack pointer during illegal instruction exception handling and the PC value that will be saved are
also not guaranteed.
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4.8
Section 4 Exception Handling
Stack Status after Exception Handling
Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Normal Modes*2
SP
EXR
Reserved*1
SP
CCR
CCR
CCR*1
CCR*1
PC (16 bits)
PC (16 bits)
Interrupt control mode 0
Interrupt control mode 2
Advanced Modes
SP
EXR
Reserved*1
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Notes: 1. Ignored on return.
2. Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling
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Section 4 Exception Handling
4.9
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP, ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation
when the SP value is odd.
Address
CCR
H'FFFEFA
R1L
SP
SP
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP
H'FFFEFF
TRAP instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7
Data saved above SP
Contents of CCR lost
Legend:
CCR :
PC :
R1L :
SP :
Condition code register
Program counter
General register R1L
Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• External interrupt pins
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can
be selected for IRQn-A and IRQn-B.
Note: n = 15 to 0 for H8S/2456 Group and H8S/2456R Group, n = 7 to 0 for H8S/2454
Group
• DTC and DMAC control
DTC and DMAC activations are performed by means of interrupts.
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Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1 INTM0
INTCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ITSR
ISCR
Interrupt
request
Vector
number
IER
Priority
determination
Internal
interrupt
sources
SWDTEND
to SSTXI
I
I2 to I0
CCR
EXR
IPR
Interrupt controller
[Legend]
ISCR: IRQ sense control register
IER:
IRQ enable register
ISR:
IRQ status register
IPR:
Interrupt priority register
INTCR: Interrupt control register
ITSR: IRQ pin select register
Figure 5.1 Block Diagram of Interrupt Controller
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5.2
Section 5 Interrupt Controller
Input/Output Pins
Table 5.1 shows the pin configuration of the interrupt controller.
Table 5.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt
Rising or falling edge can be selected.
IRQ15-A to IRQ0-A*
IRQ15-B to IRQ0-B*
Note:
*
Input
Maskable external interrupts
Rising, falling, or both edges, or level sensing, can be
selected.
IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in the H8S/2454 Group.
IRQ12-B to IRQ9-B are not supported in the H8S/2456 Group.
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Section 5 Interrupt Controller
5.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The interrupt controller has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interrupt control register (INTCR)
IRQ sense control register H (ISCRH)
IRQ sense control register L (ISCRL)
IRQ enable register (IER)
IRQ status register (ISR)
IRQ pin select register (ITSR)
Software standby release IRQ enable register (SSIER)
Interrupt priority register A (IPRA)
Interrupt priority register B (IPRB)
Interrupt priority register C (IPRC)
Interrupt priority register D (IPRD)
Interrupt priority register E (IPRE)
Interrupt priority register F (IPRF)
Interrupt priority register G (IPRG)
Interrupt priority register H (IPRH)
Interrupt priority register I (IPRI)
Interrupt priority register J (IPRJ)
Interrupt priority register K (IPRK)
Interrupt priority register L (IPRL)
Interrupt priority register M (IPRM)
Interrupt priority register N (IPRN)
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5.3.1
Section 5 Interrupt Controller
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the detected edge for NMI.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and the initial
value should not be changed.
5
INTM1
0
R/W
Interrupt Control Select Mode 1 and 0
4
INTM0
0
R/W
These bits select either of two interrupt control
modes for the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0, and
IPR.
11: Setting prohibited.
3
NMIEG
0
R/W
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of
NMI input
1: Interrupt request generated at rising edge of
NMI input
2 to 0
⎯
All 0
⎯
Reserved
These bits are always read as 0 and the initial
value should not be changed.
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Section 5 Interrupt Controller
5.3.2
Interrupt Priority Registers A to N (IPRA to IPRN)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.
Bit
Bit Name
Initial Value
R/W
Description
15
⎯
0
⎯
Reserved
This bit is always read as 0 and the initial value
should not be changed.
14
IPR14
1
R/W
13
IPR13
1
R/W
12
IPR12
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
11
⎯
0
⎯
Reserved
Sets the priority of the corresponding interrupt
source.
This bit is always read as 0 and the initial value
should not be changed.
10
IPR10
1
R/W
9
IPR9
1
R/W
8
IPR8
1
R/W
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Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
⎯
Reserved
This bit is always read as 0 and the initial value
should not be changed.
6
IPR6
1
R/W
5
IPR5
1
R/W
4
IPR4
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3
⎯
0
⎯
Reserved
Sets the priority of the corresponding interrupt
source.
This bit is always read as 0 and the initial value
should not be changed.
2
IPR2
1
R/W
1
IPR1
1
R/W
Sets the priority of the corresponding interrupt
source.
0
IPR0
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
5.3.3
IRQ Enable Register (IER)
IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Description
15
IRQ15E
0
R/W
IRQ15 Enable*
The IRQ15 interrupt request is enabled when this
bit is 1.
14
IRQ14E
0
R/W
IRQ14 Enable*
The IRQ14 interrupt request is enabled when this
bit is 1.
13
IRQ13E
0
R/W
IRQ13 Enable*
The IRQ13 interrupt request is enabled when this
bit is 1.
12
IRQ12E
0
R/W
IRQ12 Enable*
The IRQ12 interrupt request is enabled when this
bit is 1.
11
IRQ11E
0
R/W
IRQ11 Enable*
The IRQ11 interrupt request is enabled when this
bit is 1.
10
IRQ10E
0
R/W
IRQ10 Enable*
The IRQ10 interrupt request is enabled when this
bit is 1.
9
IRQ9E
0
R/W
IRQ9 Enable*
The IRQ9 interrupt request is enabled when this
bit is 1.
8
IRQ8E
0
R/W
IRQ8 Enable*
The IRQ8 interrupt request is enabled when this
bit is 1.
7
IRQ7E
0
R/W
IRQ7 Enable
The IRQ7 interrupt request is enabled when this
bit is 1.
6
IRQ6E
0
R/W
IRQ6 Enable
The IRQ6 interrupt request is enabled when this
bit is 1.
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
5
IRQ5E
0
R/W
IRQ5 Enable
The IRQ5 interrupt request is enabled when this
bit is 1.
4
IRQ4E
0
R/W
IRQ4 Enable
The IRQ4 interrupt request is enabled when this
bit is 1.
3
IRQ3E
0
R/W
IRQ3 Enable
The IRQ3 interrupt request is enabled when this
bit is 1.
2
IRQ2E
0
R/W
IRQ2 Enable
The IRQ2 interrupt request is enabled when this
bit is 1.
1
IRQ1E
0
R/W
IRQ1 Enable
The IRQ1 interrupt request is enabled when this
bit is 1.
0
IRQ0E
0
R/W
IRQ0 Enable
The IRQ0 interrupt request is enabled when this
bit is 1.
Note:
*
These bits are reserved in the H8S/2454 Group.
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Section 5 Interrupt Controller
5.3.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.
•
ISCRH (H8S/2456 Group only)
Bit
Bit Name
Initial Value
R/W
Description
15
IRQ15SCB
0
R/W
IRQ15 Sense Control B
14
IRQ15SCA
0
R/W
IRQ15 Sense Control A
00: Interrupt request generated at IRQ15 input low
level
01: Interrupt request generated at falling edge of
IRQ15 input
10: Interrupt request generated at rising edge of
IRQ15 input
11: Interrupt request generated at both falling and
rising edges of IRQ15 input
13
IRQ14SCB
0
R/W
IRQ14 Sense Control B
12
IRQ14SCA
0
R/W
IRQ14 Sense Control A
00: Interrupt request generated at IRQ14 input low
level
01: Interrupt request generated at falling edge of
IRQ14 input
10: Interrupt request generated at rising edge of
IRQ14 input
11: Interrupt request generated at both falling and
rising edges of IRQ14 input
11
IRQ13SCB
0
R/W
IRQ13 Sense Control B
10
IRQ13SCA
0
R/W
IRQ13 Sense Control A
00: Interrupt request generated at IRQ13 input low
level
01: Interrupt request generated at falling edge of
IRQ13 input
10: Interrupt request generated at rising edge of
IRQ13 input
11: Interrupt request generated at both falling and
rising edges of IRQ13 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
9
IRQ12SCB
0
R/W
IRQ12 Sense Control B
8
IRQ12SCA
0
R/W
IRQ12 Sense Control A
00: Interrupt request generated at IRQ12 input low
level
01: Interrupt request generated at falling edge of
IRQ12 input
10: Interrupt request generated at rising edge of
IRQ12 input
11: Interrupt request generated at both falling and
rising edges of IRQ12 input
7
IRQ11SCB
0
R/W
IRQ11 Sense Control B
6
IRQ11SCA
0
R/W
IRQ11 Sense Control A
00: Interrupt request generated at IRQ11 input low
level
01: Interrupt request generated at falling edge of
IRQ11 input
10: Interrupt request generated at rising edge of
IRQ11 input
11: Interrupt request generated at both falling and
rising edges of IRQ11 input
5
IRQ10SCB
0
R/W
IRQ10 Sense Control B
4
IRQ10SCA
0
R/W
IRQ10 Sense Control A
00: Interrupt request generated at IRQ10 input low
level
01: Interrupt request generated at falling edge of
IRQ10 input
10: Interrupt request generated at rising edge of
IRQ10 input
11: Interrupt request generated at both falling and
rising edges of IRQ10 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
IRQ9SCB
0
R/W
IRQ9 Sense Control B
2
IRQ9SCA
0
R/W
IRQ9 Sense Control A
00: Interrupt request generated at IRQ9 input low
level
01: Interrupt request generated at falling edge of
IRQ9 input
10: Interrupt request generated at rising edge of
IRQ9 input
11: Interrupt request generated at both falling and
rising edges of IRQ9 input
1
IRQ8SCB
0
R/W
IRQ8 Sense Control B
0
IRQ8SCA
0
R/W
IRQ8 Sense Control A
00: Interrupt request generated at IRQ8 input low
level
01: Interrupt request generated at falling edge of
IRQ8 input
10: Interrupt request generated at rising edge of
IRQ8 input
11: Interrupt request generated at both falling and
rising edges of IRQ8 input
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•
Section 5 Interrupt Controller
ISCRL
Bit
Bit Name
Initial Value
R/W
Description
15
IRQ7SCB
0
R/W
IRQ7 Sense Control B
14
IRQ7SCA
0
R/W
IRQ7 Sense Control A
00: Interrupt request generated at IRQ7 input low
level
01: Interrupt request generated at falling edge of
IRQ7 input
10: Interrupt request generated at rising edge of
IRQ7 input
11: Interrupt request generated at both falling and
rising edges of IRQ7 input
13
IRQ6SCB
0
R/W
IRQ6 Sense Control B
12
IRQ6SCA
0
R/W
IRQ6 Sense Control A
00: Interrupt request generated at IRQ6 input low
level
01: Interrupt request generated at falling edge of
IRQ6 input
10: Interrupt request generated at rising edge of
IRQ6 input
11: Interrupt request generated at both falling and
rising edges of IRQ6 input
11
IRQ5SCB
0
R/W
IRQ5 Sense Control B
10
IRQ5SCA
0
R/W
IRQ5 Sense Control A
00: Interrupt request generated at IRQ5 input low
level
01: Interrupt request generated at falling edge of
IRQ5 input
10: Interrupt request generated at rising edge of
IRQ5 input
11: Interrupt request generated at both falling and
rising edges of IRQ5 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
9
IRQ4SCB
0
R/W
IRQ4 Sense Control B
8
IRQ4SCA
0
R/W
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input low
level
01: Interrupt request generated at falling edge of
IRQ4 input
10: Interrupt request generated at rising edge of
IRQ4 input
11: Interrupt request generated at both falling and
rising edges of IRQ4 input
7
IRQ3SCB
0
R/W
IRQ3 Sense Control B
6
IRQ3SCA
0
R/W
IRQ3 Sense Control A
00: Interrupt request generated at IRQ3 input low
level
01: Interrupt request generated at falling edge of
IRQ3 input
10: Interrupt request generated at rising edge of
IRQ3 input
11: Interrupt request generated at both falling and
rising edges of IRQ3 input
5
IRQ2SCB
0
R/W
IRQ2 Sense Control B
4
IRQ2SCA
0
R/W
IRQ2 Sense Control A
00: Interrupt request generated at IRQ2 input low
level
01: Interrupt request generated at falling edge of
IRQ2 input
10: Interrupt request generated at rising edge of
IRQ2 input
11: Interrupt request generated at both falling and
rising edges of IRQ2 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
IRQ1SCB
0
R/W
IRQ1 Sense Control B
2
IRQ1SCA
0
R/W
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input low
level
01: Interrupt request generated at falling edge of
IRQ1 input
10: Interrupt request generated at rising edge of
IRQ1 input
11: Interrupt request generated at both falling and
rising edges of IRQ1 input
1
IRQ0SCB
0
R/W
IRQ0 Sense Control B
0
IRQ0SCA
0
R/W
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input low
level
01: Interrupt request generated at falling edge of
IRQ0 input
10: Interrupt request generated at rising edge of
IRQ0 input
11: Interrupt request generated at both falling and
rising edges of IRQ0 input
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Section 5 Interrupt Controller
5.3.5
IRQ Status Register (ISR)
ISR is an IRQ15 to IRQ0 interrupt request flag register.
Bit
15
Bit Name
IRQ15F*
2
Initial Value
0
R/W
Description
[Setting condition]
1
1
When the interrupt source selected by ISCR
occurs
1
[Clearing conditions]
1
•
Cleared by reading IRQnF flag when IRQnF =
1, then writing 0 to IRQnF flag
•
When interrupt exception handling is executed
when low-level detection is set and IRQn input
is high
•
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
•
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the DTC
is cleared to 0
R/(W)*
1
R/(W)*
2
0
R/(W)*
IRQ11F*
0
11
2
IRQ12F*
R/(W)*
12
R/(W)*
0
IRQ13F*
0
IRQ14F*
13
2
14
2
2
10
IRQ10F*
9
IRQ9F*
8
1
0
R/(W)*
2
0
R/(W)*
IRQ8F*
2
0
R/(W)*
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
1
1
1
1
1
1
1
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
1
1
1
Notes: 1. Only 0 can be written, to clear the flag.
2. These bits are reserved in the H8S/2454 Group.
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H8S/2456, H8S/2456R, H8S/2454 Group
5.3.6
Section 5 Interrupt Controller
IRQ Pin Select Register (ITSR)
ITSR selects input pins IRQ15 to IRQ0.
•
H8S/2456 Group
Bit
Bit Name
Initial Value
R/W
Description
15
ITS15
0
R/W
Selects the IRQ15 input pin.
0: PF2/IRQ15-A selected
1: P27/IRQ15-B selected
14
ITS14
0
R/W
Selects the IRQ14 input pin.
0: PF1/IRQ14-A selected
1: P26/IRQ14-B selected
13
ITS13
0
R/W
Selects the IRQ13 input pin.
0: P65/IRQ13-A selected
1: P25/IRQ13-B selected
12
⎯
0
R/W
Reserved
The initial value should not be changed.
11
⎯
0
R/W
Reserved
The initial value should not be changed.
10
⎯
0
R/W
Reserved
The initial value should not be changed.
9
⎯
0
R/W
Reserved
The initial value should not be changed.
8
ITS8
0
R/W
Selects the IRQ8 input pin.
0: P60/IRQ8-A selected
1: P20/IRQ8-B selected
7
ITS7
0
R/W
Selects the IRQ7 input pin.
0: PA7/IRQ7-A selected
1: PH3/IRQ7-B selected
6
ITS6
0
R/W
Selects the IRQ6 input pin.
0: PA6/IRQ6-A selected
1: PH2/IRQ6-B selected
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
5
ITS5
0
R/W
Selects the IRQ5 input pin.
0: PA5/IRQ5-A selected
1: P85/IRQ5-B selected
4
ITS4
0
R/W
Selects the IRQ4 input pin.
0: PA4/IRQ4-A selected
1: P84/IRQ4-B selected
3
ITS3
0
R/W
Selects the IRQ3 input pin.
0: P53/IRQ3-A selected
1: P83/IRQ3-B selected
2
ITS2
0
R/W
Selects the IRQ2 input pin.
0: P52/IRQ2-A selected
1: P82/IRQ2-B selected
1
ITS1
0
R/W
Selects the IRQ1 input pin.
0: P51/IRQ1-A selected
1: P81/IRQ1-B selected
0
ITS0
0
R/W
Selects the IRQ0 input pin.
0: P50/IRQ0-A selected
1: P80/IRQ0-B selected
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•
Bit
Section 5 Interrupt Controller
H8S/2454 Group
Bit Name
15 to 8 ⎯
Initial Value R/W
Description
All 0
Reserved
R/W
The initial value should not be changed.
7
ITS7
0
R/W
Selects the IRQ7 input pin.
0: PA7/IRQ7-A selected
1: P47/IRQ7-B selected
6
ITS6
0
R/W
Selects the IRQ6 input pin.
0: PA6/IRQ6-A selected
1: P46/IRQ6-B selected
5
ITS5
0
R/W
Selects the IRQ5 input pin.
0: PA5/IRQ5-A selected
1: P45/IRQ5-B selected
4
ITS4
0
R/W
Selects the IRQ4 input pin.
0: PA4/IRQ4-A selected
1: P44/IRQ4-B selected
3
ITS3
0
R/W
Selects the IRQ3 input pin.
0: P53/IRQ3-A selected
1: P43/IRQ3-B selected
2
ITS2
0
R/W
Selects the IRQ2 input pin.
0: P52/IRQ2-A selected
1: P42/IRQ2-B selected
1
ITS1
0
R/W
Selects the IRQ1 input pin.
0: P51/IRQ1-A selected
1: P41/IRQ1-B selected
0
ITS0
0
R/W
Selects the IRQ0 input pin.
0: P50/IRQ0-A selected
1: P40/IRQ0-B selected
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Section 5 Interrupt Controller
5.3.7
Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ pins used to recover from the software standby state.
Bit
Bit Name
Initial Value
R/W
Description
15
SSI15*
0
R/W
Software Standby Release IRQ Setting
14
SSI14*
0
R/W
13
SSI13*
0
R/W
These bits select the IRQn pins used to recover
from the software standby state.
12
SSI12*
0
R/W
11
SSI11*
0
R/W
10
SSI10*
0
R/W
9
SSI9*
0
R/W
8
SSI8*
0
R/W
7
SSI7
0
R/W
6
SSI6
0
R/W
5
SSI5
0
R/W
4
SSI4
0
R/W
3
SSI3
0
R/W
2
SSI2
0
R/W
1
SSI1
0
R/W
0
SSI0
0
R/W
Note:
*
0: IRQn requests are not sampled in the software
standby state (Initial value when n = 15 to 3)
1: When an IRQn request occurs in the software
standby state, the chip recovers from the
software standby state after the elapse of the
oscillation settling time (Initial value when n = 2
to 0)
These bits are reserved in the H8S/2454 Group.
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H8S/2456, H8S/2456R, H8S/2454 Group
5.4
Interrupt Sources
5.4.1
External Interrupts
Section 5 Interrupt Controller
The H8S/2456 Group and H8S/2456R Group each have seventeen external interrupts: NMI and
IRQ15 to IRQ0. The H8S/2454 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These
interrupts can be used to restore the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQn Interrupts (n = 0 to 15 for H8S/2456 Group and H8S/2456R Group, n = 0 to 7 for
H8S/2454 Group): An IRQn interrupt is requested by an input signal at the IRQn pin. The IRQn
interrupts have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at the IRQn pin.
• Enabling or disabling of IRQn interrupt requests can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of IRQn interrupt requests is indicated in ISR. ISR flags can be cleared to 0 by
software.
When IRQn interrupt requests occur at low level of the IRQn pin, the corresponding IRQ pin
should be held low until an interrupt handling starts. Then the corresponding IRQ pin should be
set to high in the interrupt handling routine and clear the IRQnF bit in ISR to 0. Interrupts may not
be executed when the corresponding IRQ pin is set to high before the interrupt handling starts.
Detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or
output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of IRQn interrupts is shown in figure 5.2.
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Section 5 Interrupt Controller
IRQnE
IRQnSCA, IRQnSCB
Edge/
level detection
circuit
IRQn
input
IRQnF
S
Q
IRQn interrupt
request
R
Clear signal
Note: n = 0 to 15 for H8S/2456 Group and H8S/2456R Group, n = 0 to 7 for H8S/2454 Group
Figure 5.2 Block Diagram of IRQ Interrupts
5.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
control mode or CPU interrupt mask bit.
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H8S/2456, H8S/2456R, H8S/2454 Group
5.5
Section 5 Interrupt Controller
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Table 5.2
Interrupt
Source
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Vector
1
Address*
Vector Advanced
Number Mode
IPR
Priority
DTC
Activation
DMAC
Activation
7
H'001C
⎯
High
⎯
⎯
IRQ0
16
H'0040
IPRA14 to IPRA12
⎯
IRQ1
17
H'0044
IPRA10 to IPRA8
⎯
IRQ2
18
H'0048
IPRA6 to IPRA4
⎯
IRQ3
19
H'004C
IPRA2 to IPRA0
⎯
IRQ4
20
H'0050
IPRB14 to IPRB12
⎯
IRQ5
21
H'0054
IPRB10 to IPRB8
⎯
IRQ6
22
H'0058
IPRB6 to IPRB4
⎯
23
H'005C
IPRB2 to IPRB0
⎯
24
H'0060
IPRC14 to IPRC12
⎯
External pin NMI
IRQ7
2
IRQ8*
25
H'0064
IPRC10 to IPRC8
⎯
2
26
H'0068
IPRC6 to IPRC4
⎯
2
27
H'006C
IPRC2 to IPRC0
⎯
2
28
H'0070
IPRD14 to IPRD12
⎯
2
29
H'0074
IPRD10 to IPRD8
⎯
2
30
H'0078
IPRD6 to IPRD4
⎯
2
IRQ15*
31
H'007C
IPRD2 to IPRD0
⎯
DTC
SWDTEND
32
H'0080
IPRE14 to IPRE12
⎯
WDT
WOVI0
33
H'0084
IPRE10 to IPRE8
⎯
⎯
⎯
Reserved for 34
system use
H'0088
IPRE6 to IPRE4
⎯
⎯
2
IRQ9*
IRQ10*
IRQ11*
IRQ12*
IRQ13*
IRQ14*
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Low
Page 131 of 1408
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Section 5 Interrupt Controller
Vector
1
Address*
Origin of
Interrupt
Source
Vector Advanced
Number Mode
IPR
Priority
DTC
Activation
DMAC
Activation
Refresh
controller
CMI
35
H'008C
IPRE2 to IPRE0
High
⎯
⎯
⎯
Reserved for 36
system use
37
H'0090
IPRF14 to IPRF12
⎯
⎯
⎯
⎯
ADI0
38
H'0098
Reserved for 39
system use
H'009C
⎯
⎯
TGI0A
40
H'00A0
TGI0B
41
H'00A4
⎯
TGI0C
42
H'00A8
⎯
TGI0D
43
H'00AC
TCI0V
44
H'00B0
⎯
⎯
Reserved for 45
system use
46
H'00B4
⎯
⎯
H'00B8
⎯
⎯
47
H'00BC
⎯
⎯
48
H'00C0
Interrupt
Source
A/D_0
TPU_0
TPU_1
TPU_2
TPU_3
TGI1A
H'0094
IPRF10 to IPRF8
IPRF6 to IPRF4
⎯
IPRF6 to IPRF4
IPRF2 to IPRF0
⎯
TGI1B
49
H'00C4
TCI1V
50
H'00C8
⎯
⎯
TCI1U
51
H'00CC
⎯
⎯
TGI2A
52
H'00D0
TGI2B
53
H'00D4
TCI2V
54
H'00D8
⎯
⎯
TCI2U
55
H'00DC
⎯
⎯
TGI3A
56
H'00E0
TGI3B
57
H'00E4
⎯
TGI3C
58
H'00E8
⎯
TGI3D
59
H'00EC
⎯
TCI3V
60
H'00F0
Page 132 of 1408
IPRG14 to IPRG12
⎯
IPRG10 to IPRG8
Low
⎯
⎯
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Interrupt
Source
TPU_3
TPU_4
TPU_5
TMR_0
TMR_1
Origin of
Interrupt
Source
Vector
1
Address*
Vector Advanced
Number Mode
IPR
Priority
DTC
Activation
DMAC
Activation
IPRG10 to IPRG8
High
⎯
⎯
Reserved for 61
system use
62
H'00F4
H'00F8
⎯
⎯
63
H'00FC
⎯
⎯
TGI4A
64
H'0100
TGI4B
65
H'0104
TCI4V
66
H'0108
⎯
⎯
TCI4U
67
H'010C
⎯
⎯
TGI5A
68
H'0110
TGI5B
69
H'0114
TCI5V
70
H'0118
⎯
⎯
TCI5U
71
H'011C
⎯
⎯
CMIA0
72
H'0120
CMIB0
73
H'0124
OVI0
74
H'0128
Reserved for 75
system use
H'012C
IPRH14 to IPRH12
CMIA1
76
H'0130
IPRH10 to IPRH8
CMIB1
77
H'0134
IPRG6 to IPRG4
⎯
IPRG2 to IPRG0
⎯
⎯
IPRH14 to IPRH12
⎯
⎯
⎯
⎯
⎯
⎯
⎯
78
H'0138
⎯
Reserved for 79
system use
H'013C
⎯
DMTEND0A 80
H'0140
DMTEND0B 81
H'0144
⎯
DMTEND1A 82
H'0148
⎯
DMTEND1B 83
H'014C
OVI1
DMAC
Section 5 Interrupt Controller
R01UH0309EJ0500 Rev. 5.00
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⎯
⎯
⎯
IPRH6 to IPRH4
Low
⎯
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Section 5 Interrupt Controller
Origin of
Interrupt
Source
Interrupt
Source
Vector
1
Address*
Vector
Number
Advanced
Mode
IPR
Priority
H'0150
IPRH0 to IPRH0
High
⎯
⎯
IPRI14 to IPRI12
⎯
H'0158
IPRI10 to IPRI8
⎯
⎯
87
H'015C
IPRI6 to IPRI4
⎯
⎯
ERI0
88
H'0160
IPRI2 to IPRI0
⎯
⎯
RXI0
89
H'0164
TXI0
90
H'0168
TEI0
91
H'016C
⎯
⎯
ERI1
92
H'0170
⎯
⎯
RXI1
93
H'0174
⎯
⎯
⎯
⎯
H'0154
EXDMTEND2
86
EXDMTEND3
2
SCI_1
SCI_2
SCI_3
SCI_4
DMAC
Activation
⎯
EXDMAC* Reserved for 84
system use
85
SCI_0
DTC
Activation
IPRJ14 to IPRJ12
TXI1
94
H'0178
TEI1
95
H'017C
ERI2
96
H'0180
RXI2
97
H'0184
⎯
TXI2
98
H'0188
⎯
TEI2
99
H'018C
ERI3
100
H'0190
RXI3
101
H'0194
⎯
TXI3
102
H'0198
⎯
TEI3
103
H'019C
ERI4
104
H'01A0
RXI4
105
H'01A4
⎯
TXI4
106
H'01A8
⎯
TEI4
107
H'01AC
Reserved for 108
system use
109
H'01B0
Page 134 of 1408
IPRJ10 to IPRJ8
IPRJ6 to IPRJ4
IPRJ2 to IPRJ0
IPRK14 to IPRK12
H'01B4
110
H'01B8
111
H'01BC
Low
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
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Section 5 Interrupt Controller
Vector
1
Address*
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
A/D_1
ADI1
112
H'01C0
IPRK10 to IPRK8
High
IIC2_0
IIC2_1
TPU_6
TPU_7
TPU_8
TPU_9
DTC
Activation
DMAC
Activation
⎯
⎯
Reserved for 113
system use
114
H'01C4
⎯
H'01C8
⎯
⎯
115
H'01CC
⎯
⎯
116
H'01D0
⎯
⎯
Reserved for 117
system use
H'01D4
⎯
⎯
IICI1
118
H'01D8
⎯
⎯
Reserved for 119
system use
H'01DC
⎯
⎯
TGI6A
120
H'01E0
TGI6B
121
H'01E4
⎯
TGI6C
122
H'01E8
⎯
TGI6D
123
H'01EC
⎯
TCI6V
124
H'01F0
IICI0
IPRK6 to IPRK4
⎯
IPRK2 to IPRK0
⎯
⎯
⎯
IPRL14 to IPRL12
TGI7A
125
H'01F4
TGI7B
126
H'01F8
TCI7V
127
H'01FC
⎯
⎯
TCI7U
128
H'0200
⎯
⎯
TGI8A
129
H'0204
TGI8B
130
H'0208
TCI8V
131
H'020C
TCI8U
132
H'0210
⎯
⎯
IPRL10 to IPRL8
⎯
⎯
⎯
⎯
⎯
⎯
IPRL6 to IPRL4
TGI9A
133
H'0214
TGI9B
134
H'0218
⎯
TGI9C
135
H'021C
⎯
TGI9D
136
H'0220
⎯
TCI9V
137
H'0224
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Low
⎯
⎯
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Section 5 Interrupt Controller
Vector
1
Address*
Interrupt
Source
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
Priority
TPU_10
TGI10A
138
H'0228
IPRL2 to IPRL0
High
TGI10B
139
H'022C
TCI10V
140
H'0230
⎯
⎯
TCI10U
141
H'0234
⎯
⎯
TGI11A
142
H'0238
TGI11B
143
H'023C
TCI11V
144
H'0240
⎯
⎯
TCI11U
145
H'0244
⎯
⎯
USBINTN0
146
H'0248
USBINTN1
147
H'024C
⎯
USBINTN2
148
H'0250
⎯
⎯
USBINTN3
149
H'0254
⎯
⎯
USBINTN0
150
H'0258
⎯
⎯
Reserved for 151
system use
H'025C
⎯
⎯
RESUME
152
H'0260
⎯
⎯
IIC2_2
IICI2
153
H'0264
⎯
⎯
IIC2_3
IICI3
154
H'0268
⎯
⎯
SSU
SSERI
155
H'026C
⎯
⎯
SSRXI
156
H'0270
TPU_11
USB
SSTXI
Page 136 of 1408
157
H'0274
DTC
Activation
DMAC
Activation
⎯
⎯
⎯
IPRM14 to IPRM12
⎯
⎯
IPRM10 to IPRM8
IPRM6 to IPRM4
IPRM2 to IPRM0
IPRN14 to IPRN12
Low
⎯
⎯
⎯
⎯
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Interrupt
Source
⎯
Origin of
Interrupt
Source
Section 5 Interrupt Controller
Vector
1
Address*
Vector
Number
Advanced
Mode
IPR
Priority
DTC
Activation
DMAC
Activation
H'0278
IPRN10 to IPRN8
High
⎯
⎯
⎯
Reserved for 158
system use
159
H'027C
⎯
160
H'0280
⎯
⎯
161
H'0284
⎯
⎯
162
H'0288
⎯
⎯
163
H'028C
⎯
⎯
164
H'0290
⎯
⎯
165
H'0294
⎯
⎯
166
H'0298
⎯
⎯
167
H'029C
⎯
⎯
168
H'02A0
⎯
⎯
169
H'02A4
⎯
⎯
Reserved for 170
system use
|
H'02A8
⎯
⎯
|
|
255
H'03FC
⎯
⎯
IPRN6 to IPRN4
IPRN2 to IPRN0
⎯
|
Low
Notes: 1. Lower 16 bits of the start address.
2. Not supported in the H8S/2454 Group.
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Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
Interrupt Control Modes
Interrupt
Control Mode
Priority Setting
Registers
Interrupt
Mask Bits
0
Default
I
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
2
IPR
I2 to I0
8 priority levels except for NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
Page 138 of 1408
Description
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5.6.1
Section 5 Interrupt Controller
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in
the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
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Section 5 Interrupt Controller
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
I=0
No
Hold
pending
Yes
IRQ0
Yes
No
IRQ1
Yes
No
SSTXI
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
Page 140 of 1408
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5.6.2
Section 5 Interrupt Controller
Interrupt Control Mode 2
In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Yes
Level 6 interrupt?
No
No
Yes
Mask level 5
or below?
Level 1 interrupt?
No
Yes
No
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Hold
pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
Page 142 of 1408
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5.6.3
Section 5 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
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Page 143 of 1408
Page 144 of 1408
(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination Instruction
Wait for end of instruction
prefetch
Interrupt
acceptance
(7)
(8)
(10)
(9)
(12)
(11)
Internal
operation
(14)
(13)
Interrupt handling
routine instruction
prefetch
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6)
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
Stack
Vector fetch
Section 5 Interrupt Controller
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 5.5 Interrupt Exception Handling
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5.6.4
Section 5 Interrupt Controller
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to
on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM,
enabling high-speed processing.
Table 5.4
Interrupt Response Times
Normal Mode*5
No.
Execution Status
Interrupt
control
mode 0
1
Interrupt priority determination*1
3
2
Number of wait states until executing 1 to
2
19 +2·SI
instruction ends*
Advanced Mode
Interrupt
control
mode 2
Interrupt
control
mode 0
Interrupt
control
mode 2
3
3
3
1 to
19+2·SI
1 to
19+2·SI
1 to
19+2·SI
3
PC, CCR, EXR stack save
2·SK
3·SK
2·SK
3·SK
4
Vector fetch
SI
SI
2·SI
2·SI
5
Instruction fetch*3
2·SI
2·SI
2·SI
2·SI
6
Internal processing*
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in this LSI.
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Section 5 Interrupt Controller
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
16 Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch SI
1
4
6+2m
2
3+m
Branch address read SJ
Stack manipulation SK
[Legend]
m:
Number of wait states in an external device access.
5.6.5
DTC and DMAC Activation by Interrupt
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
•
•
•
•
Interrupt request to CPU
Activation request to DTC
Activation request to DMAC
Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and
section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC).
Page 146 of 1408
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Section 5 Interrupt Controller
5.7
Usage Notes
5.7.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction
such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the
interrupt concerned will still be enabled on completion of the instruction, and so interrupt
exception handling for that interrupt will be executed on completion of the instruction. However,
if there is an interrupt request of higher priority than that interrupt, interrupt exception handling
will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example
in which the TCIEV bit in the TPU's TIER_0 register is cleared to 0. The above conflict will not
occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
TIER_0 write cycle by CPU
TCIV exception handling
φ
Internal
address bus
TIER_0 address
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5.6 Conflict between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
5.7.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt
controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask
level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
EEPMOV.W
MOV.W
R4,R4
BNEL1
5.7.5
Change of IRQ Pin Select Register (ITSR) Setting
When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15 for
H8S/2456 Group, n = 0 to 7 for H8S/2454 Group) of ISR may be set to 1 at the unintended timing
if the selected pin level before the change is different from the selected pin level after the change.
If the IRQn interrupt request (n = 0 to 15 for H8S/2456 Group, n = 0 to 7 for H8S/2454 Group) is
enabled, the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR
setting should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should
be cleared to 0.
Page 148 of 1408
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5.7.6
Section 5 Interrupt Controller
IRQ Status Register (ISR)
Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR
and clear it to 0 after resets.
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Section 5 Interrupt Controller
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Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data
transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Note: * Not supported by the H8S/2454 Group.
6.1
Features
• Manages external address space in area units
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, DRAM, synchronous DRAM*1, and address/data multiplexed I/O interfaces can
be set
• Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait cycles can be inserted for each area
Extension cycles can be inserted while CS is asserted for each area
Wait cycles can be inserted by the WAIT pin
The negation timing of the read strobe signal (RD) can be modified
• Burst ROM interface
Burst ROM interface can be set independently for areas 0 and 1
• Address/data multiplexed I/O interface
Address/data multiplexed I/O interface can be set for areas 6 and 7
• DRAM interface
DRAM interface can be set for areas 2 to 5
• Synchronous DRAM interface*1
Continuous synchronous DRAM space can be set for areas 2 to 5
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Section 6 Bus Controller (BSC)
H8S/2456, H8S/2456R, H8S/2454 Group
• Idle cycle insertion
Idle cycles can be inserted between external read cycles to different areas
Idle cycles can be inserted before the write cycle after a read cycle
Idle cycles can be inserted before the read cycle after a write cycle
• Write buffer function
External write cycles and internal accesses can be executed in parallel
DMAC single address transfers and internal accesses can be executed in parallel
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and
EXDMAC*2
Notes: 1. Not supported by the H8S/2456 Group and H8S/2454 Group.
2. Not supported by the H8S/2454 Group.
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EXDMAC address bus
Internal address bus
Section 6 Bus Controller (BSC)
Address
selector
CS7 to CS0
Area decoder
WAIT
BREQ
BACK
BREQO
External bus controller
Internal bus master bus request signal
EXDMAC bus request signal*
Internal bus master bus acknowledge signal
EXDMAC bus acknowledge signal*
External bus
arbiter
External bus
control signals
Internal bus control signals
Internal bus controller
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
Internal bus
arbiter
Control registers
Internal data bus
ABWCR
ASTCR
DRAMCR
WTCRAH WTCRAL
DRACCRH DRACCRL
WTCRBH WTCRBL
REFCR
RTCNT
RDNCR
CSACRH
RTCOR
CSACRL
BROMCRH BROMCRL
BCR
[Legend]
ABWCR:
ASTCR:
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL:
RDNCR:
CSACRH and CSACRL:
BROMCRH:
BROMCRL :
BCR:
MPXCR:
DRAMCR:
DRACCRH and DRACCRL:
REFCR:
RTCNT:
RTCOR:
MPXCR
Bus width control register
Access state control register
Wait control registers AH, AL, BH, and BL
Read strobe timing control register
CS assertion period control registers H and L
Area 0 burst ROM interface control register
Area 1 burst ROM interface control register
Bus control register
Address/data multiplexed I/O control register
DRAM control register
DRAM access control registers H and L
Refresh control register
Refresh timer counter
Refresh time constant register
Note: * Not supported in the H8S/2454 Group.
Figure 6.1 Block Diagram of Bus Controller
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Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 shows the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that normal space
is accessed and address output on
address bus is enabled.
Address hold
AH
Output
Signal indicating the timing for latching the
address when the address/data
multiplexed I/O space is set.
Read
RD
Output
Strobe signal indicating that normal space
is being read.
High write/write enable
HWR/WE
Output
Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Low write
LWR
Output
Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Chip select 0
CS0
Output
Strobe signal indicating that area 0 is
selected.
Chip select 1
CS1
Output
Strobe signal indicating that area 1 is
selected
Chip select 2/
row address strobe 2/
row address strobe*1
CS2/
RAS2/
RAS*1
Output
Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to
5 are set as continuous DRAM space, or
row address strobe signal of the
synchronous DRAM when the
synchronous DRAM interface is selected.
Chip select 3/
row address strobe 3/
column address strobe*1
CS3/
RAS3/
CAS*1
Output
Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space, or column
address strobe signal of the synchronous
DRAM when the synchronous DRAM
interface is selected.
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Section 6 Bus Controller (BSC)
Name
Symbol
I/O
Function
Chip select 4/
row address strobe 4/
1
write enable*
CS4/
RAS4/
WE*1
Output
Strobe signal indicating that area 4 is
selected, DRAM row address strobe signal
when area 4 is DRAM space, or write
enable signal of the synchronous DRAM
when the synchronous DRAM interface is
selected.
Chip select 5/
row address strobe 5/
1
SDRAMφ*
CS5/
Output
RAS5/
SDRAMφ*1
Strobe signal indicating that area 5 is
selected, DRAM row address strobe signal
when area 5 is DRAM space, or dedicated
clock signal for the synchronous DRAM
when the synchronous DRAM interface is
selected.
Chip select 6
CS6
Output
Strobe signal indicating that area 6 is
selected.
Chip select 7
CS7
Output
Strobe signal indicating that area 7 is
selected.
Upper column address strobe/
1
upper data mask enable*
UCAS/
DQMU*1
Output
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal, upper data mask
signal of 16-bit synchronous DRAM space,
or data mask signal of 8-bit synchronous
DRAM space.
Lower column address strobe/
lower data mask enable*1
LCAS/
DQML*1
Output
16-bit DRAM space lower column address
strobe signal or lower data mask signal for
the 16-bit synchronous DRAM space.
Output enable/clock enable
OE/
CKE*1
Output
Output enable signal for the DRAM space
or clock enable signal for the synchronous
DRAM space.
Wait
WAIT
Input
Wait request signal when accessing
external address space.
Bus request
BREQ
Input
Request signal for release of bus to
external bus master.
Bus request acknowledge
BACK
Output
Acknowledge signal indicating that bus has
been released to external bus master.
Bus request output
BREQO
Output
External bus request signal used when
internal bus master accesses external
address space when external bus is
released.
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Section 6 Bus Controller (BSC)
Name
Symbol
I/O
Function
Data transfer acknowledge 1
(DMAC)
DACK1
Output
Data transfer acknowledge signal for
single address transfer by DMAC channel
1.
Data transfer acknowledge 0
(DMAC)
DACK0
DACK0
Data transfer acknowledge signal for
single address transfer by DMAC channel
0.
Data transfer acknowledge 3*2 EDACK3*2 Output
(EXDMAC)
Data transfer acknowledge signal for
single address transfer by EXDMAC
channel 3.
Data transfer acknowledge 2*2
(EXDMAC)
Data transfer acknowledge signal for
single address transfer by EXDMAC
channel 2.
EDACK2*2 Output
Notes: 1. Not supported by the H8S/2456 Group and H8S/2454 Group
2. Not supported by the H8S/2454 Group.
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6.3
Section 6 Bus Controller (BSC)
Register Descriptions
The bus controller has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bus width control register (ABWCR)
Access state control register (ASTCR)
Wait control register AH (WTCRAH)
Wait control register AL (WTCRAL)
Wait control register BH (WTCRBH)
Wait control register BL (WTCRBL)
Read strobe timing control register (RDNCR)
CS assertion period control register H (CSACRH)
CS assertion period control register L (CSACRL)
Area 0 burst ROM interface control register (BROMCRH)
Area 1 burst ROM interface control register (BROMCRL)
Bus control register (BCR)
Address/data multiplexed I/O control register (MPXCR)
DRAM control register (DRAMCR)
DRAM access control register (DRACCR)
Refresh control register (REFCR)
Refresh timer counter (RTCNT)
Refresh time constant register (RTCOR)
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Section 6 Bus Controller (BSC)
6.3.1
Bus Width Control Register (ABWCR)
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
Bit Name
Initial Value*
R/W
Description
7
ABW7
1/0
R/W
Area 7 to 0 Bus Width Control
6
ABW6
1/0
R/W
5
ABW5
1/0
R/W
4
ABW4
1/0
R/W
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
3
ABW3
1/0
R/W
2
ABW2
1/0
R/W
1
ABW1
1/0
R/W
0
ABW0
1/0
R/W
Note:
6.3.2
*
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
(n = 7 to 0)
In modes 2 and 4, ABWCR is initialized to 1. In modes 1 and 7, ABWCR is initialized to
0.
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
Bit Name
Initial Value
R/W
Description
7
AST7
1
R/W
Area 7 to 0 Access State Control
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
0: Area n is designated as 2-state access
space
Wait state insertion in area n access is
disabled
1: Area n is designated as 3-state access
space
Wait state insertion in area n access is
enabled
(n = 7 to 0)
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6.3.3
Section 6 Bus Controller (BSC)
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,
and WTCRBL)
WTCRA and WTCRB select the number of program wait states for each area in the external
address space.
In addition, CAS latency is set when a synchronous DRAM* is connected.
Note: * The synchronous DRAM interface is not supported by the H8S/2456 Group and
H8S/2454 Group.
• WTCRAH
Bit
Bit Name
Initial Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
W72
1
R/W
Area 7 Wait Control 2 to 0
13
W71
1
R/W
12
W70
1
R/W
These bits select the number of program wait
states when accessing area 7 while AST7 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
W62
1
R/W
Area 6 Wait Control 2 to 0
9
W61
1
R/W
8
W60
1
R/W
These bits select the number of program wait
states when accessing area 6 while AST6 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WTCRAL
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
W52
1
R/W
Area 5 Wait Control 2 to 0
5
W51
1
R/W
4
W50
1
R/W
These bits select the number of program wait
states when accessing area 5 while AST5 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
W42
1
R/W
Area 4 Wait Control 2 to 0
1
W41
1
R/W
0
W40
1
R/W
These bits select the number of program wait
states when accessing area 4 while AST4 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WTCRBH
Bit
Bit Name
Initial Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
W32
1
R/W
Area 3 Wait Control 2 to 0
13
W31
1
R/W
12
W30
1
R/W
These bits select the number of program wait
states when accessing area 3 while AST3 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
W22
1
R/W
Area 2 Wait Control 2 to 0
9
W21
1
R/W
8
W20
1
R/W
These bits select the number of program wait
states when accessing area 2 while AST2 bit in
ASTCR = 1.
A CAS latency is set when the synchronous
DRAM* is connected. The setting of area 2 is
reflected to the setting of areas 2 to 5. A CAS
latency can be set regardless of whether or not an
ASTCR wait state insertion is enabled.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
000: Synchronous DRAM of CAS latency 1 is
connected to areas 2 to 5.
001: Synchronous DRAM of CAS latency 2 is
connected to areas 2 to 5.
010: Synchronous DRAM of CAS latency 3 is
connected to areas 2 to 5.
011: Synchronous DRAM of CAS latency 4 is
connected to areas 2 to 5.
1XX: Setting prohibited.
[Legend]
X:
Don't care.
Note: * The synchronous DRAM interface is not supported by the H8S/2456 Group and
H8S/2454 Group.
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Section 6 Bus Controller (BSC)
• WTCRBL
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
W12
1
R/W
Area 1 Wait Control 2 to 0
5
W11
1
R/W
4
W10
1
R/W
These bits select the number of program wait
states when accessing area 1 while AST1 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
W02
1
R/W
Area 0 Wait Control 2 to 0
1
W01
1
R/W
0
W00
1
R/W
These bits select the number of program wait
states when accessing area 0 while AST0 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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6.3.4
Section 6 Bus Controller (BSC)
Read Strobe Timing Control Register (RDNCR)
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
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As shown in figure 6.2, the read strobe for an area
for which the RDNn bit is set to 1 is negated one
half-state earlier than that for an area for which the
RDNn bit is cleared to 0. The read data setup and
hold time specifications are also one half-state
earlier.
0: In an area n read access, the RD is negated at
the end of the read cycle
1: In an area n read access, the RD is negated
one half-state before the end of the read cycle
(n = 7 to 0)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
RD
RDNn = 0
Data
RD
RDNn = 1
Data
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
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6.3.5
Section 6 Bus Controller (BSC)
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the Th cycle is to
be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state Th cycle, in which only the CSn and
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Th) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Th) is extended
(n = 7 to 0)
• CSACRL
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the Tt cycle
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state Tt cycle, in which only the
CSn and address signals are asserted, is inserted
after the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Tt) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Tt) is extended
(n = 7 to 0)
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Section 6 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
Tt
φ
Address
CS
RD
Read
Data
HWR, LWR
Write
Data
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)
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6.3.6
Section 6 Bus Controller (BSC)
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL)
BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1
burst ROM interface settings can be made independently in BROMCRH and BROMCRL,
respectively.
Bit
Bit Name
Initial Value
R/W
Description
7
BSRMn
0
R/W
Burst ROM Interface Select
Selects the basic bus interface or burst ROM
interface.
0: Basic bus interface space
1: Burst ROM interface space
6
BSTSn2
0
R/W
Burst Cycle Select
5
BSTSn1
0
R/W
These bits select the number of burst cycle states.
4
BSTSn0
0
R/W
000: 1 state
001: 2 states
010: 3 states
011: 4 states
100: 5 states
101: 6 states
110: 7 states
111: 8 states
3
⎯
0
R/W
Reserved
2
⎯
0
R/W
These bits are always read as 0. The initial value
should not be changed.
1
BSWDn1
0
R/W
Burst Word Number Select
0
BSWDn0
0
R/W
These bits select the number of words that can be
burst-accessed on the burst ROM interface.
00: Maximum 4 words
01: Maximum 8 words
10: Maximum 16 words
11: Maximum 32 words
(n = 1 or 0)
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Section 6 Bus Controller (BSC)
6.3.7
Bus Control Register (BCR)
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
Bit Name
Initial Value
R/W
15
BRLE
0
R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used
as I/O ports
1: External bus release enabled
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal bus
master performs an external address space
access, or when a refresh request is generated.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
13
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
12
IDLC
1
R/W
Idle Cycle State Number Select
Specifies the number of states in the idle cycle set
by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
11
ICIS1
1
R/W
Idle Cycle Insert 1
When consecutive external read cycles are
executed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
ICIS0
1
R/W
Idle Cycle Insert 0
When an external read cycle and external write
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
9
WDBE
0
R/W
Write Data Buffer Enable
The write data buffer function can be used for an
external write cycle or DMAC single address
transfer cycle.
0: Write data buffer function not used
1: Write data buffer function used
8
WAITE
0
R/W
WAIT Pin Enable
Selects enabling or disabling of wait input by the
WAIT pin.
0: Wait input by WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input by WAIT pin enabled
7 to 3 ⎯
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
2
ICIS2
0
R/W
Idle Cycle Insert 2
When an external write cycle and external read
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
1, 0
⎯
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
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Section 6 Bus Controller (BSC)
6.3.8
Address/Data Multiplexed I/O Control Register (MPXCR)
MPXCR is used to make address/data multiplexed I/O interface settings.
Bit
Bit Name
Initial Value
R/W
Description
7
MPXE
0
R/W
Address/Data Multiplexed I/O Interface Enable
These bits select the bus interface for areas 6 and
7.
0: Basic bus interface
1: Address/data multiplexed I/O interface
6 to 1 ⎯
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
0
ADDEX
0
R/W
Address Output Cycle Extension
Specifies whether a wait cycle is inserted for the
address output cycle of the address/data
multiplexed I/O interface.
0: No wait cycle inserted
1: One wait cycle inserted
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6.3.9
Section 6 Bus Controller (BSC)
DRAM Control Register (DRAMCR)
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
Bit
Bit Name
Initial Value
R/W
Description
15
OEE
0
R/W
OE Output Enable
The OE signal used when EDO page mode DRAM
is connected can be output. The OE signal is
common to all areas designated as DRAM space.
When the synchronous DRAM is connected, the
CKE signal can be output. The CKE signal is
common to the continuous synchronous DRAM
space.
0: OE/CKE signal output disabled
OE/CKE pin can be used as an I/O port.
1: OE/CKE signal output enabled.
14
RAST
0
R/W
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS signal
is asserted from the start of the Tr cycle (rising
edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in Tr cycle
1: RAS is asserted from start of Tr cycle
13
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
12
CAST
0
R/W
Column Address Output Cycle Number Select
Selects whether the column address output cycle
in DRAM access comprises 3 states or 2 states.
The setting of this bit applies to all areas
designated as DRAM space.
0: Column address output cycle comprises
2 states
1: Column address output cycle comprises
3 states
11
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
RMTS2
0
R/W
9
RMTS1
0
R/W
DRAM/Continuous Synchronous DRAM Space
Select
8
RMTS0
0
R/W
These bits designate DRAM/continuous
synchronous DRAM space for areas 2 to 5.
When continuous DRAM space is set, it is
possible to connect large-capacity DRAM
exceeding 2 Mbytes per area. In this case, the
RAS signal is output from the CS2 pin.
When continuous synchronous DRAM space is
set, it is possible to connect large-capacity
synchronous DRAM exceeding 2 Mbytes per area.
In this case, the RAS, CAS, and WE signals are
output from CS2, CS3, and CS4 pins,
respectively. When synchronous DRAM mode is
set, the mode registers of the synchronous DRAM
can be set.
000: Normal space
001: Normal space in areas 3 to 5
DRAM space in area 2
010: Normal space in areas 4 and 5
DRAM space in areas 2 and 3
011: DRAM space in areas 2 to 5
100: Continuous synchronous DRAM space
(setting possible only in H8S/2456R Group)
101: Synchronous DRAM mode setting (setting
possible only in H8S/2456R Group)
110: Setting prohibited
111: Continuous DRAM space in areas 2 to 5
7
BE
0
R/W
Burst Access Enable
Selects enabling or disabling of burst access to
areas designated as DRAM/continuous
synchronous DRAM space. DRAM/continuous
synchronous DRAM space burst access is
performed in fast page mode. When using EDO
page mode DRAM, the OE signal must be
connected.
0: Full access
1: Access in fast page mode
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
6
RCDM
0
R/W
RAS Down Mode
When access to DRAM space is interrupted by an
access to normal space, an access to an internal
I/O register, etc., this bit selects whether the RAS
signal is held low while waiting for the next DRAM
access (RAS down mode), or is driven high again
(RAS up mode). The setting of this bit is valid only
when the BE bit is set to 1.
If this bit is cleared to 0 when set to 1 in the RAS
down state, the RAS down state is cleared at that
point, and RAS goes high.
When continuous synchronous DRAM space is
set, reading from and writing to this bit is enabled.
However, the setting does not affect the operation.
0: RAS up mode selected for DRAM space access
1: RAS down mode selected for DRAM space
access
5
DDS
0
R/W
DMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when DMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, DMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.
This bit has no effect on other bus master external
accesses or DMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
4
EDDS
0
R/W
EXDMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when EXDMAC single
address transfer is performed on the
DRAM/synchronous DRAM.
When the BE bit is cleared to 0 in DRAMCR,
disabling DRAM/synchronous DRAM burst
access, EXDMAC single address transfer is
performed in full access mode regardless of the
setting of this bit.
This bit has no effect on other bus master external
accesses or EXDMAC dual address transfers.
0: Full access is always executed
1: Burst access is enabled
3
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
MXC2
0
R/W
Address Multiplex Select
1
MXC1
0
R/W
0
MXC0
0
R/W
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM/synchronous DRAM
interface, these bits also select the row address
bits to be used for comparison.
When the MXC2 bit is set to 1 while continuous
synchronous DRAM space is set, the address
precharge setting command (Precharge-sel) is
output to the upper column address. For details,
refer to sections 6.7.2 and 6.8.2, Address
Multiplexing.
DRAM interface
000: 8-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
001: 9-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
010: 10-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
MXC2
0
R/W
011: 11-bit shift
1
MXC1
0
R/W
•
0
MXC0
0
R/W
When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
Synchronous DRAM interface
100: 8-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
The precharge-sel is A15 to A9 of the column
address.
101: 9-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
The precharge-sel is A15 to A10 of the column
address.
110: 10-bit shift
•
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
The precharge-sel is A15 to A11 of the column
address.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
2
MXC2
0
R/W
111: 11-bit shift
1
MXC1
0
R/W
•
0
MXC0
0
R/W
When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
•
When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
The precharge-sel is A15 to A12 of the column
address.
Bus cycle
Tp
Tr
Tc1
Tc2
φ
Row address
Address
Column address
RAST = 0 RAS
RAST = 1 RAS
UCAS, LCAS
Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)
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6.3.10
Section 6 Bus Controller (BSC)
DRAM Access Control Register (DRACCR)
DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
Bit
Bit Name
Initial Value
R/W
Description
15
DRMI
0
R/W
Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when a
continuous normal space access cycle follows a
DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
14
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
13
TPC1
0
R/W
Precharge State Control
12
TPC0
0
R/W
These bits select the number of states in the RAS
precharge cycle in normal access and refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
11
SDWCD
0*
R/W
CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tcl) inserted
by WTCRB (H) settings during synchronous
DRAM write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
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Bit
Bit Name
Initial Value
R/W
Description
10
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
9
RCD1
0
R/W
RAS-CAS Wait Control
8
RCD0
0
R/W
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted
7 to 4 ⎯
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
3
CKSPE*
0
R/W
Clock Suspend Enable
Enables clock suspend mode for extend read data
during DMAC and EXDMAC single address
transfer with the synchronous DRAM interface.
0: Disables clock suspend mode
1: Enables clock suspend mode
2
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
1
0
RDXC1*
RDXC0*
0
R/W
Read Data Extension Cycle Number Selection
0
R/W
Selects the number of read data extension cycle
(Tsp) insertion state in clock suspend mode.
These bits are valid when the CKSPE bit is set to
1.
00: Inserts 1 state
01: Inserts 2 state
10: Inserts 3 state
11: Inserts 4 state
Note:
*
Not supported by the H8S/2456 Group and H8S/2454 Group.
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address
Precharge-sel
Column address
Row address
Row address
RAS
SDWCD 0
CAS
WE
CKE
High
DQMU, DQML
Data bus
Address bus
PALL
ACTV
NOP
WRIT
Tp
Tr
Tc1
Tc2
Column address
Precharge-sel
Row address
NOP
Column address
Row address
RAS
SDWCD 1
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.3.11
Refresh Control Register (REFCR)
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
Bit
Bit Name
Initial Value
R/W
Description
15
CMF
0
R/(W)*
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
When 0 is written to CMF after reading CMF =
1 while the RFSHE bit is cleared to 0
•
When CBR refreshing is executed while the
RFSHE bit is set to 1
[Setting condition]
When RTCOR = RTCNT
14
CMIE
0
R/W
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
13
RCW1
0
R/W
CAS-RAS Wait Control
12
RCW0
0
R/W
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Note:
*
Only 0 can be written, to clear the flag.
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
11
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
10
RTCK2
0
R/W
Refresh Counter Clock Select
9
RTCK1
0
R/W
8
RTCK0
0
R/W
These bits select the clock to be used to
increment the refresh counter. When the input
clock is selected with bits RTCK2 to RTCK0, the
refresh counter begins counting up.
000: Count operation halted
001: Count on φ/2
010: Count on φ/8
011: Count on φ/32
100: Count on φ/128
101: Count on φ/512
110: Count on φ/2048
111: Count on φ/4096
7
RFSHE
0
R/W
Refresh Control
Refresh control can be performed. When refresh
control is not performed, the refresh timer can be
used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
6
CBRM
0
R/W
CBR Refresh Mode
Selects CBR refreshing performed in parallel with
other external accesses, or execution of CBR
refreshing alone.
When the continuous synchronous DRAM space
is set, this bit can be read/written, but the setting
contents do not affect operations.
0: External access during CAS-before-RAS
refreshing is enabled
1: External access during CAS-before-RAS
refreshing is disabled
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
5
RLW1
0
R/W
Refresh Cycle Wait Control
4
RLW0
0
R/W
These bits select the number of wait states to be
inserted in a DRAM interface CAS-before-RAS
refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas
designated as DRAM/continuous synchronous
DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
3
SLFRF
0
R/W
Self-Refresh Enable
If this bit is set to 1, DRAM/synchronous DRAM
self-refresh mode is selected when a transition is
made to the software standby state. This bit is
valid when the RFSHE bit is set to 1, enabling
refresh operations. It is cleared after recovery from
software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
2
TPCS2
0
R/W
Self-Refresh Precharge Cycle Control
1
TPCS1
0
R/W
0
TPCS0
0
R/W
These bits select the number of states in the
precharge cycle immediately after self-refreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to the
number of states set by bits TPC1 and TPC0 in
DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states
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6.3.12
Section 6 Bus Controller (BSC)
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock
selected by bits RTCK2 to RTCK0 in REFCR.
When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and
RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is
started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match
interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
6.3.13
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that sets the period for compare match operations
with RTCNT.
The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in
REFCR is set to 1 and RTCNT is cleared to H'00.
RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Section 6 Bus Controller (BSC)
6.4
Bus Control
6.4.1
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,
and performs bus control for external address space in area units. Chip select signals (CS0 to CS7)
can be output for each area. In normal mode, a part of area 0, 64-Kbyte address space, is
controlled. Figure 6.6 shows an outline of the memory map.
H'000000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
Figure 6.6 Area Divisions
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6.4.2
Section 6 Bus Controller (BSC)
Bus Specifications
The external address space bus specifications consist of five elements: bus width, number of
access states, number of program wait states, read strobe timing, and chip select (CS) assertion
period extension states. The bus width and number of access states for on-chip memory and
internal I/O registers are fixed, and are not affected by the bus controller.
(1)
Bus Width
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is
selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions
as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if
any area is designated as 16-bit access space, 16-bit bus mode is set.
(2)
Number of Access States
Two or three access states can be selected with ASTCR. An area for which 2-state access is
selected functions as a 2-state access space, and an area for which 3-state access is selected
functions as a 3-state access space. With the DRAM or synchronous DRAM interface and burst
ROM interface, the number of access states may be determined without regard to the setting of
ASTCR.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the WAIT pin.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
(3)
Number of Program Wait States
When 3-state access space is designated by ASTCR, the number of program wait states to be
inserted automatically is selected with WTCRA and WTCRB. From 0 to 7 program wait states can
be selected. Table 6.2 shows the bus specifications (bus width, and number of access states and
program wait states) for each basic bus interface area.
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Section 6 Bus Controller (BSC)
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
ABWn
ASTn
Wn2
Wn1
Wn0
Bus Width
Access
States
Program Wait
States
0
0
⎯
⎯
⎯
16
2
0
1
0
0
0
3
0
WTCRA, WTCRB
1
1
0
2
1
3
0
0
4
1
5
1
0
6
1
7
1
1
1
0
⎯
⎯
⎯
1
0
0
0
1
1
Bus Specifications (Basic Bus Interface)
0
1
8
2
0
3
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
(n = 0 to 7)
(4)
Read Strobe Timing
RDNCR can be used to select either of two negation timings (at the end of the read cycle or one
half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface
space.
(5)
Chip Select (CS) Assertion Period Extension States
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. CSACR can be used to insert states in which only the
CS, AS, and address signals are asserted before and after a basic bus space access cycle.
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6.4.3
Section 6 Bus Controller (BSC)
Memory Interfaces
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; an address/data multiplexed I/O interface that allows direct connection
of peripheral LSIs that require address/data multiplexing, a DRAM interface that allows direct
connection of DRAM; a synchronous DRAM interface that allows direct connection of
synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The
interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space. An area for
which the address/data multiplexed I/O interface is designated functions as address/data
multiplexed I/O space, an area for which the DRAM interface is designated functions as DRAM
space, an area for which the synchronous DRAM interface is designated functions as continuous
synchronous DRAM space, and an area for which the burst ROM interface is designated functions
as burst ROM space.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
(1)
Area 0
Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space
excluding on-chip ROM is external address space, and in expanded mode with on-chip ROM
disabled, all of area 0 is external address space.
When area 0 external space is accessed, the CS0 signal can be output.
Either the basic bus interface or burst ROM interface can be selected for the memory interface of
area 0.
(2)
Area 1
In externally expanded mode, all of area 1 is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Either the basic bus interface or burst ROM interface can be selected for the memory interface of
area 1.
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Section 6 Bus Controller (BSC)
(3)
H8S/2456, H8S/2456R, H8S/2454 Group
Areas 2 to 5
In externally expanded mode, areas 2 to 5 are all external address space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the
memory interface of areas 2 to 5. With the DRAM interface, signals CS2 and CS5 are used as
RAS signals.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM
space.
If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are
used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The
OE pin is used as the CKE signal.
(4)
Area 6
In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Either the basic bus interface or address/data multiplexed I/O interface can be used for the
memory interface of area 6.
(5)
Area 7
Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space
excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM
is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Either the basic bus interface or address/data multiplexed I/O interface can be used for the
memory interface of area 7.
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6.4.4
Section 6 Bus Controller (BSC)
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
and PFCR0 bits should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits and PFCR0 bits should be set to 1 when
outputting signals CS0 to CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.
When areas 2 to 5 are designated as continuous synchronous DRAM* space in the H8S/2456R
Group, outputs CS2, CS3, CS4, and CS5 are used as RAS, CAS, WE, and CLK signals.
Note: The A23E bit in PFCR1 should be cleared to 0 when CS7 signal is output in the H8S/2454
Group.
* The synchronous DRAM interface is not supported by the H8S/2456 Group and
H8S/2454 Group.
Bus cycle
T1
T2
T3
φ
Address bus
Area n external address
CSn
Figure 6.7 CSn Signal Output Timing (n = 0 to 7)
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Section 6 Bus Controller (BSC)
6.5
Basic Bus Interface
The basic bus interface enables direct connection of ROM, SRAM, and so on.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external address space, controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
(1)
8-Bit Access Space
Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word access is performed as two byte accesses, and a longword
access, as four byte accesses.
Upper data bus
D15
Lower data bus
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword
size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)
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(2)
Section 6 Bus Controller (BSC)
16-Bit Access Space
Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access
space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The
amount of data that can be accessed at one time is one byte or one word, and a longword access is
executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Upper data bus
D15
Byte size
• Even address
Byte size
• Odd address
Lower data bus
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
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Section 6 Bus Controller (BSC)
6.5.2
Valid Strobes
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3
Data Buses Used and Valid Strobes
Access
Size
Read/
Write
Address
Valid
Strobe
Upper Data Bus Lower Data
(D15 to D8)
Bus (D7 to D0)
8-bit access
space
Byte
Read
⎯
RD
Valid
Write
⎯
HWR
16-bit access
space
Byte
Read
Even
RD
Area
Odd
Hi-Z
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Hi-Z
Odd
LWR
Hi-Z
Valid
Read
⎯
RD
Valid
Valid
Write
⎯
HWR, LWR
Valid
Valid
Write
Word
Invalid
Note: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
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6.5.3
(1)
Section 6 Bus Controller (BSC)
Basic Timing
8-Bit, 2-State Access Space
Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high.
Wait states can be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space
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Section 6 Bus Controller (BSC)
(2)
8-Bit, 3-State Access Space
Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high.
Wait states can be inserted.
Bus cycle
T1
T3
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
High
LWR
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space
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(3)
Section 6 Bus Controller (BSC)
16-Bit, 2-State Access Space
Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space
(Word Access)
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Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Access Space
Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the
lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Bus cycle
T1
T3
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space
(Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space
(Word Access)
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6.5.4
Section 6 Bus Controller (BSC)
Wait Control
When accessing external space, this LSI can extend the bus cycle by inserting one or more wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
(1)
Program Wait Insertion
From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an
individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB.
(2)
Pin Wait Insertion
Setting the WAITE bit to 1 in BCR enables wait input by means of the WAIT pin. When external
space is accessed in this state, a program wait is first inserted in accordance with the settings in
WTCRA and WTCRB. If the WAIT pin is low at the falling edge of φ in the last T2 or Tw state,
another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high.
This is useful when inserting seven or more Tw states, or when changing the number of Tw states to
be inserted for different external devices. The WAITE bit setting applies to all areas. Figure 6.18
shows an example of wait state insertion timing.
The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input
disabled.
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Section 6 Bus Controller (BSC)
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Notes: 1. Downward arrows indicate the timing of WAIT pin sampling.
2. When RDNn = 0
Figure 6.18 Example of Wait State Insertion Timing
6.5.5
Read Strobe (RD) Timing
The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to
1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed
in basic bus 3-state access space.
When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is
changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or
EDACK.
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
RDNn = 0
Data bus
RD
RDNn = 1
Data bus
DACK,
EDACK
Figure 6.19 Example of Read Strobe Timing
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Section 6 Bus Controller (BSC)
6.5.6
Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Bus cycle
Th
T1
T2
T3
Tt
φ
Address bus
CSn
AS
Read
(when
RDNn = 0)
RD
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended
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Section 6 Bus Controller (BSC)
Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0).
6.6
Address/Data Multiplexed I/O Interface
If areas 6 and 7 of the external address space are specified as address/data multiplexed I/O space
in this LSI, the address/data multiplexed I/O interfacing can be performed. In the address/data
multiplexed I/O interface, peripheral LSIs that require address/data multiplexing can be connected
directly to this LSI.
6.6.1
Setting Address/Data Multiplexed I/O Space
In the address/data multiplexed I/O interface, areas 6 and 7 are designated as the address/data
multiplexed I/O space by setting the MPXE bit in MPXCR to 1.
6.6.2
Address/Data Multiplexing
With the address/data multiplexed I/O space, the data bus and address bus are multiplexed. Table
6.4 shows the relation between the bus width and corresponding address output.
Table 6.4
Multiplexed Address/Data
Data Pins
Bus
Width
Cycle
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
8 bits
Address
A7
A6
A5
A4
A3
A2
A1
A0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Data
D15
D14
D13
D12
D11
D10
D9
D8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Address
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
16 bits
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Section 6 Bus Controller (BSC)
6.6.3
H8S/2456, H8S/2456R, H8S/2454 Group
Data Bus
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access
space, AD15 to AD8 are valid for both address and data. For the 16-bit access space, AD15 to
AD0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the
corresponding address will be output to the address bus. For details on access size and data
alignment, see section 6.5.1, Data Size and Data Alignment.
6.6.4
Address Hold Signal
In the address/data multiplexed I/O space, a hold signal (AH) that indicates the timing for latching
the address is output. The AH output pin is multiplexed with the AS output pin. When the external
address space is specified as the address/data multiplexed I/O space, the multiplexed pin functions
as the AH output pin. Note however that the multiplexed pin will function as the AS output pin
until the address/data multiplexed I/O space is specified.
6.6.5
Basic Timing
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data
cycle. The data cycle is based on the basic bus interface timing specified by ABWCR, ASTCR,
WTCRAH, RDNCR, and CSACR.
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(1)
Section 6 Bus Controller (BSC)
8-Bit, 2-State Data Access Space
Figure 6.21 shows the bus timing for an 8-bit, 2-state data access space. When an 8-bit access
space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used.
Wait states cannot be inserted in the data cycle.
Address cycle
Tma1
Tma2
Data cycle
T1
T2
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Read
data
Address
HWR
LWR
Write
AD15 to AD8
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.21 Bus Timing for 8-Bit, 2-State Data Access Space
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Section 6 Bus Controller (BSC)
(2)
8-Bit, 3-State Data Access Space
Figure 6.22 shows the bus timing for an 8-bit, 3-state data access space. When an 8-bit access
space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used.
Wait states can be inserted in the data cycle.
Address cycle
Tma1
Tma2
Data cycle
T1
T2
T3
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Read
data
Address
HWR
LWR
Write
AD15 to AD8
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.22 Bus Timing for 8-Bit, 3-State Data Access Space
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(3)
Section 6 Bus Controller (BSC)
16-Bit, 2-State Data Access Space
Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access
space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper
half (AD15 to AD0) of the data bus is used for even addresses and the lower half (AD7 to AD0) of
the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle.
Address cycle
Tma1
Tma2
Data cycle
T1
T2
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.23 Bus Timing for 16-Bit, 2-State Data Access Space (Even Address Byte Access)
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Address cycle
Tma1
Tma2
Data cycle
T1
T2
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Address cycle
Tma1
Tma2
Data cycle
T1
T2
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
Read
data
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
Write data
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.25 Bus Timing for 16-Bit, 2-State Data Access Space
(Word Access)
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Section 6 Bus Controller (BSC)
(4)
16-Bit, 3-State Data Access Space
Figures 6.26 to 6.28 show bus timings for a 16-bit, 3-state data access space. When a 16-bit access
space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper
half (AD15 to AD8) of the data bus is used for even addresses and the lower half (AD7 to AD0) of
the data bus is used for odd addresses. Wait states can be inserted in the data cycle.
Address cycle
Tma1
Tma2
Data cycle
T1
T2
T3
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 1
Figure 6.26 Bus Timing for 16-Bit, 3-State Data Access Space
(Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Address cycle
Tma1
Tma2
Data cycle
T1
T2
T3
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 1
Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space
(Odd Address Byte Access)
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Address cycle
Tma1
Tma2
Data cycle
T1
T2
T3
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
Read
data
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
Write data
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 1
Figure 6.28 Bus Timing for 16-Bit, 3-State Data Access Space
(Word Access)
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6.6.6
(1)
Section 6 Bus Controller (BSC)
Wait Control
Address Cycle
A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the
ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three
cycles.
Address cycle
Tma1
Tmaw
Data cycle
Tma2
T1
T2
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.29 Example of Access Timing with Address Wait
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Section 6 Bus Controller (BSC)
(2)
Data Cycle
In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the
same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait
control settings do not affect the address cycles.
6.6.7
Read Strobe (RD) Timing
In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified
in the same way as in the basic bus interface. For details, refer to section 6.5.5, Read Strobe (RD)
Timing. Figure 6.30 shows an example when the read strobe timing is modified.
Address cycle
Tma1
Tma2
Data cycle
T1
T2
φ
Address bus
CSn
AH
RD
RDNn = 0
AD15 to AD8
Read
data
Address
RD
RDNn = 1
AD15 to AD8
Address
Read
data
Note: n = 6, 7
Figure 6.30 Example of Read Strobe Timing
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6.6.8
Section 6 Bus Controller (BSC)
Extension of Chip Select (CS) Assertion Period in Data Cycle
In the address/data multiplexed I/O interface, extension cycles can be inserted before and after the
data cycle. For details, see section 6.5.6, Extension of Chip Select (CS) Assertion Period. Figure
6.31 shows an example of the timing when the chip select assertion period is extended in the data
cycle.
Address cycle
Tma1
Tma2
Data cycle
Th
T1
T2
Tt
φ
Address bus
CSn
AH
RD
Read
AD15 to AD8
Address
Read
data
AD7 to AD0
Address
Read
data
HWR
LWR
Write
AD15 to AD8
Address
Write data
AD7 to AD0
Address
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.31 Example of Timing when Chip Select Assertion Period Is Extended
in Data Cycle
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When consecutively reading from the same area connected to a peripheral LSI whose output
floating time is long, data outputs from the peripheral LSI may conflict with address outputs from
this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle
after the access cycle. Figure 6.32 shows an example of the operation. In the figure, both bus
cycles A and B are read access cycles to the same area which is address/data multiplexed I/O
space. (a) shows an example of conflict occurring between data outputs from the peripheral LSI
whose output floating time is long and address outputs from this LSI because the CS assertion
period extension cycle is not inserted. (b) shows an example of the data conflict being avoided by
inserting the CS assertion period extension cycle.
Bus cycle A
Bus cycle A
Bus cycle B
φ
φ
Address bus
Address bus
CS
CS
AH
WR
RD
RD
Address/data
bus
Address/data
bus
Bus cycle B
Data conflict
Output floating
time is long
(a) Without CS assertion period extension cycle
(CSXTn = 0)
(b) With CS assertion period extension cycle
(CSXTn = 1)
Figure 6.32 Consecutive Read Accesses to Same Area
(Address/Data Multiplexed I/O Space)
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6.7
Section 6 Bus Controller (BSC)
DRAM Interface
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.7.1
Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.5
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS2
RMTS1
RMTS0
Area 5
Area 4
Area 3
Area 2
0
0
1
Normal space
Normal space
Normal space
DRAM space
1
0
Normal space
Normal space
DRAM space
DRAM space
1
DRAM space
DRAM space
DRAM space
DRAM space
0
Continuous synchronous DRAM space*
1
Mode register settings of synchronous DRAM*
0
Reserved (setting prohibited)
1
Continuous
DRAM space
1
0
1
Note:
*
Continuous
DRAM space
Continuous
DRAM space
Continuous
DRAM space
Reserved (setting prohibited) in the H8S/2456 Group and H8S/2454 Group.
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
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Section 6 Bus Controller (BSC)
6.7.2
Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
Table 6.6
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR
Address Pins
A23
Row
MXC2
MXC1
MXC0
0
0
0
Shift
to
Size
A16 A15 A14 A13 A12 A11 A10 A9
8 bits
address
A8
A7
A6
A5
A4
A3
A2
A23 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A1
A0
A9
A8
A23 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
to
A16
1
9 bits
to
A16
1
0
10 bits
A23 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
to
A16
1
11 bits
A23 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
to
A16
Column
1
×
×
0
×
×
address
Reserved (setting prohibited)
⎯
A23 A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
to
A16
1
×
×
Reserved (setting prohibited)
[Legend]
×:
Don't care.
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6.7.3
Section 6 Bus Controller (BSC)
Data Bus
If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
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Section 6 Bus Controller (BSC)
6.7.4
Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions.
Table 6.7
DRAM Interface Pins
Pin
With DRAM
Setting
Name
I/O
Function
HWR
WE
Write enable
Output
Write enable for DRAM space
access
CS2
RAS2
Row address strobe 2
Output
Row address strobe when area
2 is designated as DRAM space
or row address strobe when
areas 2 to 5 are designated as
continuous DRAM space
CS3
RAS3
Row address strobe 3
Output
Row address strobe when area
3 is designated as DRAM space
CS4
RAS4
Row address strobe 4
Output
Row address strobe when area
4 is designated as DRAM space
CS5
RAS5
Row address strobe 5
Output
Row address strobe when area
5 is designated as DRAM space
UCAS
UCAS
Upper column address
strobe
Output
Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access
LCAS
LCAS
Lower column address
strobe
Output
Lower column address strobe
signal for 16-bit DRAM space
access
RD, OE
OE
Output enable
Output
Output enable signal for DRAM
space access
WAIT
WAIT
Wait
Input
Wait request signal
A15 to A0
A15 to A0
Address pins
Output
Row address/column address
multiplexed output
D15 to D0
D15 to D0
Data pins
I/O
Data input/output pins
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6.7.5
Section 6 Bus Controller (BSC)
Basic Timing
Figure 6.33 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address
output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.33 DRAM Basic Access Timing (RAST = 0, CAST = 0)
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When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM
space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output
from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,
the signal is output only from the RD pin.
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6.7.6
Section 6 Bus Controller (BSC)
Column Address Output Cycle Control
The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34
shows an example of the timing when a 3-state column address output cycle is selected.
Tp
Tr
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.34 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0)
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Section 6 Bus Controller (BSC)
6.7.7
Row Address Output State Control
If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
frequency of this LSI. Figure 6.35 shows an example of the timing when the RAS signal goes low
from the beginning of the Tr state.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.35 Example of Access Timing when RAS Signal Goes Low from Beginning
of Tr State (CAST = 0)
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Section 6 Bus Controller (BSC)
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained,
to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the RAS signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.36 shows an example of the timing when one Trw state is set.
Tp
Tr
Trw
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.36 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
6.7.8
Precharge State Control
When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is
always inserted when DRAM space is accessed. From one to four Tp states can be selected by
setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the
DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when
two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh
cycles.
Tp1
Tp2
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.37 Example of Timing with Two-State Precharge Cycle
(RAST = 0, CAST = 0)
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6.7.9
Section 6 Bus Controller (BSC)
Wait Control
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and
pin wait insertion using the WAIT pin.
Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and
to extend the write data setup time relative to the falling edge of CAS in a write access.
(1)
Program Wait Insertion
When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to
7 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the
settings in WTCR.
(2)
Pin Wait Insertion
When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait input by means of the
WAIT pin is enabled. When DRAM space is accessed in this state, a program wait (Tw) is first
inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or Tw state, another Tw state
is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high.
Figures 6.38 and 6.39 show examples of wait cycle insertion timing in the case of 2-state and 3state column address output cycles.
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By program wait
Tp
Tr
Tc1
Tw
By WAIT pin
Tw
Tc2
φ
WAIT
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
Read
WE (HWR)
High
OE (RD)
Data bus
UCAS, LCAS
Write
WE (HWR)
OE (RD)
High
Data bus
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.38 Example of Wait State Insertion Timing
(2-State Column Address Output)
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Tp
Section 6 Bus Controller (BSC)
Tr
By program wait
By WAIT pin
Tc1
Tw
Tw
Tc2
Tc3
φ
WAIT
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
Read
WE (HWR)
High
OE (RD)
Data bus
UCAS, LCAS
Write
WE (HWR)
OE (RD)
High
Data bus
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.39 Example of Wait State Insertion Timing
(3-State Column Address Output)
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Section 6 Bus Controller (BSC)
6.7.10
Byte Access Control
When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the
control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access,
and figure 6.41 shows an example of 2-CAS DRAM connection.
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS
LCAS
High
WE (HWR)
OE (RD)
High
Write data
Upper data bus
High-Z
Lower data bus
Note: n = 2 to 5
Figure 6.40 2-CAS Control Timing
(Upper Byte Write Access: RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
2-CAS type 16-Mbit DRAM
1-Mbyte × 16-bit configuration
10-bit column address
This LSI
(Address shift size
set to 10 bits)
RASn (CSn)
RAS
UCAS
UCAS
LCAS
LCAS
HWR (WE)
RD (OE)
A10
WE
OE
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
Row address input:
A9 to A0
Column address input:
A9 to A0
D15 to D0
Figure 6.41 Example of 2-CAS DRAM Connection
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Section 6 Bus Controller (BSC)
6.7.11
H8S/2456, H8S/2456R, H8S/2454 Group
Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
(1)
Burst Access (Fast Page Mode)
Figures 6.42 and 6.43 show the operation timing for burst access. When there are consecutive
access cycles for DRAM space, the CAS signal and column address output cycles (two states)
continue as long as the row address is the same for consecutive access cycles. The row address
used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
Tc1
Tc2
φ
Address bus
Row address
Column address 1 Column address 2
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
High
OE (RD)
Data bus
Note: n = 2 to 5
Figure 6.42 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 0)
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Tp
Tr
Tc1
Tc2
Tc3
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address 1
Column address 2
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
Note: n = 2 to 5
Figure 6.43 Operation Timing in Fast Page Mode
(RAST = 0, CAST = 1)
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details see section 6.7.9, Wait Control.
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(2)
Section 6 Bus Controller (BSC)
RAS Down Mode and RAS Up Mode
Even when burst operation is selected, it may happen that access to DRAM space is not
continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low
during the access to the other space, burst operation can be resumed when the same row address in
DRAM space is accessed again.
• RAS Down Mode
To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access
to DRAM space is interrupted and another space is accessed, the RAS signal is held low
during the access to the other space, and burst access is performed when the row address of the
next DRAM space access is the same as the row address of the previous DRAM space access.
Figure 6.44 shows an example of the timing in RAS down mode.
Note, however, that the RAS signal will go high if:
⎯ a refresh operation is initiated in the RAS down state
⎯ self-refreshing is performed
⎯ the chip enters software standby mode
⎯ the external bus is released
⎯ the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
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DRAM space read
Tp
Tr
Tc1
Tc2
Normal space
read
DRAM space
read
T1
Tc1
T2
Tc2
φ
Row address
Address bus
Column address 1
External address Column address 2
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2 to 5
Figure 6.44 Example of Operation Timing in RAS Down Mode
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
• RAS Up Mode
To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM
space is interrupted and another space is accessed, the RAS signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of
the timing in RAS up mode.
DRAM space read
Tp
Tr
Tc1
Tc2
DRAM space
read
Normal space
read
Tc1
T1
Tc2
T2
φ
Address bus
Row address
Column address 1 Column address 2
External address
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2 to 5
Figure 6.45 Example of Operation Timing in RAS Up Mode
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
6.7.12
Refresh Control
This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing
is used. In addition, self-refreshing can be executed when the chip enters the software standby
state.
Refresh control is enabled when any area is designated as DRAM space in accordance with the
setting of bits RMTS2 to RMTS0 in DRAMCR.
(1)
CAS-before-RAS (CBR) Refreshing
To select CBR refreshing, set the RFSHE bit to 1 in REFCR.
With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the DRAM used.
When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR
settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is
shown in figure 6.46, compare match timing in figure 6.47, and CBR refresh timing in figure 6.48.
When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is
performed in parallel during the CBR refresh period.
RTCNT
RTCOR
H'00
Refresh request
Figure 6.46 RTCNT Operation
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Section 6 Bus Controller (BSC)
φ
RTCNT
N
H'00
RTCOR
N
Refresh request
signal and CMF bit
setting signal
Figure 6.47 Compare Match Timing
TRp
TRr
TRc1
TRc2
φ
CSn (RASn)
UCAS, LCAS
Figure 6.48 CBR Refresh Timing
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Section 6 Bus Controller (BSC)
A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.49 shows the timing when bits RCW1 and RCW0 are set.
TRp
TRrw
TRr
TRc1
TRc2
φ
CSn (RASn)
UCAS, CAS
Figure 6.49 CBR Refresh Timing
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)
Depending on the DRAM used, modification of the WE signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example
of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and
retains its value prior to the start of the refresh period.
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Normal space access request
φ
A23 to A0
CS
AS
RD
HWR (WE)
Refresh period
RAS
CAS
Figure 6.50 Example of CBR Refresh Timing (CBRM = 1)
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Section 6 Bus Controller (BSC)
(2)
H8S/2456, H8S/2456R, H8S/2454 Group
Self-Refreshing
A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In
this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP
instruction is executed to enter software standby mode, the CAS and RAS signals are output and
DRAM enters self-refresh mode, as shown in figure 6.51.
When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is
exited automatically. If a CBR refresh request occurs when making a transition to software
standby mode, CBR refreshing is executed, and then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.
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TRp
Section 6 Bus Controller (BSC)
Software
standby
TRr
TRc3
φ
CSn (RASn)
UCAS, LCAS
HWR (WE)
High
Note: n = 2 to 5
Figure 6.51 Self-Refresh Timing
In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately
after self-refreshing is longer than the normal precharge time. A setting can be made in bits
TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1
to 7 states longer than the normal precharge time. In this case, too, normal precharging is
performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting
should be made to give the optimum post-self-refresh precharge time, including this time. Figure
6.52 shows an example of the timing when the precharge time immediately after self-refreshing is
extended by 2 states.
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Software
standby
DRAM space write
TRc3
TRp1
TRp2
Tp
Tr
Tc1
Tc2
φ
Address bus
RASn (CSn)
UCAS, LCAS
OE (RD)
WE (HWR)
Data bus
Note: n = 2 to 5
Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States
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Section 6 Bus Controller (BSC)
Refreshing and All-Module-Clocks-Stopped Mode
In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR
= H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is
entered, in which the bus controller and I/O port clocks are also stopped. As the bus controller
clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is connected
externally and DRAM data is to be retained in sleep mode, the ACSE bit must be cleared to 0 in
MSTPCRH.
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Section 6 Bus Controller (BSC)
6.7.13
H8S/2456, H8S/2456R, H8S/2454 Group
DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.
(1)
When DDS = 1 or EDDS = 1
Burst access is performed by determining the address only, irrespective of the bus master. With
the DRAM interface, the DACK or EDACK output goes low from the Tc1 state.
Figure 6.53 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tc2
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
DACK or EDACK
Note: n = 2 to 5
Figure 6.53 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
(2)
When DDS = 0 or EDDS = 0
When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access
(normal access) is always performed. With the DRAM interface, the DACK or EDACK output
goes low from the Tr state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 6.54 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
Tp
Tr
Tc1
Tc2
Tc3
φ
Address bus
Row address
Column address
RASn (CSn)
UCAS, LCAS
WE (HWR)
Read
High
OE (RD)
Data bus
WE (HWR)
Write
OE (RD)
High
Data bus
DACK or EDACK
Note: n = 2 to 5
Figure 6.54 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)
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6.8
Section 6 Bus Controller (BSC)
Synchronous DRAM Interface
In the H8S/2456R Group, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
6.8.1
Setting Continuous Synchronous DRAM Space
Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.8. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.8
Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
RMTS2
RMTS1
RMTS0
Area 5
Area 4
Area 3
Area 2
0
0
1
Normal space
Normal space
Normal space
DRAM space
1
0
Normal space
Normal space
DRAM space
DRAM space
1
DRAM space
DRAM space
DRAM space
DRAM space
0
Continuous synchronous DRAM space
1
Mode settings of synchronous DRAM
0
Reserved (setting prohibited)
1
Continuous DRAM space
1
0
1
With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE
signal. The OE pin of the DRAM is used as the CKE signal, and the CS5 pin is used as
synchronous DRAM clock (SDRAMφ). The bus specifications for continuous synchronous
DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous
synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and
address-precharge-setting command (Precharge-sel) output on the upper column addresses.
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Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.
6.8.2
Address Multiplexing
With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Precharge-sel) can be output on
the upper column address. Table 6.9 shows the relation between the settings of MXC2 to MXC0
and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is
used.
Table 6.9
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR
MXC2
Row
address
MXC1
Address Pins
MXC0
A23 to
A16
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
x
x
1
0
0
8
bits
A23 to
A16
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
A8
1
9
bits
A23 to
A16
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A9
0
10
bits
A23 to
A16
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1
11
bits
A23 to
A16
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
1
Column
address
Shift
Size
Reserved (setting prohibited)
0
×
×
1
0
0
⎯
A23 to
A16
P
P
P
P
P
P
P
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
⎯
A23 to
A16
P
P
P
P
P
P
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
⎯
A23 to
A16
P
P
P
P
P
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
⎯
A23 to
A16
P
P
P
P
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
Reserved (setting prohibited)
[Legend]
x:
Don't care.
P:
Precharge-sel
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6.8.3
Section 6 Bus Controller (BSC)
Data Bus
If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous
DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM
space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM
space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM
can be connected directly.
In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is
enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of
the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
6.8.4
Pins Used for Synchronous DRAM Interface
Table 6.10 shows pins used for the synchronous DRAM interface and their functions.
Set the OEE bit of the DRAMCR register to 1 when the CKE signal is output.
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Section 6 Bus Controller (BSC)
Table 6.10 Synchronous DRAM Interface Pins
Pin
With
Synchronous
DRAM Setting
Name
I/O
Function
CS2
RAS
Row address strobe
Output
Row address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
CS3
CAS
Column address strobe
Output
Column address strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
CS4
WE
Write enable
Output
Write enable strobe when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
CS5
SDRAMφ
Clock
Output
Clock only for synchronous
DRAM
(OE)
(CKE)
Clock enable
Output
Clock enable signal when
areas 2 to 5 are designated
as continuous synchronous
DRAM space
UCAS
DQMU
Upper data mask enable Output
Upper data mask enable for
16-bit continuous
synchronous DRAM space
access/data mask enable for
8-bit continuous synchronous
DRAM space access
LCAS
DQML
Lower data mask enable Output
Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access
A15 to A0
A15 to A0
Address pins
Output
Row address/column address
multiplexed output pins
D15 to D0
D15 to D0
Data pins
I/O
Data input/output pins
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6.8.5
Section 6 Bus Controller (BSC)
Synchronous DRAM Clock
The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase
from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the
rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAMφ.
Tcyc
φ
1/4 Tcyc (90°)
SDRAMφ
Figure 6.55 Relationship between φ and SDRAMφ
6.8.6
Basic Timing
The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address
output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.56 shows the basic timing for synchronous DRAM.
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Tp
Tr
Column address
Row address
Tc1
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1)
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6.8.7
Section 6 Bus Controller (BSC)
CAS Latency Control
CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency
count, as shown in table 6.11, by the setting of synchronous DRAM. Depending on the setting, the
CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the
AST2 bit of ASTCR. Figure 6.57 shows the CAS latency control timing when synchronous
DRAM of CAS latency 3 is connected.
The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of
synchronous DRAM to be connected.
Table 6.11 Setting CAS Latency
CAS Latency Control
Cycle Inserted
W22
W21
W20
Description
0
0
0
Connect synchronous DRAM of CAS
latency 1
0 state
1
Connect synchronous DRAM of CAS
latency 2
1 state
0
Connect synchronous DRAM of CAS
latency 3
2 states
1
Connect synchronous DRAM of CAS
latency 4
3 states
0
Reserved (must not be used)
⎯
1
Reserved (must not be used)
⎯
0
Reserved (must not be used)
⎯
1
Reserved (must not be used)
⎯
1
1
0
1
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl1
Tcl2
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
Figure 6.57 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3)
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6.8.8
Section 6 Bus Controller (BSC)
Row Address Output State Control
When the command interval specification from the ACTV command to the next READ/WRIT
command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted
between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column
address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait
time according to the synchronous DRAM connected and the operating frequency of this LSI.
Figure 6.58 shows an example of the timing when the one Trw state is set.
Tp
Tr
Trw
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column
address
Row address
Column address
Row address
Precharge-sel
RAS
CAS
Read
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
READ
NOP
RAS
CAS
Write
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
Figure 6.58 Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.8.9
H8S/2456, H8S/2456R, H8S/2454 Group
Precharge State Count
When the interval specification from the PALL command to the next ACTV/REF command
cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in
DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected
and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are
inserted.
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Section 6 Bus Controller (BSC)
The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles.
Tp1
Tp2
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address
Row address
Column address
Row address
Precharge-sel
RAS
CAS
Read
WE
CKE
High
DQMU, DQML
Data bus
PALL
NOP
ACTV
READ
NOP
RAS
CAS
Write
WE
CKE
High
DQMU, DQML
Data bus
PALL
NOP
ACTV
NOP
WRIT
NOP
Figure 6.59 Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.8.10
Bus Cycle Control in Write Cycle
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS
latency control cycle is disabled.
Tp
Tr
Column address
Row address
Tc1
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.60 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1)
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6.8.11
Section 6 Bus Controller (BSC)
Byte Access Control
When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are
used for the control signals needed for byte access.
Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of
connection of byte control by DQMU and DQML.
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
CKE
High
DQMU
DQML
High
Upper data bus
Lower data bus
High impedance
PALL
ACTV
NOP
WRIT
NOP
Figure 6.61 DQMU and DQML Control Timing
(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
CKE
High
DQMU
High
DQML
Upper data bus
High impedance
Lower data bus
PALL
ACTV
READ
NOP
Figure 6.62 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)
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Section 6 Bus Controller (BSC)
This LSI
(Address shift size set to 8 bits)
16-Mbit synchronous DRAM
1 Mword × 16 bits × 4-bank configuration
8-bit column address
CS2 (RAS)
RAS
CS3 (CAS)
CAS
CS4 (WE)
UCAS (DQMU)
LCAS (DQML)
CS5 (SDRAMφ)
WE
DQMU
DQML
CLK
A23
A13 (BS1)
A21
A12 (BS0)
A12
A11
A11
A10
A10
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
OE (CKE)
I/O PORT
Row address
input: A11 to A0
Column address
input: A7 to A0
Bank select
address: A13/A12
DQ15 to DQ0
CKE
CS
Notes: 1. Bank control is not available.
2. The CKE and CS pins must be fixed to 1 when the power supply is input.
3. The CS pin must be fixed to 0 before accessing synchronous DRAM.
Figure 6.63 Example of DQMU and DQML Byte Control
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Section 6 Bus Controller (BSC)
6.8.12
H8S/2456, H8S/2456R, H8S/2454 Group
Burst Operation
With synchronous DRAM, in addition to full access (normal access) in which data is accessed by
outputting a row address for each access, burst access is also provided which can be used when
making consecutive accesses to the same row address. This access enables fast access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal
cannot be specified to the Tc2 cycle data output if the Tc1 cycle is executed for second or
following column address when the CAS latency is set to 1 to issue the READ command. Do not
set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected.
(1)
Burst Access Operation Timing
Figure 6.64 shows the operation timing for burst access. When there are consecutive access cycles
for continuous synchronous DRAM space, the column address output cycles continue as long as
the row address is the same for consecutive access cycles. The row address used for the
comparison is set with bits MXC2 to MXC0 in DRAMCR.
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Section 6 Bus Controller (BSC)
Tp
Tr
Column
address 1
Row address
Tc1
Tcl
Tc2
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address
Column address 2
Row address
Precharge-sel
RAS
CAS
Read
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
READ
NOP
RAS
CAS
Write
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
WRIT
NOP
Figure 6.64 Operation Timing of Burst Access
(BE = 1, SDWCD = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
(2)
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RAS Down Mode
Even when burst operation is selected, it may happen that access to continuous synchronous
DRAM space is not continuous, but is interrupted by access to another space. In this case, if the
row address active state is held during the access to the other space, the read or write command
can be issued without ACTV command generation similarly to DRAM RAS down mode.
To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.
Figure 6.65 shows an example of the timing in RAS down mode.
Note, however, the next continuous synchronous DRAM space access is a full access if:
•
•
•
•
•
•
a refresh operation is initiated in the RAS down state
self-refreshing is performed
the chip enters software standby mode
the external bus is released
the BE bit is cleared to 0
the mode register of the synchronous DRAM is set
There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not
guaranteed that other row address are accessed in a period in which program execution ensures the
value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of
the maximum active state time of each bank must be satisfied. When refresh is not used, programs
must be developed so that the bank is not in the active state for more than the specified time.
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Section 6 Bus Controller (BSC)
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
External
space read
Tc2
T1
T2
Continuous synchronous
DRAM space read
Tc1
Tcl
Tc2
φ
Address bus
Column
Row
address address
Precharge-sel
Row
address
Column address
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL ACTV READ
NOP
READ
NOP
Figure 6.65 Example of Operation Timing in RAS Down Mode
(BE = 1, CAS Latency 2)
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Section 6 Bus Controller (BSC)
6.8.13
H8S/2456, H8S/2456R, H8S/2454 Group
Refresh Control
This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.
In addition, self-refreshing can be executed when the chip enters the software standby state.
Refresh control is enabled when any area is designated as continuous synchronous DRAM space
in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
(1)
Auto Refreshing
To select auto refreshing, set the RFSHE bit to 1 in REFCR.
With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the synchronous DRAM used.
When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown
in figure 6.66.
Since the refresh counter operation is the same as the operation in the DRAM interface, see
section 6.7.12, Refresh Control.
When the continuous synchronous DRAM space is set, access to external address space other than
continuous synchronous DRAM space cannot be performed in parallel during the auto refresh
period, since the setting of the CBRM bit of REFCR is ignored.
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TRp
Section 6 Bus Controller (BSC)
TRr
TRc1
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
REF
NOP
Figure 6.66 Auto Refresh Timing
When the interval specification from the PALL command to the REF command cannot be
satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be
inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum
number of waits according to the synchronous DRAM connected and the operating frequency of
this LSI. Figure 6.67 shows the timing when one wait state is inserted. Since the setting of bits
TPC1 and TPC0 of DRACCR is also valid in refresh cycles, the command interval can be
extended by the RCW1 and RCW0 bits after the precharge cycles.
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Section 6 Bus Controller (BSC)
TRp1
TRp2
TRrw
TRr
TRc1
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
REF
NOP
Figure 6.67 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.68 shows the timing when one wait state is inserted.
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TRp
Section 6 Bus Controller (BSC)
TRr
TRr1
TRcw
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
REF
NOP
Figure 6.68 Auto Refresh Timing
(TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)
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Section 6 Bus Controller (BSC)
(2)
H8S/2456, H8S/2456R, H8S/2454 Group
Self-Refreshing
A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the
synchronous DRAM.
To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is
executed to enter software standby mode, the SELF command is issued, as shown in figure 6.69.
When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh
mode is exited automatically. If an auto refresh request occurs when making a transition to
software standby mode, auto refreshing is executed, and then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR.
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Section 6 Bus Controller (BSC)
TRp
TRr
PALL
SELF
Software standby
TRc2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
CKE
NOP
Figure 6.69 Self-Refresh Timing
(TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0)
In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing
self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0
in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the
normal precharge time. In this case, too, normal precharging is performed according to the setting
of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum
post-self-refresh precharge time, including this time. Figure 6.70 shows an example of the timing
when the precharge time after self-refreshing is extended by 2 states.
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Section 6 Bus Controller (BSC)
Continuous synchronous DRAM space write
Software
standby
TRc2
TRp1
TRp2
Tp
Tr
Column address
Row address
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
CKE
DQMU, DQML
Data bus
NOP
PALL
ACTV
NOP
NOP
NOP
Figure 6.70 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
(3)
Refreshing and All-Module-Clocks-Stopped Mode
In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR
= H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is
entered, in which the bus controller and I/O port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected to the external address space and DRAM data is to be retained
in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR.
(4)
Software Standby
When a transition is made to normal software standby, the PALL command is not output. If
synchronous DRAM is connected and DRAM data is to be retained in software standby, selfrefreshing must be set.
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6.8.14
Section 6 Bus Controller (BSC)
Mode Register Setting of Synchronous DRAM
To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of
address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.
The value of the address signal is fetched at the issuance time of the MRS command as the setting
value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the
synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous
DRAM, set the burst read/single write with the burst length of 1. Figure 6.71 shows the setting
timing of the mode in the synchronous DRAM.
Tp
Tr
Tc1
Tc2
φ
SDRAMφ
Address bus
Mode setting value
Mode setting value
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
MRS
NOP
Figure 6.71 Synchronous DRAM Mode Setting Timing
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Section 6 Bus Controller (BSC)
6.8.15
H8S/2456, H8S/2456R, H8S/2454 Group
DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM
Interface
When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output
timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous
DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits
select whether or not burst access is to be performed. The establishment time for the read data can
be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits.
(1) Output Timing of DACK or EDACK
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK
output goes low from the Tc1 state.
Figure 6.72 shows the DACK or EDACK output timing for the synchronous DRAM interface
when DDS = 1 or EDDS = 1.
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Section 6 Bus Controller (BSC)
Tp
Tr
Column address
Row address
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Precharge-sel
Column address
Row address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
DACK or EDACK
Figure 6.72 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
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Section 6 Bus Controller (BSC)
H8S/2456, H8S/2456R, H8S/2454 Group
When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in
DMAC or EXDMAC single address transfer mode, full access (normal access) is always
performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from
the Tr state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing continuous synchronous DRAM space.
Figure 6.73 shows the DACK or EDACK output timing for connecting the synchronous DRAM
interface when DDS = 0 or EDDS = 0.
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Section 6 Bus Controller (BSC)
Tp
Tr
Tc1
Tcl
Tc2
φ
SDRAMφ
Address bus
Column address Row address
Precharge-sel
Row address
Column address
RAS
CAS
WE
Read
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
READ
NOP
RAS
CAS
WE
Write
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
NOP
DACK or RDACK
Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
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Section 6 Bus Controller (BSC)
(2) Read Data Extension
If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can
be extended by clock suspend mode. The number of states for insertion of the read data extension
cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in
DRAMCR when the read data will be extended. The extension of the read data is not in
accordance with the bits DDS and EDDS.
Figure 6.74 shows the timing chart when the read data is extended by two cycles.
Tp
Tr
Tc1
Tcl
Tc2
Tsp1
Tsp2
φ
SDRAMφ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address
RAS
CAS
WE
CKE
DQMU, DQML
Data bus
DACK or EDACK
PALL ACTV READ
NOP
Figure 6.74 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)
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6.9
Section 6 Bus Controller (BSC)
Burst ROM Interface
In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst
ROM interfacing performed. The burst ROM space enables ROM with burst access capability to
be accessed at high speed.
Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in
BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the
setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for
burst access.
Settings can be made independently for area 0 and area 1.
In burst ROM space, burst access covers only CPU read accesses.
6.9.1
Basic Timing
The number of access states in the initial cycle (full access) on the burst ROM interface is
determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and
CSACRH. When area 0 or area 1 is designated as burst ROM space, the settings in RDNCR and
CSACRL are ignored.
From 1 to 8 states can be selected for the burst cycle, according to the settings of bits BSTS02 to
BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up
to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, and
BSTS10 in BROMCR.
The basic access timing for burst ROM space is shown in figures 6.75 and 6.76.
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Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
Note: n = 1 and 0
Figure 6.75 Example of Burst ROM Access Timing
(ASTn = 1, 2-State Burst Cycle)
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Section 6 Bus Controller (BSC)
Full access
T1
T2
Burst access
T1
T1
φ
Upper address bus
Lower address bus
CSn
AS
RD
Data bus
Note: n = 1 and 0
Figure 6.76 Example of Burst ROM Access Timing
(ASTn = 0, 1-State Burst Cycle)
6.9.2
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4,
Wait Control. Wait states cannot be inserted in a burst cycle.
6.9.3
Write Access
When a write access to burst ROM space is executed, burst access is interrupted at that point and
the write access is executed in line with the basic bus interface settings. Write accesses are not
performed in burst mode even though burst ROM space is designated.
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Section 6 Bus Controller (BSC)
6.10
Idle Cycle
6.10.1
Operation
When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
(1)
Consecutive Reads in Different Areas
If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCR, an idle cycle is
inserted at the start of the second read cycle.
Figure 6.77 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
φ
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS1 = 0)
T1
T2
T3
Data collision
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.77 Example of Idle Cycle Operation
(Consecutive Reads in Different Areas)
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(2)
Section 6 Bus Controller (BSC)
Write after Read
If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the write cycle.
Figure 6.78 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
φ
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS0 = 0)
Data collision
T1
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS0 = 1, initial value)
Figure 6.78 Example of Idle Cycle Operation (Write after Read)
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Section 6 Bus Controller (BSC)
(3)
Read after Write
If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the read cycle.
Figure 6.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
φ
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR, LWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS2 = 0)
Data collision
T1
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS2 = 1, initial value)
Figure 6.79 Example of Idle Cycle Operation (Read after Write)
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(4)
Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there
may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals. In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
φ
T1
T2
T3
Bus cycle B
T1
T2
Bus cycle A
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T1
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.80 Relationship between Chip Select (CS) and Read (RD)
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Section 6 Bus Controller (BSC)
(5)
Idle Cycle in Case of DRAM Space Access after Normal Space Access
In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1,
ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas,
for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a
Ti cycle is not. The timing in this case is shown in figure 6.81.
External read
T1
T2
T3
DRAM space read
Tp
Tr
Tc1
Tc2
φ
Address bus
RD
Data bus
Figure 6.81 Example of DRAM Full Access after External Read
(CAST = 0)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.82 and 6.83.
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Section 6 Bus Controller (BSC)
External read
DRAM space read
Tp
Tr
Tc1
Tc2
T1
T2
T3
DRAM space read
Ti
Tc1
Tc2
φ
Address bus
RD
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.82 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
External read
DRAM space read
Tp
Tr
Tc1
Tc2
T1
T2
T3
DRAM space write
Ti
Tc1
Tc2
φ
Address bus
RD
HWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.83 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
(6)
Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal
Space Access
In a continuous synchronous DRAM space access following a normal space access, the settings of
bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads
in different areas, for example, if the second read is a full access to continuous synchronous
DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in
figure 6.84.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
External space read
T1
T2
T3
Synchronous DRAM space read
Tp
Tr
Tc1
Tcl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address
RAS
CAS
WE
CKE
DQMU, DQML
RD
Data bus
NOP
PALL ACTV READ
NOP
Figure 6.84 Example of Synchronous DRAM Full Access after External Read
(CAS Latency 2)
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Section 6 Bus Controller (BSC)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85
and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC
bit. The timing in this case is illustrated in figure 6.87.
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
External space read
Tc2
T1
T2
T3
Continuous synchronous
DRAM space read
Ti
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
High
Data bus
PALL ACTV READ
NOP
READ
NOP
Idle cycle
Figure 6.85 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 0, CAS Latency 2)
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Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
Continuous synchronous
DRAM space read
External space read
Tc2
T1
T2
T3
Ti
Ti
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
High
Data bus
PALL ACTV READ
NOP
READ
NOP
Idle cycle
Figure 6.86 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 1, CAS Latency 2)
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Section 6 Bus Controller (BSC)
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
External space read
Tc2
T1
T2
T3
Continuous synchronous
DRAM space write
Ti
Tc1
Tc2
TCl
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
High
Data bus
PALL ACTV READ
NOP
WRIT
NOP
Idle cycle
Figure 6.87 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
(7)
Idle Cycle in Case of Normal Space Access after DRAM Space Access
(a)
Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access
is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI
bit to 1. The conditions and number of states of the idle cycle to be inserted are in accordance
with the settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show
examples of idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even
if bits ICIS1 and ICIS0 are set to 1.
External address space read
DRAM space read
Tp
Tr
Tc1
Tc2
Ti
T1
T2
T3
DRAM space read
Ti
Tc1
Tc2
φ
Address bus
RD
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.88 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
DRAM space read
Tp
Tr
Tc1
External address space write DRAM space read
Tc2
Ti
T1
T2
T3
Tc1
Tc2
φ
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.89 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
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Section 6 Bus Controller (BSC)
(b)
Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM
space write access, idle cycle is inserted in the first read cycle. The number of states of the idle
cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the
DRMI bit in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2
bit is set to 1.
External space read
DRAM space read
Tp
Tr
Tc1
Tc2
Ti
T1
T2
DRAM space read
T3
Tc1
Tc2
φ
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
(8)
Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM
Space Access:
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
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(a)
Section 6 Bus Controller (BSC)
Normal space access after a continuous synchronous DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous
synchronous DRAM space read access is disabled. Idle cycle insertion after continuous
synchronous DRAM space read access can be enabled by setting the DRMI bit to 1. The
conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in RCR. Figure 6.91 shows an example of idle cycle
operation when the DRMI bit is set to 1. When the DRMI bit is cleared to 0, an idle cycle is
not inserted after continuous synchronous DRAM space read access even if bits ICIS1 and
ICIS0 are set to 1.
Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
Continuous synchronous
DRAM space read
External space read
Tc2
Ti
T1
T2
T3
Ti
Tc1
TCl
Tc2
φ
Address bus
Row
Column
address address
Precharge-sel
Row
address
Column address 1
External address
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
Data bus
PALL ACTV READ
NOP
READ
NOP
Idle cycle
Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
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Section 6 Bus Controller (BSC)
(b)
Normal space access after a continuous synchronous DRAM space write access
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It
is not in accordance with the DRMI bit in DRACCR.
Figure 6.92 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Continuous synchronous
DRAM space write
φ
Tp
Tr
Address bus
Row
Column
address address
Precharge-sel
Row
address
Tc1
Tc2
Synchronous
External address space read DRAM space read
Ti
Column
address
T1
T2
External address
T3
Tc1
TCl
Tc2
Column address 2
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
RD
HWR, LWR
Data bus
PALL ACTV
NOP
NOP WRIT
READ
NOP
Idle cycle
Figure 6.92 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
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Section 6 Bus Controller (BSC)
Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.
Table 6.12 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space
Previous Access
Next Access
ICIS2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
Normal space read
Normal space read
(different area)
⎯
0
⎯
⎯
⎯
Disabled
⎯
1
⎯
⎯
0
1 state inserted
1
2 states inserted
⎯
0
⎯
⎯
⎯
Disabled
⎯
1
⎯
⎯
DRAM/continuous
synchronous DRAM*
space read
Normal space write
DRAM/continuous
synchronous DRAM*
space write
DRAM/continuous
synchronous
DRAM*
space read
Normal space read
DRAM/continuous
synchronous DRAM*
space read
Normal space write
DRAM/continuous
synchronous DRAM*
space write
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⎯
⎯
0
⎯
⎯
⎯
1
⎯
⎯
⎯
0
⎯
⎯
⎯
1
⎯
⎯
0
⎯
⎯
1
⎯
⎯
0
⎯
⎯
1
⎯
⎯
⎯
0
⎯
⎯
1
⎯
⎯
0
⎯
⎯
1
⎯
0
1 state inserted
1
2 states inserted
⎯
Disabled
0
1 state inserted
1
2 states inserted
⎯
Disabled
0
1 state inserted
1
2 states inserted
⎯
Disabled
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
⎯
Disabled
⎯
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
⎯
⎯
Disabled
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
⎯
⎯
Disabled
0
⎯
Disabled
1
0
1 state inserted
1
2 states inserted
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Section 6 Bus Controller (BSC)
Previous Access
Next Access
ICIS2
ICIS1
ICIS0
DRMI
IDLC
Idle cycle
Normal space write
Normal space read
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
DRAM/continuous
synchronous
DRAM*
DRAM/continuous
synchronous DRAM*
space read
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
Normal space read
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
space write
DRAM/continuous
synchronous DRAM*
space read
Note:
*
0
⎯
⎯
⎯
⎯
Disabled
1
⎯
⎯
⎯
0
1 state inserted
1
2 states inserted
Not supported by the H8S/2456 Group and H8S/2454 Group.
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
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DRAM space read
φ
Tp
Tr
Tc1
DRAM space write
Tc2
Ti
Tc1
Tc2
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
Note: n = 2 to 5
Idle cycle
Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode
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Continuous synchronous
DRAM space read
Tp
Tr
Tc1
Tcl
Continuous synchronous
DRAM space write
Tc2
Ti
Tc1
Tc2
φ
Address bus
Column Row
address address
Precharge-sel
Row
address
Column
address
External address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL ACTV READ
NOP
WRIT
Idle cycle
Figure 6.94 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode
(SDWCD = 1, CAS Latency 2)
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6.10.2
Section 6 Bus Controller (BSC)
Pin States in Idle Cycle
Table 6.13 shows the pin states in an idle cycle.
Table 6.13 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
CSn (n = 7 to 0)
High impedance
High*1 *2
UCAS, LCAS
High*2
AS/AH
High
RD
High
OE
High
HWR, LWR
High
DACKn (n = 1, 0)
High
EDACKn (n = 3 to 0)
High
Notes: 1. Remains low in DRAM space RAS down mode.
2. Remains low in a DRAM space refresh cycle.
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Section 6 Bus Controller (BSC)
6.11
Write Data Buffer Function
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes and DMA single address mode transfers to be executed in parallel
with internal accesses. The write data buffer function is made available by setting the WDBE bit
to 1 in BCR.
Figure 6.95 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or DMA single address mode transfer continues
for two states or longer, and there is an internal access next, an external write only is executed in
the first state, but from the next state onward an internal access (on-chip memory or internal I/O
register read/write) is executed in parallel with the external address space write rather than waiting
until it ends.
On-chip memory read Internal I/O register read
External write cycle
T1
T2
TW
TW
T3
φ
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
A23 to A0
External address
CSn
External space
write
HWR, LWR
D15 to D0
Figure 6.95 Example of Timing when Write Data Buffer Function Is Used
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6.12
Section 6 Bus Controller (BSC)
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC* continue to operate as long
as there is no external access. If any of the following requests are issued in the external bus
released state, the BREQO signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
Note: * Not supported by the H8S/2454 Group.
6.12.1
Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters except the EXDMAC* can perform
accesses using the internal bus. When an internal bus master wants to make an external access, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled. If a refresh request is generated in the external bus released state, or if a
SLEEP instruction is executed to place the chip in software standby mode or all-module-clocksstopped mode, refresh control and software standby or all-module-clocks-stopped control is
deferred until the bus request from the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
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Section 6 Bus Controller (BSC)
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
(High) External bus release > External access by internal bus master (Low)
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh > External bus release (Low)
Note: * Not supported by the H8S/2454 Group.
6.12.2
Pin States in External Bus Released State
Table 6.14 shows pin states in the external bus released state.
Table 6.14 Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
CSn (n = 7 to 0)
High impedance
UCAS, LCAS
High impedance
AS/AH
High impedance
RD
High impedance
OE
High impedance
HWR, LWR
High impedance
DACKn (n = 1, 0)
High
EDACKn* (n = 3, 2)
High
Note: Not supported by the H8S/2454 Group.
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6.12.3
Section 6 Bus Controller (BSC)
Transition Timing
Figure 6.96 shows the timing for transition to the bus released state.
External space
access cycle
CPU
cycle
External bus released state
T1
T2
φ
High impedance
Address bus
High impedance
Data bus
High impedance
AS
High impedance
RD
High impedance
HWR, LWR
BREQ
BACK
BREQO
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of CBR refreshing request, it retains low until CBR refresh cycle starts up.
Figure 6.96 Bus Released State Transition Timing
Figure 6.97 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
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Section 6 Bus Controller (BSC)
External space read
T1
CPU
cycle
External bus released state
T2
φ
SDRAMφ
High impedance
Address bus
High impedance
Data bus
Row
address
Precharge-sel
High impedance
High impedance
RAS
High impedance
CAS
High impedance
WE
High impedance
CKE
High impedance
DQMU, DQML
BREQ
BACK
BREQO
NOP
PALL
[1]
[2]
NOP
[3]
NOP
[4]
[5]
[8]
[6]
[7]
[9]
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
Figure 6.97 Bus Release State Transition Timing when Synchronous DRAM Interface
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
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6.13
Section 6 Bus Controller (BSC)
Bus Arbitration
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC*⎯that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.
Note: * The EXDMAC is not supported by the H8S/2454 Group.
6.13.1
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one
bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a
bus master receives the bus request acknowledge signal, it takes possession of the bus until that
signal is canceled.
The order of priority of the bus mastership is as follows:
(High) EXDMAC* > DMAC > DTC > CPU (Low)
An internal bus access by internal bus masters except the EXDMAC* and external bus release, a
refresh when the CBRM bit is 0, and an external bus access by the EXDMAC* can be executed in
parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
(High) Refresh > EXDMAC* > External bus release (Low)
(High) External bus release > External access by internal bus master except EXDMAC* (Low)
As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
Note: * The EXDMAC is not supported by the H8S/2454 Group.
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Section 6 Bus Controller (BSC)
6.13.2
H8S/2456, H8S/2456R, H8S/2454 Group
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
(1)
CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC,
or EXDMAC*, the bus arbiter transfers the bus to the bus master that issued the request. The
timing for transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
• With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
• If the CPU is in sleep mode, the bus is transferred immediately.
Note: * The EXDMAC is not supported by the H8S/2454 Group.
(2)
DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
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(3)
Section 6 Bus Controller (BSC)
DMAC
The DMAC sends the bus arbiter a request for the bus when an activation request is generated.
In the case of an external request in short address mode or normal mode, and in cycle steal mode,
the DMAC releases the bus after a single transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after
completion of the transfer. However, in the event of an EXDMAC* or external bus release
request, which have a higher priority than the DMAC, the bus may be transferred to the bus master
even if block or burst transfer is in progress.
Note: * The EXDMAC is not supported by the H8S/2454 Group.
(4)
EXDMAC
The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated.
As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is
transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in
parallel.
In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single
transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode,
after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify
temporary release of the bus in the event of an external access request from an internal bus master.
For details see section 8, EXDMA Controller (EXDMAC).
Note: The EXDMAC is not supported by the H8S/2454 Group.
(5)
External Bus Release
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is
set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
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Section 6 Bus Controller (BSC)
6.14
H8S/2456, H8S/2456R, H8S/2454 Group
Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.15
Usage Notes
6.15.1
External Bus Release Function and All-Module-Clocks-Stopped Mode
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR =
H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered
in which the clock is also stopped for the bus controller and I/O ports. In this state, the external
bus release function is halted. To use the external bus release function in sleep mode, the ACSE
bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in allmodule-clocks-stopped mode is executed in the external bus released state, the transition to allmodule-clocks-stopped mode is deferred and performed until after the bus is recovered.
6.15.2
External Bus Release Function and Software Standby
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.15.3
External Bus Release Function and CBR Refreshing/Auto Refreshing
CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR
refresh/auto refresh request is issued.
Note: The auto refresh control function is not supported by the H8S/2456 Group and H8S/2454
Group.
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6.15.4
Section 6 Bus Controller (BSC)
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
6.15.5
(1)
Notes on Usage of the Synchronous DRAM
Connection Clock
Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ.
(2)
WAIT Pin
In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is
disabled regardless of the setting of the WAITE bit in BCR.
(3)
Bank Control
This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected.
(4)
Burst Access
The burst read/burst write mode of the synchronous DRAM is not supported. When setting the
mode register of the synchronous DRAM, set to the burst read/single write and set the burst length
to 1.
(5)
CAS Latency
When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the
DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Group.
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Section 6 Bus Controller (BSC)
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Section 7 DMA Controller (DMAC)
Section 7 DMA Controller (DMAC)
This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
•
•
•
•
•
Features
Selectable as short address mode or full address mode
Short address mode
⎯ Maximum of 4 channels can be used
⎯ Dual address mode or single address mode can be selected
⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
⎯ In single address mode, transfer source or transfer destination address only is specified as
24 bits
⎯ In single address mode, transfer can be performed in one bus cycle
⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
⎯ Maximum of 2 channels can be used
⎯ Transfer source and transfer destination addresses as specified as 24 bits
⎯ Choice of normal mode or block transfer mode
16-Mbyte address space can be specified directly
Byte or word can be set as the transfer unit
Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
⎯ Six compare match/input capture interrupts of 16-bit timer-pulse unit (TPU0 to TPU5)
⎯ Transmit data empty and receive data full interrupts of serial communication interface
(SCI_0, SCI_1)
⎯ Conversion end interrupt of A/D converter (A/D_0)
⎯ EP1FIFO full interrupt and EP2FIFO empty interrupt of USB
⎯ External request
⎯ Auto-request
Module stop state can be set.
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Section 7 DMA Controller (DMAC)
A block diagram of the DMAC is shown in figure 7.1.
Internal address bus
Address buffer
Processor
DMAWER
DMACR_0A
DMACR_0B
DMACR_1A
DMACR_1B
Channel 1
DMATCR
MAR_0AH
MAR_0AL
IOAR_0A
ETCR_0A
MAR_0BH
MAR_0BL
IOAR_0B
ETCR_0B
MAR_1AH
Module data bus
Channel 0
Control logic
Channel 1B Channel 1A Channel 0B Channel 0A
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI0
USBINTN0
USBINTN1
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
MAR_1AL
IOAR_1A
ETCR_1A
MAR_1BH
MAR_1BL
IOAR_1B
ETCR_1B
DMABCR
Data buffer
Internal data bus
[Legend]
DMAWER:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
DMA write enable register
DMA terminal control register
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Execute transfer count register
Figure 7.1 Block Diagram of DMAC
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7.2
Section 7 DMA Controller (DMAC)
Input/Output Pins
Table 7.1 shows the pin configuration of the interrupt controller.
Table 7.1
Pin Configuration
Channel
Pin Name
Symbol
I/O
Function
0
DMA request 0
DREQ0
Input
Channel 0 external request
DMA transfer acknowledge 0
DACK0
Output
Channel 0 single address
transfer acknowledge
DMA transfer end 0
TEND0
Output
Channel 0 transfer end
DMA request 1
DREQ1
Input
Channel 1 external request
DMA transfer acknowledge 1
DACK1
Output
Channel 1 single address
transfer acknowledge
DMA transfer end 1
TEND1
Output
Channel 1 transfer end
1
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Section 7 DMA Controller (DMAC)
7.3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
Memory address register_0AH (MAR_0AH)
Memory address register_0AL (MAR_0AL)
I/O address register_0A (IOAR_0A)
Transfer count register_0A (ECTR_0A)
Memory address register_0BH (MAR_0BH)
Memory address register_0BL (MAR_0BL)
I/O address register_0B (IOAR_0B)
Transfer count register_0B (ECTR_0B)
Memory address register_1AH (MAR_1AH)
Memory address register_1AL (MAR_1AL)
I/O address register_1A (IOAR_1A)
Transfer count register_1A (ETCR_1A)
Memory address register_1BH (MAR_1BH)
Memory address register_1BL (MAR_1BL)
I/O address register_1B (IOAR_1B)
Transfer count register_1B (ETCR_1B)
DMA control register_0A (DMACR_0A)
DMA control register_0B (DMACR_0B)
DMA control register_1A (DMACR_1A)
DMA control register_1B (DMACR_1B)
DMA band control register H (DMABCRH)
DMA band control register L (DMABCRL)
DMA write enable register (DMAWER)
DMA terminal control register (DMATCR)
The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer
mode (short address mode or full address mode). The transfer mode can be selected by means of
the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and
full address mode of channel 0 are shown in table 7.2.
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Table 7.2
Section 7 DMA Controller (DMAC)
Short Address Mode and Full Address Mode (Channel 0)
0
Short address mode specified (channels 0A and 0B operate independently)
MAR_0AH
MAR_0BH
MAR_0AL
Specifies transfer source/transfer destination address
IOAR_0A
Specifies transfer destination/transfer source address
ETCR_0A
Specifies number of transfers
DMACR_0A
MAR_0BL
Specifies transfer size, mode, activation source.
Specifies transfer source/transfer destination address
IOAR_0B
Specifies transfer destination/transfer source address
ETCR_0B
Specifies number of transfers
DMACR_0B
Specifies transfer size, mode, activation source.
Full address mode specified (channels 0A and 0B operate in combination as channel 0)
MAR_0AH
MAR_0AL
Specifies transfer source address
MAR_0BH
MAR_0BL
Specifies transfer destination address
Channel 0
1
Channel 0A
Description
Channel 0B
FAE0
IOAR_0A
IOAR_0B
ETCR_0A
ETCR_0B
DMACR_0A DMACR_0B
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Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
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Section 7 DMA Controller (DMAC)
7.3.1
H8S/2456, H8S/2456R, H8S/2454 Group
Memory Address Registers (MARA and MARB)
MAR is a 32-bit readable/writable register that specifies the source address (transfer source
address) or destination address (transfer destination address). MAR consists of two 16-bit registers
MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and
cannot be modified.
The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0
(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).
MAR is not initialized by a reset or in standby mode.
Short Address Mode: In short address mode, MARA and MARB operate independently.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated.
Full Address Mode: In full address mode, MARA functions as the source address register, and
MARB as the destination address register.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination address is constantly updated.
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7.3.2
Section 7 DMA Controller (DMAC)
I/O Address Registers (IOARA and IOARB)
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address
(transfer source address) or destination address (transfer destination address). The upper 8 bits of
the transfer address are automatically set to H'FF.
The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0
(channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B).
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is not incremented or decremented each time a data transfer is executed, so the address
specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
IOAR can be used in short address mode but not in full address mode.
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Section 7 DMA Controller (DMAC)
7.3.3
H8S/2456, H8S/2456R, H8S/2454 Group
Execute Transfer Count Registers (ETCRA and ETCRB)
ETCR is a 16-bit readable/writable register that specifies the number of transfers.
The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0
(channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B).
ETCR is not initialized by a reset or in standby mode.
(1)
Short Address Mode
The function of ETCR in sequential mode and idle mode differs from that in repeat mode.
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is
decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit
in DMABCRL is cleared, and transfer ends.
In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer
count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when
the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is
automatically restored to the value it had when the count was started. The DTE bit in DMABCRL
is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the
user.
(2)
Full Address Mode
The function of ETCR in normal mode differs from that in block transfer mode.
In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each
time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not
used in normal mode.
In block transfer mode, ETCRA functions as an 8-bit block size counter (ETCRAL) and ETCRAH
functions as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in
ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly
transfer blocks consisting of any desired number of bytes or words.
In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
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7.3.4
Section 7 DMA Controller (DMAC)
DMA Control Registers (DMACRA and DMACRB)
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B). In short address mode, channels A and B operate independently, and in full address
mode, channels A and B operate together. The bit functions in the DMACR registers differ
according to the transfer mode.
(1)
•
Short Address Mode:
DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
Bit
Bit Name
Initial Value
R/W
Description
7
DTSZ
0
R/W
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
6
DTID
0
R/W
Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.
0: MAR is incremented after a data transfer
(Initial value)
• When DTSZ = 0, MAR is incremented by 1
• When DTSZ = 1, MAR is incremented by 2
1: MAR is decremented after a data transfer
• When DTSZ = 0, MAR is decremented by 1
• When DTSZ = 1, MAR is decremented by 2
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Bit
Bit Name
Initial Value
R/W
Description
5
RPE
0
R/W
Repeat Enable
Used in combination with the DTIE bit in DMABCR
to select the mode (sequential, idle, or repeat) in
which transfer is to be performed.
•
When DTIE = 0 (no transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in repeat mode
•
When DTIE = 1 (with transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in idle mode
4
DTDIR
0
R/W
Data Transfer Direction
Used in combination with the SAE bit in DMABCR
to specify the data transfer direction (source or
destination). The function of this bit is therefore
different in dual address mode and single address
mode.
•
When SAE = 0
0: Transfer with MAR as source address and
IOAR as destination address
1: Transfer with IOAR as source address and
MAR as destination address
•
When SAE = 1
0: Transfer with MAR as source address and
DACK pin as write strobe
1: Transfer with DACK pin as read strobe and
MAR as destination address
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Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
Data Transfer Factor 3 to 0
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
These bits select the data transfer factor
(activation source). There are some differences in
activation sources for channel A and channel B.
•
Channel A
0000: Setting prohibited
0001: Activated by conversion end interrupt of A/D
converter unit 0
0010: Setting prohibited
0011: Setting prohibited
0100: Activated by SCI channel 0 transmit data
empty interrupt
0101: Activated by SCI channel 0 receive data full
interrupt
0110: Activated by SCI channel 1 transmit data
empty interrupt
0111: Activated by SCI channel 1 receive data full
interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
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Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
•
2
DTF2
0
R/W
0000: Setting prohibited
1
DTF1
0
R/W
0
DTF0
0
R/W
0001: Activated by conversion end interrupt of A/D
converter unit 0
Channel B
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)*
0011: Activated by DREQ pin low-level input*
0100: Activated by SCI channel 0 transmit data
empty interrupt
0101: Activated by SCI channel 0 receive data full
interrupt
0110: Activated by SCI channel 1 transmit data
empty interrupt
0111: Activated by SCI channel 1 receive data full
interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than
one channel. In this case, activation starts with the
highest-priority channel according to the relative
channel priorities. For relative channel priorities,
see section 7.5.12, Multi-Channel Operation.
Note: This setting is prohibited when the USBDRQE bit in PFCR3 is 1.
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•
Section 7 DMA Controller (DMAC)
Full Address Mode
DMACR_0A and DMACR_1A
Bit
Bit Name
Initial Value
R/W
Description
15
DTSZ
0
R/W
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
14
SAID
0
R/W
Source Address Increment/Decrement
13
SAIDE
0
R/W
Source Address Increment/Decrement Enable
These bits specify whether source address
register MARA is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARA is fixed
01: MARA is incremented after a data transfer
•
When DTSZ = 0, MARA is incremented by 1
•
When DTSZ = 1, MARA is incremented by 2
10: MARA is fixed
11: MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by 1
•
When DTSZ = 1, MARA is decremented by 2
12
BLKDIR
0
R/W
Block Direction
11
BLKE
0
R/W
Block Enable
These bits specify whether normal mode or block
transfer mode is to be used for data transfer. If
block transfer mode is specified, the BLKDIR bit
specifies whether the source side or the
destination side is to be the block area.
x0: Transfer in normal mode
01: Transfer in block transfer mode (destination
side is block area)
11: Transfer in block transfer mode (source side is
block area)
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Bit
Bit Name
Initial Value
R/W
Description
10 to 8
⎯
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
[Legend]
x:
Don't care
•
DMACR_0B and DMACR_1B
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
6
DAID
0
R/W
Destination Address Increment/Decrement
5
DAIDE
0
R/W
Destination Address Increment/Decrement Enable
These bits specify whether destination address
register MARB is to be incremented,
decremented, or left unchanged, when data
transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
•
When DTSZ = 0, MARB is incremented by 1
•
When DTSZ = 1, MARB is incremented by 2
10: MARB is fixed
11: MARB is decremented after a data transfer
4
⎯
0
R/W
•
When DTSZ = 0, MARB is decremented by 1
•
When DTSZ = 1, MARB is decremented by 2
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
Data Transfer Factor 3 to 0
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
These bits select the data transfer factor
(activation source). The factors that can be
specified differ between normal mode and block
transfer mode.
•
Normal Mode
0000: Setting prohibited
0001: Setting prohibited
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)*
0011: When USBDRQE bit in PFCR3 is 0:
Activated by DREQ pin low-level input
When USBDRQE bit in PFCR3 is 1:
Activated by USB interrupt signal low-level
input
010x: Setting prohibited
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1xxx: Setting prohibited
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Bit
Bit Name
Initial Value
R/W
Description
3
DTF3
0
R/W
•
2
DTF2
0
R/W
0000: Setting prohibited
1
DTF1
0
R/W
0
DTF0
0
R/W
0001: Activated by A/D converter unit 0
conversion end interrupt
Block Transfer Mode
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)*
0011: When USBDRQE bit in PFCR3 is 0:
Activated by DREQ pin low-level input
When USBDRQE bit in PFCR3 is 1:
Activated by USB interrupt signal low-level
input
0100: Activated by SCI channel 0 transmit data
empty interrupt
0101: Activated by SCI channel 0 receive data full
interrupt
0110: Activated by SCI channel 1 transmit data
empty interrupt
0111: Activated by SCI channel 1 receive data full
interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than
one channel. In this case, activation starts with the
highest-priority channel according to the relative
channel priorities. For relative channel priorities,
see section 7.5.12, Multi-Channel Operation.
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[Legend]
×:
Don't care
Note: * This setting is prohibited when the USBDRQE bit in PFCR3 is 1.
7.3.5
DMA Band Control Registers H and L (DMABCRH and DMABCRL)
DMABCR controls the operation of each DMAC channel. The bit functions in the DMABCR
registers differ according to the transfer mode.
(1)
•
Short Address Mode:
DMABCRH
Bit
Bit Name
Initial Value
R/W
Description
15
FAE1
0
R/W
Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode. In short
address mode, channels 1A and 1B can be used
as independent channels.
0: Short address mode
1: Full address mode
14
FAE0
0
R/W
Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode. In short
address mode, channels 0A and 0B can be used
as independent channels.
0: Short address mode
1: Full address mode
13
SAE1
0
R/W
Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
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Bit
Bit Name
Initial Value
R/W
Description
12
SAE0
0
R/W
Single Address Enable 0
Specifies whether channel 0B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
11
DTA1B
0
R/W
Data Transfer Acknowledge 1B
10
DTA1A
0
R/W
Data Transfer Acknowledge 1A
9
DTA0B
0
R/W
Data Transfer Acknowledge 0B
8
DTA0A
0
R/W
Data Transfer Acknowledge 0A
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR.
If the DTA bit is set to 1 when DTE = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE = 1 and DTA = 1, the
internal interrupt source does not issue an
interrupt request to the CPU or DTC.
If the DTA bit is cleared to 0 when DTE = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this
case, the interrupt source should be cleared by
the CPU or DTC transfer.
When DTE = 0, the internal interrupt source issues
an interrupt request to the CPU or DTC regardless
of the DTA bit setting.
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Section 7 DMA Controller (DMAC)
DMABCRL
Bit
Bit Name
Initial Value
R/W
Description
7
DTE1B
0
R/W
Data Transfer Enable 1B
6
DTE1A
0
R/W
Data Transfer Enable 1A
5
DTE0B
0
R/W
Data Transfer Enable 0B
4
DTE0A
0
R/W
Data Transfer Enable 0A
If the DTE bit is cleared to 0 when DTIE = 1, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 0, data transfer is disabled and the
DMAC ignores the activation source selected by
the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation source
selected by the DTF3 to DTF0 bits in DMACR.
When a request is issued by the activation source,
DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed in a transfer mode other than
repeat mode
•
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE bit after reading DTE
=0
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Bit
Bit Name
Initial Value
R/W
Description
3
DTIE1B
0
R/W
Data Transfer End Interrupt Enable 1B
2
DTIE1A
0
R/W
Data Transfer End Interrupt Enable 1A
1
DTIE0B
0
R/W
Data Transfer End Interrupt Enable 0B
0
DTIE0A
0
R/W
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit is
set to 1 when DTE = 0, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the transfer counter and
address register again, and then setting the DTE
bit to 1.
(2)
•
Full Address Mode:
DMABCRH
Bit
Bit Name
Initial Value
R/W
Description
15
FAE1
0
R/W
Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are
used together as channel 1.
0: Short address mode
1: Full address mode
14
FAE0
0
R/W
Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are
used together as channel 0.
0: Short address mode
1: Full address mode
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Bit
Bit Name
Initial Value
R/W
Description
13, 12
⎯
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
11
DTA1
0
R/W
Data Transfer Acknowledge 1
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE1 = 1 and DTA1 = 1,
the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this
case, the interrupt source should be cleared by
the CPU or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
10
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Bit
Bit Name
Initial Value
R/W
Description
9
DTA0
0
R/W
Data Transfer Acknowledge 0
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 0.
It the DTA0 bit is set to 1 when DTE0 = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE0 = 1 and DTA0 = 1,
the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
It the DTA0 bit is cleared to 0 when DTE0 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this
case, the interrupt source should be cleared by
the CPU or DTC transfer.
When DTE0 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA0 bit setting.
The state of the DTME0 bit does not affect the
above operations.
8
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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•
Section 7 DMA Controller (DMAC)
DMABCRL
Bit
Bit Name
Initial Value
R/W
Description
7
DTME1
0
R/W
Data Transfer Master Enable 1
Together with the DTE1 bit, this bit controls
enabling or disabling of data transfer on channel
1. When both the DTME1 bit and DTE1 bit are set
to 1, transfer is enabled for channel 1.
If channel 1 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME1 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME1 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME1 bit is not cleared by
an NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
•
When initialization is performed
•
When NMI is input in burst mode
•
When 0 is written to the DTME1 bit
[Setting condition]
When 1 is written to DTME1 after reading DTME1
=0
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Bit
Bit Name
Initial Value
R/W
Description
6
DTE1
0
R/W
Data Transfer Enable 1
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
When DTE1 = 0, data transfer is disabled and the
activation source is ignored. If the activation
source is an internal interrupt, an interrupt request
is issued to the CPU or DTC. If the DTE1 bit is
cleared to 0 when DTIE1 = 1, the DMAC regards
this as indicating the end of a transfer, and issues
a transfer end interrupt request to the CPU.
When DTE1 = 1 and DTME1 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed
•
When 0 is written to the DTE1 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE1 bit after reading
DTE1 = 0
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Bit
Bit Name
Initial Value
R/W
Description
5
DTME0
0
R/W
Data Transfer Master Enable 0
Together with the DTE0 bit, this bit controls
enabling or disabling of data transfer on channel
0. When both the DTME0 bit and DTE0 bit are set
to 1, transfer is enabled for channel 0.
If channel 0 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME0 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME0 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME0 bit is not cleared by
an NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
•
When initialization is performed
•
When NMI is input in burst mode
•
When 0 is written to the DTME0 bit
[Setting condition]
When 1 is written to DTME0 after reading DTME0
=0
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Bit
Bit Name
Initial Value
R/W
Description
4
DTE0
0
R/W
Data Transfer Enable 0
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 0.
When DTE0 = 0, data transfer is disabled and the
activation source is ignored. If the activation
source is an internal interrupt, an interrupt request
is issued to the CPU or DTC. If the DTE0 bit is
cleared to 0 when DTIE0 = 1, the DMAC regards
this as indicating the end of a transfer, and issues
a transfer end interrupt request to the CPU.
When DTE0 = 1 and DTME0 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
When initialization is performed
•
When the specified number of transfers have
been completed
•
When 0 is written to the DTE0 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE0 bit after reading
DTE0 = 0
3
DTIE1B
0
R/W
Data Transfer Interrupt Enable 1B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted. If
the DTME1 bit is cleared to 0 when DTIE1B = 1,
the DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE1B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME1 bit to 1.
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Bit
Bit Name
Initial Value
R/W
Description
2
DTIE1A
0
R/W
Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE1 bit is cleared
to 1 when DTIE1A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
1
DTIE0B
0
R/W
Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted. If
the DTME0 bit is cleared to 0 when DTIE0B = 1,
the DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
0
DTIE0A
0
R/W
Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE0 bit is cleared
to 0 when DTIE0A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.
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Section 7 DMA Controller (DMAC)
7.3.6
DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
3
WE1B
0
R/W
Write Enable 1B
Enables or disables writes to all bits in DMACR1B,
bits 11, 7, and 3 in DMABCR, and bit 5 in
DMATCR.
0: Writes are disabled
1: Writes are enabled
2
WE1A
0
R/W
Write Enable 1A
Enables or disables writes to all bits in DMACR1A,
and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
1
WE0B
0
R/W
Write Enable 0B
Enables or disables writes to all bits in DMACR0B,
bits 9, 5, and 1 in DMABCR, and bit 4 in
DMATCR.
0: Writes are disabled
1: Writes are enabled
0
WE0A
0
R/W
Write Enable 0A
Enables or disables writes to all bits in DMACR0A,
and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled
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Section 7 DMA Controller (DMAC)
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
MAR_0AH
First transfer area
MAR_0AL
IOAR_0A
ETCR_0A
MAR_0BH
MAR_0BL
IOAR_0B
ETCR_0B
MAR_1AH
MAR_1AL
DTC
IOAR_1A
ETCR_1A
MAR_1BH
MAR_1BL
IOAR_1B
ETCR_1B
Second transfer area
using chain transfer
DMAWER
DMATCR
DMACR_0A
DMACR_0B
DMACR_1A
DMACR_1B
DMABCR
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
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Section 7 DMA Controller (DMAC)
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
7.3.7
DMA Terminal Control Register (DMATCR)
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
TEE1
0
R/W
Transfer End Enable 1
Enables or disables transfer end pin 1 (TEND1)
output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
4
TEE0
0
R/W
Transfer End Enable 0
Enables or disables transfer end pin 0 (TEND0)
output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
3 to 0
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
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7.4
Section 7 DMA Controller (DMAC)
Activation Sources
DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and
channel, as shown in table 7.3.
Table 7.3
DMAC Activation Sources
Short Address Mode
Activation Source
Internal
interrupts
Channels
0B and
1B
Normal
Mode
ADI0
×
TXI0
×
RXI0
×
TXI1
×
RXI1
×
TGI0A
×
TGI1A
×
TGI2A
×
TGI3A
×
TGI4A
×
TGI5A
×
×
×
USBINTN1
×
×
DREQ pin falling edge input
×
DREQ pin low-level input
×
USBINTN0
External
requests
Channels
0A and 1A
Full Address Mode
Auto-request
×
×
Block
Transfer
Mode
×
[Legend]
:
Can be specified
×:
Cannot be specified
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Section 7 DMA Controller (DMAC)
7.4.1
H8S/2456, H8S/2456R, H8S/2454 Group
Activation by Internal Interrupt Request
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated. Transfer requests for other channels are held pending in the DMAC,
and activation is carried out in order of priority.
When DTE = 0 after completion of a transfer, an interrupt request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit setting. In this case, the relevant
interrupt request is sent to the CPU or DTC.
When an interrupt request signal for DMAC activation is also used for an interrupt request to the
CPU or DTC activation (DTA = 0), the interrupt request flag is not cleared by the DMAC.
If the DMAC is activated by a USB interrupt source, setting bits DTF[3:0] in DMACR to 4'b0011
and the USBDRQE bit in PFCR3 to 1 activates the DMAC at a low-level input of the USB
interrupt signal.
The DMAC stands by for a transfer request while the USB interrupt source is held high. While the
USB interrupt source is held low, transfers continue in succession, with the bus being released
each time a byte or word is transferred. If the USB interrupt source goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
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7.4.2
Section 7 DMA Controller (DMAC)
Activation by External Request
If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port
should be set to input mode in advance*. Level sensing or edge sensing can be used for external
requests.
External request operation in normal mode of short address mode or full address mode is
described below.
When edge sensing is selected, a byte or word is transferred each time a high-to-low transition is
detected on the DREQ pin. The next data transfer may not be performed if the next edge is input
before data transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Note: * If the relevant port is set as an output pin for another function, DMA transfers using the
channel in question cannot be guaranteed.
7.4.3
Activation by Auto-Request
Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
7.5
Operation
7.5.1
Transfer Modes
Table 7.4 lists the DMAC transfer modes.
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Section 7 DMA Controller (DMAC)
Table 7.4
DMAC Transfer Modes
Transfer Mode
Transfer Source
Remarks
Short
address
mode
• TPU channel 0 to 5
compare match/input
capture A interrupt
• Up to 4 channels can
operate independently
Dual address mode
• 1-byte or 1-word transfer
for a single transfer
request
• Specify source and
destination addresses to
transfer data in two bus
cycles.
(1) Sequential mode
• Memory address
incremented or
decremented by 1 or 2
• SCI transmit data
empty interrupt
• SCI receive data full
interrupt
• External request applies
to channel B only
• Single address mode
applies to channel B
only
• A/D converter
conversion end
interrupt
• External request
• Number of transfers: 1 to
65,536
(2) Idle mode
• Memory address fixed
• Number of transfers: 1 to
65,536
(3) Repeat mode
• Memory address
incremented or
decremented by 1 or 2
• Continues transfer after
sending number of
transfers (1 to 256) and
restoring the initial value
Single address mode
• External request
• 1-byte or 1-word transfer
for a single transfer
request
• 1-bus cycle transfer by
means of DACK pin
instead of using address
for specifying I/O
• Sequential mode, idle
mode, or repeat mode can
be specified
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Section 7 DMA Controller (DMAC)
Transfer Mode
Transfer Source
Remarks
Full
address
mode
• Auto-request
• Max. 2-channel
operation, combining
channels A and B
Normal mode
(1) Auto-request
• Transfer request is
internally held
• Number of transfers (1 to
65,536) is continuously
sent
• Burst/cycle steal transfer
can be selected
(2) External request
• External request
• 1-byte or 1-word transfer
for a single transfer
request
• Number of transfers: 1 to
65,536
(3) Internal request
• USB interrupt
• 1-byte or 1-word transfer
for a single transfer
request
• Number of transfers: 1 to
65,536
Block transfer mode
• Transfer of 1-block, size
selected for a single
transfer request
• Number of transfers: 1 to
65,536
• Source or destination can
be selected as block area
• Block size: 1 to 256 bytes
or word
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmit data
empty interrupt
• SCI receive data full
interrupt
• A/D converter
conversion end
interrupt
• USB interrupt
• External request
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Section 7 DMA Controller (DMAC)
7.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.5 summarizes register functions in sequential mode.
Table 7.5
Register Functions in Sequential Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR
23
15
H'FF
IOAR
15
0
Operation
0
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7.3 illustrates operation in sequential mode.
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Address T
Section 7 DMA Controller (DMAC)
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.3 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data
transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or
DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 7.4 shows an example of the setting procedure for sequential mode.
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[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Sequential mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Sequential mode
Figure 7.4 Example of Sequential Mode Setting Procedure
7.5.3
Idle Mode
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
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Table 7.6
Section 7 DMA Controller (DMAC)
Register Functions in Idle Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
Transfer counter
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR
23
15
H'FF
IOAR
15
0
Operation
0
Destination Start address of
Fixed
address
transfer destination
register
or transfer source
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Figure 7.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
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Section 7 DMA Controller (DMAC)
Figure 7.6 shows an example of the setting procedure for idle mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Idle mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTIE bit to 1.
• Set the DTE bit to 1 to enable transfer.
Read DMABCRL
[5]
Set DMABCRL
[6]
Idle mode
Figure 7.6 Example of Idle Mode Setting Procedure
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7.5.4
Section 7 DMA Controller (DMAC)
Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7
Register Functions in Repeat Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
Source
address
register
0
Destination Source
address
address
register
register
Start address of
Fixed
transfer source or
transfer destination
Holds number of
transfers
Number of transfers Fixed
Transfer counter
Number of transfers Decremented every
transfer.
Loaded with
ETCRH value when
the value reaches
H'00
MAR
23
15
H'FF
IOAR
7
0
ETCRAH
7
0
ETCRAL
Operation
0
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer.
Initial setting is
restored when the
value reaches
H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
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Section 7 DMA Controller (DMAC)
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In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)DTID · 2DTSZ · ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the
transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is
not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the
operation can be restarted from the transfer after that terminated when the DTE bit was cleared.
Figure 7.7 illustrates operation in repeat mode.
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Address T
Section 7 DMA Controller (DMAC)
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
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Figure 7.8 shows an example of the setting procedure for repeat mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Repeat mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in both ETCRH and
ETCRL.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Clear the DTIE bit to 0.
• Set the DTE bit to 1 to enable transfer.
Repeat mode
Figure 7.8 Example of Repeat Mode Setting Procedure
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7.5.5
Section 7 DMA Controller (DMAC)
Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in single address mode.
Table 7.8
Register Functions in Single Address Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0
MAR
DACK pin
15
0
ETCR
Operation
Source
address
register
Destination Start address of
See sections 7.5.2,
address
transfer destination Sequential Mode,
register
or transfer source
7.5.3, Idle Mode,
and 7.5.4, Repeat
Mode.
Write
strobe
Read
strobe
Transfer counter
(Set automatically
by SAE bit in
DMABCRH; IOAR
is invalid)
Strobe for external
device
Number of transfers See sections 7.5.2,
Sequential Mode,
7.5.3, Idle Mode,
and 7.5.4, Repeat
Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
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Section 7 DMA Controller (DMAC)
Address T
DACK
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N – 1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)
Figure 7.10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).
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Single address
mode setting
Set DMABCRH
Set transfer source and
transfer destination
addresses
[1]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Set the SAE bit to 1 to select single address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address/transfer
destination address in MAR.
[2]
Set number of transfers
[3]
Set DMACR
[4]
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Single address mode
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode Is Specified)
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Section 7 DMA Controller (DMAC)
7.5.6
Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in
DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response
to a single transfer request, and this is executed the number of times specified in ETCRA. The
transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9
summarizes register functions in normal mode.
Table 7.9
Register Functions in Normal Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
0
Destination
address register
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
MARA
23
MARB
15
0
ETCRA
Transfer counter Number of transfers Decremented every
transfer; transfer ends
when count reaches
H'0000
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time
a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared
and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent
to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Figure 7.11 illustrates operation in normal mode.
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Transfer
Address TA
Address BB
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
Address TB
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
Figure 7.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests, EP1FIFO full interrupt and EP2FIFO
empty interrupt of the USB, and auto-requests. With auto-requests, the DMAC is only activated by
register setting, and the specified number of transfers are performed automatically. With autorequests, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released
to another bus master each time a transfer is performed. In burst mode, the bus is held
continuously until transfer ends.
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Figure 7.12 shows an example of the setting procedure for normal mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Normal mode setting
Set DMABCRH
[1]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the number of transfers in ETCRA.
Set transfer source and
transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Clear the BLKE bit to 0 to select normal
mode.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Normal mode
Figure 7.12 Example of Normal Mode Setting Procedure
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7.5.7
Section 7 DMA Controller (DMAC)
Block Transfer Mode
In block transfer mode, data transfer is performed with channels A and B used in combination.
Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in
DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either
the transfer source or the transfer destination can be selected as a block area (an area composed of
a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
Function
Initial Setting
Operation
0
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
0
Destination
address register
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
Holds block
size
Block size
Fixed
Block size
counter
Block size
Decremented every
transfer; ETCRAH value
copied when count
reaches H'00
Block transfer
counter
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
MARA
23
MARB
7
0
ETCRAH
7
0
ETCRAL
15
0
ETCRB
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
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Section 7 DMA Controller (DMAC)
Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
Address TB
Address TA
1st block
2nd block
Transfer
Block area
Address BB
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Nth block
Address BA
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)
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Section 7 DMA Controller (DMAC)
Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Address TA
Address TB
Block area
Transfer
1st block
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BA
2nd block
Nth block
Address BB
Legend:
Address
Address
Address
Address
Where :
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)
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ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at
this point, an interrupt request is sent to the CPU or DTC.
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Section 7 DMA Controller (DMAC)
Figure 7.15 shows the operation flow in block transfer mode.
Start
(DTE = DTME = 1)
Transfer request?
No
Yes
Acquire bus
Read address specified by MARA
MARA = MARA + SAIDE·(–1)SAID·2DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE·(–1)DAID ·2DTSZ
ETCRAL = ETCRAL – 1
ETCRAL = H'00
No
Yes
Release bus
ETCRAL = ETCRAH
BLKDIR = 0
No
Yes
MARB = MARB – DAIDE·(–1)DAID·2DTSZ·ETCRAH
MARA = MARA – SAIDE·(–1)SAID·2DTSZ·ETCRAH
ETCRB = ETCRB – 1
No
ETCRB = H'0000
Yes
Clear DTE bit to 0
to end transfer
Figure 7.15 Operation Flow in Block Transfer Mode
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Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, EP1FIFO full interrupt and
EP2FIFO empty interrupt of the USB, and TPU channel 0 to 5 compare match/input capture A
interrupts.
Figure 7.16 shows an example of the setting procedure for block transfer mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Block transfer
mode setting
Set DMABCRH
Set transfer source
and transfer destination
addresses
[1]
[2]
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
Set DMABCRL
[6]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Set the BLKE bit to 1 to select block transfer
mode.
• Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Block transfer mode
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Figure 7.16 Example of Block Transfer Mode Setting Procedure
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7.5.8
Section 7 DMA Controller (DMAC)
Basic Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
CPU cycle
DMAC cycle (1-word transfer)
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
φ
Source
address
Destination address
Address bus
RD
HWR
LWR
Figure 7.17 Example of DMA Transfer Bus Timing
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Section 7 DMA Controller (DMAC)
7.5.9
(1)
DMA Transfer (Dual Address Mode) Bus Cycles
Short Address Mode
Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short
address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state
access space to internal I/O space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.
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(2)
Section 7 DMA Controller (DMAC)
Full Address Mode (Cycle Steal Mode)
Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
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Section 7 DMA Controller (DMAC)
(3)
Full Address Mode (Burst Mode)
Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Last transfer cycle
Bus release
Bus release
Burst transfer
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI interrupt is generated while a channel designated for burst transfer is in the transfer
enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer
disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on
completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is
suspended. If the last transfer cycle of the burst transfer has already been activated inside the
DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.
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(4)
Section 7 DMA Controller (DMAC)
Full Address Mode (Block Transfer Mode)
Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Block transfer
Bus release
Last block transfer
Bus
release
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is
generated during data transfer, block transfer operation is not affected until data transfer for one
block has ended.
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Section 7 DMA Controller (DMAC)
DREQ Pin Falling Edge Activation Timing
(5)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
DMA
read
Bus release
DMA
write
Bus
release
DMA
read
DMA
write
Bus
release
Transfer source
Transfer destination
φ
DREQ
Address
bus
DMA
control
Transfer source Transfer destination
Idle
Channel
Read
Write
Idle
Read
Request clear period
Request
[1]
[2]
Idle
Request clear period
Request
Minimum
of 2 cycles
Write
Minimum
of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
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DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
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Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling
edge.
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
write
DMA Bus
dead release
DMA
read
DMA
write
DMA
dead
Bus
release
φ
DREQ
Address
bus
DMA
control
Transfer source
Read
Idle
Channel
Request
Transfer destination
Dead
Write
Request clear period
Idle
[2]
Read
Write
Transfer destination
Dead
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
Transfer source
Minimum
of 2 cycles
[3]
[4]
[5]
[6]
[7]
Acceptance resumes
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
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Section 7 DMA Controller (DMAC)
DREQ Pin Low Level Activation Timing (Normal Mode)
(6)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
DMA
read
DMA
write
Transfer source
Transfer destination
Bus
release
DMA
read
DMA
write
Transfer source
Transfer destination
Bus
release
Bus
release
φ
DREQ
Address
bus
DMA
control
Idle
Read
Channel
Request
Write
Idle
Read
Request clear period
[1]
[2]
Idle
Request clear period
Request
Minimum
of 2 cycles
Write
Minimum
of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
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Section 7 DMA Controller (DMAC)
Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
write
DMA
Bus
dead release
DMA
read
DMA
write
DMA
dead
Bus
release
φ
DREQ
Address
bus
DMA
control
Transfer source
Idle
Read
Channel
Dead
Write
Request clear period
Request
Idle
[2]
Read
Write
Transfer destination
Dead
Idle
Request clear period
Request
Minimum
of 2 cycles
[1]
Transfer source
Transfer destination
Minimum
of 2 cycles
[3]
[4]
[5]
[6]
[7]
Acceptance resumes
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
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7.5.10
(1)
Section 7 DMA Controller (DMAC)
DMA Transfer (Single Address Mode) Bus Cycles
Single Address Mode (Read)
Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
DMA read
DMA read
DMA
DMA read dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
cycle
release
Bus
release
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)
Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
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Section 7 DMA Controller (DMAC)
DMA read
DMA read
DMA read
DMA
dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 7.27 Example of Single Address Mode (Word Read) Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
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(2)
Section 7 DMA Controller (DMAC)
Single Address Mode (Write)
Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
DMA write
DMA write
DMA write
DMA
DMA write dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
release
cycle
Bus
release
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)
Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
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Section 7 DMA Controller (DMAC)
DMA write
DMA write
DMA write
DMA
dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
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(3)
Section 7 DMA Controller (DMAC)
DREQ Pin Falling Edge Activation Timing
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
Bus release
DMA single
Bus release
DMA single
Bus release
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Idle
Single
Channel
Request
Idle
Request clear
period
Single
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
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DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
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Section 7 DMA Controller (DMAC)
DREQ Pin Low Level Activation Timing
(4)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
Bus release
DMA single
Bus release
Bus
release
DMA single
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Single
Idle
Channel
Single
Idle
Request clear
period
Request
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
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When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.11
Write Data Buffer Function
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfer and internal accesses
(on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are
independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output from the TEND pin is an external bus cycle. However, a low level is not output from the
TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal
bus cycle, and an external write cycle is executed in parallel with this cycle.
Figure 7.32 shows an example of dual address transfer using the write data buffer function. The
data is transferred from on-chip RAM to external memory.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Internal address
Internal read signal
External address
HWR, LWR
TEND
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function
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Section 7 DMA Controller (DMAC)
Figure 7.33 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
DMA
read
DMA
single
CPU
read
DMA
single
CPU
read
φ
Internal address
Internal read signal
External address
RD
DACK
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.12
Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.11 summarizes the priority order for DMAC channels.
Table 7.11 DMAC Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1B
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Section 7 DMA Controller (DMAC)
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA read
DMA write
DMA read
DMA write
DMA read
DMA
DMA write read
φ
Address bus
RD
HWR
LWR
DMA control Idle Read
Channel 0A
Idle
Write
Read
Write
Idle
Read
Write
Read
Request clear
Channel 0B
Request
hold
Selection
Channel 1
Request
hold
Nonselection
Bus
release
Channel 0A
transfer
Request clear
Request
hold
Bus
release
Selection
Channel 0B
transfer
Request clear
Channel 1 transfer
Bus
release
Figure 7.34 Example of Multi-Channel Transfer
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7.5.13
Section 7 DMA Controller (DMAC)
Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC*
When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle*, or
external bus release cycle may arise. In this case, the bus controller will suspend the transfer and
insert a refresh cycle, EXDMAC cycle*, or external bus release cycle, in accordance with the
external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An
external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed
until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle, EXDMAC cycle*, or external bus
release cycle.
Note: * Not supported by the H8S/2454 Group.
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Section 7 DMA Controller (DMAC)
7.5.14
DMAC and NMI Interrupts
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit in
DMABCRL are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt
is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1
again. Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an
NMI interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
DTE bit = 1
DTME bit = 0
[1]
Check that DTE = 1 and
DTME = 0 in DMABCRL.
[2]
Write 1 to the DTME bit.
[1]
No
Yes
Set DTME bit to 1
Transfer continues
[2]
Transfer ends
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted by
NMI Interrupt
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7.5.15
Section 7 DMA Controller (DMAC)
Forced Termination of DMAC Operation
If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops
on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the
DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL.
Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
[1]
Forced termination
of DMAC
Clear DTE bit to 0
Clear the DTE bit in DMABCRL to 0.
To prevent interrupt generation after forced
termination of DMAC operation, clear the DTIE bit
to 0 at the same time.
[1]
Forced termination
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation
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Section 7 DMA Controller (DMAC)
7.5.16
Clearing Full Address Mode
Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address
mode. After full address mode has been cleared, the channel can be set to another transfer mode
using the appropriate setting procedure.
[1] Clear both the DTE bit and DTME bit in
DMABCRL to 0, or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0. Also clear the corresponding
DTIE bit to 0 at the same time.
Clearing full
address mode
Stop the channel
[1]
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
Initialize DMACR
[2]
Clear FAE bit to 0
[3]
Initialization;
operation halted
Figure 7.37 Example of Procedure for Clearing Full Address Mode
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7.6
Section 7 DMA Controller (DMAC)
Interrupt Sources
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt Source
Interrupt Name
Short Address Mode
Full Address Mode
DMTEND0A
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
DMTEND0B
Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
DMTEND1A
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
DMTEND1B
Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1
Interrupt
Priority Order
High
Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for
the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt
controller independently. The priority of transfer end interrupts on each channel is decided by the
interrupt controller, as shown in table 7.12.
Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.
DTE/
DTME
Transfer end/transfer
break interrupt
DTIE
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR
should be set so as to prevent the occurrence of a combination that constitutes a condition for
interrupt generation during setting.
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Section 7 DMA Controller (DMAC)
7.7
(1)
Usage Notes
DMAC Register Access during Operation
Except for forced termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
•
DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an
example of the update timing for DMAC registers in dual address transfer mode.
DMA last transfer cycle
DMA transfer cycle
DMA read
DMA read
DMA write
DMA write
DMA
dead
φ
DMA Internal
address
DMA control
Idle
DMA register
operation
[1]
Transfer
source
Transfer
destination
Read
Write
[2]
Transfer
destination
Transfer
source
Read
Idle
[1]
Dead
Write
[2']
Idle
[3]
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2']Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Figure 7.39 DMAC Register Update Timing
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Section 7 DMA Controller (DMAC)
• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 7.40.
DMA transfer cycle
CPU longword read
MAR upper
word read
MAR lower
word read
DMA read
DMA write
φ
DMA internal
address
DMA control
DMA register
operation
Idle
[1]
Transfe
source
Transfer
destination
Read
Write
Idle
[2]
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 7.40 Contention between DMAC Register Update and CPU Read
(2)
Module Stop
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
•
•
•
Transfer end/break interrupt (DTE = 0 and DTIE = 1)
TEND pin enable (TEE = 1)
DACK pin enable (FAE = 0 and SAE = 1)
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Section 7 DMA Controller (DMAC)
(3)
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Write Data Buffer Function
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfers and internal
accesses (on-chip memory or internal I/O registers) are executed in parallel.
•
Write data buffer function and DMAC register setting
If the setting of a register that controls external accesses is changed during execution of an
external access by means of the write data buffer function, the external access may not be
performed normally. Registers that control external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not
performed in parallel with external access.
• Write data buffer function and next DMAC operation
The DMAC can start its next operation during external access using the write data buffer
function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are
different from the case in which the write data buffer function is disabled. Also, internal bus
cycles maybe hidden, and not visible.
(4)
TEND Output
If the last transfer cycle is for an internal address, note that even if low-level output at the TEND
pin has been set, a low level may not be output at the TEND pin under the following external bus
conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed
in parallel.
1.
2.
3.
4.
5.
EXDMAC cycle*
Write cycle with write buffer mode enabled
DMAC single address cycle for a different channel with write buffer mode enabled
Bus release cycle
CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
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Section 7 DMA Controller (DMAC)
However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in
this case for the refresh cycle.
Note: * Not supported by the H8S/2454 Group.
DMA
read
DMA
write
φ
Internal address
Internal read signal
Internal write signal
External address
HWR, LWR
TEND
Not output
External write by CPU, etc.
Figure 7.41 Example in which Low Level Is Not Output at TEND Pin
(5)
Activation by Falling Edge on DREQ Pin
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is
enabled is performed on detection of a low level.
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Section 7 DMA Controller (DMAC)
(6)
H8S/2456, H8S/2456R, H8S/2454 Group
Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge
sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is
detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that
occurs before write to DMABCRL to enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
(7)
Internal Interrupt after End of Transfer
When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible
termination, the selected internal interrupt request will be sent to the CPU or DTC even if the
DTA bit in DMABCRH is set to 1.
Also, if internal DMAC activation has already been initiated when operation is forcibly
terminated, the transfer is executed but flag clearing is not performed for the selected internal
interrupt even if the DTA bit is set to 1.
An internal interrupt request following the end of transfer or a forcible termination should be
handled by the CPU as necessary.
(8)
Channel Re-Setting
To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write 1 to them.
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Section 8 EXDMA Controller (EXDMAC)
Section 8 EXDMA Controller (EXDMAC)
This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The
EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external
devices and external memory with a DACK (EXDMA transfer notification) facility.
Note: This EXDMAC is not supported by the H8S/2454 Group.
8.1
Features
•
•
•
•
•
•
•
•
•
•
•
Direct specification of 16-Mbyte address space
Selection of byte or word transfer data length
Maximum number of transfers: 16M (16,777,215)/infinite (free-running)
Selection of dual address mode or single address mode
Selection of cycle steal mode or burst mode as bus mode
Selection of normal mode or block transfer mode as transfer mode
Two kinds of transfer requests: external request and auto-request
An interrupt request can be sent to the CPU at the end of the specified number of transfers.
Repeat area designation function:
Operation in parallel with internal bus master:
Acceptance of a transfer request and the start of transfer processing can be reported to an
external device via the EDRAK pin.
• Module stop state can be set.
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Section 8 EXDMA Controller (EXDMAC)
Figure 8.1 shows a block diagram of the EXDMAC.
Bus controller
Data buffer
Control logic
EDRAK
Processor
ETEND
EDACK
Interrupt request
signals to CPU
for individual
channels
Address buffer
EDSAR
EDDAR
EDMDR
EDACR
Module data bus
External pins
EDREQ
EDTCR
Internal data bus
[Legend]
EDSAR:
EDDAR:
EDTCR:
EDMDR:
EDACR:
EXDMA source address register
EXDMA destination address register
EXDMA transfer count register
EXDMA mode control register
EXDMA address control register
Figure 8.1 Block Diagram of EXDMAC
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8.2
Section 8 EXDMA Controller (EXDMAC)
Input/Output Pins
Table 8.1 shows the pin configuration of the EXDMAC.
Table 8.1
Pin Configuration
Channel
Name
Abbreviation
I/O
Function
2
EXDMA transfer request 2
EDREQ2
Input
Channel 2 external request
EXDMA transfer
acknowledge 2
EDACK2
Output
Channel 2 single address transfer
acknowledge
EXDMA transfer end 2
ETEND2
Output
Channel 2 transfer end
EDREQ2 acceptance
acknowledge
EDRAK2
Output
Notification to external device of
channel 2 external request
acceptance and start of transfer
processing
EXDMA transfer request 3
EDREQ3
Input
Channel 3 external request
EXDMA transfer
acknowledge 3
EDACK3
Output
Channel 3 single address transfer
acknowledge
EXDMA transfer end 3
ETEND3
Output
Channel 3 transfer end
EDREQ3 acceptance
acknowledge
EDRAK3
Output
Notification to external device of
channel 3 external request
acceptance and start of transfer
processing
3
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Section 8 EXDMA Controller (EXDMAC)
8.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The EXDMAC has the following registers.
•
•
•
•
•
•
•
•
•
•
EXDMA source address register_2 (EDSAR_2)
EXDMA destination address register_2 (EDDAR_2)
EXDMA transfer count register_2 (EDTCR_2)
EXDMA mode control register_2 (EDMDR_2)
EXDMA address control register_2 (EDACR_2)
EXDMA source address register_3 (EDSAR_3)
EXDMA destination address register_3 (EDDAR_3)
EXDMA transfer count register_3 (EDTCR_3)
EXDMA mode control register_3 (EDMDR_3)
EXDMA address control register_3 (EDACR_3)
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8.3.1
Section 8 EXDMA Controller (EXDMAC)
EXDMA Source Address Register (EDSAR)
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the EDSAR value is ignored
when a device with DACK is specified as the transfer source.
The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR
are undefined.
8.3.2
EXDMA Destination Address Register (EDDAR)
EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
EDDAR value is ignored when a device with DACK is specified as the transfer destination.
The upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
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Section 8 EXDMA Controller (EXDMAC)
8.3.3
EXDMA Transfer Count Register (EDTCR)
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
(1)
Normal Transfer Mode
Bit
Bit Name
Initial Value
R/W
Description
31 to 24
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
23 to 0
All 0
R/W
24-Bit Transfer Counter
These bits specify the number of transfers. Setting
H'000001 specifies one transfer. Setting H'000000
means no specification for the number of
transfers, and the transfer counter function is
halted. In this case, there is no transfer end
interrupt by the transfer counter. Setting
H'FFFFFF specifies the maximum number of
transfers, that is 16,777,215. During EXDMA
transfer, this counter shows the remaining number
of transfers.
This counter can be read at all times. When
reading EDTCR for a channel on which EXDMA
transfer processing is in progress, a longword-size
read must be executed.
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Section 8 EXDMA Controller (EXDMAC)
(2)
Block Transfer Mode
Bit
Bit Name
Initial Value
R/W
Description
31 to 24
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
23 to 16
Undefined
R/W
Block Size
These bits specify the block size (number of bytes
or number of words) for block transfer. Setting
H'01 specifies one as the block, while setting H'00
specifies the maximum block size, that is 256. The
register value always indicates the specified block
size.
15 to 0
Undefined
R/W
16-Bit Transfer Counter
These bits specify the number of block transfers.
Setting H'0001 specifies one block transfer.
Setting H'0000 means no specification for the
number of transfers, and the transfer counter
function is halted. In this case, there is no transfer
end interrupt by the transfer counter. Setting
H'FFFF specifies the maximum number of block
transfers, that is 65,535. During EXDMA transfer,
this counter shows the remaining number of block
transfers.
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Section 8 EXDMA Controller (EXDMAC)
8.3.4
EXDMA Mode Control Register (EDMDR)
EDMDR controls EXDMAC operations.
Bit
Bit Name
Initial Value
R/W
Description
15
EDA
0
R/(W)
EXDMA Active
Enables or disables data transfer on the
corresponding channel. When this bit is set to 1,
this indicates that an EXDMA operation is in
progress.
When auto request mode is specified (by bits
MDS1 and MDS0), transfer processing begins
when this bit is set to 1. With external requests,
transfer processing begins when a transfer
request is issued after this bit has been set to 1.
When this bit is cleared to 0 during an EXDMA
operation, transfer is halted. If this bit is cleared to
0 during an EXDMA operation in block transfer
mode, transfer processing is continued for the
currently executing one-block transfer, and the bit
is cleared on completion of the currently executing
one-block transfer.
If an external source that ends (aborts) transfer
occurs, this bit is automatically cleared to 0 and
transfer is terminated. Do not change the
operating mode, transfer method, or other
parameters while this bit is set to 1.
0: Data transfer disabled on corresponding
channel
[Clearing conditions]
•
When the specified number of transfers end
•
When operation is halted by a repeat area
overflow interrupt
•
When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective after
end of one-block transfer)
•
Reset, NMI interrupt, hardware standby mode
1: Data transfer enabled on corresponding
channel
Note: The value written in the EDA bit may not
be effective immediately.
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
14
BEF
0
R/(W)*
Block Transfer Error Flag
Flag that indicates the occurrence of an error
during block transfer. If an NMI interrupt is
generated during block transfer, the EXDMAC
immediately terminates the EXDMA operation and
sets this bit to 1. The address registers indicate
the next transfer addresses, but the data for which
transfer has been performed within the block size
is lost.
0: No block transfer error
[Clearing condition]
Writing 0 to BEF after reading BEF = 1
1: Block transfer error
[Setting condition]
NMI interrupt during block transfer
13
EDRAKE
0
R/W
EDRAK Pin Output Enable
Enables output from the EDREQ
acknowledge/transfer processing start (EDRAK)
pin.
0: EDRAK pin output disabled
1: EDRAK pin output enabled
12
ETENDE
0
R/W
ETEND Pin Output Enable
Enables output from the EXDMA transfer end
(ETEND) pin.
0: ETEND pin output disabled
1: ETEND pin output enabled
11
EDREQS
0
R/W
EDREQ Select
Specifies low level sensing or falling edge sensing
as the sampling method for the EDREQ pin used
in external request mode.
0: Low level sensing (Low level sensing is used
for the first transfer after transfer is enabled.)
1: Falling edge sensing
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
10
AMS
0
R/W
Address Mode Select
Selects single address mode or dual address
mode. When single address mode is selected, the
EDACK pin is valid.
0: Dual address mode
1: Single address mode
9
MDS1
0
R/W
Mode Select 1 and 0
8
MDS0
0
R/W
These bits specify the activation source, bus
mode, and transfer mode.
00: Auto request, cycle steal mode, normal
transfer mode
01: Auto request, burst mode, normal transfer
mode
10: External request, cycle steal mode, normal
transfer mode
11: External request, cycle steal mode, block
transfer mode
7
EDIE
0
R/W
EXDMA Interrupt Enable
Enables or disables interrupt requests. When this
bit is set to 1, an interrupt is requested when the
IRF bit is set to 1. The interrupt request is cleared
by clearing this bit or the IRF bit to 0.
0: Interrupt request is not generated
1: Interrupt request is generated
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
6
IRF
0
R/(W)*
Interrupt Request Flag
Flag indicating that an interrupt request has
occurred and transfer has ended.
0: No interrupt request
[Clearing conditions]
•
Writing 1 to the EDA bit
•
Writing 0 to IRF after reading IRF = 1
1: Interrupt request occurrence
[Setting conditions]
5
TCEIE
0
R/W
•
Transfer end interrupt request generated by
transfer counter
•
Source address repeat area overflow interrupt
request
•
Destination address repeat area overflow
interrupt request
Transfer Counter End Interrupt Enable
Enables or disables transfer end interrupt requests
by the transfer counter. When transfer ends
according to the transfer counter while this bit is
set to 1, the IRF bit is set to 1, indicating that an
interrupt request has occurred.
0: Transfer end interrupt requests by transfer
counter are disabled
1: Transfer end interrupt requests by transfer
counter are enabled
4
SDIR
0
R/W
Single Address Direction
Specifies the data transfer direction in single
address mode. In dual address mode, the
specification by this bit is ignored.
0: Transfer direction: EDSAR → external device
with DACK
1: Transfer direction: External device with
DACK→ EDDAR
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
3
DTSIZE
0
R/W
Data Transmit Size
Specifies the size of data to be transferred.
0: Byte-size
1: Word-size
2
BGUP
0
R/W
Bus Give-Up
When this bit is set to 1, the bus can be
transferred to an internal bus master in burst mode
or block transfer mode. This setting is ignored in
normal mode and cycle steal mode.
0: Bus is not released
1: Bus is transferred if requested by an internal
bus master
1
⎯
0
R/W
Reserved
0
⎯
0
R/W
These bits are always read as 0. The initial values
should not be modified.
Note:
*
Only 0 can be written, to clear the flag.
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8.3.5
Section 8 EXDMA Controller (EXDMAC)
EXDMA Address Control Register (EDACR)
EDACR specifies address register incrementing/decrementing and use of the repeat area function.
Bit
Bit Name
Initial Value
R/W
Description
15
SAT1
0
R/W
Source Address Update Mode
14
SAT0
0
R/W
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0x: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
13
SARIE
0
R/W
Source Address Repeat Interrupt Enable
When this bit is set to 1, in the event of source
address repeat area overflow, the IRF bit is set to
1 and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU.
When used together with block transfer mode, a
source address repeat interrupt is requested at the
end of a block-size transfer. If the EDA bit is set to
1 in EDMDR for the channel on which transfer is
terminated by a source address repeat interrupt,
transfer can be resumed from the state in which it
ended. If a source address repeat area has not
been designated, this bit is ignored.
0: Source address repeat interrupt is not
requested
1: When source address repeat area overflow
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
12
SARA4
0
R/W
Source Address Repeat Area
11
SARA3
0
R/W
10
SARA2
0
R/W
9
SARA1
0
R/W
8
SARA0
0
R/W
These bits specify the source address (EDSAR)
repeat area. The repeat area function updates the
specified lower address bits, leaving the remaining
upper address bits always the same. A repeat
area size of 2 bytes to 8 Mbytes can be specified.
The setting interval is a power-of-two number of
bytes. When repeat area overflow results from
incrementing or decrementing an address, the
lower address is the start address of the repeat
area in the case of address incrementing, or the
last address of the repeat area in the case of
address decrementing. If the SARIE bit is set to 1,
an interrupt can be requested when repeat area
overflow occurs.
00000: Not designated as repeat area
00001: Lower 1 bit (2-byte area) designated as
repeat area
00010: Lower 2 bits (4-byte area) designated as
repeat area
00011: Lower 3 bits (8-byte area) designated as
repeat area
00100: Lower 4 bits (16-byte area) designated as
repeat area
:
:
10011: Lower 19 bits (512-Kbyte area) designated
as repeat area
10100: Lower 20 bits (1-Mbyte area) designated
as repeat area
10101: Lower 21 bits (2-Mbyte area) designated
as repeat area
10110: Lower 22 bits (4-Mbyte area) designated
as repeat area
10111: Lower 23 bits (8-Mbyte area) designated
as repeat area
11xxx: Setting prohibited
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
7
DAT1
0
R/W
Destination Address Update Mode
6
DAT0
0
R/W
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0x: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
5
DARIE
0
R/W
Destination Address Repeat Interrupt Enable
When this bit is set to 1, in the event of destination
address repeat area overflow the IRF bit is set to 1
and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU. When used
together with block transfer mode, a destination
address repeat interrupt is requested at the end of
a block-size transfer. If the EDA bit is set to 1 in
EDMDR for the channel on which transfer is
terminated by a destination address repeat
interrupt, transfer can be resumed from the state
in which it ended. If a destination address repeat
area has not been designated, this bit is ignored.
0: Destination address repeat interrupt is not
requested
1: When destination address repeat area overflow
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
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Section 8 EXDMA Controller (EXDMAC)
Bit
Bit Name
Initial Value
R/W
Description
4
DARA4
0
R/W
Destination Address Repeat Area
3
DARA3
0
R/W
2
DARA2
0
R/W
1
DARA1
0
R/W
0
DARA0
0
R/W
These bits specify the destination address
(EDDAR) repeat area. The repeat area function
updates the specified lower address bits, leaving
the remaining upper address bits always the
same. A repeat area size of 2 bytes to 8 Mbytes
can be specified. The setting interval is a powerof-two number of bytes. When repeat area
overflow results from incrementing or
decrementing an address, the lower address is the
start address of the repeat area in the case of
address incrementing, or the last address of the
repeat area in the case of address decrementing.
If the DARIE bit is set to 1, an interrupt can be
requested when repeat area overflow occurs.
00000: Not designated as repeat area
00001: Lower 1 bit (2-byte area) designated as
repeat area
00010: Lower 2 bits (4-byte area) designated as
repeat area
00011: Lower 3 bits (8-byte area) designated as
repeat area
00100: Lower 4 bits (16-byte area) designated as
repeat area
:
:
10011: Lower 19 bits (512-Kbyte area) designated
as repeat area
10100: Lower 20 bits (1-Mbyte area) designated
as repeat area
10101: Lower 21 bits (2-Mbyte area) designated
as repeat area
10110: Lower 22 bits (4-Mbyte area) designated
as repeat area
10111: Lower 23 bits (8-Mbyte area) designated
as repeat area
11xxx: Setting prohibited
[Legend]
x:
Don't care
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8.4
Operation
8.4.1
Transfer Modes
Section 8 EXDMA Controller (EXDMAC)
The transfer modes of the EXDMAC are summarized in table 8.2.
Table 8.2
EXDMAC Transfer Modes
Transfer Mode
Dual
address
mode
Normal
transfer
mode
Auto request mode
• Burst/cycle steal
mode
External request
mode
Address Registers
Transfer
Origin
Number of
Transfers
Auto
request
1 to
EDSAR
16,777,215
or no
specification
Source
Destination
EDDAR
External
request
• Cycle steal mode
Block
transfer
mode
External request
mode
External
request
• Burst transfer of
specified block
size for a single
transfer request
1 to 65,535
or no
specification
• Block size: 1 to
256 bytes or
words
Single
address
mode
• Direct data transfer to/from external device using
EDACK pin instead of source or destination address
register
EDSAR/
EDACK
EDACK/
EDDAR
• Above transfer mode can be specified in addition to
address register setting
• One transfer possible in one bus cycle
(Transfer mode variations are the same as in dual
address mode.)
The transfer mode can be set independently for each channel.
In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer
request. With auto requests, burst or cycle steal transfer mode can be set. In burst transfer mode,
continuous, high-speed transfer can be performed until the specified number of transfers have
been executed or the transfer enable bit is cleared to 0.
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Section 8 EXDMA Controller (EXDMAC)
H8S/2456, H8S/2456R, H8S/2454 Group
In block transfer mode, a transfer of the specified block size is executed in response to one transfer
request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be
performed at the same high speed as in block transfer mode.
When the "no specification" setting (EDTCR = H'000000) is made for the number of transfers, the
transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be
performed endlessly.
Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged,
can be specified independently for each address register.
In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of
bytes.
8.4.2
(1)
Address Modes
Dual Address Mode
In dual address mode, both the transfer source and transfer destination are specified by registers in
the EXDMAC, and one transfer is executed in two bus cycles.
The transfer source address is set in the source address register (EDSAR), and the transfer
destination address is set in the transfer destination address register (EDDAR).
In a transfer operation, the value in external memory specified by the transfer source address is
read in the first bus cycle, and is written to the external memory specified by the transfer
destination address in the next bus cycle.
These consecutive read and write cycles are indivisible: another bus cycle (external access by an
internal bus master, refresh cycle, or external bus release cycle) does not occur between these two
cycles.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for two consecutive bus cycles. The EDACK signal is not output.
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Section 8 EXDMA Controller (EXDMAC)
Figure 8.2 shows an example of the timing in dual address mode.
EXDMA
read cycle
EXDMA
write cycle
φ
Address bus
EDSAR
EDDAR
RD
WR
ETEND
Figure 8.2 Example of Timing in Dual Address Mode
(2)
Single Address Mode
In single address mode, the EDACK signal is used instead of the source or destination address
register to transfer data directly between an external device and external memory. In this mode,
the EXDMAC accesses the transfer source or transfer destination external device by outputting the
external I/O strobe signal (EDACK), and at the same time accesses the other external device in the
transfer by outputting an address. In this way, EXDMA transfer can be executed in one bus cycle.
In the example of transfer between external memory and an external device with DACK shown in
figure 8.3, data is output to the data bus by the external device and written to external memory in
the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from
the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the
external device with DACK to the external memory (EDDAR) when SDIR = 1.
The setting in the source or destination address register not used in the transfer is ignored.
The EDACK pin becomes valid automatically when single address mode is selected. The EDACK
pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in
EDMDR. ETEND is output for one bus cycle.
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Section 8 EXDMA Controller (EXDMAC)
Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the
timing.
External
address bus
External
data bus
Microcomputer
External
memory
EXDMAC
External device
with DACK
EDACK
EDREQ
Data flow
Figure 8.3 Data Flow in Single Address Mode
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Section 8 EXDMA Controller (EXDMAC)
Transfer from external memory to external device with DACK
EXDMA cycle
φ
Address bus
EDSAR
RD
Address to external memory space
RD signal to external memory space
WR
EDACK
Data output from external memory
Data bus
ETEND
Transfer from external device with DACK to external memory
EXDMA cycle
φ
Address bus
EDDAR
Address to external memory space
RD
WR
WR signal to external memory space
EDACK
Data output from external device
with DACK
Data bus
ETEND
Figure 8.4 Example of Timing in Single Address Mode
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Section 8 EXDMA Controller (EXDMAC)
8.4.3
(1)
H8S/2456, H8S/2456R, H8S/2454 Group
EXDMA Transfer Requests
Auto Request Mode
In auto request mode, transfer request signals are automatically generated within the EXDMAC in
cases where a transfer request signal is not issued from outside, such as in transfer between two
memories, or between a peripheral module that is not capable of generating transfer requests and
memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR.
In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.
Block transfer mode cannot be used.
(2)
External Request Mode
In external request mode, transfer is started by a transfer request signal (EDREQ) from a device
external to this LSI. EXDMA transfer is started when EDREQ is input while EXDMA transfer is
enabled (EDA = 1).
The transfer request source need not be the data transfer source or data transfer destination.
The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level
sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level
sensing when EDREQS = 0, falling edge sensing when EDREQS = 1).
Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance
to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer
processing has been started in response to a single external request. The EDRAK signal enables
the external device to determine the timing of EDREQ signal negation, and makes it possible to
provide handshaking between the transfer request source and the EXDMAC.
In external request mode, block transfer mode can be used instead of burst mode. Block transfer
mode allows continuous execution (burst operation) of the specified number of transfers (the block
size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output
only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block
unit.
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8.4.4
Section 8 EXDMA Controller (EXDMAC)
Bus Modes
There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto
request, either cycle steal mode or burst mode can be selected. When the activation source is an
external request, cycle steal mode is used.
(1)
Cycle Steal Mode
In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit
(byte, word, or block). If there is a subsequent transfer request, the EXDMAC takes back the bus,
performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated
until the transfer end condition is satisfied.
If a transfer request occurs in another channel during EXDMA transfer, the bus is temporarily
released, then transfer is performed on the channel for which the transfer request was issued. If
there is no external space bus request from another bus master, a one-cycle bus release interval is
inserted. For details on the operation when there are requests for a number of channels, see section
8.4.8, Channel Priority Order.
Figure 8.5 shows an example of the timing in cycle steal mode.
EDREQ
EDRAK
Bus cycle
CPU
CPU
EXDMAC
CPU
CPU
EXDMAC
Bus returned temporarily to CPU
Transfer conditions:
· Single address mode, normal transfer mode
· EDREQ low level sensing
· CPU internal bus master is operating in external space
Figure 8.5 Example of Timing in Cycle Steal Mode
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Section 8 EXDMA Controller (EXDMAC)
(2)
Burst Mode
In burst mode, once the EXDMAC acquires the bus it continues transferring data, without
releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external
request mode.
In burst mode, once transfer is started it is not interrupted even if there is a transfer request from
another channel with higher priority. When the burst mode channel finishes its transfer, it releases
the bus in the next cycle in the same way as in cycle steal mode.
When the EDA bit is cleared to 0 in EDMDR, EXDMA transfer is halted. However, EXDMA
transfer is executed for all transfer requests generated within the EXDMAC up until the EDA bit
was cleared to 0.
If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is
terminated.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during burst transfer. If there is no bus request, burst transfer is executed even if the
BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
Bus cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU
CPU cycle not generated
Transfer conditions:
Auto request mode, BGUP = 0
Bus cycle
CPU
EXDMAC
CPU
EXDMAC
CPU
EXDMAC
CPU
EXDMAC operates alternately with CPU
Transfer conditions:
Auto request mode, BGUP = 1
Figure 8.6 Examples of Timing in Burst Mode
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8.4.5
Section 8 EXDMA Controller (EXDMAC)
Transfer Modes
There are two transfer modes: normal transfer mode and block transfer mode. When the activation
source is an external request, either normal transfer mode or block transfer mode can be selected.
When the activation source is an auto request, normal transfer mode is used.
(1)
Normal Transfer Mode
In normal transfer mode, transfer of one transfer unit is processed in response to one transfer
request. EDTCR functions as a 24-bit transfer counter.
The ETEND signal is output only for the last EXDMA transfer. The EDRAK signal is output each
time a transfer request is accepted and transfer processing is started.
Figure 8.7 shows examples of EXDMA transfer timing in normal transfer mode.
Bus cycle
EXDMA
transfer cycle
Last EXDMA
transfer cycle
Read
Read
Write
Write
ETEND
Transfer conditions:
Dual address mode, auto request mode
EDREQ
EDRAK
Bus cycle
EXDMA
EXDMA
EDACK
Transfer conditions:
Single address mode, external request mode
Figure 8.7 Examples of Timing in Normal Transfer Mode
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Section 8 EXDMA Controller (EXDMAC)
(2)
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Block Transfer Mode
In block transfer mode, the number of bytes or words specified by the block size is transferred in
response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower
16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During
transfer of a block, transfer requests for other higher-priority channels are held pending. When
transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the
block ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 8.4.6, Repeat Area Function, for details.
Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending EXDMA
Transfer, for details.
Figure 8.8 shows an example of EXDMA transfer timing in block transfer mode.
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Section 8 EXDMA Controller (EXDMAC)
EDREQ
EDRAK
One-block transfer cycle
Bus cycle
CPU
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU cycle not generated
ETEND
Transfer conditions:
· Single address mode
· BGUP = 0
· Block size (EDTCR[23:16]) = 3
Figure 8.8 Example of Timing in Block Transfer Mode
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8.4.6
H8S/2456, H8S/2456R, H8S/2454 Group
Repeat Area Function
The EXDMAC has a function for designating a repeat area for source addresses and/or destination
addresses. When a repeat area is designated, the address register values repeat within the range
specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is
required to restore the address register value to the buffer start address each time the address
register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but
if the repeat area function is used, the operation that restores the address register value to the
buffer start address is performed automatically within the EXDMAC.
The repeat area function can be set independently for the source address register and the
destination address register.
The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the
destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat
area can be specified independently.
When the address register value is the last address in the repeat area and repeat area overflow
occurs, EXDMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the
SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the
IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1
in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to
the destination address register.
If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9
illustrates the operation of the repeat area function.
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Section 8 EXDMA Controller (EXDMAC)
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area
(SARA4 to SARA0 = 3)
External memory
:
Range of
EDSAR values
H'23FFFE
H'23FFFF
H'240000
H'240000
H'240001
H'240001
H'240002
H'240002
H'240003
H'240003
H'240004
H'240004
H'240005
H'240005
H'240006
H'240006
H'240007
H'240007
H'240008
H'240009
Repeated
Repeat area overflow
interrupt can be
requested
:
Figure 8.9 Example of Repeat Area Function Operation
Caution is required when the repeat area overflow interrupt function is used together with block
transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer
mode, the block size must be a power of two, or alternatively, the address register value must be
set so that the end of a block coincides with the end of the repeat area range.
If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat
interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure
8.10 shows an example in which block transfer mode is used together with the repeat area
function.
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Section 8 EXDMA Controller (EXDMAC)
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3),
and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode
External memory
Range of
EDSAR values
First block
transfer
Second block
transfer
H'240000
H'240000
H'240000
H'240000
H'240001
H'240001
H'240001
H'240001
H'240002
H'240002
H'240002
H'240003
H'240003
H'240003
H'240004
H'240004
H'240004
H'240005
H'240005
H'240005
H'240006
H'240006
H'240006
H'240007
H'240007
H'240007
:
H'23FFFE
H'23FFFF
H'240008
Interrupt
requested
Block transfer
in progress
H'240009
:
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode
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8.4.7
Section 8 EXDMA Controller (EXDMAC)
Registers during EXDMA Transfer Operation
EXDMAC register values are updated as EXDMA transfer processing is performed. The updated
values depend on various settings and the transfer status. The following registers and bits are
updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR,
(1)
EXDMA Source Address Register (EDSAR)
When the EDSAR address is accessed as the transfer source, after the EDSAR value is output,
EDSAR is updated with the address to be accessed next. Bits SAT1 and SAT0 in EDACR specify
incrementing or decrementing. The address is fixed when SAT1 = 0, incremented when SAT1 = 1
and SAT0 = 0, and decremented when SAT1 = 1 and SAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.
Do not write to EDSAR for a channel on which a transfer operation is in progress.
(2)
EXDMA Destination Address Register (EDDAR)
When the EDDAR address is accessed as the transfer destination, after the EDDAR value is
output, EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in
EDACR specify incrementing or decrementing. The address is fixed when DAT1 = 0, incremented
when DAT1 = 1 and DAT0 = 0, and decremented when DAT1 = 1 and DAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
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When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
Do not write to EDDAR for a channel on which a transfer operation is in progress.
(3)
EXDMA Transfer Count Register (EDTCR)
When an EXDMA transfer is performed, the value in EDTCR is decremented by 1. However,
when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change.
EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to
specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function
as a transfer counter, the value of which is decremented by 1 when an EXDMA transfer is
performed. However, when the EDTCR[15:0] value is 0, transfers are not counted and the
EDTCR[15:0] value does not change.
In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read
by the CPU during EXDMA transfer, a longword access must be used. During a transfer
operation, EDTCR may be updated without regard to accesses from the CPU, and the correct
values may not be read if the upper and lower words are read separately. In a longword access, the
EXDMAC buffers the EDTCR value to ensure that the correct value is output.
In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word
access.
Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is
contention between an address update associated with EXDMA transfer and a write by the CPU,
the CPU write has priority.
In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value)
by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated.
Transfer does not end if the CPU writes 0 to EDTCR.
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Section 8 EXDMA Controller (EXDMAC)
Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
EDTCR in normal transfer mode
Before update
23
After update
0
EDTCR
Fixed
23
0
0
23
EDTCR
0
0
–1
1 to H'FFFFFF
23
0
0 to H'FFFFFE
EDTCR in block transfer mode
EDTCR
Before update
23
16 15
Block
0
size
EDTCR
23
16 15
Block
1 to H'FFFF
size
0
0
Fixed
–1
After update
23
16 15
Block
0
size
0
23
16 15
Block
0 to H'FFFE
size
0
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
Block Transfer Mode
(4)
EDA Bit in EDMDR
The EDA bit in EDMDR is written to by the CPU to control enabling and disabling of data
transfer, but may be cleared automatically by the EXDMAC due to the EXDMA transfer status.
There are also periods during transfer when a 0-write to the EDA bit by the CPU is not
immediately effective.
Conditions for EDA bit clearing by the EXDMAC include the following:
•
•
•
•
•
•
When the EDTCR value changes from 1 to 0, and transfer ends
When a repeat area overflow interrupt is requested, and transfer ends
When an NMI interrupt is generated, and transfer halts
A reset
Hardware standby mode
When 0 is written to the EDA bit, and transfer halts
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When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the EXDMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
In burst mode, transfer is halted for up to three EXDMA transfers following the bus cycle in
which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until
the end of the last DMA cycle.
Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set
to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that
the EDA bit has been cleared to 0.
Figure 8.12 shows the procedure for changing register settings in an operating channel.
[1] Write 0 to the EDA bit in EDMDR.
Changing register settings
in operating channel
Write 0 to EDA bit
[2] Read the EDA bit.
[1]
[3] Confirm that EDA = 0. If EDA = 1, this
indicates that EXDMA transfer is in progress.
[4] Write the required set values to the registers.
Read EDA bit
EDA bit = 0?
[2]
[3]
No
Yes
Change register settings
[4]
Register setting
changes completed
Figure 8.12 Procedure for Changing Register Settings in Operating Channel
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(5)
Section 8 EXDMA Controller (EXDMAC)
BEF Bit in EDMDR
In block transfer mode, the specified number of transfers (equivalent to the block size) is
performed in response to a single transfer request. To ensure that the correct number of transfers is
carried out, a block-size transfer is always executed, except in the event of a reset, transition to
standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
(6)
IRF Bit in EDMDR
The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in
EDMDR is 1 at this time, an interrupt is requested.
The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer
ends following the end of the EXDMA transfer bus cycle in which the source generating the
interrupt occurred.
If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared.
For details on interrupts, see section 8.5, Interrupt Sources.
8.4.8
Channel Priority Order
The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the
EXDMAC channel priority order.
Table 8.3
EXDMAC Channel Priority Order
Channel
Channel 2
Priority
High
Channel 3
Low
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order in table 8.3 is selected for transfer.
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Section 8 EXDMA Controller (EXDMAC)
(1)
Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode)
If transfer requests for different channels are issued during a transfer operation, the highestpriority channel (excluding the currently transferring channel) is selected. The selected channel
begins transfer after the currently transferring channel releases the bus. If there is a bus request
from a bus master other than the EXDMAC at this time, a cycle for the other bus master is
initiated. If there is no other bus request, the bus is released for one cycle.
Channel switching does not take place during a burst transfer or a block transfer of a single block.
Figure 8.13 shows a case in which transfer requests for channels 2 and 3 are issued
simultaneously. The example shown in the figure illustrates the handling of external requests in
the cycle steal mode.
Channel 2 transfer
Channel 3 transfer
φ
Channel 2
Address bus
EXDMA control
Idle
Channel 2
Channel 2
Request cleared
Channel 3
Request Selected
held
Bus
release
Channel 3
Bus
release
Channel 3
Request cleared
Figure 8.13 Example of Channel Priority Timing
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(2)
Section 8 EXDMA Controller (EXDMAC)
Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode
If transfer requests for different channels are issued during a transfer in auto request cycle steal
mode, the operation depends on the channel priority. If the channel that made the transfer request
is of higher priority than the channel currently performing transfer, the channel that made the
transfer request is selected.
If the channel that made the transfer request is of lower priority than the channel currently
performing transfer, that channel's transfer request is held pending, and the currently transferring
channel remains selected.
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other
bus master is initiated. If there is no other bus request, the bus is released for one cycle.
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Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
Conditions (1)
Channel 2: Auto request, cycle steal mode
Channel 3: External request, cycle steal mode, low level activation
Bus
Channel 2
*
Channel 2
*
Channel 2
*
Channel 3
*
Channel 3
*
Channel 2
EDA bit
Channel 3/
EDREQ3 pin
Conditions (2)
Channel 2: External request, cycle steal mode, low level activation
Channel 3: Auto request, cycle steal mode
Bus
Channel 3
*
Channel 3
*
Channel 2
*
Channel 3
*
Channel 2
*
Channel 2
*
Channel 2
*
Channel 3
Channel 2
*
Channel 2/
EDREQ2 pin
Channel 2
EDA bit
Conditions (3)
Channel 2: Auto request, cycle steal mode
Channel 3: Auto request, cycle steal mode
Bus
Channel 3
*
Channel 3
*
Channel 2
EDA bit
Channel 3
EDA bit
*:
Bus release
Figure 8.14 Examples of Channel Priority Timing
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8.4.9
(1)
Section 8 EXDMA Controller (EXDMAC)
EXDMAC Bus Cycles (Dual Address Mode)
Normal Transfer Mode (Cycle Steal Mode)
Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
After one byte or word has been transferred, the bus is released. While the bus is released, one
CPU, DMAC, or DTC bus cycle is initiated.
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
φ
Address bus
RD
HWR
LWR
ETEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
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Section 8 EXDMA Controller (EXDMAC)
(2)
Normal Transfer Mode (Burst Mode)
Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space.
In burst mode, one-byte or one-word transfers are executed continuously until transfer ends.
Once burst transfer starts, requests from other channels, even of higher priority, are held pending
until transfer ends.
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
φ
Address bus
RD
HWR
LWR
ETEND
Bus
release
Last transfer cycle
Burst transfer
Bus
release
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer
If an NMI interrupt is generated while a channel designated for burst transfer is enabled for
transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been
initiated within the EXDMAC, the bus is released on completion of the currently executing byte or
word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been
initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared.
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(3)
Section 8 EXDMA Controller (EXDMAC)
Block Transfer Mode (Cycle Steal Mode)
Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
One block is transferred in response to one transfer request, and after the transfer, the bus is
released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
EXDMA EXDMA EXDMA
read
write
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
φ
Address bus
RD
HWR
LWR
ETEND
Bus
release
Block transfer
Bus
release
Last block transfer
Bus
release
Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer
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Section 8 EXDMA Controller (EXDMAC)
(4)
EDREQ Pin Falling Edge Activation Timing
Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
EXDMA
read
EXDMA
write
Transfer source
Transfer
destination
Write
Idle
Bus release
EXDMA
read
Bus release
EXDMA
write
Bus release
φ
EDREQ
Address bus
EXDMA control
Read
Idle
Channel
Transfer source
Read
Request clearance period
Request
[1]
[2]
[3]
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request clearance period
Request
Minimum 3 cycles
Write
Transfer
destination
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes
after the end of the write cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling
edge.
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Section 8 EXDMA Controller (EXDMAC)
One block transfer
One block transfer
EXDMA
read
EXDMA
write
Transfer source
Transfer
destination
Bus release
EXDMA
read
Bus release
EXDMA
write
Bus release
φ
EDREQ
Address bus
EXDMA control Idle
Read
Channel
Idle
Minimum 3 cycles
[2]
[3]
Idle
Request clearance period
Request
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Transfer
destination
Read Write
Request clearance period
Request
[1]
Write
Transfer source
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.19 Example of Block Transfer Mode Transfer Activated
by EDREQ Pin Falling Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes
after the end of the write cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
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Section 8 EXDMA Controller (EXDMAC)
(5)
EDREQ Pin Low Level Activation Timing
Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
EXDMA
read
EXDMA
write
Transfer source
Transfer
destination
Bus release
EXDMA
read
EXDMA
write
Transfer source
Transfer
destination
Bus release
Bus release
φ
EDREQ
Address bus
EXDMA control Idle
Read
Write
Idle
Request clearance period
Request
Minimum 3 cycles
Channel
[1]
[2]
[3]
Read
Idle
Request clearance period
Request
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Write
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle is started.
Acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low
level.
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Section 8 EXDMA Controller (EXDMAC)
One block transfer
EXDMA
read
Bus release
One block transfer
EXDMA
write
EXDMA
read
Bus release
EXDMA
write
Bus release
φ
EDREQ
Address bus
Transfer source
EXDMA control Idle
Read
Channel
Write
Transfer
destination
Transfer source
Read Write
Idle
Request clearance period
Request
[2]
[3]
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request clearance period
Request
Minimum 3 cycles
[1]
Transfer
destination
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle is started.
Acceptance is resumed after completion of dead cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
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Section 8 EXDMA Controller (EXDMAC)
8.4.10
(1)
EXDMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read)
Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
EXDMA read
EXDMA read
EXDMA read
EXDMA read
φ
Address bus
RD
EDACK
ETEND
Bus release
Bus release
Bus release
Bus release
Bus release
Last
transfer
cycle
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer
Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
EXDMA read
EXDMA read
EXDMA read
φ
Address bus
RD
EDACK
ETEND
Bus release
Bus release
Bus release
Last transfer cycle
Bus
release
Figure 8.23 Example of Single Address Mode (Word Read) Transfer
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Section 8 EXDMA Controller (EXDMAC)
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
(2)
Single Address Mode (Write)
Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
EXDMA write
EXDMA write
EXDMA write
EXDMA write
φ
Address bus
HWR
LWR
EDACK
ETEND
Bus release
Bus release
Bus release
Bus release
Last
Bus release
transfer
cycle
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
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Section 8 EXDMA Controller (EXDMAC)
EXDMA write
EXDMA write
EXDMA write
φ
Address bus
HWR
LWR
EDACK
ETEND
Bus release
Bus release
Bus release
Last transfer cycle
Bus
release
Figure 8.25 Example of Single Address Mode (Word Write) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
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(3)
Section 8 EXDMA Controller (EXDMAC)
EDREQ Pin Falling Edge Activation Timing
Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling
edge.
EXDMA
single
cycle
Bus release
EXDMA
single
cycle
Bus release
Bus release
φ
EDREQ
Transfer source/
destination
Address bus
Transfer source/
destination
EDACK
EXDMA control Idle
Single
Channel
Request
Minimum 3 cycles
[1]
Idle
Single
Request
clearance period
[2]
[3]
Request
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request
clearance period
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.26 Example of Single Address Mode Transfer Activated
by EDREQ Pin Falling Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA single cycle, acceptance resumes
after the end of the single cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
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Section 8 EXDMA Controller (EXDMAC)
(4)
EDREQ Pin Low Level Activation Timing
Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low
level.
EXDMA
single
cycle
Bus release
EXDMA
single
cycle
Bus release
Bus release
φ
EDREQ
Transfer source/
destination
Address bus
Transfer source/
destination
EDACK
EXDMA control
Idle
Single
Channel
Request
Minimum 3 cycles
[1]
Idle
Single
Request
clearance period
[2]
[3]
Request
Minimum 3 cycles
[4]
Acceptance
resumed
[1]
[2], [5]
[3], [6]
[4], [7]
Idle
Request
clearance period
[5]
[6]
[7]
Acceptance
resumed
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle is started.
Acceptance is resumed after completion of single cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low
level sampling is performed again; this sequence of operations is repeated until the end of the
transfer.
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8.4.11
(1)
Section 8 EXDMA Controller (EXDMAC)
Examples of Operation Timing in Each Mode
Auto Request/Cycle Steal Mode/Normal Transfer Mode
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit
EXDMA cycle and the start of the next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 8.28 to 8.30 show operation timing examples for various conditions.
φ pin
1 cycle
3 cycles
Bus release
Bus cycle
EXDMA
read
EXDMA
write
EXDMA
read
Bus
release
CPU
operation
EDA = 1
write
Last transfer cycle
EXDMA
write
EXDMA
read
EXDMA
write
Bus
release
Internal bus space
cycles
ETEND
EDA bit
0
1
0
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
1 bus cycle
Bus cycle
CPU cycle
CPU
operation
External
space
EXDMA single
transfer cycle
CPU cycle
External space
Last transfer cycle
EXDMA single
transfer cycle
CPU cycle
EXDMA single
transfer cycle
External space
CPU cycle
External space
EDACK
ETEND
Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode)
φ pin
1 cycle
Bus cycle
EXDMA
single cycle
EXDMA
single cycle
Bus
release
1 cycle
1 cycle
EXDMA
single cycle
Bus
release
EXDMA
single cycle
Higher-priority channel EXDMA cycle
Bus
release
Bus
release
Bus
release
Current
channel
EDACK
Other
channel
transfer
request
(EDREQ)
Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)
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(2)
Section 8 EXDMA Controller (EXDMAC)
Auto Request/Burst Mode/Normal Transfer Mode
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is
satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 8.31 to 8.34 show operation timing examples for various conditions.
φ pin
Last transfer cycle
Bus cycle
CPU
operation
CPU cycle CPU cycle
External
space
External
space
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
CPU cycle
External
space
ETEND
EDA bit
1
0
Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 0)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
1 bus cycle
Bus cycle
CPU
operation
CPU cycle CPU cycle
External
space
External
space
EXDMA
read
EXDMA
write
CPU cycle
External
space
1 bus cycle
EXDMA
read
EXDMA
write
CPU cycle
EXDMA
read
EXDMA
write
External
space
Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 1)
φ pin
Last transfer cycle
1 bus cycle
Bus cycle
CPU
operation
EXDMA
EXDMA
EXDMA
EXDMA
EXDMA
CPU cycle CPU cycle single
cycle single cycle CPU cycle single cycle single cycle CPU cycle single cycle CPU cycle
External
space
External
space
External
space
External
space
External
space
EDACK
ETEND
Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/BGUP = 1)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
Last transfer
cycle
Bus cycle
Bus release
EXDMA single
transfer cycle
EXDMA single
transfer cycle
1 cycle
EXDMA single
transfer cycle
Other channel EXDMA cycle
Bus
release
Bus
release
Original
channel
EDACK
Original
channel
ETEND
Other
channel
transfer
request
(EDREQ)
Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)
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Section 8 EXDMA Controller (EXDMAC)
(3)
External Request/Cycle Steal Mode/Normal Transfer Mode
In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a
transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated
before the next EXDMA cycle.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next EXDMA cycle.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.35 to 8.38 show operation timing examples for various conditions.
φ pin
EDREQ
EDRAK
3 cycles
Bus release
Bus cycle
EXDMA
read
EXDMA
write
Bus release
Last transfer cycle
EXDMA
read
EXDMA
write
Bus release
ETEND
EDA bit
1
0
Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
EDREQ
EDRAK
2 bus cycles
Bus cycle
CPU cycle CPU cycle CPU cycle
External
space
CPU
operation
External
space
External
space
EXDMA single
transfer cycle
Last transfer cycle
CPU cycle CPU cycle
External
space
External
space
EXDMA single
transfer cycle
CPU cycle
External
space
EDACK
ETEND
Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing)
φ pin
EDREQ
EDRAK
EDREQ
acceptance
internal
processing
state
Edge confirmation
Start of transfer
processing
Start of high
level sensing
Bus cycle
Bus release
EXDMA single
transfer cycle
Edge confirmation
Start of transfer
processing
Bus release
Start of high
level sensing
EXDMA single
transfer cycle
Edge confirmation
Start of transfer
processing
Bus release
Start of high
level sensing
EXDMA single
transfer cycle
EDACK
Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing)
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Section 8 EXDMA Controller (EXDMAC)
φ pin
Original
channel
EDREQ
Original
channel
EDRAK
1 cycle
3 cycles
Bus cycle
EXDMA transfer
cycle
Bus release
EXDMA
read
1 cycle
Other channel
transfer cycle
EXDMA
write
Bus
release
EXDMA
read
EXDMA
write
Bus
release
Other
channel
EDREQ
Other
channel
EDRAK
Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention
with Another Channel/Dual Address Mode/Low Level Sensing
(4)
External Request/Cycle Steal Mode/Block Transfer Mode
In block transfer mode, transfer of one block is performed continuously in the same way as in
burst mode. The timing of the start of the next block transfer is the same as in normal transfer
mode.
If a transfer request is generated for another channel, an EXDMA cycle for the other channel is
generated before the next block transfer.
The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 8.39 to 8.44 show operation timing examples for various conditions.
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EDA bit
ETEND
Bus cycle
EDRAK
EDREQ
φ pin
1
Bus release
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Last transfer
in block
Repeated
1-block-size transfer period
Bus release
3 cycles
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
0
EXDMA
write
Bus
release
Last transfer cycle
Last block
H8S/2456, H8S/2456R, H8S/2454 Group
Section 8 EXDMA Controller (EXDMAC)
Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0)
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ETEND
EDACK
Bus cycle
EDRAK
EDREQ
φ pin
Bus release
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Last transfer
in block
Repeated
1-block-size transfer period
Bus release
3 cycles
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Bus
release
Last transfer cycle
Last block
Section 8 EXDMA Controller (EXDMAC)
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)
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External
space
CPU
operation
ETEND
EDACK
CPU
cycle
Bus cycle
EDRAK
EDREQ
φ pin
External
space
CPU
cycle
External
space
CPU
cycle
External
space
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Last transfer
in block
1-block-size transfer period
CPU
cycle
External
space
CPU
cycle
2 bus cycles
External
space
EXDMA single
transfer cycle
Repeated
EXDMA single
transfer cycle
Last transfer
in block
1-block-size transfer period
CPU
cycle
H8S/2456, H8S/2456R, H8S/2454 Group
Section 8 EXDMA Controller (EXDMAC)
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0)
Page 467 of 1408
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External
space
CPU
operation
ETEND
CPU
cycle
Bus cycle
EDRAK
EDREQ
φ pin
External
space
CPU
cycle
External
space
CPU
cycle
External
space
EXDMA
read
EXDMA
write
CPU
cycle
1 bus cycle
External
space
EXDMA
read
EXDMA
write
CPU
cycle
1 bus cycle
External
space
CPU
cycle
1 bus cycle
Repeated
EXDMA
read
1-block-size transfer period
External
space
EXDMA
read
EXDMA
write
Last transfer
in block
CPU
cycle
External
space
CPU
cycle
Section 8 EXDMA Controller (EXDMAC)
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)
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External
space
External
space
CPU
operation
ETEND
EDACK
CPU
cycle
CPU
cycle
Bus cycle
EDRAK
EDREQ
φ pin
External
space
CPU
cycle
External
space
EXDMA
EXDMA
transfer cycle transfer cycle
CPU
cycle
1 bus cycle
External
space
EXDMA
EXDMA
transfer cycle transfer cycle
CPU
cycle
1 bus cycle
External
space
Repeated
EXDMA
transfer cycle
1-block-size transfer period
CPU
cycle
1 bus cycle
External
space
EXDMA
EXDMA
transfer cycle transfer cycle
Last transfer
in block
CPU
cycle
External
space
CPU
cycle
H8S/2456, H8S/2456R, H8S/2454 Group
Section 8 EXDMA Controller (EXDMAC)
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1)
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Other
channel
EDRAK
Other
channel
EDREQ
ETEND
Bus cycle
EDRAK
EDREQ
φ pin
Bus release
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
Last transfer
in block
1-block-size transfer period
Bus
release
Other channel
EXDMA cycle
Bus
release
EXDMA
read
EXDMA
write
Repeated
EXDMA
read
EXDMA
write
Last transfer
in block
1-block-size transfer period
Section 8 EXDMA Controller (EXDMAC)
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
(Contention with Another Channel/Dual Address Mode/Low Level Sensing)
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8.4.12
Section 8 EXDMA Controller (EXDMAC)
Ending EXDMA Transfer
The operation for ending EXDMA transfer depends on the transfer end conditions. When
EXDMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that EXDMA
transfer has ended.
(1)
Transfer End by 1 → 0 Transition of EDTCR
When the value of EDTCR changes from 1 to 0, EXDMA transfer ends on the corresponding
channel and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this
time, a transfer end interrupt request is generated by the transfer counter and the IRF bit in
EDMDR is set to 1.
In block transfer mode, EXDMA transfer ends when the value of bits 15 to 0 in EDTCR changes
from 1 to 0.
EXDMA transfer does not end if the EDTCR value has been 0 since before the start of transfer.
(2)
Transfer End by Repeat Area Overflow Interrupt
If an address overflows the repeat area when a repeat area specification has been made and repeat
interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow
interrupt is requested. EXDMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF
bit in EDMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
(3)
Transfer End by 0-Write to EDA Bit in EDMDR
When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of
the DMA cycle in which transfer is in progress or a transfer request was accepted.
In block transfer mode, EXDMA transfer halts after completion of one-block-size transfer.
The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that
point, the value of the EDA bit will be read as 1.
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Section 8 EXDMA Controller (EXDMAC)
(4)
H8S/2456, H8S/2456R, H8S/2454 Group
Transfer Abort by NMI Interrupt
EXDMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all
channels. In external request mode, EXDMA transfer is performed for all transfer requests for
which EDRAK has been output. In dual address mode, processing is executed for the write cycle
following the read cycle.
In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the
transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the
block transfer was not carried out normally.
When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit
is 1 in EDMDR, transfer can be resumed from midway through a block.
(5)
Hardware Standby Mode and Reset Input
The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not
guaranteed in these cases.
8.4.13
Relationship between EXDMAC and Other Bus Masters
The read and write operations in an EXDMA transfer cycle are indivisible, and a refresh cycle,
external bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access
cycle never occurs between the two.
When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or
external bus release state may be inserted after the write cycle. As the internal bus masters are of
lower priority than the EXDMAC, external space accesses by internal bus masters are not
executed until the EXDMAC releases the bus.
The EXDMAC releases the bus in the following cases:
1.
2.
3.
4.
5.
When EXDMA transfer is performed in cycle steal mode
When switching to a different channel
When transfer ends in burst transfer mode
When transfer of one block ends in block transfer mode
When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1
(however, the bus is not released between read and write cycles)
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8.5
Section 8 EXDMA Controller (EXDMAC)
Interrupt Sources
EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area
overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.
Table 8.4
Interrupt Sources and Priority Order
Interrupt
Interrupt source
Interrupt Priority
EXDMTEND2
Transfer end indicated by channel 2 transfer counter
High
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
EXDMTEND3
Transfer end indicated by channel 3 transfer counter
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow
Low
Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
IRF bit
Transfer end interrupt
EDIE bit
Figure 8.45 Transfer End Interrupt Logic
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of
the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of
the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by
means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding
interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt
sources indiscriminately.
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Section 8 EXDMA Controller (EXDMAC)
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of
the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
Transfer end interrupt
exception handling routine
Transfer restart after end
of interrupt handling routine
Transfer continuation
processing
Change register settings
[1]
Clear IRF bit to 0
[4]
Write 1 to EDA bit
[2]
End of interrupt handling
routine
[5]
End of interrupt handling
routine
(RTE instruction execution)
[3]
Change register settings
[6]
Write 1 to EDA bit
[7]
End of transfer restart
processing
End of transfer restart
processing
[1] Write set values to the registers (transfer counter, address registers, etc.).
[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA
bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared.
[3] The interrupt handling routine is ended with an RTE instruction, etc.
[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.
[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is
cleared.
[6] Write set values to the registers (transfer counter, address registers, etc.).
[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer
End Interrupt Occurred
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8.6
(1)
Section 8 EXDMA Controller (EXDMAC)
Usage Notes
EXDMAC Register Access during Operation
Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in
operation (including the transfer standby state). Transfer must be disabled before changing a
setting for an operational channel.
(2)
Module Stop State
When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC
enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the
EXDMAC’s channels is enabled for transfer, or when an interrupt is being requested. Before
setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in
EDMDR to 0.
When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following
EXDMAC register settings remain valid in the module stop state, and so should be changed, if
necessary, before making the module stop transition.
• ETENDE = 1 in EDMDR (ETEND pin enable)
• EDRAKE = 1 in EDMDR (EDRAK pin enable)
• AMS = 1 in EDMDR (EDACK pin enable)
(3)
EDREQ Pin Falling Edge Activation
Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal
operations, as indicated below.
[1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2].
[2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3].
[3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1].
After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used
for the initial activation after transfer is enabled.
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Section 8 EXDMA Controller (EXDMAC)
(4)
H8S/2456, H8S/2456R, H8S/2454 Group
Activation Source Acceptance
At the start of activation source acceptance, low level sensing is used for both falling edge sensing
and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low
level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state.
When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the
EDREQ pin from the previous end of transfer, etc.
(5)
Enabling Interrupt Requests when IRF = 1 in EDMDR
When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in
EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be
requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request
when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1.
(6)
ETEND Pin and CBR Refresh Cycle
If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that
although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may
also go low in this case for the refresh cycle.
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Section 9 Data Transfer Controller (DTC)
Section 9 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 9.1 shows a block diagram of the DTC.
9.1
Features
• Transfer possible over any number of channels
• Three transfer modes
1. Normal mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
From 1 to 65,536 transfers can be specified.
2. Repeat mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and
transfer is repeated.
3. Block transfer mode
One operation transfers one block of data.
The block size is 1 to 256 bytes or words.
From 1 to 65,536 transfers can be specified.
Either the transfer source or the transfer destination is designated as a block area.
• One activation source can trigger a number of data transfers (chain transfer).
• Direct specification of 16-Mbyte address space possible.
• Activation by software is possible.
• Transfer can be set in byte or word units.
• A CPU interrupt can be requested for the interrupt that activated the DTC.
• Module stop state can be set.
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Section 9 Data Transfer Controller (DTC)
The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR and MSTP32 bit in RMMSTPCR must be set to 1 and 0, respectively. A 32-bit bus
connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of
the DTC register information.
Internal address bus
Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC activation
request
On-chip RAM
Control logic
DTC
DTCCR
DTVECR
Interrupt
request
DTCERA
to
DTCERI
Interrupt controller
Internal data bus
CPU interrupt
request
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERI:
DTVECR:
DTCCR:
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to I
DTC vector register
DTC control register
Figure 9.1 Block Diagram of DTC
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9.2
Section 9 Data Transfer Controller (DTC)
Register Descriptions
DTC has the following registers.
•
•
•
•
•
•
DTC mode register A (MRA)
DTC mode register B (MRB)
DTC source address register (SAR)
DTC destination address register (DAR)
DTC transfer count register A (CRA)
DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a
set of register information that is stored in an on-chip RAM to the corresponding DTC registers
and transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
•
•
•
DTC enable registers A to I (DTCERA to DTCERI)
DTC vector register (DTVECR)
DTC control register (DTCCR)
9.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
SM1
Undefined
⎯
Source Address Mode 1 and 0
6
SM0
Undefined
⎯
These bits specify an SAR operation after a data
transfer.
0x: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
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Section 9 Data Transfer Controller (DTC)
Bit
Bit Name
Initial Value
R/W
Description
5
DM1
Undefined
⎯
Destination Address Mode 1 and 0
4
DM0
Undefined
⎯
These bits specify a DAR operation after a data
transfer.
0x: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
3
MD1
Undefined
⎯
DTC Mode
2
MD0
Undefined
⎯
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTS
Undefined
⎯
DTC Transfer Mode Select
Specifies whether the source side or the
destination side is set to be a repeat area or block
area, in repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0
Sz
Undefined
⎯
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
[Legend]
x:
Don't care
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9.2.2
Section 9 Data Transfer Controller (DTC)
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
CHNE
Undefined
⎯
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4,
Chain Transfer.
In data transfer with CHNE set to 1, determination
of the end of the specified number of transfers,
clearing of the activation source flag, and clearing
of DTCER is not performed.
6
DISEL
Undefined
⎯
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number
of data transfer ends.
5
CHNS
Undefined
⎯
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4 to 0
⎯
Undefined
⎯
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
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Section 9 Data Transfer Controller (DTC)
9.2.3
H8S/2456, H8S/2456R, H8S/2454 Group
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
9.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
9.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
9.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not
available in normal and repeat modes.
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9.2.7
Section 9 Data Transfer Controller (DTC)
DTC Enable Registers A to I (DTCERA to DTCERI)
DTCER which is comprised of registers, DTCERA to DTCERI, is a register that specifies DTC
activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit
Bit Name
Initial Value
R/W
Description
7
DTCE7
0
R/W
DTC Activation Enable
6
DTCE6
0
R/W
5
DTCE5
0
R/W
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
4
DTCE4
0
R/W
[Clearing conditions]
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
•
When the DISEL bit is 1 and the data transfer has
ended
•
When the specified number of transfers have
ended
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of transfers
have not ended
•
9.2.8
When 0 is written to DTCE after reading DTCE = 1
DTC Vector Register (DTVECR)
DTVECR sets a vector number for the software activation interrupt.
Bit
Bit Name
Initial Value
R/W
Description
7
DTVEC7
0
R/W
DTC Software Activation Vectors 7 to 0
6
DTVEC6
0
R/W
5
DTVEC5
0
R/W
These bits specify a vector number for DTC
software activation.
4
DTVEC4
0
R/W
3
DTVEC3
0
R/W
2
DTVEC2
0
R/W
1
DTVEC1
0
R/W
0
DTVEC0
0
R/W
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The vector address is expressed as H'0400 +
(vector number × 2). For example, when DTVEC7
to DTVEC0 = H'10, the vector address is H'0420.
These bits can be written to only when the
SWDTE bit is 0.
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Section 9 Data Transfer Controller (DTC)
9.2.9
DTC Control Register (DTCCR)
DTCCR enables or disables DTC activation by software.
Bit
Bit Name
Initial Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates the DTC. Only 1 can
be written to this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified
number of transfers have not ended
•
When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the
CPU.
When the DISEL bit is 1 and data transfer has
ended or when the specified number of transfers
have ended, this bit will not be cleared.
6 to 0
⎯
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
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9.3
Section 9 Data Transfer Controller (DTC)
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR or DTCCR by
software. An interrupt request can be directed to the CPU or DTC, as designated by the
corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case
of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation
source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Table 9.1 shows a relationship between activation sources and DTCER clear conditions. Figure
9.2 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
Table 9.1
Relationship between Activation Sources and DTCER Clearing
Activation Source
DISEL = 0 and Specified
Number of Transfers Has
Not Ended
DISEL = 1 or Specified Number
of Transfers Has Ended
Activation by software
SWDTE bit is cleared to 0
•
SWDTE bit remains set to 1
•
Interrupt request to CPU
Activation by an interrupt
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•
Corresponding DTCER bit
remains set to 1.
•
Corresponding DTCER bit is
cleared to 0.
•
Activation source flag is
cleared to 0.
•
Activation source flag remains
set to 1.
•
Interrupt that became the
activation source is requested
to the CPU.
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Section 9 Data Transfer Controller (DTC)
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
peripheral
modules
IRQ interrupt
DTVECR
DTCCR
Interrupt
request
Selection circuit
Select
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 9.2 Block Diagram of DTC Activation Source Control
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9.4
Section 9 Data Transfer Controller (DTC)
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 9.3 and the register information start address should be located at the
corresponding vector address to the activation source. Figure 9.4 shows correspondences between
the DTC vector address and register information. The DTC reads the start address of the register
information from the vector address set for each activation source, and then reads the register
information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[7:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Note: * Not available in this LSI.
Lower addresses
0
Start address of
register information
1
2
MRA
SAR
MRB
DAR
3
Register information
CRB
CRA
Chain transfer
MRA
SAR
MRB
DAR
CRB
CRA
Register information
for second transfer
in case of chain
transfer
Four bytes
Figure 9.3 Correspondence between DTC Vector Address and Register Information
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Section 9 Data Transfer Controller (DTC)
DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 9.4 Correspondence between DTC Vector Address and Register Information
Table 9.2
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC Vector
Address
Software
Write to
DTVECR
DTVECR
H'0400 +
(DTVECR[7:0] × 2)
⎯
External pin
IRQ0
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
IRQ6
22
H'042C
DTCEA1
IRQ7
23
H'042E
DTCEA0
IRQ8*2
IRQ9*2
24
H'0430
DTCEB7
25
H'0432
DTCEB6
IRQ10*
IRQ11*2
26
H'0434
DTCEB5
17
H'0436
DTCEB4
IRQ12*2
18
H'0438
DTCEB3
IRQ13*2
19
H'043A
DTCEB2
IRQ14*2
IRQ15*2
30
H'043C
DTCEB1
31
H'043E
DTCEB0
ADI0
38
H'044C
DTCEC6
2
A/D_0
Page 488 of 1408
DTCE*
1
Priority
High
Low
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Section 9 Data Transfer Controller (DTC)
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC Vector
Address
DTCE*
TPU_0
TGI0A
40
H'0450
DTCEC5
TGI0B
41
H'0452
DTCEC4
TGI0C
42
H'0454
DTCEC3
TGI0D
43
H'0456
DTCEC2
TGI1A
48
H'0460
DTCEC1
TGI1B
49
H'0462
DTCEC0
TGI2A
52
H'0468
DTCED7
TGI2B
53
H'046A
DTCED6
TGI3A
56
H'0470
DTCED5
TGI3B
57
H'0472
DTCED4
TGI3C
58
H'0474
DTCED3
TGI3D
59
H'0476
DTCED2
TGI4A
64
H'0480
DTCED1
TGI4B
65
H'0482
DTCED0
TGI5A
68
H'0488
DTCEE7
TGI5B
69
H'048A
DTCEE6
CMIA0
72
H'0490
DTCEE3
CMIB0
73
H'0492
DTCEE2
CMIA1
76
H'0498
DTCEE1
CMIB1
77
H'049A
DTCEE0
DMTEND0A
80
H'04A0
DTCEF7
DMTEND0B
81
H'04A2
DTCEF6
DMTEND1A
82
H'04A4
DTCEF5
DMTEND1B
83
H'04A6
DTCEF4
RXI0
89
H'04B2
DTCEF3
TXI0
90
H'04B4
DTCEF2
TPU_1
TPU_2
TPU_3
TPU_4
TPU_5
TMR_0
TMR_1
DMAC
SCI_0
SCI_1
SCI_2
1
RXI1
93
H'04BA
DTCEF1
TXI1
94
H'04BC
DTCEF0
RXI2
97
H'04C2
DTCEG7
TXI2
98
H'04C4
DTCEG6
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Priority
High
Low
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Section 9 Data Transfer Controller (DTC)
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC Vector
Address
DTCE*
SCI_3
RXI3
101
H'04CA
DTCEF5
TXI3
102
H'04CC
DTCEF4
SCI_4
1
RXI4
105
H'04D2
DTCEG3
TXI4
106
H'04D4
DTCEG2
A/D_1
ADI1
112
H'04E0
DTCEG1
TPU_6
TGI6A
120
H'04F0
DTCEG0
TGI6B
121
H'04F2
DTCEH7
TGI6C
122
H'04F4
DTCEH6
TGI6D
123
H'04F6
DTCEH5
TPU_7
TGI7A
125
H'04FA
DTCEH4
TGI7B
126
H'04FC
DTCEH3
TPU_8
TGI8A
129
H'0502
DTCEH2
TGI8B
130
H'0504
DTCEH1
TGI9A
133
H'050A
DTCEH0
TGI9B
134
H'050C
DTCEI7
TGI9C
135
H'050E
DTCEI6
TGI9D
136
H'0510
DTCEI5
TGI10A
138
H'0514
DTCEI4
TGI10B
139
H'0516
DTCEI3
TGI11A
142
H'051C
DTCEI2
TGI11B
143
H'051E
DTCEI1
TPU_9
TPU_10
TPU_11
Priority
High
Low
Notes: 1. DTCE bits with no corresponding interrupt are reserved, and 0 should be written to.
When clearing the software standby state or all-module-clocks-stop state with an
interrupt, write 0 to the corresponding DTCE bit.
2. Not supported by the H8S/2454 Group.
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9.5
Section 9 Data Transfer Controller (DTC)
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
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Section 9 Data Transfer Controller (DTC)
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1?
Yes
No
CHNS = 0?
Yes
Transfer counter = 0
or DISEL = 1?
No
No
Yes
Transfer
counter = 0?
Yes
No
DISEL = 1?
Yes
No
Clear activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 9.5 Flowchart of DTC Operation
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Table 9.3
Section 9 Data Transfer Controller (DTC)
Chain Transfer Conditions
1st Transfer
CHNE
CHNS
DISEL
0
⎯
0
⎯
0
1
2nd Transfer
CR
CHNE
CHNS
DISEL
CR
DTC Transfer
0
Not 0
⎯
⎯
⎯
⎯
Ends at 1st transfer
0
0
⎯
⎯
⎯
⎯
Ends at 1st transfer
⎯
1
⎯
⎯
⎯
⎯
⎯
Interrupt request to CPU
0
⎯
⎯
0
⎯
0
Not 0
Ends at 2nd transfer
0
⎯
0
0
Ends at 2nd transfer
0
⎯
1
⎯
Interrupt request to CPU
1
1
0
Not 0
⎯
⎯
⎯
⎯
Ends at 1st transfer
1
1
⎯
0
0
⎯
0
Not 0
Ends at 2nd transfer
0
⎯
0
0
Ends at 2nd transfer
0
⎯
1
⎯
Interrupt request to CPU
⎯
⎯
⎯
⎯
Ends at 1st transfer
1
1
1
Not 0
Interrupt request to CPU
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Section 9 Data Transfer Controller (DTC)
9.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 9.4
Register Function in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 9.6 Memory Mapping in Normal Mode
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9.5.2
Section 9 Data Transfer Controller (DTC)
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register
function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of
transfers has ended, the initial state of the transfer counter and the address register specified as the
repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not
reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
Table 9.5
Register Function in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
or
DAR
Repeat area
Transfer
DAR
or
SAR
Figure 9.7 Memory Mapping in Repeat Mode
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Section 9 Data Transfer Controller (DTC)
9.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 9.6 lists the register function in block
transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. Once the specified number of transfers has ended, a CPU interrupt is requested.
Table 9.6
Register Function in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Designates transfer count
First block
SAR
or
DAR
DAR
or
SAR
Block area
Transfer
Nth block
Figure 9.8 Memory Mapping in Block Transfer Mode
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9.5.4
Section 9 Data Transfer Controller (DTC)
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 9.9 shows the operation of chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is
1, the next register information, which is located consecutively, is read and transfer is performed.
This operation is repeated until the end of data transfer of register information with CHNE = 0. It
is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain
transfer only when the transfer counter value is 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
Destination
Register information
CHNE=1
DTC vector
address
Register information
start address
Register information
CHNE=0
Source
Destination
Figure 9.9 Operation of Chain Transfer
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Section 9 Data Transfer Controller (DTC)
9.5.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has
ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
9.5.6
Operation Timing
φ
DTC activation
request
DTC
request
Vector read
Data transfer
Address
Read Write
Transfer
information read
Transfer
information write
Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 9 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Read Write Read Write
Address
Transfer
information read
Transfer
information write
Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information read
Transfer
information
write
Transfer
information
read
Transfer
information write
Figure 9.12 DTC Operation Timing (Example of Chain Transfer)
9.5.7
Number of DTC Execution States
Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of
states required for each execution status.
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Section 9 Data Transfer Controller (DTC)
Table 9.7
DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
[Legend]
N:
Block size (initial setting of CRAH and CRAL)
Table 9.8
Number of States Required for Each Execution Status
OnChip
RAM
Object to be Accessed
OnChip On-Chip I/O
ROM Registers
Bus width
32
16
8
16
Access states
1
1
2
2
Execution
status
External Devices
8
16
2
3
2
3
SI
⎯
1
⎯
⎯
4
6+2m
2
3+m
Register information
read/write
SJ
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Byte data read
SK
1
1
2
2
2
3+m
2
3+m
Word data read
SK
1
1
4
2
4
6+2m
2
3+m
Byte data write
SL
1
1
2
2
2
3+m
2
3+m
Word data write
SL
1
1
4
2
4
6+2m
2
3+m
Internal operation
SM
Vector read
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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9.6
Procedures for Using DTC
9.6.1
Activation by Interrupt
Section 9 Data Transfer Controller (DTC)
The procedure for using the DTC with interrupt activation is as follows:
1.
2.
3.
4.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
Set the start address of the register information in the DTC vector address.
Set the corresponding bit in DTCER to 1.
Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
9.6.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1.
2.
3.
4.
5.
6.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
Set the start address of the register information in the DTC vector address.
Check that the SWDTE bit is 0.
Write 1 to SWDTE bit and the vector number to DTVECR.
Check the vector number written to DTVECR.
After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 9 Data Transfer Controller (DTC)
9.7
Examples of Use of the DTC
9.7.1
Normal Mode
H8S/2456, H8S/2456R, H8S/2454 Group
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
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9.7.2
Section 9 Data Transfer Controller (DTC)
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain
transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
1. Perform settings for transfer to NDR of the PPG. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in
DAR, and the data table size in CRA. CRB can be set to any value.
3. Locate the TPU transfer register information consecutively after the NDR transfer register
information.
4. Set the start address of the NDR transfer register information to the DTC vector address.
5. Set the bit corresponding to TGIA in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
R01UH0309EJ0500 Rev. 5.00
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Page 503 of 1408
Section 9 Data Transfer Controller (DTC)
9.7.3
H8S/2456, H8S/2456R, H8S/2454 Group
Chain Transfer when Counter = 0
By executing a second data transfer, and performing re-setting of the first data transfer, only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is
assumed to have been set to start at lower address H'0000. Figure 9.13 shows the chain transfer
when the counter value is 0.
1. For the first transfer, set the normal mode for input data. Set fixed transfer source address
(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of
the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper 8 bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
an interrupt request is not sent to the CPU.
Page 504 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 9 Data Transfer Controller (DTC)
Input circuit
Input buffer
First data
transfer register
information
Chain transfer
(counter = 0)
Second data
transfer register
information
Upper 8 bits
of DAR
Figure 9.13 Chain Transfer when Counter = 0
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Sep 24, 2012
Page 505 of 1408
Section 9 Data Transfer Controller (DTC)
9.7.4
H8S/2456, H8S/2456R, H8S/2454 Group
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTCCR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'60.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Page 506 of 1408
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Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
9.8
Usage Notes
9.8.1
Module Stop Function Setting
Section 9 Data Transfer Controller (DTC)
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting the module stop
state. The module stop state cannot be set while the DTC is activated. For details, refer to section
24, Power-Down Modes.
9.8.2
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0 and the corresponding MSTP bit
in RMMSTPCR must not be set to 1.
9.8.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
9.8.4
DMAC Transfer End Interrupt
When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer
counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has
priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer
counter reaches 0.
9.8.5
Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. SCI and high-speed A/D converter
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a
read/write of the relevant register is not included in the last chained data transfer, the interrupt or
activation source will be retained.
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Sep 24, 2012
Page 507 of 1408
Section 9 Data Transfer Controller (DTC)
Page 508 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Section 10 I/O Ports
Table 10.1 summarizes the port functions of the H8S/2456 Group and H8S/2456R Group. Table
10.2 summarizes the port functions of the H8S/2454 Group. The pins of each port also have other
functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each
I/O port includes a data direction register (DDR) that controls input/output, a data register (DR)
that stores output data, a port register (PORT) used to read the pin states, and a port function
control register (PFCR) used to set input/output destination. Before enabling each input/output
pins, select the input/output destination by PFCR. The input-only ports do not have a DR or DDR
register.
Ports A to E have a built-in pull-up MOS function and a pull-up MOS control register (PCR) to
control the on/off state of the input pull-up MOS.
Ports 1 to 3, 5 to 8, and A to J include an open-drain control register (ODR) that controls the
on/off state of the output buffer PMOS.
Ports 1 to 3 and 5 to 8 can drive a single TTL load and 30-pF capacitive load. Ports A to J can
drive a single TTL load and 50-pF capacitive load.
All of the I/O ports can drive a Darlington transistor when outputting data.
Ports 1 and 2 are Schmitt-triggered inputs. The other ports are Schmitt-triggered inputs when used
as IRQ inputs, 16-bit timer pulse unit (TPU) inputs, 8-bit timer (TMR) inputs, and I2C bus
interface (IIC) inputs.
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Sep 24, 2012
Page 509 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Table 10.1 Port Functions of H8S/2456 Group and H8S/2456R Group
Mode 3, 7
Mode 2
Mode 4
Schmitt-
Input
Open
triggered
input
Pin*2
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
⎯
All output
⎯
Port
Description
Mode 1
Port 1
General I/O port also
P17/PO15/TIOCB2/TCLKD/EDRAK3/
P17/PO15/
P17,
functioning as PPG
outputs,
TPU I/Os, EXDMAC
outputs, and
SSU I/Os
SCS0-A
TIOCB2/
TCLKD/
SCS0-A
TIOCB2,
TCLKD
P16/PO14/TIOCA2/EDRAK2/SSCK0-A
P16/PO14/
TIOCA2/
SSCK0-A
P16,
TIOCA2
EXPE = 1 EXPE = 0
Tolerance
pin
functions
P15,
P15/PO13/TIOCB1/TCLKC/SSI0-A
TIOCB1
P14,
P14/PO12/TIOCA1/SSO0-A
TIOCA1
P13/PO11/TIOCD0/TCLKB
All input pin
functions
P12/PO10/TIOCC0/TCLKA
All input pin
functions
All input pin
P11/PO9/TIOCB0
functions
Port 2
General I/O port also
functioning as PPG
outputs,
TPU I/Os, interrupt
inputs, SCI I/Os,
I2C I/Os,
A/D converter inputs,
bus control signal
I/Os, and USB I/Os.
P10/PO8/TIOCA0
All input pin
functions
P27/IRQ15-B/PO7/TIOCB5/SCL2
All input pin
⎯
functions
Ο
pin
functions
P26,
P26/IRQ14-B/PO6/TIOCA5/SDA2/ADTRG1
All output
IRQ14-B,
TIOCA5,
SDA2
P25/WAIT-B/IRQ13-B/PO5-A/TIOCB4-A/VBUS
P25/
IRQ13-B/
PO5-A/
TIOCB4-A/
VBUS
P25,
IRQ13-B,
TIOCB4-A
All input pin
P20/IRQ8-B/PO0-A/TIOCA3-A/PUPD+
functions
Port 3
General I/O port also
P35/OE-B/CKE-B*1/SCK1/SCL0
functioning as SCI
I/Os, I2C I/Os, and
bus control signal
I/Os
P35/SCK1/
SCL0
SCL0
⎯
All output
Ο
pin
functions
other than
OE-B and
CKE-B*1
P34/SCK0/SCK4-A/SDA0
SDA0
P33/RxD1/SCL1
SCL1
P32/RxD0/IrRxD/SDA1
SDA1
P31/TxD1
⎯
All output
pin
functions
⎯
P30/TxD0/IrTxD
Page 510 of 1408
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Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Mode 3, 7
Port
Description
Mode 1
Port 4
General I/O port also
P47/AN7_0
functioning as A/D
converter analog
inputs
P46/AN6_0
Mode 2
Mode 4
EXPE = 1 EXPE = 0
Schmitt-
Input
Open
triggered
input
Pin*2
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
⎯
⎯
⎯
⎯
IRQ3-A
⎯
All output
pin
functions
⎯
Tolerance
P45/AN5_0
P44/AN4_0
P43/AN3_0
P42/AN2_0
P41/AN1_0
P40/AN0_0
Port 5
General I/O port also
functioning as
interrupt inputs,
A/D converter inputs,
SCI I/Os,
PPG outputs, TPU
I/Os, TMR I/Os,
I2C I/Os, and bus
P53/IRQ3-A/ADTRG0-A
P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/
P52/
IRQ2-A,
All output
TMO0-B/SCK2
IRQ2-A/
PO4-B/
TIOCA4-B/
TIOCA4-B
pin
functions
other than
Port 6
General I/O port also
functioning as
interrupt inputs, TMR
I/Os, and DMAC I/Os
BACK-B
TMO0-B/
SCK2
control signal I/Os
P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/
P51/
IRQ1-A,
All output
TMCI0-B/RxD2/SCL3
IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
TIOCC3-B,
TMCI0-B,
SCL3
pin
functions
P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/
TMRI0-B/TxD2/SDA3
P50/
IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
IRQ0-A,
TIOCA3-B,
TMRI0-B,
SDA3
All output
pin
functions
other than
BREQO-B
P65/IRQ13-A/DACK1/TMO1-A
IRQ13-A
P64/IRQ12-A/DACK0/TMO0-A
IRQ12-A
P63/IRQ11-A/TEND1/TMCI1-A
IRQ11-A,
TMCI1-A
P62/IRQ10-A/TEND0/TMCI0-A
IRQ10-A,
⎯
All output
O
⎯
pin
functions
TMCI0-A
P61/IRQ9-A/DREQ1/TMRI1-A
IRQ9-A,
TMRI1-A
P60/IRQ8-A/DREQ0/TMRI0-A
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
IRQ11-A,
TMRI0-A
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Mode 3, 7
Mode 2
Mode 4
Schmitt-
Input
Open
triggered
input
Pin*2
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
⎯
All output
⎯
Port
Description
Mode 1
Port 8
General I/O port also
P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/
P85/IRQ5-B/
IRQ5-B,
functioning as
EXDMAC I/Os, PPG
outputs, TPU I/Os,
TMR I/Os, SCI I/Os
and interrupt inputs
EDACK3
PO5-B/
TIOCB4-B/
TMO1-B/
SCK3
TIOCB4-B
P84/IRQ4-B/EDACK2
P84/IRQ4-B
IRQ4-B
P83/IRQ3-B/PO3-B/TIOCD3-B/TMCI1-B/RxD3/
P83/IRQ3-B/
IRQ3-B,
ETEND3
PO3-B/
TIOCD3-B/
TMCI1-B/
TIOCD3-B,
TMCI1-B
EXPE = 1 EXPE = 0
Tolerance
pin
functions
RxD3
P82/IRQ2-B/ETEND2
Port 9
P82/IRQ2-B
IRQ2-B
P81/IRQ1-B/PO1-B/TIOCB3-B/ TMRI1-B/TxD3/ P81/IRQ1-B/
EDREQ3
PO1-B/
TIOCB3-B/
TMRI1-B/
TxD3
IRQ1-B,
TIOCB3-B,
TMRI1-B
P80/IRQ0-B/EDREQ2
IRQ0-B
Dedicated input port
P97/AN15_1
also functioning as
A/D converter analog
inputs and D/A
converter analog
outputs
P96/AN14_1
P80/IRQ0-B
⎯
⎯
⎯
⎯
Ο
All output ⎯
pin
functions
other than
address
outputs
P95/AN13_1/DA3
P94/AN12_1/DA2
P93/AN11_1
P92/AN10_1
P91/AN9_1
P90/AN8_1
Port A
General I/O port also
functioning as
address outputs,
interrupt inputs, SSU
I/Os, and SCI I/Os
Page 512 of 1408
PA7/A23/IRQ7-A/
SSO0-B
PA7/A23/IRQ7-A/
SSO0-B
PA7/IRQ7-A/
SSO0-B
IRQ7-A
PA6/A22/IRQ6-A/
PA6/A22/IRQ6-A/
PA6/IRQ6-A/
IRQ6-A
SSI0-B
SSI0-B
SSI0-B
PA5/A21/IRQ5-A/
PA5/A21/IRQ5-A/
PA5/IRQ5-A/
SSCK0-B
SSCK0-B
SSCK0-B
A20/IRQ4-A
PA4/A20/IRQ4-A/
SCS0-B
PA4/IRQ4-A/
SCS0-B
IRQ4-A
A19
PA3/A19/SCK4-B
PA3/SCK4-B
⎯
A18
PA2/A18/RxD4-B
PA2/RxD4-B
A17
PA1/A17/TxD4-B
PA1/TxD4-B
A16
PA0/A16
PA0
IRQ5-A
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Mode 3, 7
Port
Description
Mode 1
Port B
General I/O port also
A15
functioning as
address outputs and
TPU I/Os
Mode 2
Mode 4
PB7/A15
EXPE = 1 EXPE = 0
Open
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
Ο
All output
⎯
TCLKH
TCLKH
TIOCA8
A14
PB6/A14
PB6/TIOCA8
A13
PB5/A13
PB5/TIOCB7/ TIOCB7/
TCLKG
TCLKG
A12
PB4/A12
PB4/TIOCA7
TIOCA7
A11
PB3/A11
PB3/TIOCD6/ TIOCD6/
Tolerance
pin
functions
other than
address
outputs
TCLKF
A10
PB2/A10
PB2/TIOCC6/ TIOCC6/
TCLKE
TCLKE
A9
PB1/A9
PB1/TIOCB6
TIOCB6
A8
PB0/A8
PB0/TIOCA6
TIOCA6
A7
PC7/A7
PC7/TIOCB11
TIOCB11
A6
PC6/A6
PC6/TIOCA11
TIOCA11
A5
PC5/A5
PC5/TIOCB10
TIOCB10
Ο
All output
⎯
pin
functions
other than
address
outputs
A4
PC4/A4
PC4/TIOCA10
TIOCA10
A3
PC3/A3
PC3/TIOCD9
TIOCD9
A2
PC2/A2
PC2/TIOCC9
TIOCC9
A1
PC1/A1
PC1/TIOCB9
TIOCB9
A0
PC0/A0
PC0/TIOCA9
TIOCA9
D15/AD15
PD7
⎯
Ο
D14/AD14
PD6
D13/AD13
PD5
D12/AD12
PD4
D11/AD11
PD3
D10/AD10
PD2
D9/AD9
PD1
All output ⎯
pin
functions
other than
data
outputs
and
address
outputs
D8/AD8
PD0
General I/O port also
PE7/D7/AD7
PE7
⎯
Ο
All output
functioning as data
I/Os and address
outputs
PE6/D6/AD6
PE6
PE5/D5/AD5
PE5
PE4/D4/AD4
PE4
PE3/D3/AD3
PE3
PE2/D2/AD2
PE2
PE1/D1/AD1
PE1
PE0/D0/AD0
PE0
Port D General I/O port also
functioning as data
I/Os and address
outputs
Port E
Input
triggered
input
Pin*2
PB7/TIOCB8/ TIOCB8/
TCLKF
Port C General I/O port also
functioning as
address outputs and
TPU I/Os
Schmitt-
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
⎯
pin
functions
other than
data
outputs
and
address
outputs
Page 513 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Mode 3, 7
Port
Description
Mode 1
Port F
General I/O port also
PF7/φ
PF7/φ
PF6/AS/AH
PF6
functioning as
interrupt inputs, bus
control signal I/Os,
SSU I/Os, and A/D
converter inputs
Mode 2
Mode 4
EXPE = 1 EXPE = 0
Schmitt-
Input
Open
triggered
input
Pin*2
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
⎯
⎯
⎯
⎯
Tolerance
All output
pin
functions
other than
AS and
AH
RD
All output
PF5
pin
functions
other than
RD
HWR
PF4
All output
pin
functions
other than
HWR
PF3/LWR/SSO0-C
PF3/SSO0-C
All output
pin
functions
other than
LWR
PF2/LCAS/DQML*1/IRQ15-A/SSI0-C
PF2/
IRQ15-A
IRQ15-A/
SSI0-C
pin
functions
other than
LCAS and
DQML*1
PF1/UCAS/DQMU*1/IRQ14-A/SSCK0-C
PF1/
IRQ14-A/
SSCK0-C
IRQ14-A
All output
pin
functions
other than
UCAS and
DQMU*1
PF0/WAIT-A/ADTRG0-B/SCS0-C
PF0/
⎯
All output
ADTRG0-B/
SCS0-C
Page 514 of 1408
All output
pin
functions
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Mode 3, 7
Port
Description
Port G General I/O port also
functioning as bus
control signal I/Os
Mode 1
Mode 2
PG6/BREQ-A
Mode 4
EXPE = 1 EXPE = 0
PG6
Schmitt-
Input
Open
triggered
input
Pin*2
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
⎯
⎯
All output
⎯
Tolerance
pin
functions
PG5/BACK-A
PG5
All output
pin
functions
other than
BACK-A
PG4/BREQO-A
PG4
All output
pin
functions
other than
BREQO-A
PG3/CS3/RAS3/CAS*1
PG3
All output
pin
functions
other than
CS3,
RAS3,
and
CAS*1
PG2/CS2/RAS2/RAS*1
PG2
All output
pin
functions
other than
CS2,
RAS2,
and
1
RAS*
PG1/CS1
PG1
All output
pin
functions
other than
CS1
PG0/CS0
PG0
All output
pin
functions
other than
CS0
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Section 10 I/O Ports
Mode 3, 7
Port
Description
Port H General I/O port also
functioning as
interrupt inputs and
bus control signal
I/Os
Mode 1
Mode 2
Mode 4
PH3/CS7/OE-A/CKE-A*1/IRQ7-B
EXPE = 1 EXPE = 0
PH3/IRQ7-B
Schmitt-
Input
Open
triggered
input
Pin*2
Pull-up
MOS
Capability
Drain
Output
Capability
5-V
IRQ7-B
⎯
All output
⎯
Tolerance
pin
functions
other than
CS7, OEA and
CKE-A*1
PH2/CS6/IRQ6-B
PH2/IRQ6-B
IRQ6-B
All output
pin
functions
other than
CS6
PH1/CS5/RAS5/SDRAMφ*1
PH1/
⎯
All output
PH0/CS4/RAS4/WE*1
SDRAMφ*
pin
functions
other than
RAS5 and
SDRAMφ*1
PH0
All output
pin
functions
other than
RAS4 and
WE*1
Port J
General I/O port
PJ2
⎯
⎯
⎯
Ο
All output
pin
functions
PJ1
PJ0
Notes: 1. Not supported in the H8S/2456 Group.
2. Pins other than Schmitt triggered input pins are CMOS input pins.
Page 516 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Table 10.2 Port Functions of H8S/2454 Group
Input
Mode 3, 7
SchmittPort
Description
Mode 1
Port 1
General I/O port also
P17/PO15/TIOCB2/TCLKD/SCS0-A
functioning as PPG
outputs,
TPU I/Os, DMAC
I/Os, and SSU I/Os
Mode 2
Mode 4
EXPE = 1
EXPE = 0
Pull-up
triggered MOS
input Pin* Capability
P17,
⎯
TIOCB2,
TCLKD
P16/PO14/TIOCA2/SSCK0-A
P16,
TIOCA2
P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
P15,
Open
Drain
Output
Capability
5-V
All output
⎯
Tolerance
pin
functions
TIOCB1
P14,
P14/DACK1/PO12/TIOCA1/SSO0-A
TIOCA1
P13/TEND1/PO11/TIOCD0/TCLKB
All input pin
functions
P12/TEND0/PO10/TIOCC0/TCLKA
All input pin
functions
All input pin
P11/DREQ1/PO9/TIOCB0
functions
Port 2
General I/O port also
functioning as PPG
outputs,
TPU I/Os, SCI I/Os,
TMR I/Os,
I2C I/Os,
A/D converter inputs,
bus control signal
I/Os, and USB I/Os.
P10/DREQ0/PO8/TIOCA0
All input pin
functions
P27/PO7/TIOCB5/SCL2
All input pin
⎯
functions
Ο
pin
functions
P26,
P26/PO6/TIOCA5/SDA2/ADTRG1
All output
TIOCA5,
SDA2
P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A/VBUS
P25/
PO5-A/
TIOCB4-A/
TMO1-A/
VBUS
P25,
TIOCB4-A
All input pin
P20/PO0-A/TIOCA3-A/TMRI0
functions
Port 3
General I/O port also
P35/OE-B/SCK1/SCL0
functioning as SCI
I/Os, I2C I/Os, and
bus control signal
I/Os
P35/SCK1/
SCL0
SCL0
⎯
All output
Ο
pin
functions
other than
OE-B
P34/SCK0/SCK4-A/SDA0
SDA0
P33/RxD1/SCL1
SCL1
P32/RxD0/IrRxD/SDA1
SDA1
P31/TxD1
⎯
All output
pin
functions
⎯
P30/TxD0/IrTxD
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Input
Mode 3, 7
Schmitt-
5-V
⎯
⎯
⎯
⎯
All output
pin
functions
⎯
Description
Mode 1
Port 4
General I/O port also
P47/IRQ7-B/AN7_0
IRQ7-B
functioning as A/D
converter analog
inputs and interrupt
inputs
P46/IRQ6-B/AN6_0
IRQ6-B
P45/IRQ5-B/AN5_0
IRQ5-B
P44/IRQ4-B/AN4_0
IRQ4-B
P43/IRQ3-B/AN3_0
IRQ3-B
P42/IRQ2-B/AN2_0
IRQ2-B
P41/IRQ1-B/AN1_0
IRQ1-B
General I/O port also
functioning as
interrupt inputs,
A/D converter inputs,
SCI I/Os,
PPG outputs, TPU
I/Os, TMR I/Os,
I2C I/Os, bus control
Mode 4
Drain
Output
Capability
Port
Port 5
Mode 2
EXPE = 1
P40/IRQ0-B /AN0_0
IRQ0-B
P53/IRQ3-A/ADTRG0-A
IRQ3-A
P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/
P52/
IRQ2-A,
All output
TMO0-B/SCK2
IRQ2-A/
PO4-B/
TIOCA4-B/
TIOCA4-B
pin
functions
other than
General I/O port also
functioning as PPG
outputs, TPU I/Os,
TMR I/Os, SCI I/Os
and interrupt inputs
Port 9
P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/
P51/
IRQ1-A,
All output
TMCI0-B/RxD2/SCL3
IRQ1-A/
PO2-B/
TIOCC3-B/
TMCI0-B/
RxD2/SCL3
TIOCC3-B,
TMCI0-B,
SCL3
pin
functions
P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/
TMRI0-B/TxD2/SDA3
P50/
IRQ0-A/
PO0-B/
TIOCA3-B/
TMRI0-B/
TxD2/SDA3
IRQ0-A,
TIOCA3-B,
TMRI0-B,
SDA3
All output
pin
functions
other than
BREQO-B
P85/PO5-B/TIOCB4-B/TMO1-B/SCK3
TIOCB4-B
P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3
TIOCD3-B,
⎯
TMCI1-B
P81/PO1-B/TIOCB3-B/ TMRI1-B/TxD3
TIOCB3-B,
TMRI1-B
Dedicated input port
P95/AN13_1/DA3
⎯
also functioning as
A/D converter analog
inputs and D/A
converter analog
outputs
P94/AN12_1/DA2
Page 518 of 1408
Tolerance
BACK-B
TMO0-B/
SCK2
signal I/Os, and JTAG
inputs
Port 8
EXPE = 0
Open
Pull-up
triggered MOS
input Pin* Capability
O
All output
⎯
pin
functions
Ο
Ο
⎯
⎯
⎯
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Input
Mode 3, 7
SchmittPort
Description
Mode 1
Port A
General I/O port also
PA7/A23/CS7/IRQ7-A/
PA7/A23/CS7/IRQ7-A/
functioning as
address outputs,
interrupt inputs, SSU
I/Os, SCI I/Os, and
bus control signal
outputs
SSO0-B
SSO0-B
PA7/IRQ7-A/ IRQ7-A
SSO0-B
PA6/A22/IRQ6-A/
SSI0-B
PA6/A22/IRQ6-A/
SSI0-B
PA6/IRQ6-A/ IRQ6-A
SSI0-B
PA5/A21/IRQ5-A/
PA5/A21/IRQ5-A/
PA5/IRQ5-A/ IRQ5-A
SSCK0-B
SSCK0-B
SSCK0-B
A20/IRQ4-A
PA4/A20/IRQ4-A/
PA4/IRQ4-A/ IRQ4-A
SCS0-B
SCS0-B
A19
PA3/A19/SCK4-B
PA3/SCK4-B ⎯
A18
PA2/A18/RxD4-B
PA2/RxD4-B
A17
PA1/A17/TxD4-B
PA1/TxD4-B
A16
PA0/A16
PA0
A15
PB7/A15
PB7/TIOCB8 TIOCB8/
/TCLKH
TCLKH
A14
PB6/A14
PB6/TIOCA8 TIOCA8
A13
PB5/A13
PB5/TIOCB7 TIOCB7/
A12
PB4/A12
PB4/TIOCA7 TIOCA7
A11
PB3/A11
PB3/TIOCD
TIOCD6/
6/TCLKF
TCLKF
PB2/TIOCC
TIOCC6/
6/TCLKE
TCLKE
Port B
General I/O port also
functioning as
address outputs and
TPU I/Os
Mode 2
Mode 4
Pull-up
triggered MOS
input Pin* Capability
EXPE = 1
EXPE = 0
/TCLKG
A10
Port C General I/O port also
functioning as
address outputs and
TPU I/Os
PB2/A10
Ο
PB1/A9
PB1/TIOCB6 TIOCB6
A8
PB0/A8
PB0/TIOCA6 TIOCA6
A7
PC7/A7
PC7/
TIOCB11
TIOCB11
A6
PC6/A6
PC6/
TIOCA11
TIOCA11
A5
PC5/A5
PC5/
TIOCB10
Drain
Output
Capability
5-V
All output
⎯
Tolerance
pin
functions
other than
address
outputs
and CS7
Ο
All output ⎯
pin
functions
other than
address
outputs
Ο
All output
TCLKG
A9
Open
⎯
pin
functions
other than
address
outputs
TIOCB10
A4
PC4/A4
PC4/
TIOCA10
TIOCA10
A3
PC3/A3
PC3/
TIOCD9
TIOCD9
A2
PC2/A2
PC2/
TIOCC9
TIOCC9
A1
PC1/A1
PC1/
TIOCB9
TIOCB9
A0
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
PC0/A0
PC0/
TIOCA9
TIOCA9
Page 519 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Input
Mode 3, 7
SchmittPort
Description
Port D General I/O port also
functioning as data
I/Os and address
outputs
Port E
General I/O port also
functioning as data
I/Os and address
outputs
Page 520 of 1408
Open
Drain
Output
Capability
5-V
EXPE = 0
Pull-up
triggered MOS
input Pin* Capability
D15/AD15
PD7
⎯
All output
⎯
D14/AD14
PD6
D13/AD13
PD5
D12/AD12
PD4
D11/AD11
PD3
D10/AD10
PD2
D9/AD9
PD1
D8/AD8
PD0
PE7/D7/AD7
PE7
PE6/D6/AD6
PE6
PE5/D5/AD5
PE5
PE4/D4/AD4
PE4
PE3/D3/AD3
PE3
PE2/D2/AD2
PE2
PE1/D1/AD1
PE1
PE0/D0/AD0
PE0
Mode 1
Mode 2
Mode 4
EXPE = 1
Ο
Tolerance
pin
functions
other than
address
outputs
⎯
Ο
All output ⎯
pin
functions
other than
data
outputs
and
address
outputs
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Input
Mode 3, 7
SchmittMode 4
5-V
EXPE = 0
Drain
Output
Capability
⎯
⎯
⎯
Port
Description
Mode 1
Port F
General I/O port also
PF7/φ
PF7/φ
PF6/AS/AH
PF6
functioning as bus
control signal I/Os,
SSU I/Os, and A/D
converter inputs
Mode 2
EXPE = 1
Open
Pull-up
triggered MOS
input Pin* Capability
⎯
Tolerance
All output
pin
functions
other than
AS and
AH
RD
PF5
All output
pin
functions
other than
RD
HWR
PF4
All output
pin
functions
other than
HWR
PF3/LWR/SSO0-C
PF3/
All output
SSO0-C
pin
functions
other than
LWR
PF2/SSI0-C
All output
PF2/CS6/LCAS/SSI0-C
pin
functions
other than
CS6 and
LCAS
PF1/CS5/UCAS/DQMU/IRQ14-A/SSCK0-C
PF1/
IRQ14-A/
SSCK0-C
All output
pin
functions
other than
CS5 and
UCAS
PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C
PF0/
All output
ADTRG0-B/
SCS0-C
pin
functions
other than
OE-A
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 521 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Input
Mode 3, 7
SchmittPort
Description
Port G General I/O port also
functioning as bus
control signal I/Os
Mode 1
Mode 2
PG6/BREQ-A
Mode 4
EXPE = 1
Open
Drain
Output
Capability
5-V
EXPE = 0
Pull-up
triggered MOS
input Pin* Capability
PG6
⎯
All output
⎯
⎯
Tolerance
pin
functions
PG5/BACK-A
PG5
All output
pin
functions
other than
BACK-A
PG4/BREQO-A/CS4
PG4
All output
pin
functions
other than
BREQO-A
and CS4
PG3/CS3/RAS3
All output
PG3
pin
functions
other than
CS3 and
RAS3
PG2/CS2/RAS2
PG2
All output
pin
functions
other than
CS2 and
RAS2
PG1/CS1
PG1
All output
pin
functions
other than
CS1
PG0/CS0
All output
PG0
pin
functions
other than
CS0
Note:
*
Pins other than Schmitt triggered input pins are CMOS input pins.
Page 522 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.1
Section 10 I/O Ports
Port 1
Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
Port 1 data direction register (P1DDR)
Port 1 data register (P1DR)
Port 1 register (PORT1)
Port 1 open drain control register (P1ODR)
Port function control register 5 (PFCR5)
10.1.1
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1. P1DDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
10.1.3
Port 1 Register (PORT1)
PORT1 shows the pin states of port 1. PORT1 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P17
⎯*
R
6
P16
⎯*
R
5
P15
⎯*
R
If this register is read while a P1DDR bit is set to 1,
the corresponding P1DR value is read. If this
register is read while a P1DDR bit is cleared to 0,
the corresponding pin state is read.
4
P14
⎯*
R
3
P13
⎯*
R
2
P12
⎯*
R
1
P11
⎯*
R
0
P10
⎯*
R
Note:
*
Determined by the states of pins P17 to P10.
Page 524 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
10.1.4
Section 10 I/O Ports
Port 1 Open Drain Control Register (P1ODR)
P1ODR specifies the output type of each port 1 pin.
Bit
Bit Name
Initial Value
R/W
Description
7
P17ODR
0
R/W
6
P16ODR
0
R/W
5
P15ODR
0
R/W
Setting a P1ODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a P1ODR bit to 0 makes the corresponding pin a
CMOS output pin.
4
P14ODR
0
R/W
3
P13ODR
0
R/W
2
P12ODR
0
R/W
1
P11ODR
0
R/W
0
P10ODR
0
R/W
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Sep 24, 2012
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.1.5
Pin Functions
Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2456 group,
H8S/2456R group), SSU I/Os, and DMAC I/Os (H8S/2454 group). The correspondence between
the register specification and the pin functions is shown below.
(1)
Pin Functions of H8S/2456 Group and H8S/2456R Group
• P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to
IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0
and TCR_5, bit NDER15 in NDERH of PPG, bit EDRAKE in EDMDR_3 of EXDMAC, bits
MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits SCS0S1 and
SCS0S0 in PFCR5, and bit P17DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
SSU settings
(1) in table below
⎯
(2) in table below
⎯
⎯
0
(1) in table
below
P17DDR
⎯
0
1
1
⎯
NDER15
⎯
⎯
0
1
⎯
TIOCB2
output
P17
input
P17
output
PO15
output
Pin function
TIOCB2 input*
2
TCLKD input*
Page 526 of 1408
(4) in
table
below
1
EDRAKE
TPU channel
2 settings
(2) in
table
below
0*6
0*6
(3) in
table
below
⎯
⎯
EDRAK3 SCS0-A
output input*3*7
SCS0-A SCS0-A
I/O*5*7 output*4*7
1
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
SSU settings
(1) in table below
(2) in table (4) in table (3) in table
below
below
below
0
⎯
EDRAKE
TPU channel 2
settings
(1) in table
below
⎯
(2) in table below
P17DDR
⎯
0
1
1
NDER15
⎯
⎯
0
1
TIOCB2
output
P17
input
P17
output
PO15
output
Pin function
TIOCB2 input*
0*6
0*6
⎯
⎯
SCS0-A
input*3*7
SCS0-A
I/O*5*7
SCS0-A
output*4*7
1
TCLKD input*
2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
3. When using as SCS0-A input, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SCS0-A output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before
other register setting.
5. When using as SCS0-A input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'00
before other register setting.
6. P17DDR = 0 when the SSU pin is used as input.
7. Do not set up for SSU unless SCS0S1 and SCS0S0 = B'00 in PFCR5.
Use as I/O port, TPU or EXDMAC pin.
TPU channel 2
settings
MD3 to MD0
(2)
(1)
B'0000, B'01xx
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Other than B'xx00
Page 527 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
SSU settings
(2)
(1)
(2)
SSUMS
(4)
(1)
0
1
MSS
0
CSS1
x
CSS0
x
0
1
SCS input
⎯
SCS input
Pin state
(3)
1
x
0
1
0
x
1
x
Automatic SCS SCS output
I/O
⎯
[Legend]
x:
Don't care
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
• P16/PO14/TIOCA2/EDRAK2/SSCK0-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to
IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of PPG,
bit EDRAKE in EDMDR_2 of EXDMAC, bits MSS and SCKS in SSCRH and bit SSUMS in
SSCRL of SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
SSU settings
(1) in table below
EDRAKE
0
TPU channel 2 (1) in table
settings
below
P16DDR
NDER14
Pin function
(2) in table (3) in table
below
below
⎯
⎯
TIOCA2
output
(2) in table below
0
1
⎯
0
P16 input P16 output
⎯
⎯
⎯
⎯
1
1
⎯
PO14
output
EDRAK2
output
TIOCA2 input*
Page 528 of 1408
1
⎯
0*5
⎯
SSCK0-A
input*3*6
SSCK0-A
output*4*6
1
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
SSU settings
(1) in table below
EDRAKE
TPU channel 2
settings
(2) in table
below
⎯
0
(1) in table
below
⎯
(2) in table below
P16DDR
⎯
0
1
1
NDER14
⎯
⎯
0
1
TIOCA2
output
P16
input
P16
output
PO14
output
Pin function
TIOCA2 input*
TPU channel 2
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
(3) in table
below
⎯
(1)
B'001x
B'0010
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
SSCK0-A
input*3*6
SSCK0-A
output*4*6
1
(2)
B'0000,
B'0100,
B'1xxx
⎯
0*5
(1)
(2)
B'0011
Other than B'xx00
⎯
Other than
B'01
B'01
PWM*2 mode PWM mode 2
1 output
output
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. TIOCB2 output disabled.
3. When using as SSCK0-A input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'00 before
other register setting.
4. When using as SSCK0-A output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'00 before
other register setting.
5. P16DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'00 in PFCR5.
Use as I/O port, TPU or EXDMAC pin.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 529 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
SSU settings
(1)
(2)
SSUMS
(1)
(3)
(1)
(2)
(1)
0
MSS
(3)
1
0
1
0
1
SCKS
0
1
0
1
0
1
0
1
Pin state
⎯
SSCK
input
⎯
SSCK
output
⎯
SSCK
input
⎯
SSCK
output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note:
See tables 20.4 to 20.6.
• P15/PO13/TIOCB1/TCLKC/SSI0-A
The pin function is switched as shown below according to the combination of TPU channel 1
settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit
NDER13 in NDERH of PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits
TE and RE in SSER of SSU, bits SSI0S1 and SSI0S0 in PFCR5, and bit P15DDR.
SSU settings
TPU channel 1
settings
(1) in table below
(1) in table
below
(2) in table
below
⎯
(2) in table below
P15DDR
⎯
0
1
1
NDER13
⎯
⎯
0
1
TIOCB1 output
P15 input
Pin function
(3) in table
below
P15 output PO13 output
TIOCB1 input*1
⎯
0*5
⎯
SSI0-A
input*3*6
SSI0-A
output*4*6
TCLKC input*2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC
input when phase counting mode is set for channels 2 and 4.
3. When using as SSI0-A input, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SSI0-A output, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other
register setting.
5. P15DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'00 in PFCR5.
Use as I/O port or TPU pin.
Page 530 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 1
settings
Section 10 I/O Ports
(2)
MD3 to MD0
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
SSU
(1)
(1)
(3)
(3)
(2)
(1)
(2)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(2)
(1)
(2)
settings
SSUMS
0
0
BIDE
0
1*
MSS
0
TE
1
0
1
0
1
1*
2
0
0
1
0
1
1
0
0
1
0
1
1
0
1
RE
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
Pin
⎯
⎯
SSI
SSI
SSI
⎯
SSI
⎯
⎯
⎯
⎯
SSI
⎯
SSI
SSI
⎯
SSI
input
input
state
output output
input
input
input
input
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
R01UH0309EJ0500 Rev. 5.00
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Page 531 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P14/PO12/TIOCA1/SSO0-A
The pin function is switched as shown below according to the combination of TPU channel 1
settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bit NDER12 in NDERH of PPG, bits MSS and BIDE in SSCRH, bit
SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bits SSO0S1 and SSO0S0 in
PFCR5, and bit P14DDR.
SSU settings
TPU channel 1
settings
(1) in table below
(1) in table
below
(2) in table
below
⎯
(2) in table below
P14DDR
⎯
0
1
1
NDER12
⎯
⎯
0
1
TIOCA1
output
P14 input
Pin function
TPU channel 1
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
(3) in table
below
P14 output PO12 output
TIOCA1 input*1
⎯
0*5
⎯
SSO0-A
input*3*6
SSO0-A
output*4*6
(1)
(2)
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'01
B'01
Output function
⎯
Output
compare
output
⎯
PWM*2
mode 1
output
PWM mode
2 output
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
2. TIOCB1 output disabled.
3. When using as SSO0-A input, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SSO0-A output, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before
other register setting.
5. P14DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SSO0S1 and SSO0S0 = B'00 in PFCR5.
Use as I/O port or TPU pin.
Page 532 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
SSU
(1)
(2)
(1)
(2)
(1)
Section 10 I/O Ports
(3)
(3)
(2)
(3)
(2)
(3)
(1)
(3)
(3)
(1)
(3)
(3)
settings
SSUMS
0
0
BIDE
0
1*
MSS
2
0
TE
1
0
1
1*
0
0
0
1
0
1
1
1
0
0
1
0
1
1
0
1
RE
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
Pin
⎯
SSO
⎯
SSO
⎯
SSO
SSO
SSO
SSO
SSO
SSO
⎯
SSO
SSO
⎯
SSO
SSO
output
output
input
output
output
state
input
input
output input output
output output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
• P13/PO11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits
CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in
NDERH of PPG, and bit P13DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P13DDR
⎯
0
NDER11
⎯
⎯
0
TIOCD0 output
P13 input
P13 output
Pin function
1
TIOCD0 input*
2
TCLKB input*
1
PO11 output
1
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101.
TCLKB input when phase counting mode is set for channels 1 and 5.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 533 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 0
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Other than B'xx00
[Legend]
x:
Don't care
• P12/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of
PPG, and bit P12DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P12DDR
⎯
0
NDER10
⎯
⎯
0
1
TIOCC0 output
P12 input
P12 output
PO10 output
Pin function
1
1
TIOCC0 input*
TCLKA input*
2
Page 534 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 0
settings
(2)
MD3 to MD0
IOC3 to IOC0
Section 10 I/O Ports
(1)
B'0000
(2)
(1)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2)
Other than
B'101
B'101
⎯
PWM*3 mode PWM mode
1 output
2 output
[Legend]
x:
Don't care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_0.
• P11/PO9/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of PPG, and bit P11DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P11DDR
⎯
0
NDER9
⎯
⎯
0
1
TIOCB0 output
P11 input
P11 output
PO9 output
Pin function
1
TIOCB0 input*
Note:
*
TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 535 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 0
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
• P10/PO8/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of PPG, and bit P10DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P10DDR
⎯
0
NDER8
⎯
⎯
0
1
TIOCA0 output
P10 input
P10 output
PO8 output
Pin function
1
TIOCA0 input*1
Page 536 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 0
settings
(2)
MD3 to MD0
IOA3 to IOA0
Section 10 I/O Ports
(1)
B'0000
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'001
B'001
Output function
⎯
Output
compare
output
⎯
PWM*2
mode 1
output
PWM mode
2 output
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. TIOCB0 output disabled.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 537 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
(2)
Pin Functions of H8S/2454 Group
• P17/PO15/TIOCB2/TCLKD/SCS0-A
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH
of PPG, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits
SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR.
SSU settings
(1) in table below
TPU channel 2 (1) in table
settings
below
P17DDR
NDER15
Pin function
⎯
(2) in
table
below
⎯
⎯
TIOCB2
output
P17 input
(3) in
table
below
⎯
(2) in table below
0
(4) in
table
below
1
1
0
1
P17 output PO15 output
1
TIOCB2 input*
0*6
0*6
⎯
⎯
SCS0-A
3 7
input* *
SCS0-A SCS0-A
5 7
4 7
I/O* * output* *
TCLKD input*2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
3. When using as SCS0-A input, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SCS0-A output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before
other register setting.
5. When using as SCS0-A input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'00
before other register setting.
6. P17DDR = 0 when the SSU pin is used as input.
7. Do not set up for SSU unless SCS0S1 and SCS0S0 = B'00 in PFCR5.
Use as I/O port or TPU pin.
Page 538 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 2
settings
MD3 to MD0
(2)
Section 10 I/O Ports
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
(2)
(1)
(3)
(1)
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
SSU settings
(2)
SSUMS
(4)
0
1
MSS
0
CSS1
x
CSS0
x
0
1
0
1
x
SCS input
⎯
SCS input
Automatic
SCS I/O
SCS output
⎯
Pin state
1
x
0
1
x
[Legend]
x:
Don't care
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 539 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P16/PO14/TIOCA2/SSCK0-A
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bit NDER14 in NDERH of PPG, bits MSS and SCKS in SSCRH and
bit SSUMS in SSCRL of SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR.
SSU settings
TPU channel 2
settings
(1) in table below
(1) in table
below
(2) in table
below
⎯
(2) in table below
P16DDR
⎯
0
1
1
NDER14
⎯
⎯
0
1
TIOCA2
output
P16 input
Pin function
TPU channel 2
settings
MD3 to MD0
IOA3 to IOA0
(2)
B'0000, B'01xx
0*4
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
1
⎯
P16 output PO14 output
1
TIOCA2 input*
(1)
(3) in table
below
SSCK0-A
input*2*5
SSCK0-A
output*3*5
(1)
(2)
B'0011
Other than B'xx00
⎯
Other than
B'01
PWM*2 mode PWM mode
1 output
2 output
B'01
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. When using as SSCK0-A input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'00 before
other register setting.
3. When using as SSCK0-A output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'00 before
other register setting.
4. P16DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'00 in PFCR5.
Use as I/O port or TPU pin.
Page 540 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
SSU settings
(1)
Section 10 I/O Ports
(2)
(1)
SSUMS
(3)
(1)
(2)
(1)
0
MSS
(3)
1
0
1
0
1
SCKS
0
1
0
1
0
1
0
1
Pin state
⎯
SSCK input
⎯
SSCK output
⎯
SSCK input
⎯
SSCK output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
• P15/DACK1/PO13/TIOCB1/TCLKC/SSI0-A
The pin function is switched as shown below according to the combination of bit SAE1 in
DMABCRH of DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3
to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in
TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH of PPG, bits MSS and BIDE in
SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bits SSI0S1 and SSI0S0
in PFCR5, and bit P15DDR.
SSU settings
(1) in table below
SAE1
(2) in table (3) in table
below
below
0
TPU channel 1 (1) In table
settings
below
(2) In table below
1
⎯
⎯
⎯
P15DDR
⎯
0
1
1
⎯
NDER13
⎯
⎯
0
1
⎯
TIOCB1
output
P15
input
P15
output
PO13
output
DACK1
output
Pin function
TIOCB1 input*
⎯
0*5
⎯
SSI0-A
input*3*6
SSI0-A
output*4*6
1
2
TCLKC input*
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR_0 or TCR_2 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC
input when phase counting mode is set for channels 2 and 4.
3. When using as SSI0-A input, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SSI0-A output, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other
register setting.
5. P15DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'00 in PFCR5.
Use as I/O port, TPU or DMAC pin.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 541 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 1
settings
(2)
MD3 to MD0
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to B'0011,
B'0101 to B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
SSU
(1)
(1)
(3)
(3)
(2)
(1)
(2)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(2)
(1)
(2)
settings
SSUMS
0
0
BIDE
0
1*
MSS
0
TE
1
0
1
RE
0
1
Pin state
⎯
⎯
0
1
1
0
SSI
SSI
SSI
⎯
output output input
2
0
0
1
0
1
1*
1
0
0
1
0
1
0
1
1
0
1
0
1
0
SSI
⎯
⎯
⎯
⎯
SSI
⎯
input
input
1
1
0
1
1
1
0
SSI
SSI
⎯
input
input
1
SSI
input
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
Page 542 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P14/DACK0/PO12/TIOCA1/SSO0-A
The pin function is switched as shown below according to the combination of bit SAE0 in
DMABCRH of DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3
to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of
PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of
SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR.
SSU settings
(1) in table below
SAE0
(2) in table (3) in table
below
below
0
TPU channel 1 (1) in table
settings
below
(2) in table below
1
⎯
⎯
⎯
P14DDR
⎯
0
1
1
⎯
NDER12
⎯
⎯
0
1
⎯
TIOCA1
output
P14
input
P14
output
PO12
output
DACK0
output
Pin function
TIOCA1 input*
TPU channel 1
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000, B'01xx
⎯
0*4
⎯
SSO0-A
input*2*5
SSO0-A
output*3*5
(1)
(2)
1
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to B'0011,
B'0101 to B'0111
B'xx00
Other than
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output compare
output
⎯
Other than
B'01
PWM*2 mode PWM mode
1 output
2 output
B'01
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
2. When using as SSO0-A input, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before other
register setting.
3. When using as SSO0-A output, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before
other register setting.
4. P14DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSO0S1 and SSO0S0 = B'00 in PFCR5.
Use as I/O port, TPU or DMAC pin.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 543 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
SSU
(1)
(2)
(1)
(2)
(1)
(3)
(3)
(2)
(3)
(2)
(3)
(1)
(3)
(3)
(1)
(3)
(3)
settings
SSUMS
0
0
BIDE
0
1*
MSS
0
TE
1
0
1
0
1
1*
2
0
0
1
1
0
1
0
0
1
1
0
1
0
1
RE
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
Pin state
⎯
SSO
⎯
SSO
⎯
SSO
SSO
SSO
SSO
SSO
SSO
⎯
SSO
SSO
⎯
SSO
SSO
input
output
output
output
input
input
output output
input output
output output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
• P13/TEND1/PO11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of bit TEE1 in
DMATCR of DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to
IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to
TCR_2, bit NDER11 in NDERH of PPG, and bit P13DDR.
TEE1
TPU channel 0
settings
(1) in table
below
0
1
(2) in table below
⎯
P13DDR
⎯
0
1
1
⎯
NDER11
⎯
⎯
0
1
⎯
TIOCD0 output
P13 input
P13 output
PO11 output
TEND1 output
Pin function
TIOCD0 input*
1
2
TCLKB input*
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101.
TCLKB input when phase counting mode is set for channels 1 and 5.
Page 544 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 0
settings
Section 10 I/O Ports
(2)
MD3 to MD0
(1)
(2)
B'0000
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Other than B'xx00
[Legend]
x:
Don't care
• P12/TEND0/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of bit TEE0 in
DMATCR of DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to
IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to
TCR_5, bit NDER10 in NDERH of PPG, and bit P12DDR.
TEE0
TPU channel 0
settings
(1) in table
below
0
1
(2) in table below
⎯
P12DDR
⎯
0
1
1
⎯
NDER10
⎯
⎯
0
1
⎯
TIOCC0 output
P12 input
P12 output
PO10 output
TEND0 output
Pin function
TIOCC0 input*
1
TCLKA input*2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 545 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 0
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2)
Other than
B'101
B'101
⎯
PWM*3 mode PWM mode
1 output
2 output
[Legend]
x:
Don't care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for any of TCR_0 to TCR_5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
3. TIOCD0 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_0.
• P11/DREQ1/PO9/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of PPG, bit USBDRQE in PFCR3 and
bit P11DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P11DDR
⎯
0
NDER9
⎯
⎯
0
TIOCB0 output
P11 input
P11 output
Pin function
1
TIOCB0 input*
1
PO9 output
1
DREQ1 input*
2
Notes: 1. TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
2. DREQ1 input when the USBDRQE bit in PFCR3 is 0. Do not set the DREQ1 pin as an
activation source when USBDRQE is 1.
Page 546 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 0
settings
Section 10 I/O Ports
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
• P10/DREQ0/PO8/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of PPG, bit USBDRQE in PFCR3, and
bit P10DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P10DDR
⎯
0
NDER8
⎯
⎯
0
TIOCA0 output
P10 input
P10 output
Pin function
1
TIOCA0 input*
1
PO8 output
1
DREQ0 input*
3
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 547 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 0
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
Other than
B'001
PWM*2 mode PWM mode
1 output
2 output
B'001
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. TIOCB0 output disabled.
3. When using as DREQ0 input, set USBDRQE in PFCR3 to 0 before other register
setting. When USBDRQE is 1, use of the DREQ0 signal from the DREQ0 input pin is
not allowed.
Page 548 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.2
Section 10 I/O Ports
Port 2
Port 2 is an 8-bit I/O port that also has other functions. Port 2 has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
Port 2 data direction register (P2DDR)
Port 2 data register (P2DR)
Port 2 register (PORT2)
Port 2 open drain control register (P2ODR)
Port function control register 3 (PFCR3)
10.2.1
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
4
⎯
0
⎯
Bits 4 to 0 are reserved.
3
⎯
0
⎯
2
⎯
0
⎯
1
⎯
0
⎯
0
P20DDR
0
W
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
Page 549 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
P25DR
0
R/W
4
⎯
0
⎯
Bits 4 to 1 are reserved.
3
⎯
0
⎯
2
⎯
0
⎯
These bits are read as 0.
When written, the initial value should be written to.
1
⎯
0
⎯
0
P20DR
0
R/W
10.2.3
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
Port 2 Register (PORT2)
PORT2 shows the pin states of port 2. PORT2 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P27
⎯*
R
6
P26
⎯*
R
5
P25
⎯*
R
If this register is read while a P2DDR bit is set to 1,
the corresponding P2DR value is read. If this
register is read while a P2DDR bit is cleared to 0,
the corresponding pin state is read.
4
⎯
Undefined
⎯
Bits 4 to 1 are reserved.
3
⎯
Undefined
⎯
The read value is undefined.
2
⎯
Undefined
⎯
1
⎯
Undefined
⎯
0
P20
⎯*
R
Note:
*
If this register is read while a P2DDR bit is set to 1,
the corresponding P2DR value is read. If this
register is read while a P2DDR bit is cleared to 0,
the corresponding pin state is read.
Determined by the states of pins P27 to P25 and P20.
Page 550 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.2.4
Section 10 I/O Ports
Port 2 Open Drain Control Register (P2ODR)
P2ODR specifies the output type of each port 2 pin.
Bit
Bit Name
Initial Value
R/W
Description
7
P27ODR
0
R/W
6
P26ODR
0
R/W
5
P25ODR
0
R/W
Setting a P2ODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a P2ODR bit to 0 makes the corresponding pin a
CMOS output pin.
4
⎯
0
⎯
Bits 4 to 1 are reserved.
3
⎯
0
⎯
When written, the initial value should be written to.
2
⎯
0
⎯
1
⎯
0
⎯
0
P20ODR
0
R/W
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Setting a P2ODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing a
P2ODR bit to 0 makes the corresponding pin a
CMOS output pin.
Page 551 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.2.5
Pin Functions
Port 2 pins also function as the pins for PPG outputs, TPU I/Os, interrupt inputs (H8S/2456 group,
H8S/2456R group), 8-bit timer I/Os (H8S/2454 group), I2C I/Os, USB I/Os, and bus control signal
inputs. The correspondence between the register specification and the pin functions is shown
below.
(1)
Pin Functions of H8S/2456 Group and H8S/2456R Group
• P27/PO7/TIOCB5/IRQ15-B/SCL2
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER7 in NDERL of PPG, bit ICE in ICCRA_2 of I2C, bit
P27DDR, and bit ITS15 in ITSR of the interrupt controller.
ICE
TPU channel 5
settings
(1) in table
below
0
1
(2) in table below
⎯
P27DDR
⎯
0
1
1
⎯
NDER7
⎯
⎯
0
1
⎯
TIOCB5 output
P27 input
P27 output
PO7 output
SCL2 I/O*3
Pin function
TIOCB5 input*
2
IRQ15-B interrupt input*
1
Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. IRQ15-B input when the ITS15 bit in ITSR is 1.
3. NMOS open-drain output regardless of P27ODR.
Page 552 of 1408
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Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 5
settings
(2)
MD3 to MD0
Section 10 I/O Ports
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
• P26/PO6/TIOCA5/IRQ14-B/SDA2/ADTRG1
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL of PPG, bits TRGS1, TRGS0, and EXTRGS in
ADCR_1 of ADC, bit ICE in ICCRA_2 of I2C, bit P26DDR, and bit ITS14 in ITSR of the
interrupt controller.
ICE
TPU channel 5
settings
(1) in table
below
0
1
(2) in table below
⎯
P26DDR
⎯
0
1
1
⎯
NDER6
⎯
⎯
0
1
⎯
TIOCA5 output
P26 input
P26 output
PO6 output
SDA2 I/O*5
Pin function
TIOCA5 input*
IRQ14-B interrupt input*2
1
ADTRG1 input*
4
R01UH0309EJ0500 Rev. 5.00
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Page 553 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 5
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
Other than
B'01
PWM*3 mode PWM mode
1 output
2 output
B'01
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1.
2. IRQ14-B input when the ITS14 bit in ITSR is 1.
3. TIOCB5 output disabled.
4. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1.
5. NMOS open-drain output regardless of P26ODR.
Page 554 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P25/PO5-A/TIOCB4-A/IRQ13-B/WAIT-B/VBUS
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings by bits
MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in
TCR_4, bit NDER5 in NDERL of PPG, bits PPGS and TPUS in PFCR3, bit WAITS in
PFCR4, bit P25DDR, and bit ITS13 in ITSR of the interrupt controller.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
WAITE
TPU channel 4
settings
(1) in table
below
0
1
(2) in table below
⎯
P25DDR
⎯
0
1
1
⎯
NDER5
⎯
⎯
0
1
⎯
Pin function
TIOCB4-A
4
output*
P25 input
P25 output
PO5-A output*3 WAIT-B input*5
TIOCB4-A input*1*4
IRQ13-B interrupt input*2
VBUS input
• Modes 3 and 7 (EXPE = 0)
⎯
WAITE
TPU channel 4
settings
(1) in table below
(2) in table below
P25DDR
⎯
0
0
1
NDER5
⎯
⎯
⎯
0
P25 input
P25 output
PO5-A output*3
Pin function
TIOCB4-A output*
4
TIOCB4-A input*1*4
IRQ13-B interrupt input*2
VBUS input
Notes: 1.
2.
3.
4.
TIOCB4-A input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
IRQ13-B input when the ITS13 bit in ITSR is 1.
When using as PO5-A output, set PPGS in PFCR3 to 0 before other register setting.
When using as TIOCB4-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
5. WAIT-B input when the WAITS bit in PFCR4 is 1. Not used as WAIT-B input when
WAITS is 0.
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 4
settings
MD3 to MD0
(2)
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
•
P20/PO0-A/TIOCA3-A/IRQ8-B/PUPD+
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIOR H_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bit PULLUP_E in CTLR of
the USB, bits PPGS and TPUS in PFCR3, bit P20DDR, and bit ITS8 in ITSR of the interrupt
controller.
PULLUP_E
TPU channel 3
settings
(1) in table
below
P20DDR
⎯
0
NDER0
⎯
⎯
Pin function
TIOCA3-A
output*5
P20 input
0
1
(2) in table below
⎯
1
⎯
⎯
1
0
P20 output
PO0-A output*
1
TIOCA3-A input* *
5
4
⎯
PUPD+ output
IRQ8-B interrupt input*
2
Page 556 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 3
settings
(2)
MD3 to MD0
IOA3 to IOA0
Section 10 I/O Ports
(1)
B'0000
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
Other than
B'001
PWM*3 mode PWM mode 2
1 output
output
B'001
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. IRQ8-B input when the ITS8 bit in ITSR is 1.
3. TIOCB3 output disabled.
4. When using as PO0-A output, set PPGS in PFCR3 to 0 before other register setting.
5. When using as TIOCA3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
(2)
Pin Functions of H8S/2454 Group
• P27/PO7/TIOCB5/SCL2
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER7 in NDERL of PPG, bit ICE in ICCRA_2 of I2C, and bit
P27DDR.
ICE
TPU channel 5
settings
(1) in table
below
0
1
(2) in table below
⎯
P27DDR
⎯
0
1
1
⎯
NDER7
⎯
⎯
0
1
⎯
TIOCB5 output
P27 input
P27 output
PO7 output
SCL2 I/O*2
Pin function
TIOCB5 input*
1
Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. NMOS open-drain output regardless of P27ODR.
TPU channel 5
settings
MD3 to MD0
(2)
(1)
B'0000, B'01xx
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Page 558 of 1408
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Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P26/PO6/TIOCA5/SDA2/ADTRG1
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL of PPG, bits TRGS1, TRGS0, and EXTRGS in
ADCR_1 of ADC, bit ICE in ICCRA_2 of I2C, and bit P26DDR.
ICE
TPU channel 5
settings
(1) in table
below
0
1
(2) in table below
⎯
P26DDR
⎯
0
1
1
⎯
NDER6
⎯
⎯
0
1
⎯
TIOCA5 output
P26 input
P26 output
PO6 output
SDA2 I/O*4
Pin function
TIOCA5 input*1
ADTRG1 input*
3
TPU channel 5
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
Other than
B'01
PWM*2 mode PWM mode
1 output
2 output
B'01
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. TIOCB5 output disabled.
3. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1.
4. NMOS open-drain output regardless of P26ODR.
R01UH0309EJ0500 Rev. 5.00
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Page 559 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A/VBUS
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits
MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in
TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of PPG, bits
PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, and bit P25DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
WAITE
0
TPU channel 4 (1) In table
settings
below
⎯
(2) In table below
OS3 to OS0
⎯
P25DDR
⎯
0
1
NDER5
⎯
⎯
0
Pin function
1
Not all 0
⎯
1
⎯
⎯
1
⎯
⎯
TMO1-A
4
output*
WAIT-B
input*5
All 0
TIOCB4-A
3
output*
P25 input P25 output PO5-A output*2
TIOCB4-A input*1*3
VBUS input
• Modes 3 and 7 (EXPE = 0)
⎯
WAITE
TPU channel 4
settings
(1) In table below
(2) In table below
OS3 to OS1
⎯
P25DDR
⎯
0
NDER5
⎯
⎯
TIOCB4-A output*3
P25 input
Pin function
All 0
1
Not all 0
⎯
1
⎯
2
*
P25 output PO5-A output TMO1-A output*4
0
1
1
3
TIOCB4-A input* *
VBUS input
Notes: 1. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. When using as PO5-A output, set PPGS in PFCR3 to 0 before other register setting.
3. When using as TIOCB4-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
4.When using as TMO1-A output, set TMRS in PFCR3 to 0 before other register setting.
5. WAIT-B input when the WAITS bit in PFCR4 is 1. Not used as WAIT-B input when WAITS is 0.
Page 560 of 1408
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Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 4
settings
MD3 to MD0
(2)
Section 10 I/O Ports
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
• P20/PO0-A/TIOCA3-A/TMRI0-A/PUPD+
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIOR H_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bit PULLUP_E in CTLR of
the USB, bits PPGS, TPUS and TMRS in PFCR3, and bit P20DDR.
PULLUP_E
TPU channel 3
settings
(1) in table
below
P20DDR
⎯
0
NDER0
⎯
⎯
Pin function
TIOCA3-A
output*5
P20 input
0
1
(2) in table below
⎯
1
⎯
0
⎯
1
P20 output
PO0-A output*
1
4
PUPD+ output
5
TIOCA3-A input* *
IRQ8-B-A input*2*6
R01UH0309EJ0500 Rev. 5.00
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Page 561 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
TPU channel 3
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
Other than
B'001
PWM*3 mode PWM mode 2
1 output
output
B'001
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. When used as the counter reset input pin for the TMR, the external reset should be
selected using the bits CCLR1 and CCLR0 in TCR_0 and TMRIS bit in TCCR_0 after
the TMRS bit in PFCR3 is set to 0.
3. TIOCB3 output disabled.
4. When using as PO0-A output, set PPGS in PFCR3 to 0 before other register setting.
5. When using as TIOCA3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
6. When using as TMRI0-A input, set TMRS in PFCR3 to 0 before other register setting.
Page 562 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
10.3
Section 10 I/O Ports
Port 3
Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
Port 3 data direction register (P3DDR)
Port 3 data register (P3DR)
Port 3 register (PORT3)
Port 3 open drain control register (P3ODR)
Port function control register 2 (PFCR2)
10.3.1
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
7, 6
⎯
All 0
⎯
Reserved
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
R/W
Description
Page 563 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
10.3.3
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
Port 3 Register (PORT3)
PORT3 shows the pin states of port 3. PORT3 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
Undefined
⎯
Reserved
If these bits are read, they will return an undefined
value.
5
P35
⎯*
R
4
P34
⎯*
R
3
P33
⎯*
R
2
P32
⎯*
R
1
P31
⎯*
R
0
P30
⎯*
R
Note:
*
If this register is read while a P3DDR bit is set to 1,
the corresponding P3DR value is read. If this
register is read while a P3DDR bit is cleared to 0,
the corresponding pin state is read.
Determined by the states of pins P35 to P30.
Page 564 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
10.3.4
Section 10 I/O Ports
Port 3 Open Drain Control Register (P3ODR)
P3ODR specifies the output type of each port 3 pin.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
5
P35ODR
0
R/W
When OE-B/CKE-B* output is not selected, setting
this bit to 1 makes the corresponding pin an NMOS
open-drain output pin, while clearing the bit to 0
makes the corresponding pin a CMOS output pin.
4
P34ODR
0
R/W
3
P33ODR
0
R/W
Setting a bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing a bit to
0 makes the corresponding pin a CMOS output pin.
2
P32ODR
0
R/W
1
P31ODR
0
R/W
0
P30ODR
0
R/W
Note: Not supported in the H8S/2456 Group and H8S/2454 Group.
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.3.5
Pin Functions
Port 3 pins also function as the pins for SCI I/Os, I2C I/Os, and bus control signal outputs. The
correspondence between the register specification and the pin functions is shown below.
• P35/OE-B/CKE-B*2/SCK1/SCL0
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit ICE in ICCRA_0 of I2C, bit C/A in SMR_1 and bits CKE0 and CKE1 in
SCR_1 of SCI, bits OEE and RMTS2 to RMTS0 in DRAMCR of the bus controller, bit OES
in PFCR2, and bit P35DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
OEE
0
1
OES
⎯
1
RMTS2
⎯
⎯
0
Any of
Areas 2 to
to
areas 2
5 are
RMTS0
to 5 is
continuous
DRAM
SDRAM
space
space
ICE
0
CKE1
0
C/A
0
0
1
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Pin
P35
P35
SCK1
SCK1
function
input
output
output
output
Page 566 of 1408
1
1
0
CKE0
P35DDR
1
1
⎯
1
⎯
⎯
0
0
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0
0
1
SCK1 SCL0 P35
P35
input I/O*1 input output
SCK1
output
SCK1 SCK1 SCL0
input I/O*1
output
OE-B
CKE-B
output
output*2
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
OEE
⎯
OES
⎯
RMTS2 to
RMTS0
⎯
ICE
0
CKE1
C/A
⎯
1
⎯
⎯
1
⎯
⎯
⎯
0
CKE0
0
0
1
⎯
⎯
⎯
⎯
P35
input
P35
output
SCK1 output
SCK1
output
SCK1
input
SCL0
I/O*1
P35DDR
Pin function
1
1
0
Notes: 1. NMOS open-drain output regardless of P35ODR.
2. Not supported in the H8S/2456 Group and H8S/2454 Group.
• P34/SCK0/SCK4-A/SDA0
The pin function is switched as shown below according to the combination of bit ICE in
ICCRA_0 of I2C, bit C/A in SMR_0 and bits CKE0 and CKE1 in SCR_0 and SCR_4 of SCI,
and bit P34DDR.
ICE
0
CKE1
0
C/A
0
CKE0
P34DDR
Pin function
1
0
0
1
P34
input
P34
output
1
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SCK0/SCK4-A SCK0/SCK4-A SCK0/SCK4-A
output*2*3
output*2*3
input*3
SDA0
I/O*1
Notes: 1. NMOS open-drain output regardless of P34ODR.
2. Simultaneous output of SCK0 and SCK4 cannot be set.
3. When using as SCK4-A input/output, set SCK4S in PFCR4 to 0 before other register
setting.
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Section 10 I/O Ports
• P33/RxD1/SCL1
The pin function is switched as shown below according to the combination of bit ICE in
ICCRA_1 of I2C, bit RE in SCR_1 of SCI, and bit P33DDR.
ICE
0
RE
P33DDR
Pin function
1
0
1
⎯
0
1
⎯
⎯
P33 input
P33 output
RxD1 input
SCL1 I/O*
Note: NMOS open-drain output regardless of P33ODR.
• P32/RxD0/IrRxD/SDA1
The pin function is switched as shown below according to the combination of bit ICE in
ICCRA_1 of I2C, bit RE in SCR_0 of SCI, and bit P32DDR.
ICE
0
RE
P32DDR
Pin function
1
0
1
⎯
0
1
⎯
⎯
P32 input
P32 output
RxD0/IrRxD input
SDA1 I/O*
Note: NMOS open-drain output regardless of P33ODR.
• P31/TxD1
The pin function is switched as shown below according to the combination of bit TE in SCR_1
of SCI and bit P31DDR.
TE
P31DDR
Pin function
Page 568 of 1408
0
1
0
1
⎯
P31 input
P31 output
TxD1 output
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P30/TxD0/IrTxD
The pin function is switched as shown below according to the combination of bit TE in SCR_0
of SCI and bit P30DDR.
TE
P30DDR
Pin function
R01UH0309EJ0500 Rev. 5.00
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0
1
0
1
⎯
P30 input
P30 output
TxD0/IrTxD output
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Section 10 I/O Ports
10.4
Port 4
Port 4 is an 8-bit input-only port that also has other functions, such as analog input pins. Port 4 has
the following register.
• Port 4 register (PORT4)
10.4.1
Port 4 Register (PORT4)
PORT4 is an 8-bit read-only register that shows the pin states of port 4. PORT4 cannot be
modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P47
⎯*
R
The pin states are always read from this register.
6
P46
⎯*
R
5
P45
⎯*
R
4
P44
⎯*
R
3
P43
⎯*
R
2
P42
⎯*
R
1
P41
⎯*
R
0
P40
⎯*
R
Note:
*
10.4.2
Determined by the states of pins P47 to P40.
Pin Functions
Port 4 also functions as the pins for A/D converter analog inputs and interrupt inputs (the
H8S/2454 Group). The correspondence between pins is as follows.
(1)
Pin Functions of H8S/2456 Group and H8S/2456R Group
• P40/AN0_0, P41/AN1_0, P42/AN2_0, P43/AN3_0, P44/AN4_0, P45/AN5_0, P46/AN6_0,
P47/AN7_0
Pin function
ANn_0 input
[Legend]
n = 7 to 0
Page 570 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
(2)
Section 10 I/O Ports
Pin Functions of H8S/2454 Group
• P47/IRQ7-B/AN7_0
Pin function
AN7_0 input
IRQ7-B interrupt input*
• P46/IRQ6-B/AN6_0
Pin function
AN6_0 input
IRQ6-B interrupt input*
• P45/IRQ5-B/AN5_0
Pin function
AN5_0 input
IRQ5-B interrupt input*
• P44/IRQ4-B/AN4_0
Pin function
AN4_0 input
IRQ4-B interrupt input*
• P43/IRQ3-B/AN3_0
Pin function
AN3_0 input
IRQ3-B interrupt input*
• P42/IRQ2-B/AN2_0
Pin function
AN2_0 input
IRQ2-B interrupt input*
• P41/IRQ1-B/AN1_0
Pin function
AN1_0 input
IRQ1-B interrupt input*
• P40/IRQ0-B/AN0_0
Pin function
AN0_0 input
IRQ0-B interrupt input*
Note:
*
IRQn input when the ITSn bit in ITSR is 1. (n = 7 to 0)
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Section 10 I/O Ports
10.5
Port 5
Port 5 is a 4-bit I/O port. Port 5 has the following registers. For the port function control registers,
refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
Port 5 data direction register (P5DDR)
Port 5 data register (P5DR)
Port 5 register (PORT5)
Port 5 open drain control register (P5ODR)
Port function control register 4 (PFCR4)
10.5.1
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be
read; if it is, an undefined value will be read.
Bit
Initial Value
R/W
Description
7 to 4 ⎯
All 0
⎯
Reserved
3
P53DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
0
P50DDR
0
W
10.5.2
Bit Name
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
Page 572 of 1408
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
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H8S/2456, H8S/2456R, H8S/2454 Group
10.5.3
Section 10 I/O Ports
Port 5 Register (PORT5)
PORT5 shows the pin states of port 5. PORT5 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
Undefined
R
Reserved
If these bits are read, they will return an undefined
value.
3
P53
⎯*
R
2
P52
⎯*
R
1
P51
⎯*
R
0
P50
⎯*
R
Note:
*
10.5.4
If the P53 to P50 bits are read while a P5DDR bit is
set to 1, the corresponding P5DR value is read. If
this register is read while a P5DDR bit is cleared to
0, the corresponding pin state is read.
Determined by the states of pins P53 to P50.
Port 5 Open Drain Control Register (P5ODR)
P5ODR specifies the output type of each port 5 pin.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
3
P53ODR
0
R/W
Setting this bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing the bit
to 0 makes the corresponding pin a CMOS output
pin.
2
P52ODR
0
R/W
When BACK-B output is not selected, setting this bit
to 1 makes the corresponding pin an NMOS opendrain output pin, while clearing the bit to 0 makes
the corresponding pin a CMOS output pin.
1
P51ODR
0
R/W
Setting this bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing the bit
to 0 makes the corresponding pin a CMOS output
pin.
0
P50ODR
0
R/W
When BREQO-B output is not selected, setting this
bit to 1 makes the corresponding pin an NMOS
open-drain output pin, while clearing the bit to 0
makes the corresponding pin a CMOS output pin.
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Section 10 I/O Ports
10.5.5
Pin Functions
Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, interrupt inputs, I2C I/Os,
bus control signal I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between
the register specification and the pin functions is shown below.
• P53/IRQ3-A/ADTRG0-A
The pin function is switched as shown below according to the combination of bits TRGS1,
TRGS0, and EXTRGS in ADCR_0 of ADC, bit P53DDR, and bit ITS3 in ITSR of the
interrupt controller.
P53DDR
Pin function
0
1
P53 input
P53 output
ADTRG0-A input*
1
IRQ3-A interrupt input*
2
Notes: 1. ADTRG0-A input when the EXTRGS in ADCR0 is 0, and TRGS1 = TRGS0 = 1.
2. IRQ3-A input when the ITS3 bit in ITSR is 0.
Page 574 of 1408
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Section 10 I/O Ports
• P52/SCK2/IRQ2-A/BACK-B/PO4-B/TIOCA4-B/TMO0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bits OS3 to OS0 in TCSR0 of 8-bit
timer, bits MD3 to MD0 in TMDR_4 of TPU, bits IOA3 to IOA0 in TIOR_4, TPU channel 4
settings by bits CCLR1 and CCLR0 in TCR_4, bit NDER4 in NDERL of PPG, bit C/A in
SMR_2 and bits CKE0 and CKE1 in SCR_2 of SCI, bits PPGS, TPUS, and TMRS in PFCR3,
bit BACKS in PFCR4, bit P52DDR, bit NDER4 in NDERL of PPG, and bit ITS2 in ITSR of
the interrupt controller.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
BRLE
BACKS
BRLE = 0, or BRLE = 1 and BACKS = 0
TPU channel (1) in table
4 settings
below
OS3 to OS0
⎯
CKE1
⎯
C/A
⎯
CKE0
⎯
P52DDR
⎯
NDER4
Pin function
BRLE = 1
and
BACKS = 1
⎯
(2) in table below
Not all 0
⎯
1
⎯
⎯
⎯
⎯
⎯
All 0
0
0
1
0
0
1
1
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
1
⎯
⎯
⎯
⎯
⎯
TIOCA4-B
5
output*
P52
input
P52
output
PO4-B
4
output*
SCK2
output
SCK2
output
SCK2
input
TMO0-B
6
output*
BACK-B
output
1 5
TIOCA4-B input* *
IRQ2-A interrupt input*
2
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Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
⎯
BRLE
BACKS
TPU channel 4
settings
(1) in table
below
(2) in table
below
OS3 to OS0
⎯
CKE1
⎯
C/A
⎯
CKE0
⎯
P52DDR
⎯
0
1
NDER4
⎯
⎯
0
TIOCA4-B
5
output*
P52
input
P52
output
Pin function
All 0
Not all 0
1
⎯
1
⎯
⎯
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
PO4-B
4
output*
SCK2
output
SCK2
output
SCK2
input
TMO0-B
6
output*
0
0
0
TIOCA4-B input*1*5
IRQ2-A interrupt input*2
TPU channel 4
settings
MD3 to MD0
IOBA to IOA0
(2)
(1)
B'0000, B'01xx
(1)
(2)
(1)
(2)
B'0010
B'001x
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
Other than
B'xx00
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
PWM*3
mode 1
output
⎯
PWM mode 2
output
⎯
Notes: 1.
2.
3.
4.
5.
TIOCA4-B input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
IRQ2-A input when the ITS2 bit in ITSR is 0.
TIOCB4-B output disabled.
When using as PO4-B output, set PPGS in PFCR3 to 1 before other register setting.
When using as TIOCA4-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
6. When using as TMO0-B output, set TMRS in PFCR3 to 1 before other register setting.
Page 576 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I 2 C, bits
MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by
bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI,
bit P51DDR, bits PPGS, TPUS, and TMRS in PFCR3, and bit BREQS in PFCR4, and bit ITS1
in ITSR of the interrupt controller.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
BRLE
BREQS
BRLE = 0, or BRLE = 1 and BREQS = 0
ICE
TPU channel 3
settings
(1) in table
below
⎯
P51DDR
⎯
Pin function
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
0
RE
NDER2
BRLE = 1
and
BREQS = 1
(2) in table below
0
0
1
1
⎯
⎯
0
1
⎯
⎯
TIOCC3-B
7
output*
P51 input
P51 output
PO2-B
6
output*
RxD2 input
SCL3* I/O
⎯
5
BREQ-B
input
1 7
TIOCC3-B input* *
IRQ1-A interrupt input*
2
3 8
TMCI0-B input* *
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Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
⎯
BRLE
BREQS
ICE
TPU channel 3
settings
0
(1) in table
below
⎯
(2) in table below
RE
⎯
P51DDR
⎯
0
1
NDER2
⎯
⎯
TIOCC3-B
output*7
P51 input
Pin function
1
1
⎯
1
⎯
⎯
0
1
⎯
⎯
P51 output
PO2-B
output*6
RxD2 input
SCL3 I/O
0
1
7
TIOCC3-B input* *
IRQ1-A interrupt input*2
3
8
TMCI0-B input* *
Page 578 of 1408
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TPU channel 3
settings
(2)
MD3 to MD0
IOC3 to IOC0
Section 10 I/O Ports
(1)
B'0000
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
Other than
B'101
PWM*4 mode PWM mode
1 output
2 output
B'101
⎯
Notes: 1. TIOCC3-B input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. IRQ1-A input when the ITS1 bit in ITSR is 0.
3. When used as the external clock input pin for the TMR, its pin function should be
selected to the external clock input by the CKS2 to CKS0 bits in TCR_0 after the TMRS
bit in PFCR3 is set to 1.
4. TIOCD3-B output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_3.
5. NMOS open-drain output regardless of P51ODR.
6. When using as PO2-B output, set PPGS in PFCR3 to 1 before other register setting.
7. When using as TIOCC3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
8. When using as TMCI0-B input, set TMRS in PFCR3 to 1 before other register setting.
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Section 10 I/O Ports
• P50/TxD2/IRQ0-A/SDA3/BREQO-B/PO0-B/TIOCA3-B/TMRI0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE of the bus controller, bit BREQOE, bit ICE in ICCRA_3 of the
I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3
settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2
of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BREQOS in PFCR4, bit P50DDR,
and bit ITS0 in ITSR of the interrupt controller.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
BRLE
BRLE = 0, or BRLE = 1 and BREQOE = 0,
or BRLE = 1, BREQOE = 1 and BREQOS = 0
BREQOE
BRLE = 1,
BREQOE = 1
and
BREQOS = 1
BREQOS
ICE
TPU channel 3
settings
0
(1) in table
below
(2) in table below
1
⎯
⎯
⎯
TE
⎯
1
⎯
⎯
P50DDR
⎯
0
1
1
⎯
⎯
⎯
NDER0
⎯
⎯
0
1
⎯
⎯
Pin function
TIOCA3-B
7
output*
0
P50 input
P50 output
PO0-B
6
output*
⎯
5
TxD2 output SDA3* I/O
BREQO-B
output
1 7
TIOCA3-B input* *
IRQ0-A interrupt input*
2
3 8
TMRI0-B input* *
Page 580 of 1408
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Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
BRLE
⎯
BREQOE
⎯
BREQOS
⎯
ICE
TPU channel 3
settings
0
(1) in table
below
1
TE
⎯
P50DDR
⎯
0
1
1
NDER0
⎯
⎯
0
1
Pin function
⎯
(2) in table below
0
TIOCA3-B
7
output*
1
⎯
⎯
⎯
⎯
⎯
6
P50 input P50 output PO0-B output* TxD2 output SDA3*5 I/O
TIOCA3-B input*1*7
IRQ0-A interrupt input*2
3
8
TMRI0-B input* *
TPU channel 3
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(2)
(1)
B'001x
B'0010
B'0011
Other than B'xx00
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Output function
⎯
Output compare
output
⎯
(1)
(2)
Other than
B'001
PWM*4 mode PWM mode
1 output
2 output
B'001
⎯
Notes: 1. TIOCA3-B input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. IRQ0-A input when the ITS0 bit in ITSR is 0.
3. When used as the counter reset input pin for the TMR, the external reset should be
selected using the CCLR1 and CCLR0 bits in TCR_0 and TMRIS bit in TCCR_0 after
the TMRS bit in PFCR3 is set to 1.
5. NMOS open-drain output regardless of P50ODR.
6. When using as PO0-B output, set PPGS in PFCR3 to 1 before other register setting.
7. When using as TIOCA3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
8. When using as TMRI0-B input, set TMRS in PFCR3 to 1 before other register setting.
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Section 10 I/O Ports
10.6
Port 6
Note: Port 6 is not supported in the H8S/2454 Group.
Port 6 is a 6-bit I/O port that also has other functions. Port 6 has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
Port 6 data direction register (P6DDR)
Port 6 data register (P6DR)
Port 6 register (PORT6)
Port 6 open drain control register (P6ODR)
Port function control register 3 (PFCR3)
10.6.1
Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6. P6DDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
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10.6.2
Section 10 I/O Ports
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
P65DR
0
R/W
4
P64DR
0
R/W
3
P63DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
10.6.3
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
Port 6 Register (PORT6)
PORT6 shows the pin states of port 6. PORT6 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
Undefined
⎯
Reserved
If these bits are read, they will return an undefined
value.
5
P65
⎯*
R
4
P64
⎯*
R
3
P63
⎯*
R
2
P62
⎯*
R
1
P61
⎯*
R
0
P60
⎯*
R
Note:
*
If this register is read while a P6DDR bit is set to 1,
the corresponding P6DR value is read. If this
register is read while a P6DDR bit is cleared to 0,
the corresponding pin state is read.
Determined by the states of pins P65 to P60.
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Section 10 I/O Ports
10.6.4
Port 6 Open Drain Control Register (P6ODR)
P6ODR specifies the output type of each port 6 pin.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
5
P65ODR
0
R/W
4
P64ODR
0
R/W
3
P63ODR
0
R/W
2
P62ODR
0
R/W
1
P61ODR
0
R/W
0
P60ODR
0
R/W
10.6.5
Setting a P6ODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a P6ODR bit to 0 makes the corresponding pin a
CMOS output pin.
Pin Functions
Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The
correspondence between the register specification and the pin functions is shown below.
• P65/IRQ13-A/DACK1/TMO1-A
The pin function is switched as shown below according to the combination of bit SAE1 in
DMABCRH of DMAC, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit TMRS in PFCR3,
bit P65DDR, and bit ITS13 in ITSR of the interrupt controller.
SAE1
0
OS3 to OS0
P65DDR
Pin function
All 0
0
P65 input
1
⎯
Not all 0
1
P65 output
⎯
⎯
DACK1 output
2
TMO1-A output*
IRQ13-A interrupt input*
1
Notes: 1. IRQ13-A input when the ITS13 bit in ITSR is 0.
2. When using as TMO1-A output, set TMRS in PFCR3 to 0 before other register setting.
Page 584 of 1408
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Section 10 I/O Ports
• P64/IRQ12-A/DACK0/TMO0-A
The pin function is switched as shown below according to the combination of bit SAE0 in
DMABCRH of DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit TMRS in PFCR3,
bit P64DDR, and bit ITS12 in ITSR of the interrupt controller.
SAE0
0
OS3 to OS0
All 0
P64DDR
Pin function
1
0
⎯
1
P64 input
⎯
Not all 0
P64 output
TMO0-A output*
⎯
DACK0 output
2
IRQ12-A interrupt input*
1
Notes: 1. IRQ12-A input when the ITS12 bit in ITSR is 0.
2. When using as TMO0-A output, set TMRS in PFCR3 to 0 before other register setting.
• P63/IRQ11-A/TEND1/TMCI1-A
The pin function is switched as shown below according to the combination of bit TEE1 in
DMATCR of DMAC, bit TMRS in PFCR3, bit P63DDR, and bit ITS11 in ITSR of the
interrupt controller.
TEE1
P63DDR
Pin function
0
1
0
1
P63 input
P63 output
⎯
TEND1 output
IRQ11-A interrupt input*
2
1
3
TMCI1-A input* *
Notes: 1. IRQ11-A input when the ITS11 bit in ITSR is 0.
2. When used as the external clock input pin for the TMR, the external clock should be
selected using the CKS2 to CKS0 bits in TCR_1 after the TMRS bit in PFCR3 is set to
0.
3. When using as TMCI1-A input, set TMRS in PFCR3 to 0 before other register setting.
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Section 10 I/O Ports
• P62/IRQ10-A/TEND0/TMCI0-A
The pin function is switched as shown below according to the combination of bit TEE0 in
DMATCR of DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the
interrupt controller.
TEE0
P62DDR
Pin function
0
1
0
1
P62 input
P62 output
⎯
TEND0 output
IRQ10-A interrupt input*
2
1
3
TMCI0-A input* *
Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0.
2. When used as the external clock input pin for the TMR, the external clock should be
selected using the CKS2 to CKS0 bits in TCR_0 after the TMRS bit in PFCR3 is set to
0.
3. When using as TMCI0-A input, set TMRS in PFCR3 to 0 before other register setting.
• P61/IRQ9-A/DREQ1/TMRI1-A
The pin function is switched as shown below according to the combination of bits TMRS and
USBDRQE in PFCR3, bit P61DDR, and bit ITS9 in ITSR of the interrupt controller.
P61DDR
Pin function
0
1
P61 input
P61 output
TMRI1-A input*1*3
DREQ1 input*4
IRQ9-A interrupt input*
2
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_1 should be set to 1 after the TMRS bit in PFCR3 is set to 0.
2. IRQ9-A input when the ITS9 bit in ITSR is 0.
3. When using as TMRI1-A input, set TMRS in PFCR3 to 0 before other register setting.
4. When using as DREQ1 input, set USBDRQE in PFCR3 to 0 before other register
setting.
Page 586 of 1408
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Section 10 I/O Ports
• P60/IRQ8-A/DREQ0/TMRI0-A
The pin function is switched as shown below according to the combination of bits TMRS and
USBDRQE in PFCR3, bit P60DDR, and bit ITS8 in ITSR of the interrupt controller.
P60DDR
Pin function
0
1
P60 input
P60 output
1
3.
TMRI0-A input* *
DREQ0 input*4
IRQ8-A interrupt input*
2
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_0 should be set to 1 after the TMRS bit in PFCR3 is set to 0.
2. IRQ8-A input when the ITS8 bit in ITSR is 0.
3. When using as TMRI0-A input, set TMRS in PFCR3 to 0 before other register setting.
4. When using as DREQ0 input, set USBDRQE in PFCR3 to 0 before other register
setting. When USBDRQE is 1, use of the DREQ0 signal from the DREQ0 input pin is
not allowed.
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Section 10 I/O Ports
10.7
Port 8
Port 8 is a 6-bit I/O port that also has other functions. Port 8 has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
Port 8 data direction register (P8DDR)
Port 8 data register (P8DR)
Port 8 register (PORT8)
Port 8 open drain control register (P8ODR)
Port function control register 3 (PFCR3)
10.7.1
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
7, 6
⎯
All 0
⎯
Reserved
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
Page 588 of 1408
Initial Value
R/W
Description
Bits 4, 2, and 0 are reserved in the H8S/2454
Group.
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10.7.2
Section 10 I/O Ports
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
5
P85DR
0
R/W
4
P84DR
0
R/W
3
P83DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
0
P80DR
0
R/W
10.7.3
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
Bits 4, 2, and 0 are reserved in the H8S/2454
Group.
Port 8 Register (PORT8)
PORT8 shows the pin states of port 8. PORT8 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
Undefined
⎯
Reserved
If these bits are read, they will return an undefined
value.
5
P85
⎯*
R
4
P84
⎯*
R
3
P83
⎯*
R
2
P82
⎯*
R
1
P81
⎯*
R
0
P80
⎯*
R
Note:
*
If this register is read while a P8DDR bit is set to 1,
the corresponding P8DR value is read. If this
register is read while a P8DDR bit is cleared to 0,
the corresponding pin state is read.
Bits 4, 2, and 0 are reserved in the H8S/2454
Group.
Determined by the states of pins P85 to P80.
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Section 10 I/O Ports
10.7.4
Port 8 Open Drain Control Register (P8ODR)
P8ODR specifies the output type of each port 8 pin.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
⎯
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
5
P85ODR
0
R/W
4
P84ODR
0
R/W
3
P83ODR
0
R/W
2
P82ODR
0
R/W
1
P81ODR
0
R/W
0
P80ODR
0
R/W
10.7.5
Setting a P8ODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a P8ODR bit to 0 makes the corresponding pin a
CMOS output pin.
Bits 4, 2, and 0 are reserved in the H8S/2454
Group.
Pin Functions
Port 8 pins also function as SCI I/Os, interrupt inputs, EXDMAC I/Os, PPG outputs, TPU I/Os,
and 8-bit timer I/Os. The correspondence between the register specification and the pin functions
is shown below.
(1)
Pin Functions of H8S/2456 Group and H8S/2456R Group
• P85/EDACK3/IRQ5-B/SCK3/PO5-B/TIOCB4-B/TMO1-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to
IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the
8-bit timer, bit NDER5 in NDERL of PPG, bit AMS in EDMDR_3 of EXDMAC, bit C/A in
SMR_3 and bits CKE0 and CKE1 in SCR_3 of SCI, bits PPGS, TPUS, and TMRS in PFCR3,
bit P85DDR, and bit ITS5 in ITSR of the interrupt controller.
Page 590 of 1408
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• Modes 1, 2, and 4
Section 10 I/O Ports
Modes 3 and 7 (EXPE = 1)
TPU channel
4 settings
(1) in table
below
OS3 to OS0
⎯
AMS
⎯
CKE1
⎯
C/A
⎯
CKE0
⎯
P85DDR
⎯
0
1
NDER5
⎯
⎯
Pin function
(2) in table below
All 0
Not all 0
0
1
1
⎯
⎯
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
0
1
⎯
⎯
⎯
⎯
⎯
P85
output
PO5-B
3
output*
SCK3
output
SCK3
output
SCK3
input
0
0
0
TIOCB4-B P85 input
4
output*
⎯
EDACK3 TMO1-B
5
output output*
2 4
TIOCB4-B input* *
IRQ5-B interrupt input*
1
• Modes 3 and 7 (EXPE = 0)
TPU channel
4 settings
(1) in table
below
OS3 to OS0
⎯
All 0
Not all 0
AMS
⎯
⎯
⎯
CKE1
⎯
C/A
⎯
CKE0
⎯
P85DDR
⎯
0
1
NDER5
⎯
⎯
TIOCB4-B
4
output*
P85
input
Pin function
(2) in table below
1
⎯
1
⎯
⎯
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
0
1
⎯
⎯
⎯
⎯
P85
output
PO5-B
3
output*
SCK3
output
SCK3
output
SCK3
input
TMO1-B
5
output*
0
0
0
2 4
TIOCB4-B input* *
IRQ5-B interrupt input*
1
IRQ5-B input when the ITS5 bit in ITSR is 1.
TIOCB4-B input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
When using as PO5-B output, set PPGS in PFCR3 to 1 before other register setting.
When using as TIOCB4-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
5. When using as TMO1-B output, set TMRS in PFCR3 to 1 before other register setting.
Notes: 1.
2.
3.
4.
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Section 10 I/O Ports
TPU channel 4
settings
MD3 to MD0
(2)
(1)
(2)
B'0000, B'01xx
(2)
(1)
B'0010
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
• P84/IRQ4-B/EDACK2
The pin function is switched as shown below according to the combination of bit AMS in
EDMDR_2 of EXDMAC, bit P84DDR, and bit ITS4 in ITSR of the interrupt controller.
Operating mode
1, 2, 4
AMS
3, 7 (EXPE = 1)
0
P84DDR
Pin function
3, 7 (EXPE = 0)
⎯
1
0
1
⎯
0
1
P84 input
P84 output
EDACK2
output
P84 input
P84 output
IRQ4-B interrupt input*
Note:
*
IRQ4-B input when the ITS4 bit in ITSR is 1.
Page 592 of 1408
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Section 10 I/O Ports
• P83/ETEND3/IRQ3-B/RxD3/PO3-B/TIOCD3-B/TMCI1-B
The pin function is switched as shown below according to the combination of bit ETENDE in
EDMDR_3 of EXDMAC, bit RE in SCR_3 of SCI, TPU channel 3 settings (by bits MD3 to
MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit
NDER3 in NDERL of PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P83DDR, and bit
ITS3 in ITSR of the interrupt controller.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
TPU channel 3
settings
(1) in table
below
(2) in table below
ETENDE
⎯
RE
⎯
P83DDR
⎯
0
1
NDER3
⎯
⎯
TIOCD3-B
output*5
P83 input
Pin function
0
1
1
⎯
1
⎯
⎯
0
1
⎯
⎯
P83 output
PO3-B
output*4
RxD3 input
ETEND3
output
0
2
5
TIOCD3-B input* *
IRQ3-B interrupt input*1
3
6
TMCI1-B input* *
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Section 10 I/O Ports
•
Modes 3 and 7 (EXPE = 0)
TPU channel 3
settings
(1) in table
below
(2) in table below
ETENDE
⎯
RE
⎯
P83DDR
⎯
0
NDER3
⎯
⎯
TIOCD3-B
output*5
P83 input
Pin function
0
1
1
⎯
0
1
⎯
P83 output
PO3-B output*4
0
⎯
1
2
RxD3 input
5
TIOCD3-B input* *
IRQ3-B interrupt input*1
3
6
TMCI1-B input* *
Notes: 1. IRQ3-B input when the ITS3 bit in ITSR is 1.
2. TIOCD3-B input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
3. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_1 after the TMRS
bit in PFCR3 is set to 1.
4. When using as PO3-B output, set PPGS in PFCR3 to 1 before other register setting.
5. When using as TIOCD3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
6. When using as TMCI1-B input, set TMRS in PFCR3 to 1 before other register setting.
TPU channel 3
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Other than B'xx00
[Legend]
x:
Don't care
Page 594 of 1408
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Section 10 I/O Ports
• P82/IRQ2-B/ETEND2
The pin function is switched as shown below according to the combination of bit ETENDE in
EDMDR_2 of EXDMAC, bit P82DDR, and bit ITS2 in ITSR of the interrupt controller.
Operating mode
1, 2, 4
ETENDE
3, 7 (EXPE = 1)
0
⎯
1
0
1
⎯
0
1
P82 input
P82 output
ETEND2 output
P82 input
P82 output
P82DDR
Pin function
3, 7 (EXPE = 0)
IRQ2-B interrupt input*
Note:
*
IRQ2-B input when the ITS2 bit in ITSR is 1.
• P81/EDREQ3/IRQ1-B/TxD3/PO1-B/TIOCB3-B/TMRI1-B
The pin function is switched as shown below according to the combination of bit TE in SCR_3
of SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in
TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of PPG, bits PPGS,
TPUS, and TMRS in PFCR3, bit P81DDR, and bit ITS1 in ITSR of the interrupt controller.
TPU channel 3
settings
(1) in table
below
(2) in table below
TE
⎯
P81DDR
⎯
0
1
1
NDER1
⎯
⎯
0
1
Pin function
TIOCB3-B
output*5
0
P81 input
1
P81 output
⎯
⎯
PO1-B output*
2
4
TxD3 output
5
TIOCB3-B input* *
EDREQ3 input
IRQ1-B interrupt input*1
3
6
TMRI1-B input* *
Notes: 1. IRQ1-B input when the ITS1 bit in ITSR is 1.
2. TIOCB3-B input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
3. When used as the counter reset input pin for the TMR, the external reset should be
selected using the CCLR1 and CCLR0 bits in TCR_1 and TMRIS bit in TCCR_1 after
the TMRS bit in PFCR3 is set to 1.
4. When using as PO1-B output, set PPGS in PFCR3 to 1 before other register setting.
5. When using as TIOCB3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
6. When using as TMRI1-B input, set TMRS in PFCR3 to 1 before other register setting.
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Section 10 I/O Ports
TPU channel 3
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
• P80/IRQ0-B/EDREQ2
The pin function is switched as shown below according to the combination of bit P80DDR and
bit ITS0 in ITSR of the interrupt controller.
P80DDR
Pin function
0
1
P80 input
P80 output
EDREQ2 input
IRQ0-B interrupt input*
Note:
*
IRQ0-B input when the ITS0 bit in ITSR is 1.
Page 596 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
(2)
Section 10 I/O Ports
Pin Functions of H8S/2454 Group
• P85/SCK3/PO5-B/TIOCB4-B/TMO1-B
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1
and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL
of PPG, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of SCI, bits PPGS, TPUS, and
TMRS in PFCR3, and bit P85DDR.
TPU channel
4 settings
(1) in table
below
OS3 to OS0
⎯
CKE1
⎯
C/A
⎯
CKE0
⎯
P85DDR
⎯
0
1
NDER5
⎯
⎯
TIOCB4-B
3
output*
P85
input
Pin function
(2) in table below
All 0
Not all 0
1
⎯
1
⎯
⎯
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
0
1
⎯
⎯
⎯
⎯
P85 output
PO5-B
2
output*
SCK3
output
SCK3
output
SCK3
input
TMO1-B
4
output*
0
0
0
1 3
TIOCB4-B input* *
Notes: 1. TIOCB4-B input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. When using as PO5-B output, set PPGS in PFCR3 to 1 before other register setting.
3. When using as TIOCB4-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
4. When using as TMO1-B output, set TMRS in PFCR3 to 1 before other register setting.
TPU channel 4
settings
(2)
MD3 to MD0
(1)
B'0000, B'01xx
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output compare
output
⎯
⎯
PWM mode 2
output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
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Section 10 I/O Ports
• P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of PPG, bit RE in SCR_3 of SCI, bits
PPGS, TPUS, and TMRS in PFCR3, and bit P83DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
RE
⎯
P83DDR
⎯
0
NDER3
⎯
⎯
Pin function
0
TIOCD3-B
output*4
1
⎯
1
0
P83 input
⎯
1
P83 output
PO3-B output*
1
3
RxD3 input
4
TIOCD3-B input* *
2
5
TMCI1-B input* *
Notes: 1. TIOCB4-B input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_1 after the TMRS
bit in PFCR3 is set to 1 after the TMRS bit in PFCR3 is set to 1.
3. When using as PO3-B output, set PPGS in PFCR3 to 1 before other register setting.
4. When using as TIOCD3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
5. When using as TMCI1-B input, set TMRS in PFCR3 to 1 before other register setting.
TPU channel 3
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Other than B'xx00
[Legend]
x:
Don't care
Page 598 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of PPG, bit TE in SCR_3 of SCI, bits
PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
TE
⎯
P81DDR
⎯
0
NDER1
⎯
⎯
Pin function
0
TIOCB3-B
output*4
1
⎯
1
0
P81 input
⎯
1
P81 output
PO1-B output*
1
3
TxD3 output
4
TIOCB3-B input* *
2
5
TMRI1-B input* *
Notes: 1. TIOCB3-B input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
2. When used as the counter reset input pin for the TMR, the external reset should be
selected using the CCLR1 and CCLR0 bits in TCR_1 and TMRIS bit in TCCR_1 after
the TMRS bit in PFCR3 is set to 1.
3. When using as PO1-B output, set PPGS in PFCR3 to 1 before other register setting.
4. When using as TIOCB3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
5. When using as TMRI1-B input, set TMRS in PFCR3 to 1 before other register setting.
TPU channel 3
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
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Section 10 I/O Ports
10.8
Port 9
Port 9 is an 8-bit input-only port that also has other functions. Port 9 has the following register.
• Port 9 register (PORT9)
10.8.1
Port 9 Register (PORT9)
PORT9 is an 8-bit read-only register that shows the pin states of port 9. PORT9 cannot be
modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P97
⎯*
R
6
P96
⎯*
R
5
P95
⎯*
The pin states are always read from this register.
Bits 7, 6, and 3 to0 are reserved in the H8S/2454
Group.
R
4
P99
⎯*
R
3
P93
⎯*
R
2
P92
⎯*
R
1
P91
⎯*
R
0
P90
⎯*
R
Note:
*
Determined by the states of pins P97 to P90.
Page 600 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
10.8.2
Section 10 I/O Ports
Pin Functions
Port 9 also functions as the pins for A/D converter analog inputs and D/A converter analog
outputs. The correspondence between pins is as follows.
(1)
Pin Functions of H8S/2456 Group and H8S/2456R Group
• P97/AN15_1
Pin function
AN15_1 input
• P96/AN14_1
Pin function
AN14_1 input
• P95/AN13_1/DA3
Pin function
AN13_1 input
DA3 output
• P94/AN12_1/DA2
Pin function
AN12_1 input
DA2 output
• P93/AN11_1
Pin function
AN11_1 input
• P92/AN10_1
Pin function
AN10_1 input
• P91/AN9_1
Pin function
AN9_1 input
• P90/AN8_1
Pin function
R01UH0309EJ0500 Rev. 5.00
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AN8_1 input
Page 601 of 1408
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Section 10 I/O Ports
(2)
Pin Functions of H8S/2454 Group
• P95/AN13_1/DA3
Pin function
AN13_1 input
DA3 output
• P94/AN12_1/DA2
Pin function
AN12_1 input
DA2 output
Page 602 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
10.9
Section 10 I/O Ports
Port A
Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
•
•
•
•
Port A data direction register (PADDR)
Port A data register (PADR)
Port A register (PORTA)
Port A pull-up MOS control register (PAPCR)
Port A open-drain control register (PAODR)
Port function control register 0 (PFCR0)(the H8S/2454 Group)
Port function control register 1 (PFCR1)
Port function control register 4 (PFCR4)
Port function control register 5 (PFCR5)
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Section 10 I/O Ports
10.9.1
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial
Value
R/W Description
7
PA7DDR
0
W
6
PA6DDR
0
W
Pins PA4 to PA0 are address outputs.
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
For pins PA6 and PA5, when the corresponding bit of A22E
and A21E is set to 1, setting a PADDR bit to 1 makes the
corresponding pin an address output, while clearing the bit to
0 makes the corresponding pin an input port. Clearing one of
bits A22E and A21E to 0 makes the corresponding pin an I/O
port, and its function can be switched with PADDR.
0
PA0DDR
0
W
•
Modes 1 and 2
When A23E is 1, the PA7 pin functions as an address output
pin when the PA7DDR bit is set to 1, and as an input port
when the bit is cleared to 0.
When A23E is 0, operations differ between the H8S/2456
and H8S/2456R Groups and H8S/2454 Group.
[H8S/2456 Group and H8S/2456R Group]
When the PA7 pin is a general I/O port, the function can be
switched with PA7DDR.
[H8S/2454 Group]
When the CS output enable bit (CS7E) is 1, the PA7 pin
functions as a CS output pin when the PA7DDR bit is set to
1, and as an input port when the bit is cleared to 0. When the
CS output enable bit (CS7E) is 0 and the PA7 pin is a
general I/O port, the function can be switched with PA7DDR.
Page 604 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial
Value
Section 10 I/O Ports
R/W Description
•
Mode 4, Modes 3 and 7 (EXPE = 1)
For pins PA6 to PA0, when the corresponding bit of A22E to
A16E is set to 1, setting a PADDR bit to 1 makes the
corresponding pin an address output, while clearing the bit to
0 makes the corresponding pin an input port. Clearing one of
bits A22E to A16E to 0 makes the corresponding pin an I/O
port, and its function can be switched with PADDR.
When A23E is 1, the PA7 pin functions as an address output
pin when the PA7DDR bit is set to 1, and as an input port
when the bit is cleared to 0.
When A23E is 0, operations differ between the H8S/2456
and H8S/2456R Groups and H8S/2454 Group.
[H8S/2456 Group and H8S/2456R Group]
When the PA7 pin is a general I/O port, the function can be
switched with PA7DDR.
[H8S/2454 Group]
When the CS output enable bit (CS7E) is 1, the PA7 pin
functions as a CS output pin when the PA7DDR bit is set to
1, and as an input port when the bit is cleared to 0. When the
CS output enable bit (CS7E) is 0 and the PA7 pin is a
general I/O port, the function can be switched with PA7DDR.
•
Modes 3 and 7 (EXPE = 0)
Port A is an I/O port, and its pin functions can be switched
with PADDR.
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Section 10 I/O Ports
10.9.2
Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DR
0
R/W
6
PA6DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
10.9.3
Port A Register (PORTA)
PORTA shows the pin states of port A. PORTA cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7
⎯*
R
6
PA6
⎯*
R
5
PA5
⎯*
R
If this register is read while a PADDR bit is set to 1,
the corresponding PADR value is read. If this
register is read while a PADDR bit is cleared to 0,
the corresponding pin state is read.
4
PA4
⎯*
R
3
PA3
⎯*
R
2
PA2
⎯*
R
1
PA1
⎯*
R
0
PA0
⎯*
R
Note:
*
Determined by the states of pins PA7 to PA0.
Page 606 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
10.9.4
Section 10 I/O Ports
Port A Pull-Up MOS Control Register (PAPCR)
PAPCR controls on/off of the input pull-up MOS for port A. Bits 7 to 5 are valid in modes 1 and 2
and all the bits are valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
When in a input port state, setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PA5PCR
0
R/W
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
10.9.5
These bits should not be set to 1 when the SCI is
used.
Port A Open Drain Control Register (PAODR)
PAODR specifies the output type of each port A pin.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
When not specified for address output or CS7
output*, setting a PAODR bit to 1 makes the
corresponding pin an NMOS open-drain output pin,
while clearing a PAODR bit to 0 makes the
corresponding pin a CMOS output pin.
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
Note: * Not supported in the H8S/2456 and H8S/2456R Groups.
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Section 10 I/O Ports
10.9.6
Pin Functions
Port A pins also function as the pins for address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and
bus control signal outputs. The correspondence between the register specification and the pin
functions is shown below.
• PA7/A23/CS7*6/IRQ7-A/SSO0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of SSU, bits SSO0S1 and SSO0S0 in PFCR5, bit CS7E in PFCR0 (the H8S/2454
Group), bit A23E in PFCR1, bit PA7DDR, and bit ITS7 in ITSR of the interrupt controller.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
A23E
0
6
CS7E*
SSU settings
PA7DDR
1
0
(1) in table below
0
Pin function PA7 input
1
PA7
output
(2) in
table
below
(3) in
table
below
0*4
⎯
1
⎯
⎯
⎯
0
1
0
SSO0-B SSO0-B PA7 input
CS7
PA7 input
input*2*5 output*3*5
output*6
1
A23
output
IRQ7-A interrupt input*
1
Page 608 of 1408
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Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
⎯
A23E
6
CS7E*
0
SSU settings
(1) in table below
PA7DDR
0
Pin function
(2) in table below
1
PA7 input
0*
⎯
2
PA7 output
(3) in table below
4
5
SSO0-B output*3*5
SSO0-B input* *
IRQ7-A interrupt input*
1
Notes: 1. IRQ7-A input when the ITS7 bit in ITSR is 0.
2. When using as SSO0-B input, set SSO0S1 and SSO0S0 in PFCR5 to B'01 before other
register setting.
3. When using as SSO0-B output, set SSO0S1 and SSO0S0 in PFCR5 to B'01 before
other register setting.
4. PA7DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSOS01 and SSO0S0 = B'01 in PFCR5.
Use as I/O port.
6. Not supported in the H8S/2456 and H8S/2456R Groups.
SSU
(1)
(2)
(1)
(2)
(1)
(3)
(3)
(2)
(3)
(2)
(3)
(1)
(3)
(3)
(1)
(3)
(3)
settings
SSUMS
0
0
BIDE
0
1*2
MSS
0
TE
1
0
RE
0
Pin state
⎯
1
1
0
SSO
⎯
input
0
1
1
SSO
⎯
input
1*1
0
0
1
0
1
SSO
SSO
output output
1
0
0
1
0
1
0
1
0
1
0
1
⎯
SSO
SSO
SSO
SSO
input
output
input
output
1
1
0
0
1
1
SSO
SSO
⎯
output output
1
0
1
SSO
SSO
output
output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
R01UH0309EJ0500 Rev. 5.00
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Section 10 I/O Ports
• PA6/A22/IRQ6-A/SSI0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of SSU, bit A22E in PFCR1, bits SSO0S1 and SSO0S0 in PFCR5, bit PA6DDR, and
bit ITS6 in ITSR of the interrupt controller.
• Modes 1, 2, and 4
⎯
A22E
SSU settings
(1) in table below
(3) in table
below
⎯
0
1
0*4
⎯
0
1
PA6 input
PA6 output
SSI0-B
input*2*5
SSI0-B
output*3*5
PA6 input
A22 output
PA6DDR
Pin function
(2) in table
below
IRQ6-A interrupt input*
1
• Modes 3 and 7
EXPE
1
A22E
0
SSU settings (1) in table below
PA6DDR
Pin function
0
0
1
PA6
input
PA6
output
⎯
1
(2) in
table
below
0*
4
⎯
(3) in
table
below
⎯
SSI0-B SSI0-B
output
input
2 5
3 5
**
**
(1) in table below
0
1
0
1
PA6
input
A22
output
PA6
input
PA6
output
IRQ6-A interrupt input*
(2) in
table
below
0*
4
(3) in
table
below
⎯
SSI0-B SSI0-B
input
output
2 5
3 5
**
**
1
Notes: 1. IRQ6-A input when the ITS6 bit in ITSR is 0.
2. When using as SSI0-B input, set SSI0S1 and SSI0S0 in PFCR5 to B'01 before other
register setting.
3. When using as SSI0-B output, set SSI0S1 and SSI0S0 in PFCR5 to B'01 before other
register setting.
4. PA6DDR =0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'01 in PFCR5.
Use as I/O port.
Page 610 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
SSU
(1)
(1)
(3)
(3)
(2)
Section 10 I/O Ports
(1)
(2)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(2)
(1)
(2)
settings
1
SSUMS
0
0
BIDE
0
1*
MSS
2
0
TE
1
0
1
1*
0
0
0
1
0
1
1
0
0
1
0
1
1
0
1
RE
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
Pin state
⎯
⎯
SSI
SSI
SSI
⎯
SSI
⎯
⎯
⎯
⎯
SSI
⎯
SSI
SSI
⎯
SSI
input
input
output output
input
input
input
input
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
• PA5/A21/IRQ5-A/SSCK0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of SSU, bit A21E
in PFCR1, bits SSCK0S1 and SSCK0S0 in PFCR5, bit PA5DDR, and bit ITS5 in ITSR of the
interrupt controller
• Modes 1, 2, and 4
A21E
SSU settings
PA5DDR
Pin function
0
(1) in table below
1
(2) in table
below
(3) in table
below
⎯
0
1
0*4
⎯
0
1
PA5 input
PA5 output
SSCK0-B
input*2*5
SSCK0-B
output*3*5
PA5 input
A21 output
IRQ5-A interrupt input*1
R01UH0309EJ0500 Rev. 5.00
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Section 10 I/O Ports
• Modes 3 and 7
EXPE
1
A21E
0
0
SSU settings
PA5DDR
Pin function
(1) in table
below
0
⎯
1
(2) in
table
below
(3) in
table
below
⎯
⎯
0*4
⎯
0
1
1
(1) in table
below
0
1
(2) in
table
below
(3) in
table
below
0*4
⎯
PA5 PA5 SSCK0-B SSCK0-B
PA5 SSCK0-B SSCK0-B PA5 A21
output input output input output input
output
output
input
2 5
*3*5
*2*5
*3*5
**
PA5
input
IRQ5-A interrupt input*
1
Notes: 1. IRQ5-A input when the ITS5 bit in ITSR is 0.
2. When using as SSCK0-B input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'01 before
other register setting.
3. When using as SSCK0-B output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'01 before
other register setting.
4. PA5DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'01 in PFCR5.
Use as I/O port.
SSU settings
(1)
(2)
SSUMS
(1)
(3)
(1)
(2)
(1)
0
MSS
(3)
1
0
1
0
1
SCKS
0
1
0
1
0
1
0
1
Pin state
⎯
SSCK
input
⎯
SSCK
output
⎯
SSCK
input
⎯
SSCK
output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note:
See tables 20.4 to 20.6.
Page 612 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PA4/A20/IRQ4-A/SCS0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bit
A20E in PFCR1, bit PA4DDR, and bit ITS4 in ITSR of the interrupt controller.
Operating
mode
1, 2
4
EXPE
⎯
⎯
A20E
⎯
SSU settings
⎯
(1) in table
below
PA4DDR
⎯
0
A20 output
PA4
input
Pin function
0
1
⎯
(2) in
table
below
(4) in
table
below
(3) in
table
below
1
0*5
0*5
⎯
0
1
PA4
output
SCS0-B
input*2*6
SCS0-B
I/O*4*6
SCS0-B
output*3*6
PA4
input
A20
output
IRQ4-A interrupt input*
1
Operating mode
3, 7
EXPE
0
A20E
⎯
SSU settings
PA4DDR
Pin function
1
0
1
(1) in table
(2) in
(4) in
(3) in
(1) in table
(2) in
(4) in
(3) in
below
table
table
table
below
table
table
table
below
below
below
below
below
below
0*5
0*5
⎯
0*5
0*5
⎯
0
1
PA4
PA4
input
output
SCS0-B SCS0-B SCS0-B
input*2*6 I/O*4*6
0
PA4
output*3*6 input
1
PA4
SCS0-B SCS0-B SCS0-B
output input*2*6
⎯
0
1
PA4
A20
I/O*4*6 output*3*6 input output
IRQ4-A interrupt input*1
Notes: 1. IRQ4-A input when the ITS4 bit in ITSR is 0.
2. When using as SCS0-B input, set SCS0S1 and SCS0S0 in PFCR5 to B'01 before other
register setting.
3. When using as SCS0-B output, set SCS0S1 and SCS0S0 in PFCR5 to B'01 before
other register setting.
4. When using as SCS0-B input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'01
before other register setting.
5. PA4DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SCS0S1and SCS0S0 = B'01 in PFCR5.
Use as I/O port.
R01UH0309EJ0500 Rev. 5.00
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Section 10 I/O Ports
SSU settings
(2)
(1)
(2)
SSUMS
(4)
(3)
(1)
0
1
MSS
0
CSS1
x
CSS0
x
0
1
0
1
x
SCS input
⎯
SCS input
Automatic
SCS I/O
SCS output
⎯
Pin state
1
x
0
1
x
[Legend]
x:
Don't care
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note:
See tables 20.4 to 20.6.
• PA3/A19/SCK4-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit C/A in SMR_4 and bits CKE0 and CKE1 in SCR_4 of SCI, bit A19E in
PFCR1, bit SCK4S in PFCR4, and bit PA3DDR.
Operating
mode
1, 2
4
EXPE
⎯
⎯
A19E
⎯
CKE1
⎯
C/A
⎯
CKE0
⎯
PA3DDR
⎯
0
A19
output
PA3
input
Pin function
Page 614 of 1408
0
1
1
⎯
1
⎯
⎯
1
⎯
⎯
⎯
1
⎯
⎯
⎯
0
1
PA3
output
SCK4-B
output*
SCK4-B
output*
SCK4-B
input*
PA3
input
A19
output
0
0
0
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Operating
mode
3, 7
EXPE
0
A19E
⎯
CKE1
0
0
C/A
1
⎯
1
⎯
⎯
⎯
⎯
⎯
0
PA3DDR
Pin
function
0
1
1
0
1
0
CKE0
Note:
1
0
0
0
1
1
1
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
0
1
PA3 PA3 SCK4-B SCK4-B SCK4-B PA3 PA3 SCK4-B SCK4-B SCK4-B PA3 A19
input output output* output* input* input output output* output* input* input output
*
When using as SCK4-B input/output, set SCK4S in PFCR4 to 1 before other register
setting.
• PA2/A18/RxD4-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit RE in SCR_4 of SCI, bit A18E in PFCR1, bit RXD4S in PFCR4, and bit
PA2DDR.
Operating
1, 2
4
EXPE
⎯
⎯
A18E
⎯
RE
⎯
PA2DDR
⎯
3, 7
mode
Pin function
Note:
*
0
0
0
0
⎯
1
⎯
1
1
⎯
0
1
0
1
0
0
1
1
A18
PA2
PA2
RxD4-B
PA2
A18
PA2
PA2
output
input
output
input*
input
output
input
output
⎯
0
0
RxD4-B PA2
input*
1
⎯
1
1
PA2
input output
⎯
0
RxD4-B PA2
input*
1
A18
input output
When using as RxD4-B input, set RXD4S in PFCR4 to 1 before other register setting.
R01UH0309EJ0500 Rev. 5.00
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Page 615 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PA1/A17/TxD4-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit TE in SCR_4 of SCI, bit A17E in PFCR1, bit TXD4S in PFCR4, and bit
PA1DDR.
Operating
1, 2
4
EXPE
⎯
⎯
A17E
⎯
TE
⎯
PA1DDR
⎯
3, 7
mode
Pin function
Note:
*
0
0
0
A17
PA1
output
input
⎯
1
0
⎯
1
0
0
1
⎯
PA1
TxD4-B
PA1
A17
PA1
output output*
input
output
input
0
1
1
1
0
⎯
1
PA1
1
0
0
⎯
1
TxD4-B PA1
⎯
1
PA1
0
1
TxD4-B PA1
A17
output output* input output output* input output
When using as TxD4-B output, set TXD4S in PFCR4 to 1 before other register setting.
• PA0/A16
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit A16E in PFCR1, and bit PA0DDR.
Operating mode
1, 2
4
EXPE
⎯
⎯
A16E
⎯
PA0DDR
⎯
Pin function
Page 616 of 1408
3, 7
0
0
0
⎯
1
1
0
1
1
0
0
1
0
1
1
0
1
A16
PA0
PA0
PA0
A16
PA0
PA0
PA0
PA0
PA0
A16
output
input
output
input
output
input
output
input
output
input
output
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.9.7
Section 10 I/O Ports
Port A Input Pull-Up MOS States
Port A has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used by pins PA7 to PA5 in modes 1 and 2, and by all pins in modes
3, 4, and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis.
Table 10.3 summarizes the input pull-up MOS states. The input pull-up MOS should not be turned
on when the SCI is used.
Table 10.3 Input Pull-Up MOS States for Port A
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
3, 4 or 7
PA7 to PA0
1 or 2
PA7 to PA5
On/Off
On/Off
PA4 to PA0
Off
Off
[Legend]
Off:
Input pull-up MOS is always off.
On/Off: Input pull-up MOS is on when in input port register state* and PAPCR = 1; otherwise off.
R01UH0309EJ0500 Rev. 5.00
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Page 617 of 1408
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Section 10 I/O Ports
10.10
Port B
Port B is an 8-bit I/O port that also has other functions. Port B has the following registers.
•
•
•
•
•
Port B data direction register (PBDDR)
Port B data register (PBDR)
Port B register (PORTB)
Port B pull-up MOS control register (PBPCR)
Port B open drain control register (PBODR)
10.10.1 Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DDR
0
W
•
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Modes 1 and 2
Port B pins are address outputs regardless of the
PBDDR settings.
•
Mode 4
Modes 3 and 7 (EXPE = 1)
Setting a PBDDR bit to 1 makes the
corresponding pin an address output, while
clearing a PBDDR bit to 0 makes the
corresponding pin an input port.
•
Modes 3 and 7 (EXPE = 0)
Port B is an I/O port, and its pin functions can be
switched with PBDDR.
Page 618 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.10.2 Port B Data Register (PBDR)
PBDR stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DR
0
R/W
6
PB6DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
10.10.3 Port B Register (PORTB)
PORTB shows the pin states of port B. PORTB cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7
⎯*
R
6
PB6
⎯*
R
5
PB5
⎯*
R
If this register is read while a PBDDR bit is set to 1,
the corresponding PBDR value is read. If this
register is read while a PBDDR bit is cleared to 0,
the corresponding pin state is read.
4
PB4
⎯*
R
3
PB3
⎯*
R
2
PB2
⎯*
R
1
PB1
⎯*
R
0
PB0
⎯*
R
Note:
*
Determined by the states of pins PB7 to PB0.
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Sep 24, 2012
Page 619 of 1408
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Section 10 I/O Ports
10.10.4 Port B Pull-Up MOS Control Register (PBPCR)
PBPCR controls on/off of the input pull-up MOS for port B. PBPCR is valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
When in a input port register state, setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PB5PCR
0
R/W
4
PB4PCR
0
R/W
3
PB3PCR
0
R/W
2
PB2PCR
0
R/W
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
10.10.5 Port B Open Drain Control Register (PBODR)
PBODR specifies the output type of each port B pin.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7ODR
0
R/W
6
PB6ODR
0
R/W
5
PB5ODR
0
R/W
4
PB4ODR
0
R/W
When not specified for address output, setting a
PBODR bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing a
PBODR bit to 0 makes the corresponding pin a
CMOS output pin.
3
PB3ODR
0
R/W
2
PB2ODR
0
R/W
1
PB1ODR
0
R/W
0
PB0ODR
0
R/W
Page 620 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.10.6 Pin Functions
Port B pins also function as the pins for TPU I/Os and address outputs. The correspondence
between the register specification and the pin functions is shown below.
• PB7/A15/TIOCB8/TCLKH
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOB3 to
IOB0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), bits TPSC2 to TPSC0 in TCR_6
and TCR_11, and bit PB7DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
8 settings
⎯
PB7DDR
⎯
0
1
⎯
0
1
A15 output
PB7 input
A15 output
TIOCB8
output
PB7 input
PB7 output
Pin function
⎯
3, 7 (EXPE = 0)
(1) in table
below
(2) in table below
TIOCB8 input*1
TCLKH input*2
TPU channel 8
settings
MD3 to MD0
(2)
(1)
B'0000, B'01xx
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Notes: 1. TIOCB8 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. TCLKH input when the setting for either TCR_6 or TCR_11 is TPSC2 to TPSC0 =
B'111. TCLKH input when phase counting mode is set for channels 8 and 10.
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB6/A14/TIOCA8
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOA3 to
IOA0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), and bit PB6DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
8 settings
⎯
PB6DDR
⎯
0
1
⎯
0
1
A14 output
PB6 input
A14 output
TIOCA8
output
PB6 input
PB6 output
Pin function
TPU channel 8
settings
MD3 to MD0
IOA3 to IOA0
⎯
3, 7 (EXPE = 0)
(2)
(1)
B'0000, B'01xx
(1) in table
below
(2)
(1)
B'001x
B'0010
(2) in table below
TIOCA8 input*
(1)
1
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'01
B'01
Output function
⎯
Output
compare
output
⎯
PWM*2
mode 1
output
PWM mode
2 output
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA8 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. TIOCB8 output disabled.
Page 622 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB5/A13/TIOCB7/TCLKG
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to
IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6,
TCR_8, TCR_10, and TCR_11, and bit PB5DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
7 settings
⎯
PB5DDR
⎯
0
1
⎯
0
1
A13 output
PB5 input
A13 output
TIOCB7
output
PB5 input
PB5 output
Pin function
⎯
3, 7 (EXPE = 0)
(1) in table
below
(2) in table below
TIOCB7 input*1
TCLKG input*
TPU channel 7
settings
MD3 to MD0
(2)
(1)
B'0000, B'01xx
(2)
(2)
B'0010
2
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Notes: 1. TIOCB7 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. TCLKG input when the setting for either TCR_6 or TCR_8 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_10 or TCR_11 is TPSC2 to TPSC0 = B'101. TCLKG
input when phase counting mode is set for channels 8 and 10.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 623 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB4/A12/TIOCA7
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOA3 to
IOA0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), and bit PB4DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
7 settings
⎯
PB4DDR
⎯
0
1
⎯
0
1
A12 output
PB4 input
A12 output
TIOCA7
output
PB4 input
PB4 output
Pin function
TPU channel 7
settings
MD3 to MD0
IOA3 to IOA0
⎯
3, 7 (EXPE = 0)
(2)
(1)
B'0000, B'01xx
(1) in table
below
(2)
(1)
B'001x
B'0010
(2) in table below
TIOCA7 input*
(1)
1
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
Other than B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'01
B'01
Output function
⎯
Output
compare
output
⎯
PWM*2
mode 1
output
PWM mode
2 output
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA7 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
2. TIOCB7 output disabled.
Page 624 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB3/A11/TIOCD6/TCLKF
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOD3 to
IOD0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to
TCR_8, and bit PB3DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
6 settings
⎯
PB3DDR
⎯
0
1
⎯
0
1
A11 output
PB3 input
A11 output
TIOCD6
output
PB3 input
PB3 output
Pin function
⎯
3, 7 (EXPE = 0)
(1) in table
below
(2) in table below
TIOCD6 input*1
2
TCLKF input*
TPU channel 6
settings
(2)
MD3 to MD0
(1)
B'0000
(2)
(2)
B'0010
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Other than B'××00
[Legend]
x:
Don't care
Notes: 1. TIOCD6 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. TCLKF input when the setting for any of TCR_6 to TCR_8 is TPSC2 to TPSC0 = B'101.
TCLKF input when phase counting mode is set for channels 7 and 11.
R01UH0309EJ0500 Rev. 5.00
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Page 625 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB2/A10/TIOCC6/TCLKE
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to
IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to
TCR_11, and bit PB2DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
6 settings
⎯
PB2DDR
⎯
0
1
⎯
0
1
A10 output
PB2 input
A10 output
TIOCC6
output
PB2 input
PB2 output
Pin function
⎯
3, 7 (EXPE = 0)
(1) in table
below
(2) in table below
TIOCC6 input*1
2
TCLKE input*
TPU channel 6
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(1)
(2)
B'0011
Other than B'xx00
⎯
Other than
B'101
PWM*3 mode PWM mode
1 output
2 output
B'101
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCC6 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKE input when the setting for any of TCR_6 to TCR_11 is TPSC2 to TPSC0 =
B'100. TCLKE input when phase counting mode is set for channels 7 and 11.
3. TIOCD6 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_6.
Page 626 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB1/A9/TIOCB6
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOB3 to
IOB0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB1DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
6 settings
⎯
PB1DDR
⎯
0
1
⎯
0
1
A9 output
PB1 input
A9 output
TIOCB6
output
PB1 input
PB1 output
(2)
(1)
Pin function
TPU channel 6
settings
⎯
3, 7 (EXPE = 0)
(2)
MD3 to MD0
(1)
B'0000
(1) in table
below
(2)
B'0010
(2) in table below
TIOCB6 input*
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Note: * TIOCB6 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 627 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PB0/A8/TIOCA6
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOA3 to
IOA0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB0DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
6 settings
⎯
PB0DDR
⎯
0
1
⎯
0
1
A8 output
PB0 input
A8 output
TIOCA6
output
PB0 input
PB0 output
Pin function
TPU channel 6
settings
⎯
3, 7 (EXPE = 0)
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(1) in table
below
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2) in table below
TIOCA6 input*
(1)
1
(2)
B'0011
Other than B'xx00
⎯
Other than
B'001
PWM*2 mode PWM mode
1 output
2 output
B'001
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCC6 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. TIOCB6 output disabled.
Page 628 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.10.7 Port B Input Pull-Up MOS States
Port B has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 3, 4, and 7. The input pull-up MOS can be specified
as on or off on a bit-by-bit basis.
In modes 3, 4, and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 10.4 summarizes the input pull-up MOS states.
Table 10.4 Input Pull-Up MOS States for Port B
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1 or 2
Off
Off
Off
Off
On/Off
On/Off
3, 4 or 7
[Legend]
Off:
Input pull-up MOS is always off.
On/Off: Input pull-up MOS is on when in a input port state 0 and PBPCR = 1; otherwise off.
R01UH0309EJ0500 Rev. 5.00
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Page 629 of 1408
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Section 10 I/O Ports
10.11
Port C
Port C is an 8-bit I/O port that also has other functions. Port C has the following registers.
•
•
•
•
•
Port C data direction register (PCDDR)
Port C data register (PCDR)
Port C register (PORTC)
Port C pull-up MOS control register (PCPCR)
Port C open drain control register (PCODR)
10.11.1 Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
•
6
PC6DDR
0
W
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
Modes 1 and 2
Port C pins are address outputs regardless of
the PCDDR settings.
•
Mode 4
Modes 3 and 7(EXPE = 1)
Setting a PCDDR bit to 1 makes the
corresponding pin an address output, while
clearing a PCDDR to 0 makes the corresponding
pin an input port.
•
Modes 3 and 7 (EXPE = 0)
Port C is an I/O port, and its pin functions can be
switched with PCDDR.
Page 630 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.11.2 Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DR
0
R/W
6
PC6DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
10.11.3 Port C Register (PORTC)
PORTC shows the pin states of port C. PORTC cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7
⎯*
R
6
PC6
⎯*
R
5
PC5
⎯*
R
If this register is read while a PCDDR bit is set to 1,
the corresponding PCDR value is read. If this
register is read while a PCDDR bit is cleared to 0,
the corresponding pin state is read.
4
PC4
⎯*
R
3
PC3
⎯*
R
2
PC2
⎯*
R
1
PC1
⎯*
R
0
PC0
⎯*
R
Note:
*
Determined by the states of pins PC7 to PC0.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 631 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.11.4 Port C Pull-Up MOS Control Register (PCPCR)
PCPCR controls on/off of the input pull-up MOS for port C. PCPCR is valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
When in a input port state, setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PC5PCR
0
R/W
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
10.11.5 Port C Open Drain Control Register (PCODR)
PCODR specifies the output type of each port C pin.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7ODR
0
R/W
6
PC6ODR
0
R/W
5
PC5ODR
0
R/W
4
PC4ODR
0
R/W
When not specified for address output, setting a
PCODR bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing a
PCODR bit to 0 makes the corresponding pin a
CMOS output pin.
3
PC3ODR
0
R/W
2
PC2ODR
0
R/W
1
PC1ODR
0
R/W
0
PC0ODR
0
R/W
Page 632 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.11.6 Pin Functions
Port C pins also function as the pins for TPU I/Os and address outputs. The correspondence
between the register specification and the pin functions is shown below.
• PC7/A7/TIOCB11
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOB3 to
IOB0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC7DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
11 settings
⎯
PC7DDR
⎯
0
1
⎯
0
1
A7 output
PC7 input
A7 output
TIOCB11
output
PC7 input
PC7 output
Pin function
TPU channel 11
settings
⎯
3, 7 (EXPE = 0)
(2)
MD3 to MD0
(1)
B'0000
(1) in table
below
(2)
(2)
B'0010
(2) in table below
TIOCB11 input*
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Note: * TIOCB11 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 633 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PC6/A6/TIOCA11
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOA3 to
IOA0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC6DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
11 settings
⎯
PC6DDR
⎯
0
1
⎯
0
1
A6 output
PC6 input
A6 output
TIOCA11
output
PC6 input
PC6 output
Pin function
TPU channel 11
settings
MD3 to MD0
IOA3 to IOA0
⎯
3, 7 (EXPE = 0)
(2)
(1)
B'0000, B'01xx
(1) in table
below
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2) in table below
1
TIOCA11 input*
(1)
(2)
B'0011
Other than B'xx00
⎯
Other than
B'01
PWM*2 mode PWM mode
1 output
2 output
B'01
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA11 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. TIOCB11 output disabled.
Page 634 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PC5/A5/TIOCB10
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to
IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
10 settings
⎯
PC5DDR
⎯
0
1
⎯
0
1
A5 output
PC5 input
A5 output
TIOCB10
output
PC5 input
PC5 output
Pin function
TPU channel 10
settings
MD3 to MD0
⎯
3, 7 (EXPE = 0)
(2)
(1)
B'0000, B'01xx
(1) in table
below
(2)
(2)
B'0010
(2) in table below
TIOCB10 input*
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
⎯
Other than
B'10
B'10
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Note: * TIOCB10 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 635 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PC4/A4/TIOCA10
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOA3 to
IOA0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC4DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
10 settings
⎯
PC4DDR
⎯
0
1
⎯
0
1
A4 output
PC4 input
A4 output
TIOCA10
output
PC4 input
PC4 output
Pin function
TPU channel 10
settings
MD3 to MD0
IOA3 to IOA0
⎯
3, 7 (EXPE = 0)
(2)
(1)
B'0000, B'01xx
(1) in table
below
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR1,
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2) in table below
TIOCA10 input*
(1)
1
(2)
B'0011
Other than B'xx00
⎯
Other than
B'01
PWM*2 mode PWM mode
1 output
2 output
B'01
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA10 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
2. TIOCB10 output disabled.
Page 636 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PC3/A3/TIOCD9
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOD3 to
IOD0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC3DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
9 settings
⎯
PC3DDR
⎯
0
1
⎯
0
1
A3 output
PC3 input
A3 output
TIOCD9
output
PC3 input
PC3 output
Pin function
TPU channel 9
settings
⎯
3, 7 (EXPE = 0)
(2)
MD3 to MD0
(1)
B'0000
(1) in table
below
(2)
(2)
B'0010
(2) in table below
TIOCD9 input*
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'110
B'110
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOD3 to IOD0
Other than B'xx00
[Legend]
x:
Don't care
Note: * TIOCD9 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
R01UH0309EJ0500 Rev. 5.00
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Section 10 I/O Ports
• PC2/A2/TIOCC9
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to
IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
9 settings
⎯
PC2DDR
⎯
0
1
⎯
0
1
A2 output
PC2 input
A2 output
TIOCC9
output
PC2 input
PC2 output
Pin function
TPU channel 9
settings
(2)
MD3 to MD0
IOC3 to IOC0
⎯
3, 7 (EXPE = 0)
(1)
B'0000
(1) in table
below
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2) in table below
TIOCC9 input*
(1)
1
(2)
B'0011
Other than B'xx00
⎯
Other than
B'101
PWM*2 mode PWM mode
1 output
2 output
B'101
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCC9 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TIOCD9 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_9.
Page 638 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PC1/A1/TIOCB9
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOB3 to
IOB0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC1DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
9 settings
⎯
PC1DDR
⎯
0
1
⎯
0
1
A1 output
PC1 input
A1 output
TIOCB9
output
PC1 input
PC1 output
Pin function
TPU channel 9
settings
⎯
3, 7 (EXPE = 0)
(2)
MD3 to MD0
(1)
B'0000
(1) in table
below
(2)
(2)
B'0010
(2) in table below
TIOCB9 input*
(1)
(2)
B'0011
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
⎯
Other than
B'010
B'010
Output function
⎯
Output
compare
output
⎯
⎯
PWM mode
2 output
⎯
IOB3 to IOB0
Other than B'xx00
[Legend]
x:
Don't care
Note: * TIOCB9 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
R01UH0309EJ0500 Rev. 5.00
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Page 639 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PC0/A0/TIOCA9
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to
IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR.
Operating
mode
1, 2
4
3, 7 (EXPE = 1)
TPU channel
9 settings
⎯
PC0DDR
⎯
0
1
⎯
0
1
A0 output
PC0 input
A0 output
TIOCA9
output
PC0 input
PC0 output
Pin function
TPU channel 9
settings
⎯
3, 7 (EXPE = 0)
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
(1) in table
below
(2)
(1)
B'001x
B'0010
B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00
CCLR2 to
CCLR0
⎯
⎯
⎯
Output function
⎯
Output
compare
output
⎯
(2) in table below
TIOCA9 input*
(1)
1
(2)
B'0011
Other than B'xx00
⎯
Other than
B'001
PWM*2 mode PWM mode
1 output
2 output
B'001
⎯
[Legend]
x:
Don't care
Notes: 1. TIOCA9 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. TIOCB9 output disabled.
Page 640 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.11.7 Port C Input Pull-Up MOS States
Port C has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 3, 4 and 7. The input pull-up MOS can be specified as
on or off on a bit-by-bit basis.
In modes 3, 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 10.5 summarizes the input pull-up MOS states.
Table 10.5 Input Pull-Up MOS States for Port C
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1 or 2
Off
Off
Off
Off
On/Off
On/Off
3, 4 or 7
[Legend]
Off:
Input pull-up MOS is always off.
On/Off: Input pull-up MOS is on when in a input port state and PCPCR = 1; otherwise off.
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Page 641 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.12
Port D
Port D is an 8-bit I/O port that also has other functions. Port D has the following registers.
•
•
•
•
•
Port D data direction register (PDDDR)
Port D data register (PDDR)
Port D register (PORTD)
Port D pull-up MOS control register (PDPCR)
Port D open drain control register (PDODR)
10.12.1 Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
•
6
PD6DDR
0
W
5
PD5DDR
0
W
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Page 642 of 1408
Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
Port D is automatically designated for data
input/output.
•
Modes 3 and 7 (EXPE = 0)
Port D is an I/O port, and its pin functions can be
switched with PDDDR.
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.12.2 Port D Data Register (PDDR)
PDDR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DR
0
R/W
6
PD6DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
10.12.3 Port D Register (PORTD)
PORTD shows the pin states of port D. PORTD cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7
⎯*
R
6
PD6
⎯*
R
5
PD5
⎯*
R
If this register is read while a PDDDR bit is set to 1,
the corresponding PDDR value is read. If this
register is read while a PDDDR bit is cleared to 0,
the corresponding pin state is read.
4
PD4
⎯*
R
3
PD3
⎯*
R
2
PD2
⎯*
R
1
PD1
⎯*
R
0
PD0
⎯*
R
Note:
*
Determined by the states of pins PD7 to PD0.
R01UH0309EJ0500 Rev. 5.00
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Page 643 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.12.4 Port D Pull-Up MOS Control Register (PDPCR)
PDPCR controls on/off of the input pull-up MOS for port D. PDPCR is valid in mode 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
When PDDDR = 0 (input port), setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
5
PD5PCR
0
R/W
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
10.12.5 Port D Open Drain Control Register (PDODR)
PDODR specifies the output type of each port D pin.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7ODR
0
R/W
6
PD6ODR
0
R/W
5
PD5ODR
0
R/W
4
PD4ODR
0
R/W
When not specified for data or address output,
setting a PDODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a PDODR bit to 0 makes the corresponding pin a
CMOS output pin.
3
PD3ODR
0
R/W
2
PD2ODR
0
R/W
1
PD1ODR
0
R/W
0
PD0ODR
0
R/W
Page 644 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.12.6 Pin Functions
Port D pins also function as the pins for data I/Os and address outputs. The correspondence
between the register specification and the pin functions is shown below.
• PD7/D15/AD15, PD6/D14/AD14, PD5/D13/AD13, PD4/D12/AD12, PD3/D11/AD11,
PD2/D10/AD10, PD1/D9/AD9, PD0/D8/AD8
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit MPXE in MPXCR of the bus controller, and bit PDnDDR.
Operating
mode
1, 2, 4
⎯
EXPE
MPXE
0
0
Data I/O
Address
output/
data I/O
1
⎯
1
⎯
PDnDDR
Pin function
3, 7
0
0
1
PDn input
PDn output
1
⎯
Data I/O
Address
output/
data I/O
[Legend]
n = 7 to 0
R01UH0309EJ0500 Rev. 5.00
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Page 645 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.12.7 Port D Input Pull-Up MOS States
Port D has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 3 and 7. The input pull-up MOS can be specified as
on or off on a bit-by-bit basis.
In modes 3 and 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 10.6 summarizes the input pull-up MOS states.
Table 10.6 Input Pull-Up MOS States for Port D
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, or 4
Off
Off
Off
Off
On/Off
On/Off
3, 7
[Legend]
Off:
Input pull-up MOS is always off.
On/Off: Input pull-up MOS is on when PDDDR = 0 and PDPCR = 1; otherwise off.
Page 646 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
10.13
Section 10 I/O Ports
Port E
Port E is an 8-bit I/O port that also has other functions. Port E has the following registers.
•
•
•
•
•
Port E data direction register (PEDDR)
Port E data register (PEDR)
Port E register (PORTE)
Port E pull-up MOS control register (PEPCR)
Port E open drain control register (PEODR)
10.13.1 Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
•
6
PE6DDR
0
W
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
Modes 1, 2, and 4
When 8-bit bus mode is selected, port E is an I/O
port, and its pin functions can be switched with
PEDDR.
When 16-bit bus mode is selected, port E is
designated for data input/output.
For details on 8-bit and 16-bit bus modes, see
section 6, Bus Controller (BSC).
•
Modes 3 and 7 (EXPE = 1)
When 8-bit bus mode is selected, port E is an I/O
port. Setting a PEDDR bit to 1 makes the
corresponding pin an output port, while clearing
a PEDDR bit to 0 makes the corresponding pin
an input port.
When 16-bit bus mode is selected, port E is
designated for data input/output.
•
Modes 3 and 7 (EXPE = 0)
Port E is an I/O port, and its pin functions can be
switched with PEDDR.
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Page 647 of 1408
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Section 10 I/O Ports
10.13.2 Port E Data Register (PEDR)
PEDR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DR
0
R/W
6
PE6DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
10.13.3 Port E Register (PORTE)
PORTE shows the pin states of port E. PORTE cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7
⎯*
R
6
PE6
⎯*
R
5
PE5
⎯*
R
If this register is read while a PEDDR bit is set to 1,
the corresponding PEDR value is read. If this
register is read while a PEDDR bit is cleared to 0,
the corresponding pin state is read.
4
PE4
⎯*
R
3
PE3
⎯*
R
2
PE2
⎯*
R
1
PE1
⎯*
R
0
PE0
⎯*
R
Note:
*
Determined by the states of pins PE7 to PE0.
Page 648 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.13.4 Port E Pull-Up MOS Control Register (PEPCR)
PEPCR controls on/off of the input pull-up MOS for port E. PEPCR is valid in 8-bit bus mode.
Bit
Bit Name
Initial Value
R/W
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
4
PE4PCR
0
R/W
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
Description
When PEDDR = 0 (input port), setting the
corresponding bit to 1 turns on the input pull-up
MOS for that pin.
10.13.5 Port E Open Drain Control Register (PEODR)
PEODR specifies the output type of each port E pin.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7ODR
0
R/W
6
PE6ODR
0
R/W
5
PE5ODR
0
R/W
4
PE4ODR
0
R/W
When not specified for data or address output,
setting a PEODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a PEODR bit to 0 makes the corresponding pin a
CMOS output pin.
3
PE3ODR
0
R/W
2
PE2ODR
0
R/W
1
PE1ODR
0
R/W
0
PE0ODR
0
R/W
R01UH0309EJ0500 Rev. 5.00
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Page 649 of 1408
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Section 10 I/O Ports
10.13.6 Pin Functions
Port E pins also function as the pins for data I/Os and address outputs. The correspondence
between the register specification and the pin functions is shown below.
• PE7/D7/AD7, PE6/D6/AD6, PE5/D5/AD5, PE4/D4/AD4, PE3/D3/AD3, PE2/D2/AD2,
PE1/D1/AD1, PE0/D0/AD0
The pin function is switched as shown below according to the combination of the operating
mode, bus mode, bit EXPE, bit MPXE in MPXCR of the bus controller, and bit PEnDDR.
Operating
mode
1, 2, 4
3, 7
All areas are
8-bit space
At least one
area is 16-bit
space
⎯
All areas are
8-bit space
At least one area
is 16-bit space
EXPE
⎯
⎯
0
1
1
MPXE
⎯
⎯
⎯
Bus mode
PEnDDR
Pin function
0
PEn
input
0
1
PEn Data
output I/O
1
⎯
Address
output/
data I/O
0
1
0
0
1
⎯
1
PEn PEn PEn PEn
input output input output
Data
I/O
Address
output/
data I/O
[Legend]
n = 7 to 0
Page 650 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.13.7 Port E Input Pull-Up MOS States
Port E has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in 8-bit bus mode or in modes 3 and 7. The input pull-up MOS
can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode or in modes 3 and 7, when a
PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up
MOS for that pin.
Table 10.7 summarizes the input pull-up MOS states.
Table 10.7 Input Pull-Up MOS States for Port E
Mode
1, 2, or 4
8-bit bus
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
Off
Off
On/Off
On/Off
16-bit bus
3 or 7
Off
Off
[Legend]
Off:
Input pull-up MOS is always off.
On/Off: Input pull-up MOS is on when PEDDR = 0 and PEPCR = 1; otherwise off.
R01UH0309EJ0500 Rev. 5.00
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Page 651 of 1408
Section 10 I/O Ports
10.14
H8S/2456, H8S/2456R, H8S/2454 Group
Port F
Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
•
•
•
Port F data direction register (PFDDR)
Port F data register (PFDR)
Port F register (PORTF)
Port function control register 0 (PFCR0)
Port function control register 2 (PFCR2)
Port function control register 4 (PFCR4)
Port function control register 5 (PFCR5)
Port F open drain control register (PFODR)
Page 652 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.14.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be
read; if it is, an undefined value will be read.
Bit Name
Initial
Value
R/W
Description
7
PF7DDR
1/0*
W
•
6
PF6DDR
0
W
5
PF5DDR
0
W
4
PF4DDR
0
W
3
PF3DDR
0
W
2
PF2DDR
0
W
1
PF1DDR
0
W
0
PF0DDR
0
W
Bit
Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an input port
when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when the ASOE
bit is set to 1. When the ASOE bit is cleared to 0, pin PF6
is an I/O port and its function can be switched with
PF6DDR.
Pins PF5 and PF4 are automatically designated as bus
control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when the
LWROE bit is set to 1. When the LWROE bit is cleared to
0, pin PF3 is an I/O port and its function can be switched
with PF3DDR.
Pins PF2 and PF1 function as bus control output pins
(LCAS and UCAS) when the appropriate bus controller
settings are made. Otherwise, operations differ between
the H8S/2456 and H8S/2456R Groups and H8S/2454
Group.
[H8S/2456 Group and H8S/2456R Group]
When pins PF2 and PF1 are general I/O ports, the
function can be switched with PFDDR.
R01UH0309EJ0500 Rev. 5.00
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Section 10 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
[H8S/2454 Group]
Pins PF2 and PF1 function as CS output pins when the
CS output enable bits (CS6E and CS5E) are set to 1,
and as input ports when the bits are cleared to 0. When
the CS output enable bits (CS6E and CS5E) are cleared
to 0 and pins PF2 and PF1 are general I/O ports, the
function can be switched with PFDDR.
The PF0 pin functions as a bus control input pin (WAIT)
when the appropriate bus controller settings are made.
Otherwise, PF0 is an I/O port and the function can be
switched with PF0DDR.
•
Modes 3 and 7 (EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an input port
when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions can be
switched with PFDDR.
Note:
*
PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in modes 3 and 7.
Page 654 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.14.2 Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DR
0
R/W
6
PF6DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
10.14.3 Port F Register (PORTF)
PORTF shows the pin states of port F. PORTF cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7
⎯*
R
6
PF6
⎯*
R
5
PF5
⎯*
R
If this register is read while a PFDDR bit is set to 1,
the corresponding PFDR value is read. If this
register is read while a PFDDR bit is cleared to 0,
the corresponding pin state is read.
4
PF4
⎯*
R
3
PF3
⎯*
R
2
PF2
⎯*
R
1
PF1
⎯*
R
0
PF0
⎯*
R
Note:
*
Determined by the states of pins PF7 to PF0.
R01UH0309EJ0500 Rev. 5.00
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Page 655 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.14.4 Port F Open Drain Control Register (PFODR)
PFODR specifies the output type of each port F pin.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7ODR
0
R/W
6
PF6ODR
0
R/W
5
PF5ODR
0
R/W
4
PF4ODR
0
R/W
3
PF3ODR
0
R/W
When not specified for AS, AH, RD, HWR, LWR,
1
1
2
2
LCAS, UCAS, DQML* , DQMU* , CS5* , CS6* , or
2
OE-A* output, setting a PFODR bit to 1 makes the
corresponding pin an NMOS open-drain output pin,
while clearing a PFODR bit to 0 makes the
corresponding pin a CMOS output pin.
2
PF2ODR
0
R/W
1
PF1ODR
0
R/W
0
PF0ODR
0
R/W
Notes: 1. Not supported in the H8S/2456 and H8S/2454 Groups.
2. Not supported in the H8S/2456 and H8S/2456R Groups.
10.14.5 Pin Functions
Port F pins also function as the pins for SSU I/Os, A/D converter inputs, interrupt inputs, bus
control signal I/Os, and system clock outputs. The correspondence between the register
specification and the pin functions is shown below.
• PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
Operating
mode
PF7DDR
Pin function
Page 656 of 1408
1, 2, 3, 4, 7
0
1
PF7 input
φ output
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PF6/AS/AH
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit MPXE in MPXCR of the bus controller, bit ASOE in PFCR2, and bit
PF6DDR.
Operating
mode
1, 2, 4
3, 7
⎯
EXPE
0
1
⎯
ASOE
1
PF6DDR
⎯
0
1
0
1
⎯
0
1
AS/AH*
output
PF6
input
PF6
output
PF6
input
PF6
output
AS/AH*
output
PF6
input
PF6
output
Pin function
Note:
*
0
1
0
AH output when MPXE = 1, and AS output when MPXE = 0.
• PF5/RD
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, and bit PF5DDR.
Operating
mode
1, 2, 4
3, 7
EXPE
⎯
PF5DDR
⎯
0
1
⎯
RD output
PF5 input
PF5 output
RD output
Pin function
0
1
• PF4/HWR
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, and bit PF4DDR.
Operating
mode
EXPE
PF4DDR
Pin function
1, 2, 4
3, 7
⎯
0
1
⎯
0
1
⎯
HWR output
PF4 input
PF4 output
HWR output
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PF3/LWR/SSO0-C
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of SSU, bit LWROE in PFCR2, bits SSOS1 and SSOS0 in PFCR5, and bit PF3DDR.
Operating
mode
1, 2, 4
3, 7 (EXPE = 1)
3, 7 (EXPE = 0)
0
0
LWROE
1
SSU settings
⎯
PF3DDR
⎯
0
1
LWR
output
PF3
input
PF3
output
Pin function
(1) in table below
(2) in
table
below
(3) in
table
below
(1) in table
below
⎯
3
0*
SSO0-C SSO0-C
1 4
2 4
input* * output* *
(2) in
table
below
0
1
0*
PF3
input
PF3
output
(3) in
table
below
⎯
3
SSO0-C SSO0-C
1 4
2 4
input* * output* *
Notes: 1. When using as SSO0-C input, set SSO0S1 and SSO0S0 in PFCR5 to B'10 before other
register setting.
2. When using as SSO0-C output, set SSO0S1 and SSO0S0 in PFCR5 to B'10 before
other register setting.
3. PF3DDR = 0 when the SSU pin is used as input.
4. Do not set up for SSU unless SSO0S1 and SSO0S0 = B'10 in PFCR5.
Use as I/O port.
SSU
(1)
(2)
(1)
(2)
(1)
(3)
(3)
(2)
(3)
(2)
(3)
(1)
(3)
(3)
(1)
(3)
(3)
settings
SSUMS
0
0
1*1
BIDE
0
1*2
0
MSS
0
TE
1
0
1
0
RE
0
1
0
1
1
Pin
⎯
SS
⎯
SSO
⎯
state
O
inpu
inpu
t
0
1
0
SSO
output
1
0
0
1
0
1
0
1
1
0
1
0
1
SSO
SSO
SSO
SSO
SSO
⎯
output input output input output
1
1
0
1
0
1
1
0
1
SSO
SSO
⎯
SSO
SSO
output output
outp output
ut
t
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes:
See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
Page 658 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PF2/LCAS/DQML*6/IRQ15-A/SSI0-C (H8S/2456 Group and H8S/2456R Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits ABW5 to
ABW2 in ABWCR, bits SSI0S1 and SSI0S0 in PFCR5, and bit PF2DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
Areas 2 to 5
Any DRAM/
synchronous DRAM
space area is 16-bit
bus space
SSU settings
⎯
(1) in table below
PF2DDR
⎯
0
LCAS output
DQML*6 output
PF2 input
Pin function
All DRAM/synchronous DRAM space areas are
8-bit bus space, or areas 2 to 5 are all normal space
(2) in table
below
(3) in table
below
1
0*4
⎯
PF2 output
SSI0-C
input*2*5
SSI0-C
output*3*5
IRQ15-A interrupt input*
1
• Modes 3 and 7 (EXPE = 0)
⎯
Areas 2 to 5
SSU settings
(1) in table below
PF2DDR
Pin function
0
PF2 input
(2) in table below
1
PF2 output
0*
(3) in table below
⎯
4
2
SSI0-C input* *
5
SSI0-C output*3*5
IRQ15-A interrupt input*1
Notes: 1. IRQ15 input when the ITS15 bit in ITSR is 0.
2. When using as SSI0-C input, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other
register setting.
3. When using as SSI0-C output, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other
register setting.
4. PF2DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'10 in PFCR5.
Use as I/O port.
6. Not supported in the H8S/2456 Group.
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Section 10 I/O Ports
SSU
(1)
(1)
(3)
(3)
(2)
(1)
(2)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(2)
(1)
(2)
settings
SSUMS
0
0
1*1
BIDE
0
1*2
0
MSS
0
TE
1
0
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
RE
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
Pin state
⎯
⎯
SSI
SSI
SSI
⎯
SSI
⎯
⎯
⎯
⎯
SSI
⎯
SSI
SSI
⎯
SSI
input
input
output output
input
input
input
input
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
• PF2/CS6/LCAS/SSI0-C (H8S/2454 Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS6E in
PFCR0, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit
PF2DDR.
• Modes 1, 2, and 4
Areas 2 to 5
Modes 3 and 7 (EXPE = 1)
Any DRAM/
synchronous DRAM
space area is 16-bit
bus space
All DRAM/synchronous DRAM space areas are
8-bit bus space, or areas 2 to 5 are all normal space
CS6E
⎯
SSU settings
⎯
(1) in table
below
PF2DDR
⎯
0
LCAS output
PF2
input
Pin function
Page 660 of 1408
0
1
⎯
(2) in table
below
(3) in table
below
1
0*3
⎯
0
1
PF2
output
SSI0-C
1 4
input* *
SSI0-C
output*2*4
PF2
input
CS6
output
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
Areas 2 to 5
⎯
CS6E
⎯
SSU settings
(1) in table below
PF2DDR
0
Pin function
(2) in table below
1
PF2 input
(3) in table below
⎯
3
0*
1
PF2 output
4
SSI0-C output*2*4
SSI0-C input* *
Notes: 1. When using as SSI0-C input, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other
register setting.
2. When using as SSI0-C output, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other
register setting.
3. PF2DDR = 0 when the SSU pin is used as input.
4. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'10 in PFCR5.
Use as I/O port.
SSU
(1)
(1)
(3)
(3)
(2)
(1)
(2)
(1)
(1)
(1)
(1)
(2)
(1)
(2)
(2)
(1)
(2)
settings
SSUMS
0
0
BIDE
0
1*
MSS
0
TE
0
1
RE
0
1
Pin
⎯
⎯
state
1
0
0
1
0
⎯
SSI
SSI
SSI
output
output
input
2
0
0
1
1
1
1*
1
0
0
1
0
1
0
1
1
0
1
0
1
0
SSI
⎯
⎯
⎯
⎯
SSI
⎯
input
input
1
1
0
1
1
1
0
SSI
SSI
⎯
input input
1
SSI
input
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 20.4 to 20.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PF1/UCAS/DQMU*6/IRQ14-A/SSCK0-C (H8S/2456 Group and H8S/2456R Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of SSU, bits
RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSCK0S1 and SSCK0S0 in
PFCR5, and bit PF1DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
Areas 2 to 5
Any of areas 2 to 5 is
DRAM/ synchronous
DRAM space
SSU settings
⎯
(1) in table below
PF1DDR
⎯
0
UCAS output
6
DQMU* output
PF1 input
Pin function
Areas 2 to 5 are all normal space
(2) in table
below
(3) in table
below
1
0*4
⎯
PF1 output
SSCK0-C
input*2*5
SSCK0-C
output*3*5
IRQ14-A interrupt input*
1
• Modes 3 and 7 (EXPE = 0)
⎯
Areas 2 to 5
SSU settings
PF1DDR
Pin function
(1) in table below
0
PF1 input
(2) in table below
(3) in table below
⎯
4
1
0*
PF1 output
2
5
SSCK0-C input* *
IRQ14-A interrupt input*
SSCK0-C output*3*5
1
Notes: 1. IRQ14 input when the ITS14 bit in ITSR is 0.
2. When using as SSCK0-C input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before
other register setting.
3. When using as SSCK0-C output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before
other register setting.
4. PF1DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'10 in PFCR5.
Use as I/O port.
6. Not supported in the H8S/2456 Group.
Page 662 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
SSU settings
(1)
Section 10 I/O Ports
(2)
SSUMS
(1)
(3)
(1)
(2)
0
MSS
(1)
(3)
1
0
1
0
1
SCKS
0
1
0
1
0
1
0
1
Pin state
⎯
SSCK
input
⎯
SSCK
output
⎯
SSCK
input
⎯
SSCK
output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
• PF1/CS5/UCAS/SSCK0-C (H8S/2454 Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of SSU, bits
RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS5E in PFCR0, bits SSCK0S1 and
SSCK0S0 in PFCR5, and bit PF1DDR.
• Modes 1, 2, and 4
Areas 2 to 5
Modes 3 and 7 (EXPE = 1)
DRAM space
Areas 2 to 5 are all normal space
CS5E
⎯
SSU settings
⎯
PF1DDR
⎯
0
1
0*
⎯
0
1
UCAS output
PF1
input
PF1
output
SSCK0-C
1 4
input* *
SSCK0-C
2 4
output* *
PF1
input
CS5
output
Pin function
0
(1) in table below
1
⎯
(2) in table below (3) in table below
3
• Modes 3 and 7 (EXPE = 0)
Areas 2 to 5
⎯
CS5E
⎯
SSU settings
(1) in table below
PF1DDR
Pin function
(2) in table below
0
1
PF1 input
PF1 output
0*
3
(3) in table below
⎯
SSCK0-C input*1*4 SSCK0-C output*2*4
Notes: 1. When using as SSCK0-C input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before
other register setting.
2. When using as SSCK0-C output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before
other register setting.
3. PF1DDR = 0 when the SSU pin is used as input.
4. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'10 in PFCR5.
Use as I/O port.
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Page 663 of 1408
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Section 10 I/O Ports
SSU settings
(1)
(2)
(1)
SSUMS
(3)
(1)
(2)
(1)
0
MSS
(3)
1
0
1
0
1
SCKS
0
1
0
1
0
1
0
1
Pin state
⎯
SSCK
input
⎯
SSCK
output
⎯
SSCK
input
⎯
SSCK
output
[Legend]
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
• PF0/WAIT-A/ADTRG0-B/SCS0-C (H8S/2456 Group and H8S/2456R Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, bits MSS, CSS1, and CSS0 in
SSCRH and bit SSUMS in SSCRL of SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0
of ADC, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit
PF0DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
WAITE
0
WAITS
⎯
SSU settings
PF0DDR
Pin function
(1) in table below
0
(2) in table below (4) in table below (3) in table below
0*5
1
PF0 input
⎯
0*5
PF0 output SCS0-C input* *
2
6
SCS0-C I/O* *
SCS0-C output*3*6
4 6
ADTRG0-B input*1
WAITE
1
WAITS
0
SSU settings
⎯
(1) in table
below
(2) in table
below
(4) in table
below
(3) in table
below
⎯
PF0DDR
⎯
0
0*5
0
0
1
WAIT-A input
PF0 input
SCS0-C
2 6
input* *
Setting
prohibited
Setting
prohibited
Setting
prohibited
Pin function
1
ADTRG0-B input*1
Page 664 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
⎯
WAITE
SSU settings
PF0DDR
Pin function
(1) in table below
0
(2) in table below (4) in table below
1
PF0 input
0*
5
0*
PF0 output SCS0-C input* *
2
6
(3) in table below
⎯
5
SCS0-C I/O* *
SCS0-C output*3*6
4 6
ADTRG0-B input*
1
Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and
EXTRGS = 1
2. When using as SCS0-C input, set SCS0S1 and SCS0S0 in PFCR5 to B'10 before other
register setting.
3. When using as SCS0-C output, set SCS0S1 and SCS0S0 in PFCR5 to B'10 before
other register setting.
4. When using as SCS0-C input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'10
before other register setting.
5. PF0DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SCS0S1 and SCS0S0 = B'10 in PFCR5.
Use as I/O port.
SSU settings
(2)
(1)
(2)
SSUMS
(3)
0
MSS
0
CSS1
x
CSS0
x
0
1
SCS input
⎯
SCS input
Pin state
(4)
(1)
1
1
x
0
1
0
x
1
Automatic SCS SCS output
I/O
x
⎯
[Legend]
x:
Don't care
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
R01UH0309EJ0500 Rev. 5.00
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Page 665 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A (H8S/2454 Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR, bits MSS,
CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits TRGS1, TRGS0, and
EXTRGS in ADCR_0 of ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4,
bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
OEE
0
RMTS2 to
⎯
RMTS0
WAITE
0
WAITS
⎯
SSU settings
(1) in table below
PF0DDR
Pin function
0
1
⎯
⎯
(2) in
(4) in
(3) in
table
table
table
table
table
table
below
below
below
below
below
below
0*6
0*6
⎯
⎯
0
1
0*6
0
PF0
SCS0-C
SCS0-C
SCS0-C
WAIT-A
PF0 input
Setting
SCS0-C
Setting
output
input*3*7
I/O*5*7
output*4*7
input
0
PF0 input
1
1
(1) in
(2) in
(3) (4) in
prohibited input*3*7 prohibited
ADTRG0-B input*2
OEE
1
RMTS2 to
Settings other than that for areas 2 to 5 as DRAM
Areas 2 to
RMTS0
5 are
DRAM
space
WAITE
0
WAITS
⎯
SSU settings
(1) in table below
PF0DDR
0
1
⎯
1
⎯
(4) in
(3) in
(2) in
(3) (4) in
table
table
table
table
table
table
below
below
below
below
below
below
0*
6
6
0*
(1) in
⎯
(2) in
⎯
⎯
0
PF0 input
PF0
PF0
SCS0-C
SCS0-C
SCS0-C
WAIT-A
input*3
output
input*3*7
I/O*5*7
output*4*7
input
Pin function
⎯
1
0
1
6
0*
⎯
0
⎯
Setting
SCS0-C
Setting
OE-A*1
prohibited
input*3*7
prohibited
output
ADTRG0-B input*
2
Page 666 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
OEE
⎯
Area 2
⎯
WAITE
⎯
SSU settings
(1) in table below
PF0DDR
0
PF0 input
Pin function
(2) in table
below
(4) in table
below
(3) in table
below
1
0*6
0*6
⎯
PF0 output
SCS0-C
input*3*7
SCS0-C
I/O*5*7
SCS0-C
output*4*7
ADTRG0-B input*
2
Notes: 1. OE-A input when the OES bit in PFCR2 is 1.
2. ADTRG0-B input when TRGS1 = TRGS0 = 0, EXTRGS = 1, or TRGS1 = TRGS0 =
EXTRGS = 1.
3. When using as SCS0-C input, set SCS0S1 and SCS0S0 in PFCR5 to B'10 before other
register setting.
4. When using as SCS0-C output, set SCS0S1 and SCS0S0 in PFCR5 to B'10 before
other register setting.
5. When using as SCS0-C input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'10
before other register setting.
6. PF0DDR = 0 when the SSU pin is used as input.
7. Do not set up for SSU unless SCS0S1 and SCS0S0 = B'10 in PFCR5.
Use as I/O port.
SSU settings
(2)
(1)
(2)
SSUMS
(3)
0
MSS
0
CSS1
x
CSS0
x
0
1
SCS input
⎯
SCS input
Pin state
(4)
(1)
1
1
x
0
1
0
x
1
Automatic SCS SCS output
I/O
x
⎯
[Legend]
x:
Don't care
⎯:
Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
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Page 667 of 1408
Section 10 I/O Ports
10.15
H8S/2456, H8S/2456R, H8S/2454 Group
Port G
Port G is a 7-bit I/O port that also has other functions. Port G has the following registers.
•
•
•
•
•
•
Port G data direction register (PGDDR)
Port G data register (PGDR)
Port G register (PORTG)
Port function control register 0 (PFCR0)
Port function control register 4 (PFCR4)
Port G open drain control register (PGODR)
Page 668 of 1408
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Section 10 I/O Ports
10.15.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
⎯
Reserved
6
PG6DDR
0
W
•
5
PG5DDR
0
W
4
PG4DDR
0
W
3
PG3DDR
0
W
2
PG2DDR
0
W
1
PG1DDR
0
W
0
PG0DDR
1/0*
W
Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
Pins PG6 and PG5 function as bus control
input/output pins (BREQ and BACK) when the
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
The PG4 pin function as a bus control output pin
(BREQO) when the appropriate bus controller
settings are made. Otherwise, operations differ
between the H8S/2456 and H8S/2456R Groups
and H8S/2454 Group.
[H8S/2456 Group and H8S/2456R Group]
The PG4 pin is a general I/O port and the
function can be switched with PG4DDR.
[H8S/2454 Group]
When the CS output enable bit (CS4E) is 1, the
PG4 pin functions as a CS4 output pin when the
PG4DDR is set to 1, and as an input port when
the bit is cleared to 0. When the CS output
enable bit (CS4E) is 0, the PG4 pin is a general
I/O port, and the function can be switched with
PG4DDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS
output pins when the corresponding PGDDR bit
is set to 1, and as input ports when the bit is
cleared to 0. When the CS output enable bits
(CS3E to CS0E) are cleared to 0, pins PG3 to
PG0 are I/O ports, and their functions can be
switched with PGDDR.
•
Modes 3 and 7 (EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their
functions can be switched with PGDDR.
Note:
*
PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 3, 4 and 7.
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Section 10 I/O Ports
10.15.2 Port G Data Register (PGDR)
PGDR stores output data for the port G pins.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
⎯
Reserved
This bit is always read as 0, and cannot be
modified.
6
PG6DR
0
R/W
5
PG5DR
0
R/W
4
PG4DR
0
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
Output data for a pin is stored when the pin
function is specified as a general purpose I/O.
10.15.3 Port G Register (PORTG)
PORTG shows the pin states of port G. PORTG cannot be modified.
Bit
Bit Name
Initial Value
R/W
7
⎯
Undefined
⎯
Description
Reserved
If this bit is read, it will return an undefined value.
6
PG6
⎯*
R
5
PG5
⎯*
R
4
PG4
⎯*
R
3
PG3
⎯*
R
2
PG2
⎯*
R
1
PG1
⎯*
R
0
PG0
⎯*
R
Note:
*
If this register is read while a PGDDR bit is set to 1,
the corresponding PGDR value is read. If this
register is read while a PGDDR bit is cleared to 0,
the corresponding pin state is read.
Determined by the states of pins PG6 to PG0.
Page 670 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.15.4 Port G Open Drain Control Register (PGODR)
PGODR specifies the output type of each port G pin.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
⎯
Reserved
This bit is always read as 0. Only the initial value
should be written to this bit.
6
PG6ODR
0
R/W
5
PG5ODR
0
R/W
4
PG4ODR
0
R/W
3
PG3ODR
0
R/W
2
PG2ODR
0
R/W
1
PG1ODR
0
R/W
0
PG0ODR
0
R/W
When not specified for BACK-A, BREQO-A, CS0,
2
1
CS1, CS2, CS3, CS4* , RAS2, RAS3, RAS* , or
1
CAS* output, setting a PGODR bit to 1 makes the
corresponding pin an NMOS open-drain output pin,
while clearing a PGODR bit to 0 makes the
corresponding pin a CMOS output pin.
Notes: 1. Not supported in the H8S/2456 and 2454 Groups.
2. Not supported in the H8S/2456 and 2456R Groups.
10.15.5 Pin Functions
Port G pins also function as the pins for bus control signal I/Os. The correspondence between the
register specification and the pin functions is shown below.
• PG6/BREQ-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit
PG6DDR.
Operating mode
1, 2, 4
⎯
EXPE
BRLE
BREQS
PG6DDR
Pin function
3, 7
BRLE = 0 or
BRLE = 1 and
BREQS = 1
0
1
⎯
BRLE = 1
and
BREQS = 0
BRLE = 0 or
BRLE = 1 and
BREQS = 1
0
1
⎯
0
1
0
PG6
input
PG6
output
BREQ-A
input
PG6
input
PG6
output
PG6
input
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
1
BRLE = 1
and
BREQS = 0
⎯
PG6 BREQ-A input
output
Page 671 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PG5/BACK-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BACKS in PFCR4, and bit
PG5DDR.
Operating
mode
1, 2, 4
⎯
EXPE
BRLE
BACKS
PG5DDR
Pin
function
3, 7
BRLE = 0 or
BRLE = 1 and
BACKS = 1
BRLE = 1
and
BACKS = 0
0
1
⎯
BRLE = 0 or
BRLE = 1 and
BACKS = 1
BRLE = 1
and
BACKS = 0
0
1
⎯
0
1
0
1
⎯
PG5
input
PG5
output
BACK-A
output
PG5
input
PG5
output
PG5 input
PG5
output
BACK-A
output
• PG4/BREQO-A/CS4*
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQOE, bit BREQOS in
PFCR4, bit SC4E in PFCR0, and bit PG4DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
BRLE
0
BREQOE
BREQOS
⎯
CS4E
PG4DDR
Pin function
Page 672 of 1408
0
1
BREQOE = 0 or BREQOE =
1 and BREQOS = 1
1
0
BREQOR = 1 and
BREQOS = 0
1
⎯
0
1
⎯
0
1
⎯
⎯
PG4
input
PG4
output
CS4
output*
PG4
input
PG4
output
CS4
output*
BREQO-A output
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• Modes 3 and 7 (EXPE = 0)
BRLE
⎯
BREQOE
BREQOS
⎯
CS4E
0
0
1
⎯
PG4 input
PG4 output
CS4 output*
PG4DDR
Pin function
Notes: *
1
Not supported in the H8S/2456 Group and H8S/2456R Group.
• PG3/CS3/RAS3/CAS*
The pin function is switched as shown below according to the combination of the operating
mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit
PG3DDR.
Operating
1, 2, 4
3, 7
mode
⎯
EXPE
CS3E
0
RMTS2 to
⎯
0
1
RMTS0
Area 3 is in
Area 3 is
Areas 2 to 5
normal space
in DRAM
are in
space
synchronous
1
⎯
0
⎯
⎯
1
Area 3 is in
Area 3 is
normal space in DRAM
space
DRAM* space
PG3DDR
0
Pin function
Note:
*
1
0
1
⎯
⎯
Areas 2 to 5
are in
synchronous
DRAM space
0
1
PG3
PG3
PG3
CS3
RAS3
CAS*
PG3
PG3
input
output
input
output
output
output
input
output
0
1
PG3
PG3
input output
0
1
⎯
⎯
PG3
CS3
RAS3
CAS*
input
output
output
output
Not supported in the H8S/2456 Group and H8S/2454 Group.
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Page 673 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PG2/CS2/ RAS2/RAS*
The pin function is switched as shown below according to the combination of the operating
mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit
PG2DDR.
Operating
1, 2, 4
3, 7
mode
⎯
EXPE
CS2E
0
RMTS2 to
⎯
0
1
RMTS0
Area 2 is in
Area 2 is in
Areas 2 to 5 are
normal space
DRAM space
in
and areas 2 to 5
synchronous
are in
DRAM* space
1
⎯
0
⎯
⎯
1
Area 2 is in
Area 2 is in
normal space
DRAM space
are in
and areas 2 to 5
synchronous
are in
DRAM space
synchronous
synchronous
DRAM space
PG2DDR
Pin function
1
0
1
PG2
PG2
PG2
CS2
input output input output
Note:
*
DRAM space
⎯
0
Areas 2 to 5
⎯
0
1
0
1
0
PG2
PG2
PG2
PG2
RAS2
RAS*
PG2
output
output
input output input output input
⎯
1
⎯
CS2
RAS2
RAS*
output
output
output
Not supported in the H8S/2456 Group and H8S/2454 Group.
• PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the combination of the operating
mode, bit CSnE in PFCR0, and bit PGnDDR.
Operating
mode
1, 2, 4
⎯
EXPE
CSnE
PGnDDR
Pin
function
3, 7
0
0
1
⎯
1
0
1
0
1
0
1
0
1
0
1
0
1
PGn
input
PGn
output
PGn
input
CSn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
[Legend]
n = 1 or 0
Page 674 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
10.16
Section 10 I/O Ports
Port H
Note: Port H is not supported in the H8S/2454 Group.
Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the
port function control registers, refer to section 10.18, Port Function Control Registers.
•
•
•
•
•
•
Port H data direction register (PHDDR)
Port H data register (PHDR)
Port H register (PORTH)
Port function control register 0 (PFCR0)
Port function control register 2 (PFCR2)
Port H open drain control register (PHODR)
10.16.1 Port H Data Direction Register (PHDDR)
The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
3
PH3DDR
0
W
•
2
PH2DDR
0
W
1
PH1DDR
0
W
0
PH0DDR
0
W
Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
Pin PH3 functions as the OE output pin when the
OE output enable bit (OEE) and OE output select
bit (OES) are set to 1. Otherwise, pin PH3
functions as the CS7 output pin when bit
PH3DDR is set to 1 while bit CS7E is 1, and as
an input port when the bit is cleared to 0. When
bit CS7E is cleared to 0, pin PH3 is an I/O port,
and its function can be switched with bit
PH3DDR. When areas 2 to 5 are specified as
continuous SDRAM space*, OE output is CKE
output.
Pin PH2 function as the CS6 output pin when bit
PH2DDR is set to 1 while bit CS6E is 1, and as
an I/O port when the bit is cleared to 0. When bit
CS6E is cleared to 0, pin PH2 is an I/O port, and
its function can be switched with bit PH2DDR.
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Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
0
PH0DDR
0
W
Description
Pin PH1 functions as the SDRAMφ* output pin
when the SDPSTP bit is 0 in the H8S/2456R
Group. In the H8S/2456 Group or when the
SDPSTP bit is 1 in the H8S/2456R Group, if bit
CS5E is set to 1 while area 5 is specified as
normal space, pin PH1 functions as the CS5
output pin when bit PH1DDR is set to 1, and
functions as an I/O port when the bit is cleared to
0. When bit CS5E is cleared to 0, pin PH1 is an
I/O port, and its function can be switched with bit
PH1DDR. When area 5 is specified as DRAM
space and bit CS5E is set to 1, pin PH1 functions
as the RAS5 output pin and as an I/O port when
the bit is cleared to 0.
Pin PH0 functions as the CS4 output pin when
area 4 is specified as normal space and bit
PH0DDR is set to 1. If bit PH0DDR is cleared to
0, pin PH0 functions as an I/O port. When bit
CS4E is cleared to 0, pin PH0 is an I/O port, and
its function can be switched with bit PH0DDR.
When area 4 is specified as DRAM space and bit
CS4E is set to 1, pin PH0 functions as the RAS4
output pin and as an I/O port when the bit is
cleared to 0. When areas 2 to 5 are specified as
continuous SDRAM space*, pin PH0 functions as
the WE output pin when bit CS4E is set to 1, and
as an I/O port when the bit is cleared to 0.
•
Modes 3 and 7 (EXPE = 0)
Pins PH3, PH2, and PH0 are I/O ports, and their
functions can be switched with PHDDR.
Pin PH1 functions as the SDRAMφ output pin
when the SDPSTP bit is 0 in the H8S/2456R
Group. In the H8S/2456 Group or when the
SDPSTP bit is 1 in the H8S/2456R Group, pin
PH1 is an I/O port and its function can be
switched with PHDDR.
Note:
*
Not supported in the H8S/2456 Group.
Page 676 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.16.2 Port H Data Register (PHDR)
PHDR stores output data for the port H pins.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
3
PH3DR
0
R/W
2
PH2DR
0
R/W
1
PH1DR
0
R/W
0
PH0DR
0
R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
10.16.3 Port H Register (PORTH)
PORTH shows the pin states of port H. PORTH cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
Undefined
⎯
Reserved
If these bits are read, they will return an undefined
value.
3
PH3
⎯*
R
2
PH2
⎯*
R
1
PH1
⎯*
R
0
PH0
⎯*
R
Note:
*
If this register is read while a PHDDR bit is set to 1,
the corresponding PHDR value is read. If this
register is read while a PHDDR bit is cleared to 0,
the corresponding pin state is read.
Determined by the states of pins PH3 to PH0.
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Page 677 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.16.4 Port H Open Drain Control Register (PHODR)
PHODR specifies the output type of each port H pin.
Bit
Bit Name
7 to 4 ⎯
Initial Value
R/W
Description
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
3
PH3ODR
0
R/W
2
PH2ODR
0
R/W
1
PH1ODR
0
R/W
0
PH0ODR
0
R/W
Note:
*
When not specified for CS4, CS5, CS6, CS7,
OE-A, CKE-A*, RAS4, RAS5, WE*, or SDRAMφ*
output, setting a PHODR bit to 1 makes the
corresponding pin an NMOS open-drain output pin,
while clearing a PHODR bit to 0 makes the
corresponding pin a CMOS output pin.
Not supported in the H8S/2456 Group.
Page 678 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
10.16.5 Pin Functions
Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence
between the register specification and the pin functions is shown below.
• PH3/CS7/OE-A/CKE-A*2/IRQ7-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit OEE of the bus controller, bit OES in PFCR2, bit CS7E in PFCR0, and bit
PH3DDR.
• Modes 1, 2, and 4
Modes 3 and 7 (EXPE = 1)
OEE
0
OES
⎯
0
1
RMTS2 to
RMTS0
⎯
⎯
Any of Areas 2 to
areas 2 to 5 are syn5 is
chronous
DRAM
DRAM
space
space
⎯
⎯
0
1
0
1
0
1
0
1
⎯
⎯
PH3
input
PH3
output
PH3
input
CS7
output
PH3
input
PH3
output
PH3
input
CS7
output
OE-A
output
CKE-A*2
output
CS7E
PH3DDR
Pin
function
1
0
1
0
1
IRQ7-B input*1
• Modes 3 and 7 (EXPE = 0)
OEE
⎯
OES
⎯
RMTS2 to RMTS0
⎯
CS7E
⎯
PH3DDR
Pin function
0
1
PH3 input
PH3 output
IRQ7-B input*
1
Notes: 1. IRQ7-B input when the ITS7 bit in ITSR is 1.
2. Not supported in the H8S/2456 Group.
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Page 679 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PH2/CS6/IRQ6-B
The pin function is switched as shown below according to the combination of the operating
mode, bit CS6E in PFCR0, and bit PH2DDR.
Operating
mode
1, 2, 4
⎯
EXPE
CS6E
0
0
PH2DDR
Pin
function
Note:
3, 7
*
1
⎯
1
0
0
1
0
1
0
1
PH2
input
PH2
output
PH2
input
CS6
output
PH2
input
PH2
output
0
PH2
input
IRQ6-B interrupt input*
1
1
0
1
PH2
output
PH2
input
CS6
output
IRQ6-B input when the ITS6 bit in ITSR is 1.
• PH1/CS5/RAS5/SDRAMφ*
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in
SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR.
SDPSTP
1
Operating
0
1, 2, 4
⎯
3, 7
mode
⎯
EXPE
RMTS2 to
Area 5 is normal space
0
RMTS0
Area 5 is normal space
Area 5 is DRAM
space
CS5E
0
PH1DDR
1
0
1
0
1
0
1
Pin
PH1
PH1
PH1
CS5
PH1
PH1
function
input output input output input output
*
⎯
space
⎯
1
0
Note:
⎯
1
⎯
Area 5 is DRAM
⎯
0
1
0
1
⎯
⎯
⎯
0
1
0
1
0
1
0
1
RAS5
PH1
PH1
PH1
PH1
PH1
CS5
PH1
PH1
output
input output input output input output input output output
RAS5 SDRAMφ
output*
Not supported in the H8S/2456 Group.
Page 680 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
• PH0/CS4/RAS4/WE*
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in
PFCR0, and bit PH0DDR.
Operating
1, 2, 4
3, 7
mode
⎯
EXPE
CS4E
0
RMTS2 to
⎯
0
1
RMTS0
Area 4 is
Area 4
Areas 2
normal space
is
to 5 are
DRAM
syn-
1
⎯
0
⎯
⎯
1
Area 4 is
normal space
space chronous
Area 4 Areas 2
is
to 5 are
DRAM
syn-
space chronous
DRAM
DRAM
space
0
PH0DDR
Pin
PH0
function
input
Note:
*
1
0
1
⎯
PH0
PH0
CS4
RAS4
output input output output
space
⎯
WE*
output
0
1
PH0
PH0
input output
0
PH0
input
1
0
1
⎯
PH0
PH0
CS4
RAS4
output input output output
⎯
WE*
output
Not supported in the H8S/2456 Group.
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Section 10 I/O Ports
10.17
Port J
Note: Port J is not supported in the H8S/2454 Group and in the 145-pin package.
Port J is a 3-bit I/O port. Port J has the following registers.
•
•
•
•
Port J data direction register (PJDDR)
Port J data register (PJDR)
Port J register (PORT3)
Port J open drain control register (PJODR)
10.17.1 Port J Data Direction Register (PJDDR)
The individual bits of PJDDR specify input or output for the pins of port J. PJDDR cannot be read;
if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7 to 2
⎯
All 0
⎯
Reserved
1
PJ1DDR
0
W
0
PJ0DDR
0
W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
10.17.2 Port J Data Register (PJDR)
PJDR stores output data for the port J pins.
Bit
Bit Name
Initial Value
R/W
7 to 2
⎯
All 0
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
1
PJ1DR
0
R/W
0
PJ0DR
0
R/W
Page 682 of 1408
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
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Section 10 I/O Ports
10.17.3 Port J Register (PORTJ)
PORTJ shows the pin states of port J. PORTJ cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7 to 3
⎯
Undefined
⎯
Reserved
If these bits are read, they will return an undefined
value.
2
PJ2
⎯*
R
The pin state is always read from this register.
1
PJ1
⎯*
R
0
PJ0
⎯*
R
If this register is read, the PJDR values are read for
the bits with the corresponding PJDDR bits set to 1.
For the bits with the corresponding PJDDR bits
cleared to 0, the pin states are read.
Note:
*
Determined by the state of pins PJ0 to PJ2.
10.17.4 Port J Open Drain Control Register (PJODR)
PJODR specifies the output type of each port J pin.
Bit
Bit Name
7 to 2 ⎯
Initial Value
R/W
Description
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
1
PJ1ODR
0
R/W
0
PJ0ODR
0
R/W
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Setting a PJODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a PJODR bit to 0 makes the corresponding pin a
CMOS output pin.
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Section 10 I/O Ports
10.17.5 Pin Functions
Port J pins function only as I/O ports. The correspondence between the register specification and
the pin functions is shown below.
• PJ2
The PJ2 pin is an input-only pin.
Pin function
PJ2 input
• PJ1, PJ0
The pin function is switched as shown below according to bit PJnDDR.
PJnDDR
Pin function
0
1
PJn input
PJn output
[Legend]
n = 1 or 0
Page 684 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
10.18
Section 10 I/O Ports
Port Function Control Registers
The port function controller performs I/O port control. The setting of input or output for each pin
should be enabled only after the input or output destination has been selected.
The port function controller has the following registers.
•
•
•
•
•
•
Port function control register 0 (PFCR0)
Port function control register 1 (PFCR1)
Port function control register 2 (PFCR2)
Port function control register 3 (PFCR3)
Port function control register 4 (PFCR4)
Port function control register 5 (PFCR5)
10.18.1 Port Function Control Register 0 (PFCR0)
PFCR0 switches the functions of the chip select output pins.
Bit
Bit Name
Initial Value
R/W
Description
7
CS7E
1
R/W
CS7 to CS0 Enable
6
CS6E
1
R/W
5
CS5E
1
R/W
These bits enable or disable the corresponding
CSn output.
4
CS4E
1
R/W
3
CS3E
1
R/W
2
CS2E
1
R/W
1
CS1E
1
R/W
0
CS0E
1
R/W
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
0: Pin is designated as I/O port
1: Pin is designated as CSn output pin
(n = 7 to 0)
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Section 10 I/O Ports
10.18.2 Port Function Control Register 1 (PFCR1)
PFCR1 enables or disables address output (A23 to A16).
Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
A23E
1
R/W
Address 23 Enable
Enables or disables output for address output 23
(A23).
0: DR output when PA7DDR = 1
1: A23 output when PA7DDR = 1
6
A22E
1
R/W
Address 22 Enable
Enables or disables output for address output 22
(A22).
0: DR output when PA6DDR = 1
1: A22 output when PA6DDR = 1
5
A21E
1
R/W
Address 21 Enable
Enables or disables output for address output 21
(A21).
0: DR output when PA5DDR = 1
1: A21 output when PA5DDR = 1
4
A20E
1
R/W
Address 20 Enable
Enables or disables output for address output 20
(A20).
0: DR output when PA4DDR = 1
1: A20 output when PA4DDR = 1
3
A19E
1
R/W
Address 19 Enable
Enables or disables output for address output 19
(A19).
0: DR output when PA3DDR = 1
1: A19 output when PA3DDR = 1
2
A18E
1
R/W
Address 18 Enable
Enables or disables output for address output 18
(A18).
0: DR output when PA2DDR = 1
1: A18 output when PA2DDR = 1
Page 686 of 1408
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Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
1
A17E
1
R/W
Address 17 Enable
Enables or disables output for address output 17
(A17).
0: DR output when PA1DDR = 1
1: A17 output when PA1DDR = 1
0
A16E
1
R/W
Address 16 Enable
Enables or disables output for address output 16
(A16).
0: DR output when PA0DDR = 1
1: A16 output when PA0DDR = 1
10.18.3 Port Function Control Register 2 (PFCR2)
PFCR2 enables or disables AS output, LWR output, and OE output.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
3
ASOE
1
R/W
AS Output Enable
Enables or disables the AS output pin.
0: PF6 is designated as I/O port
1: PF6 is designated as AS output pin
2
LWROE
1
R/W
LWR Output Enable
Enables or disables the LWR output pin.
0: PF3 is designated as I/O port
1: PF3 is designated as LWR output pin
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Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
1
OES
1
R/W
OE Output Select
Selects the OE/CKE* output pin port when the OEE
bit in DRAMCR is set to 1 (enabling OE/CKE*
output).
0: P35 is designated as OE-B/CKE-B*1 output pin.
1: [For H8S/2456 Group and H8S/2456R Group]
PH3 is designated as OE-A/CKE-A* output pin.
[For H8S/2454 Group]
PH0 is designated as OE-A output pin.
0
⎯
0
⎯
Reserved
This bit is always read as 0. Only the initial value
should be written to this bit.
Note:
*
Not supported in the H8S/2456 and H8S/2454 Groups.
10.18.4 Port Function Control Register 3 (PFCR3)
PFCR3 enables or disables DMAC activation interrupts from the USB, and switches the functions
of the PPG output pin, TPU input/output pin, and TMR input/output pin.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
1
⎯
Reserved
This bit is always read as 1. Only the initial value
should be written to this bit.
6
PPGS
0
R/W
PPG Pin Select
Selects the output pins of PO5 to PO0.
0: P25/PO5-A and P20/PO0-A are selected.
1: P85/PO5-B, P52/PO4-B, P83/PO3-B, P51/PO2B, P81/PO1-B, and P50/PO0-B are selected.
5
TPUS
0
R/W
TPU Pin Select
Selects the output pins of TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, and TIOCB4.
0: P25/TIOCB4-A and P20/TIOCA3-A are selected.
1: P85/TIOCB4-B, P52/TIOCA4-B, P83/TIOCD3-B,
P51/TIOCC3-B, P81/TIOCB3-B, and
P50/TIOCA3-B are selected.
Page 688 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
4
TMRS
0
R/W
TMR Pin Select
Selects the output pins of TMO1 and TMO0 and
input pins of TMCI1, TMCI0, TMRI1, and TMRI0.
0: [For H8S/2456 Group and H8S/2456R Group]
P65/TMO1-A, P64/TMO0-A, P63/TMCI1-A,
P62/TMCI0-A, P61/TMRI1-A, and P60/TMRI0-A
are selected.
[For H8S/2454 Group]
P25/TMO1-A and P20/TMRI0-A are selected.
1: P85/TMO1-B, P52/TMO0-B, P83/TMCI1-B,
P51/TMCI0-B, P81/TMRI1-B, and P50/TMRI0-B
are selected.
3, 2
⎯
All 0
⎯
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
1
USBDRQE
0
R/W
USB-DMAC Activation Interrupt Enable
Enables or disables interrupt to activate the DMAC
(USBINTN) from the USB.
0: The DREQ signal from the DREQ pin is set as a
data transfer activation source.
1: The DMAC activation interrupt signal from the
USB is set as a data transfer activation source.
0
⎯
1
⎯
Reserved
This bit is always read as 1. Only the initial value
should be written to this bit.
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Page 689 of 1408
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Section 10 I/O Ports
10.18.5 Port Function Control Register 4 (PFCR4)
PFCR4 switches the functions of the WAIT input pin, BREQ input pin, BACK output pin,
BREQO output pin, TxD4 output pin, RxD4 input pin, and SCK4 input/output pin.
Bit
Bit Name
Initial Value
R/W
Description
7
WAITS
0
R/W
WAIT Pin Select
Selects the WAIT input pin.
0: PF0/WAIT-A is selected
1: P25/WAIT-B is selected
6
BREQS
0
R/W
BREQ Pin Select
Selects the BREQ input pin.
0: PG6/BREQ-A is selected
1: P51/BREQ-B is selected
5
BACKS
0
R/W
BACK Pin Select
Selects the BACK output pin.
0: PG5/BACK-A is selected
1: P52/BACK-B is selected
4
BREQOS
0
R/W
BREQO Pin Select
Selects the BREQO output pin.
0: PG4/BREQO-A is selected
1: P50/BREQO-B is selected
3
⎯
0
⎯
Reserved
This bit is read as 0. When written, the initial value
should be written to.
2
TXD4S
0
R/W
Enables TxD4-B output.
Enables or disables TxD4-B output.
0: PA1 is designated as I/O port.
1: PA1 is designated as TxD4-B output pin.
Page 690 of 1408
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Section 10 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
1
RXD4S
0
R/W
Enables RxD4-B input.
Enables or disables RxD4-B input.
0: PA2 is designated as I/O port.
1: PA2 is designated as RxD4-B output pin.
0
SCK4S
0
R/W
SCK4 Pin Select
Selects the SCK4 input/output pin.
0: P34/SCK4-A is selected
1: PA3/SCK4-B is selected
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Section 10 I/O Ports
10.18.6 Port Function Control Register 5 (PFCR5)
PFCR5 switches the functions of the SSU input/output pins.
Bit
Bit Name
Initial Value
R/W
Description
7
SSO0S1
0
R/W
SSO0 Pin Select
6
SSO0S0
0
R/W
Selects the SSO0 input/output pin.
00: P14/SSO0-A is selected
01: PA7/SSO0-B is selected
10: PF3/SSO0-C is selected
11: Setting prohibited
5
SSI0S1
0
R/W
SSI0 Pin Select
4
SSI0S0
0
R/W
Selects the SSI0 input/output pin.
00: P15/SSI0-A is selected
01: PA6/SSI0-B is selected
10: PF2/SSI0-C is selected
11: Setting prohibited
3
SSCK0S1
0
R/W
SSCK0 Pin Select
2
SSCK0S0
0
R/W
Selects the SSCK0 input/output pin.
00: P16/SSCK0-A is selected
01: PA5/SSCK0-B is selected
10: PF1/SSCK0-C is selected
11: Setting prohibited
1
SCS0S1
0
R/W
SCS0 Pin Select
0
SCS0S0
0
R/W
Selects the SCS0 input/output pin.
00: P17/SCS0-A is selected
01: PA4/SCS0-B is selected
10: PF0/SCS0-C is selected
11: Setting prohibited
Page 692 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 11 16-Bit Timer Pulse Unit (TPU)
Section 11 16-Bit Timer Pulse Unit (TPU)
This LSI has two on-chip 16-bit timer pulse units (TPU: unit 0 and unit 1) which each comprises
six 16-bit timer channels, resulting in a total of 12 channels. The functions of unit 0 are listed in
table 11.1, and the functions of unit 1 are listed in table 11.2. The block diagram of unit 0 is shown
in figure 11.1 and the block diagram of unit 1 is shown in figure 11.2.
The descriptions in this section refer to unit 0.
11.1
Features
• Maximum 32-pulse input/output (unit 0: 16, unit 1: 16, when the EXPE bit is 0 in single-chip
mode)
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
⎯ Waveform output at compare match
⎯ Input capture function
⎯ Counter clear operation
⎯ Synchronous operations:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
⎯ Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 (6) and 3 (9)
• Phase counting mode settable independently for each of channels 1 (7), 2 (8), 4 (10), and 5
(11)
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources (per unit)
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated (only by unit 0)
• A/D converter conversion start trigger can be generated.
• Module stop state can be set.
• Activation of the DMAC (only by unit 0) and DTC
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.1 TPU (Unit 0) Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
General registers/
buffer registers
TGRC_0
TGRD_0
⎯
⎯
TGRC_3
TGRD_3
⎯
⎯
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
⎯
⎯
Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation
Page 694 of 1408
⎯
⎯
⎯
⎯
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Item
Channel 0
Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
DTC
TGR
activation compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
DMAC
TGRA_0
activation compare
match or
input capture
TGRA_1
compare
match or
input capture
TGRA_2
compare
match or
input capture
TGRA_3
compare
match or
input capture
TGRA_4
compare
match or
input capture
TGRA_5
compare
match or
input capture
A/D
TGRA_0
converter compare
trigger
match or
input capture
TGRA_1
compare
match or
input capture
TGRA_2
compare
match or
input capture
TGRA_3
compare
match or
input capture
TGRA_4
compare
match or
input capture
TGRA_5
compare
match or
input capture
PPG
trigger
TGRA_0/
TGRB_0
compare
match or
input capture
TGRA_1/
TGRB_1
compare
match or
input capture
TGRA_2/
TGRB_2
compare
match or
input capture
TGRA_3/
⎯
TGRB_3
compare
match or
input capture
⎯
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
• Compare
match or
input
capture 0A
• Compare
match or
input
capture 1A
• Compare
match or
input
capture 2A
• Compare
match or
input
capture 3A
• Compare
match or
input
capture 4A
• Compare
match or
input
capture 5A
• Compare
match or
input
capture 0B
• Compare
match or
input
capture 1B
• Compare
match or
input
capture 2B
• Compare
match or
input
capture 3B
• Compare
match or
input
capture 4B
• Compare
match or
input
capture 5B
• Compare
match or
input
capture 0C
• Overflow
• Overflow
• Overflow
• Overflow
• Underflow
• Underflow
• Compare
match or
input
capture 3C
• Underflow
• Underflow
• Compare
match or
input
capture 0D
• Compare
match or
input
capture 3D
• Overflow
• Overflow
[Legend]
:
Possible
⎯:
Not possible
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.2 TPU (Unit 1) Functions
Item
Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKE
TCLKF
TCLKG
TCLKH
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKE
TCLKF
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKE
TCLKF
TCLKG
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKE
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKE
TCLKG
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKE
TCLKG
TCLKH
General registers
(TGR)
TGRA_6
TGRB_6
TGRA_7
TGRB_7
TGRA_8
TGRB_8
TGRA_9
TGRB_9
TGRA_10
TGRB_10
TGRA_11
TGRB_11
General registers/
buffer registers
TGRC_6
TGRD_6
⎯
⎯
TGRC_9
TGRD_9
⎯
⎯
I/O pins*1
TIOCA6
TIOCB6
TIOCC6
TIOCD6
TIOCA7
TIOCB7
TIOCA8
TIOCB8
TIOCA9*2
TIOCB9
TIOCC9
TIOCD9
TIOCA10
TIOCB10
TIOCA11
TIOCB11
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
⎯
⎯
Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation
Page 696 of 1408
⎯
⎯
⎯
⎯
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Item
Channel 6
Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
DTC
TGR
activation compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
DMAC
⎯
activation
⎯
⎯
⎯
⎯
⎯
A/D
TGRA_6
converter compare
trigger
match or
input capture
TGRA_7
compare
match or
input capture
TGRA_8
compare
match or
input capture
TGRA_9
compare
match or
input capture
TGRA_10
compare
match or
input capture
TGRA_11
compare
match or
input capture
PPG
trigger
⎯
⎯
⎯
⎯
⎯
⎯
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
• Compare
match or
input
capture 6A
• Compare
match or
input
capture 7A
• Compare
match or
input
capture 8A
• Compare
match or
input
capture 9A
• Compare
match or
input
capture 6B
• Compare
match or
input
capture 7B
• Compare
match or
input
capture 8B
• Compare
match or
input
capture 9B
• Compare
match or
input
capture
10A
• Compare
match or
input
capture
11A
• Overflow
• Compare
match or
input
capture
10B
• Compare
match or
input
capture 6D
• Compare
match or
• Overflow
input
capture 9C • Underflow
• Compare
match or
input
capture 9D
• Compare
match or
input
capture
11B
• Overflow
• Overflow
• Compare
• Overflow
match or
• Underflow
input
capture 6C
• Underflow
• Overflow
• Underflow
[Legend]
:
Possible
⎯:
Not possible
Notes: 1. When the EXPE bit is 0 in single-chip mode.
2. TIOCA9-B pin can be used even when EXPE = 1 in single-chip mode. For details, refer
to section 10, I/O Port.
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TGRD
TGRB
TGRC
TGRB
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
A/D conversion start request signal
TGRD
TGRB
TGRB
TGRB
PPG output trigger signal
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
TGRA
Module data bus
TGRA
TSR
TSR
TIER
TSR
TIER
TIOR
TIORH TIORL
TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRA
TSR
TIER
TSR
TSTR TSYR
TIER
TSR
TIER
TIOR
TIOR
TIOR
TIER
TMDR
TIORH TIORL
TCR
TMDR
Channel 4
TCR
TMDR
Channel 5
TCR
Control logic
TMDR
TCR
TMDR
Channel 1
Channel 0
TCR
Common
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 2
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 0 to 2
Input/output pins
TIOCA0
Channel 0:
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Channel 1:
TIOCB1
TIOCA2
Channel 2:
TIOCB2
TCR
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Control logic for channels 3 to 5
Input/output pins
Channel 3:
TIOCA3
TIOCB3
TIOCC3
TIOCD3
Channel 4:
TIOCA4
TIOCB4
Channel 5:
TIOCA5
TIOCB5
Channel 3
Section 11 16-Bit Timer Pulse Unit (TPU)
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 11.1 Block Diagram of TPU (Unit 0)
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TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRD
TGRB
TGRC
TGRB
Interrupt request signals
Channel 9: TGI9A
TGI9B
TGI9C
TGI9D
TCI9V
Channel 10: TGI10A
TGI10B
TCI10V
TCI10U
Channel 11: TGI11A
TGI11B
TCI11V
TCI11U
Internal data bus
TGRD
TGRB
TGRB
TGRB
A/D conversion start request signal
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
Module data bus
TGRA
TGRA
TSR
TIER
TSR
TIER
TSR
TIER
TSTR TSYR
TSR
TIER
TSR
TIER
TIOR
TIORH TIORL
TSR
TIER
TMDR
TIORH TIORL
TIOR
TIOR
TIOR
Channel 9
TCR
TMDR
Channel 10
TCR
TMDR
Channel 11
TCR
Control logic
TMDR
TCR
TMDR
Channel 7
Channel 8
TCR
Common
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 6
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 6 to 8
Input/output pins
TIOCA6
Channel 6:
TIOCB6
TIOCC6
TIOCD6
TIOCA7
Channel 7:
TIOCB7
TIOCA8
Channel 8:
TIOCB8
TCR
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock: TCLKE
TCLKF
TCLKG
TCLKH
Control logic for channels 9 to 11
Input/output pins
Channel 9:
TIOCA9
TIOCB9
TIOCC9
TIOCD9
Channel 10: TIOCA10
TIOCB10
Channel 11: TIOCA11
TIOCB11
Section 11 16-Bit Timer Pulse Unit (TPU)
Interrupt request signals
Channel 6: TGI6A
TGI6B
TGI6C
TGI6D
TCI6V
Channel 7: TGI7A
TGI7B
TCI7V
TCI7U
Channel 8: TGI8A
TGI8B
TCI8V
TCI8U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 11.2 Block Diagram of TPU (Unit 1)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.2
Input/Output Pins
Table 11.3 Pin Configuration
Unit
Channel
Symbol
I/O
Function
0
All
TCLKA
Input
External clock A input pin
(Channel 1 and 5 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channel 1 and 5 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channel 2 and 4 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channel 2 and 4 phase counting mode B phase input)
TIOCA0
I/O
TGRA_0 input capture input/output compare output/
PWM output pin
TIOCB0
I/O
TGRB_0 input capture input/output compare output/
PWM output pin
TIOCC0
I/O
TGRC_0 input capture input/output compare output/
PWM output pin
TIOCD0
I/O
TGRD_0 input capture input/output compare output/
PWM output pin
TIOCA1
I/O
TGRA_1 input capture input/output compare output/
PWM output pin
TIOCB1
I/O
TGRB_1 input capture input/output compare output/
PWM output pin
TIOCA2
I/O
TGRA_2 input capture input/output compare output/
PWM output pin
TIOCB2
I/O
TGRB_2 input capture input/output compare output/
PWM output pin
TIOCA3
I/O
TGRA_3 input capture input/output compare output/
PWM output pin
TIOCB3
I/O
TGRB_3 input capture input/output compare output/
PWM output pin
TIOCC3
I/O
TGRC_3 input capture input/output compare output/
PWM output pin
TIOCD3
I/O
TGRD_3 input capture input/output compare output/
PWM output pin
0
1
2
3
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Section 11 16-Bit Timer Pulse Unit (TPU)
Unit
Channel
Symbol
I/O
Function
0
4
TIOCA4
I/O
TGRA_4 input capture input/output compare output/
PWM output pin
TIOCB4
I/O
TGRB_4 input capture input/output compare output/
PWM output pin
TIOCA5
I/O
TGRA_5 input capture input/output compare output/
PWM output pin
TIOCB5
I/O
TGRB_5 input capture input/output compare output/
PWM output pin
TCLKE
Input
External clock E input pin
(Channel 7 and 11 phase counting mode A phase input)
TCLKF
Input
External clock F input pin
(Channel 7 and 11 phase counting mode B phase input)
TCLKG
Input
External clock G input pin
(Channel 8 and 10 phase counting mode A phase input)
TCLKH
Input
External clock H input pin
(Channel 8 and 10 phase counting mode B phase input)
TIOCA6
I/O
TGRA_6 input capture input/output compare output/
PWM output pin
TIOCB6
I/O
TGRB_6 input capture input/output compare output/
PWM output pin
TIOCC6
I/O
TGRC_6 input capture input/output compare output/
PWM output pin
TIOCD6
I/O
TGRD_6 input capture input/output compare output/
PWM output pin
TIOCA7
I/O
TGRA_7 input capture input/output compare output/
PWM output pin
TIOCB7
I/O
TGRB_7 input capture input/output compare output/
PWM output pin
TIOCA8
I/O
TGRA_8 input capture input/output compare output/
PWM output pin
TIOCB8
I/O
TGRB_8 input capture input/output compare output/
PWM output pin
5
1*
All
6
7
8
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Section 11 16-Bit Timer Pulse Unit (TPU)
Unit
Channel
Symbol
I/O
Function
1*
9
TIOCA9
I/O
TGRA_9 input capture input/output compare output/
PWM output pin
TIOCB9
I/O
TGRB_9 input capture input/output compare output/
PWM output pin
TIOCC9
I/O
TGRC_9 input capture input/output compare output/
PWM output pin
TIOCD9
I/O
TGRD_9 input capture input/output compare output/
PWM output pin
TIOCA10
I/O
TGRA_10 input capture input/output compare
output/PWM output pin
TIOCB10
I/O
TGRB_10 input capture input/output compare
output/PWM output pin
TIOCA11
I/O
TGRA_11 input capture input/output compare
output/PWM output pin
TIOCB11
I/O
TGRB_11 input capture input/output compare
output/PWM output pin
10
11
Note:
*
The input and output functions of unit 1 are only available when EXPE = 0 in single-chip
mode.
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11.3
Section 11 16-Bit Timer Pulse Unit (TPU)
Register Descriptions
The TPU has the following registers in each channel. The descriptions in this section refer to the
registers of unit 0.
Unit 0:
Channel 0
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control register H_0 (TIORH_0)
• Timer I/O control register L_0 (TIORL_0)
• Timer interrupt enable register_0 (TIER_0)
• Timer status register_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer general register A_0 (TGRA_0)
• Timer general register B_0 (TGRB_0)
• Timer general register C_0 (TGRC_0)
• Timer general register D_0 (TGRD_0)
Channel 1
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register_1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer general register A_1 (TGRA_1)
• Timer general register B_1 (TGRB_1)
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Section 11 16-Bit Timer Pulse Unit (TPU)
H8S/2456, H8S/2456R, H8S/2454 Group
Channel 2
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control register_2 (TIOR_2)
• Timer interrupt enable register_2 (TIER_2)
• Timer status register_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_2)
• Timer general register B_2 (TGRB_2)
Channel 3
• Timer control register_3 (TCR_3)
• Timer mode register_3 (TMDR_3)
• Timer I/O control register H_3 (TIORH_3)
• Timer I/O control register L_3 (TIORL_3)
• Timer interrupt enable register_3 (TIER_3)
• Timer status register_3 (TSR_3)
• Timer counter_3 (TCNT_3)
• Timer general register A_3 (TGRA_3)
• Timer general register B_3 (TGRB_3)
• Timer general register C_3 (TGRC_3)
• Timer general register D_3 (TGRD_3)
Channel 4
• Timer control register_4 (TCR_4)
• Timer mode register_4 (TMDR_4)
• Timer I/O control register_4 (TIOR_4)
• Timer interrupt enable register_4 (TIER_4)
• Timer status register_4 (TSR_4)
• Timer counter_4 (TCNT_4)
• Timer general register A_4 (TGRA_4)
• Timer general register B_4 (TGRB_4)
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Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 5
• Timer control register_5 (TCR_5)
• Timer mode register_5 (TMDR_5)
• Timer I/O control register_5 (TIOR_5)
• Timer interrupt enable register_5 (TIER_5)
• Timer status register_5 (TSR_5)
• Timer counter_5 (TCNT_5)
• Timer general register A_5 (TGRA_5)
• Timer general register B_5 (TGRB_5)
Common Registers of Unit 0
• Timer start register (TSTR)
• Timer synchronous register (TSYR)
Unit 1:
Channel 6
• Timer control register_6 (TCR_6)
• Timer mode register_6 (TMDR_6)
• Timer I/O control register H_6 (TIORH_6)
• Timer I/O control register L_6 (TIORL_6)
• Timer interrupt enable register_6 (TIER_6)
• Timer status register_6 (TSR_6)
• Timer counter_6 (TCNT_6)
• Timer general register A_6 (TGRA_6)
• Timer general register B_6 (TGRB_6)
• Timer general register C_6 (TGRC_6)
• Timer general register D_6 (TGRD_6)
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Section 11 16-Bit Timer Pulse Unit (TPU)
H8S/2456, H8S/2456R, H8S/2454 Group
Channel 7
• Timer control register_7 (TCR_7)
• Timer mode register_7 (TMDR_7)
• Timer I/O control register_7 (TIOR_7)
• Timer interrupt enable register_7 (TIER_7)
• Timer status register_7 (TSR_7)
• Timer counter_7 (TCNT_7)
• Timer general register A_7 (TGRA_7)
• Timer general register B_7 (TGRB_7)
Channel 8
• Timer control register_8 (TCR_8)
• Timer mode register_8 (TMDR_8)
• Timer I/O control register_8 (TIOR_8)
• Timer interrupt enable register_8 (TIER_8)
• Timer status register_8 (TSR_8)
• Timer counter_8 (TCNT_8)
• Timer general register A_8 (TGRA_8)
• Timer general register B_8 (TGRB_8)
Channel 9
• Timer control register_9 (TCR_9)
• Timer mode register_9 (TMDR_9)
• Timer I/O control register H_9 (TIORH_9)
• Timer I/O control register L_9 (TIORL_9)
• Timer interrupt enable register_9 (TIER_9)
• Timer status register_9 (TSR_9)
• Timer counter_9 (TCNT_9)
• Timer general register A_9 (TGRA_9)
• Timer general register B_9 (TGRB_9)
• Timer general register C_9 (TGRC_9)
• Timer general register D_9 (TGRD_9)
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Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 10
• Timer control register_10 (TCR_10)
• Timer mode register_10 (TMDR_10)
• Timer I/O control register_10 (TIOR_10)
• Timer interrupt enable register_10 (TIER_10)
• Timer status register_10 (TSR_10)
• Timer counter_10 (TCNT_10)
• Timer general register A_10 (TGRA_10)
• Timer general register B_10 (TGRB_10)
Channel 11
• Timer control register_11 (TCR_11)
• Timer mode register_11 (TMDR_11)
• Timer I/O control register_11 (TIOR_11)
• Timer interrupt enable register_11 (TIER_11)
• Timer status register_11 (TSR_11)
• Timer counter_11 (TCNT_11)
• Timer general register A_11 (TGRA_11)
• Timer general register B_11 (TGRB_11)
Common Registers of Unit 1
• Timer start register B (TSTRB)
• Timer synchronous register B (TSYRB)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.1
Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel. TCR register settings should be made only when TCNT operation
is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7
CCLR2
0
R/W
Counter Clear 2 to 0
6
CCLR1
0
R/W
5
CCLR0
0
R/W
These bits select the TCNT counter clearing
source. See tables 11.4 and 11.5 for details.
4
CKEG1
0
R/W
Clock Edge 1 and 0
3
CKEG0
0
R/W
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and
the phase counting mode setting has priority.
Internal clock edge selection is valid when the
input clock is φ/4 or slower. This setting is ignored
if the input clock is φ/1, or when
overflow/underflow of another channel is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
[Legend]
x:
Don't care
2
TPSC2
0
R/W
Time Prescaler 2 to 0
1
TPSC1
0
R/W
0
TPSC0
0
R/W
These bits select the TCNT counter clock. The
clock source can be selected independently for
each channel. See tables 11.6 to 11.11 for details.
Page 708 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.4 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/
input capture
0
TCNT cleared by TGRB compare match/
input capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/
2
input capture*
0
TCNT cleared by TGRD compare match/
input capture*2
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
1
1
0
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 11.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
Bit 7
Reserved*2
Bit 6
CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/
input capture
0
TCNT cleared by TGRB compare match/
input capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.6 TPSC2 to TPSC0 (Channel 0)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
1
1
0
1
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
Table 11.7 TPSC2 to TPSC0 (Channel 1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Counts on TCNT2 overflow/underflow
1
1
0
1
Note: This setting is ignored when channel 1 is in phase counting mode.
Page 710 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.8 TPSC2 to TPSC0 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
1
1
0
1
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 11.9 TPSC2 to TPSC0 (Channel 3)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
Internal clock: counts on φ/1024
0
Internal clock: counts on φ/256
1
Internal clock: counts on φ/4096
1
1
0
1
R01UH0309EJ0500 Rev. 5.00
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.10 TPSC2 to TPSC0 (Channel 4)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
4
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
1
1
0
1
0
Internal clock: counts on φ/1024
1
Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 11.11 TPSC2 to TPSC0 (Channel 5)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
5
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/256
1
External clock: counts on TCLKD pin input
1
1
0
1
Note: This setting is ignored when channel 5 is in phase counting mode.
Page 712 of 1408
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11.3.2
Section 11 16-Bit Timer Pulse Unit (TPU)
Timer Mode Register (TMDR)
TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR
registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
1
⎯
Reserved
6
⎯
1
⎯
These bits are always read as 1 and cannot be
modified.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the
normal way, or TGRB and TGRD are to be used
together for buffer operation. When TGRD is used
as a buffer register, TGRD input capture/output
compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD,
bit 5 is reserved. It is always read as 0 and cannot
be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the
normal way, or TGRA and TGRC are to be used
together for buffer operation. When TGRC is used
as a buffer register, TGRC input capture/output
compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC,
bit 4 is reserved. It is always read as 0 and cannot
be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer
operation
3
MD3
0
R/W
Modes 3 to 0
2
MD2
0
R/W
1
MD1
0
R/W
These bits are used to set the timer operating
mode.
0
MD0
0
R/W
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
MD3 is a reserved bit. The write value should
always be 0. See table 11.12 for details.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.12 MD3 to MD0
Bit 3
1
MD3*
Bit 2
MD2*2
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
1
1
0
1
1
x
x
0
Phase counting mode 3
1
Phase counting mode 4
x
⎯
[Legend]
x:
Don't care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
Page 714 of 1408
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11.3.3
Section 11 16-Bit Timer Pulse Unit (TPU)
Timer I/O Control Register (TIOR)
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit
Bit Name
Initial Value
R/W
Description
7
IOB3
0
R/W
I/O Control B3 to B0
6
IOB2
0
R/W
Specify the function of TGRB.
5
IOB1
0
R/W
4
IOB0
0
R/W
For details, see tables 11.13, 11.15, 11.16, 11.17,
11.19, and 11.20.
3
IOA3
0
R/W
I/O Control A3 to A0
2
IOA2
0
R/W
Specify the function of TGRA.
1
IOA1
0
R/W
0
IOA0
0
R/W
For details, see tables 11.21, 11.23, 11.24, 11.25,
11.27, and 11.28.
TIORL_0, TIORL_3
Bit
Bit Name
Initial Value
R/W
Description
7
IOD3
0
R/W
I/O Control D3 to D0
6
IOD2
0
R/W
Specify the function of TGRD.
5
IOD1
0
R/W
For details, see tables 11.14 and 11.18.
4
IOD0
0
R/W
3
IOC3
0
R/W
I/O Control C3 to C0
2
IOC2
0
R/W
Specify the function of TGRC.
1
IOC1
0
R/W
For details, see tables 11.22 and 11.26.
0
IOC0
0
R/W
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.13 TIORH_0
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_0
Function
0
0
0
0
Output
compare
register
1
TIOCB0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB0 pin
Input capture at rising edge
Capture input source is TIOCB0 pin
Input capture at falling edge
1
x
Capture input source is TIOCB0 pin
Input capture at both edges
1
x
x
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down*
[Legend]
x:
Don't care
Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Page 716 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.14 TIORL_0
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
0
0
0
0
Output
compare
2
register*
1
TIOCD0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*2
Capture input source is TIOCD0 pin
Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
1
x
Capture input source is TIOCD0 pin
Input capture at both edges
1
x
x
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
1
[Legend]
x:
Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.15 TIOR_1
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
0
0
0
0
Output
compare
register
1
TIOCB1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB1 pin
Input capture at rising edge
Capture input source is TIOCB1 pin
Input capture at falling edge
1
x
Capture input source is TIOCB1 pin
Input capture at both edges
1
x
x
TGRC_0 compare match/input capture
Input capture at generation of TGRC_0 compare
match/input capture
[Legend]
x:
Don't care
Page 718 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.16 TIOR_2
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_2
Function
0
0
0
0
Output
compare
register
1
TIOCB2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Capture input source is TIOCB2 pin
Input capture at rising edge
Capture input source is TIOCB2 pin
Input capture at falling edge
1
x
Capture input source is TIOCB2 pin
Input capture at both edges
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.17 TIORH_3
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_3
Function
0
0
0
0
Output
compare
register
1
TIOCB3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB3 pin
Input capture at rising edge
Capture input source is TIOCB3 pin
Input capture at falling edge
1
x
Capture input source is TIOCB3 pin
Input capture at both edges
1
x
x
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
[Legend]
x:
Don't care
Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
Page 720 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.18 TIORL_3
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_3
Function
0
0
0
0
Output
compare
2
register*
1
TIOCD3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*2
Capture input source is TIOCD3 pin
Input capture at rising edge
Capture input source is TIOCD3 pin
Input capture at falling edge
1
x
Capture input source is TIOCD3 pin
Input capture at both edges
1
x
x
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
1
[Legend]
x:
Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.19 TIOR_4
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_4
Function
0
0
0
0
Output
compare
register
1
TIOCB4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCB4 pin
Input capture at rising edge
Capture input source is TIOCB4 pin
Input capture at falling edge
1
x
Capture input source is TIOCB4 pin
Input capture at both edges
1
x
x
Capture input source is TGRC_3 compare
match/input capture
Input capture at generation of TGRC_3 compare
match/input capture
[Legend]
x:
Don't care
Page 722 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.20 TIOR_5
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_5
Function
0
0
0
0
Output
compare
register
1
TIOCB5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Capture input source is TIOCB5 pin
Input capture at rising edge
Capture input source is TIOCB5 pin
Input capture at falling edge
1
x
Capture input source is TIOCB5 pin
Input capture at both edges
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.21 TIORH_0
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_0
Function
0
0
0
0
Output
compare
register
1
TIOCA0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA0 pin
Input capture at rising edge
Capture input source is TIOCA0 pin
Input capture at falling edge
1
x
Capture input source is TIOCA0 pin
Input capture at both edges
1
x
x
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
x:
Don't care
Page 724 of 1408
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.22 TIORL_0
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function
0
0
0
0
Output
compare
register*
1
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC0 pin
Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
1
x
Capture input source is TIOCC0 pin
Input capture at both edges
1
x
x
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
x:
Don't care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
R01UH0309EJ0500 Rev. 5.00
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.23 TIOR_1
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
0
0
0
0
Output
compare
register
1
TIOCA1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA1 pin
Input capture at rising edge
Capture input source is TIOCA1 pin
Input capture at falling edge
1
x
Capture input source is TIOCA1 pin
Input capture at both edges
1
x
x
Capture input source is TGRA_0 compare
match/input capture
Input capture at generation of channel 0/
TGRA_0 compare match/input capture
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.24 TIOR_2
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_2
Function
0
0
0
0
Output
compare
register
1
TIOCA2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Capture input source is TIOCA2 pin
Input capture at rising edge
Capture input source is TIOCA2 pin
Input capture at falling edge
1
x
Capture input source is TIOCA2 pin
Input capture at both edges
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.25 TIORH_3
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_3
Function
0
0
0
0
Output
compare
register
1
TIOCA3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA3 pin
Input capture at rising edge
Capture input source is TIOCA3 pin
Input capture at falling edge
1
x
Capture input source is TIOCA3 pin
Input capture at both edges
1
x
x
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.26 TIORL_3
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_3
Function
0
0
0
0
Output
compare
register*
1
TIOCC3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC3 pin
Input capture at rising edge
Capture input source is TIOCC3 pin
Input capture at falling edge
1
x
Capture input source is TIOCC3 pin
Input capture at both edges
1
x
x
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
[Legend]
x:
Don't care
Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.27 TIOR_4
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_4
Function
0
0
0
0
Output
compare
register
1
TIOCA4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register
Capture input source is TIOCA4 pin
Input capture at rising edge
Capture input source is TIOCA4 pin
Input capture at falling edge
1
x
Capture input source is TIOCA4 pin
Input capture at both edges
1
x
x
Capture input source is TGRA_3 compare
match/input capture
Input capture at generation of TGRA_3 compare
match/input capture
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.28 TIOR_5
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_5
Function
0
0
0
0
Output
compare
register
1
TIOCA5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
×
0
0
1
Input
capture
register
Input capture source is TIOCA5 pin
Input capture at rising edge
Input capture source is TIOCA5 pin
Input capture at falling edge
1
x
Input capture source is TIOCA5 pin
Input capture at both edges
[Legend]
x:
Don't care
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.4
Timer Interrupt Enable Register (TIER)
TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has
six TIER registers, one for each channel.
Bit
Bit Name
Initial value
R/W
Description
7
TTGE
0
R/W
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6
⎯
1
⎯
Reserved
This bit is always read as 1 and cannot be modified.
5
TCIEU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
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Section 11 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.5
Timer Status Register (TSR)
TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each
channel.
Bit
Bit Name
Initial value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always
read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6
⎯
1
⎯
Reserved
This bit is always read as 1 and cannot be
modified.
5
TCFU
0
R/(W)*
1
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to
phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4
TCFV
0
R/(W)*
1
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
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Bit
3
Bit Name
TGFD
Section 11 16-Bit Timer Pulse Unit (TPU)
Initial value
R/W
Description
0
R/(W)*
1
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRD while TGRD is
functioning as output compare register
•
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning
as input capture register
[Clearing conditions]
2
TGFC
0
R/(W)*
1
•
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFD after reading TGFD
=1
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRC while TGRC is
functioning as output compare register
•
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning
as input capture register
[Clearing conditions]
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•
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFC after reading TGFC
=1
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Section 11 16-Bit Timer Pulse Unit (TPU)
Bit
1
Bit Name
TGFB
Initial value
R/W
Description
0
R/(W)*
1
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRB while TGRB is
functioning as output compare register
•
When TCNT value is transferred to TGRB by
input capture signal while TGRB is functioning
as input capture register
[Clearing conditions]
0
TGFA
0
R/(W)*
1
•
When DTC is activated by TGIB interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFB after reading TGFB
=1
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRA while TGRA is
functioning as output compare register
•
When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
[Clearing conditions]
•
When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
•
When DMAC is activated by TGIA interrupt
2
while DTE bit of DMABCR in DTC is 1*
•
When 0 is written to TGFA after reading TGFA
=1
Notes: 1. Only 0 can be written, for flag clearing.
2. Only available in unit 0.
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11.3.6
Section 11 16-Bit Timer Pulse Unit (TPU)
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
11.3.7
Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers with a dual function as output compare
and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two
each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for
operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must
always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and
TGRB–TGRD.
11.3.8
Timer Start Register (TSTR)
TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit
Bit Name
Initial value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
The write value should always be 0.
5
CST5
0
R/W
Counter Start 5 to 0
4
CST4
0
R/W
These bits select operation or stoppage for TCNT.
3
CST3
0
R/W
2
CST2
0
R/W
1
CST1
0
R/W
0
CST0
0
R/W
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops
but the TIOC pin output compare output level is
retained. If TIOR is written to when the CST bit is
cleared to 0, the pin output level will be changed to
the set initial output value.
0: TCNT_5 to TCNT_0 count operation is stopped
1: TCNT_5 to TCNT_0 performs count operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.9
Timer Synchronous Register (TSYR)
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
The write value should always be 0.
5
SYNC5
0
R/W
Timer Synchronization 5 to 0
4
SYNC4
0
R/W
3
SYNC3
0
R/W
These bits select whether operation is independent
of or synchronized with other channels.
2
SYNC2
0
R/W
1
SYNC1
0
R/W
0
SYNC0
0
R/W
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by
means of bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.10 Timer Start Register B (TSTRB)
TSTRB selects operation/stoppage for channels 6 to 11. When setting the operating mode in
TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit
Bit Name
Initial value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
The write value should always be 0.
5
CST11
0
R/W
Counter Start 11 to 6
4
CST10
0
R/W
These bits select operation or stoppage for TCNT.
3
CST9
0
R/W
2
CST8
0
R/W
1
CST7
0
R/W
0
CST6
0
R/W
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops
but the TIOC pin output compare output level is
retained. If TIOR is written to when the CST bit is
cleared to 0, the pin output level will be changed to
the set initial output value.
0: TCNT_11 to TCNT_6 count operation is stopped
1: TCNT_11 to TCNT_6 performs count operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.11 Timer Synchronous Register B (TSYRB)
TSYRB selects independent operation or synchronous operation for the TCNT counters of
channels 6 to 11. A channel performs synchronous operation when the corresponding bit in
TSYRB is set to 1.
Bit
Bit Name
Initial value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
The write value should always be 0.
5
SYNC11
0
R/W
Timer Synchronization 11 to 6
4
SYNC10
0
R/W
3
SYNC9
0
R/W
These bits select whether operation is independent
of or synchronized with other channels.
2
SYNC8
0
R/W
1
SYNC7
0
R/W
0
SYNC6
0
R/W
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by
means of bits CCLR2 to CCLR0 in TCR.
0: TCNT_11 to TCNT_6 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_11 to TCNT_6 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)
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11.4
Operation
11.4.1
Basic Functions
Section 11 16-Bit Timer Pulse Unit (TPU)
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
(1)
Counter Operation
When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
(a)
Example of count operation setting procedure
Figure 11.3 shows an example of the count operation setting procedure.
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Section 11 16-Bit Timer Pulse Unit (TPU)
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count
[5]
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Free-running counter
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
Start count
[5]
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 11.3 Example of Counter Operation Setting Procedure
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(b)
Section 11 16-Bit Timer Pulse Unit (TPU)
Free-running count operation and periodic count operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to
H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER
is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again
from H'0000.
Figure 11.4 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 11.4 Free-Running Counter Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
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When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts
count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Figure 11.5 illustrates periodic counter operation.
TCNT value
TGR
Counter cleared by TGR
compare match
H'0000
Time
CST bit
Flag cleared by software or
DTC activation
TGF
Figure 11.5 Periodic Counter Operation
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(2)
Section 11 16-Bit Timer Pulse Unit (TPU)
Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare
match.
(a)
Example of setting procedure for waveform output by compare match
Figure 11.6 shows an example of the setting procedure for waveform output by a compare match.
Output selection
Select waveform output mode
[1]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
Set output timing
[2]
Start count
[3]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 11.6 Example of Setting Procedure for Waveform Output by Compare Match
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Section 11 16-Bit Timer Pulse Unit (TPU)
(b)
Examples of waveform output operation
Figure 11.7 shows an example of 0 output/1 output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by compare match A, and 0 is output by compare match B. When the set
level and the pin level match, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
TIOCB
No change
No change
0 output
Figure 11.7 Example of 0 Output/1 Output Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.8 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing performed
by compare match B), and settings have been made so that output is toggled by both compare
match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 11.8 Example of Toggle Output Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
(3)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3,
4, 6, 7, 9, and 10 it is also possible to specify another channel’s counter input clock or compare
match signal as the input capture source.
Note: When another channel’s counter input clock is used as the input capture input for channels
0, 3, 6, and 9, φ/1 should not be selected as the counter input clock used for input capture
input. Input capture will not be generated if φ/1 is selected.
(a)
Example of setting procedure for input capture operation
Figure 11.9 shows an example of the setting procedure for input capture operation.
[1] Designate TGR as an input capture register by
means of TIOR, and select the input capture
source and input signal edge (rising edge, falling
edge, or both edges).
Input selection
Select input capture input
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 11.9 Example of Setting Procedure for Input Capture Operation
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(b)
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of input capture operation
Figure 11.10 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input capture
input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter
clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 11.10 Example of Input Capture Operation
11.4.2
Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously
(synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously
(synchronous clearing) by making the appropriate setting in TCR.
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 and 6 to 11 can all be designated for synchronous operation.
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Section 11 16-Bit Timer Pulse Unit (TPU)
(1)
Example of Synchronous Operation Setting Procedure
Figure 11.11 shows an example of the synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the
same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 11.11 Example of Synchronous Operation Setting Procedure
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(2)
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation
Figure 11.12 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
For details on PWM modes, see section 11.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Figure 11.12 Example of Synchronous Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.3
Buffer Operation
Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as
buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 11.29 shows the register combinations used in buffer operation.
Table 11.29 Register Combinations in Buffer Operation
Unit
Channel
Timer General Register
Buffer Register
0
0
TGRA_0
TGRC_0
TGRB_0
TGRD_0
TGRA_3
TGRC_3
TGRB_3
TGRD_3
3
1
6
9
•
TGRA_6
TGRC_6
TGRB_6
TGRD_6
TGRA_9
TGRC_9
TGRB_9
TGRD_9
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 11.13.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 11.13 Compare Match Buffer Operation
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•
Section 11 16-Bit Timer Pulse Unit (TPU)
When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 11.14.
Input capture
signal
Timer general
register
Buffer register
TCNT
Figure 11.14 Input Capture Buffer Operation
(1)
Example of Buffer Operation Setting Procedure
Figure 11.15 shows an example of the buffer operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set buffer operation
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
Select TGR function
Figure 11.15 Example of Buffer Operation Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Buffer Operation
(a)
When TGR is an output compare register
Figure 11.16 shows an operation example in which PWM mode 1 has been designated for channel
0, and buffer operation has been designated for TGRA and TGRC. The settings used in this
example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at
compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time compare match A occurs.
For details on PWM modes, see section 11.4.5, PWM Modes.
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
TGRC_0 H'0200
H'0450
H'0520
Transfer
TGRA_0
H'0200
H'0450
TIOCA
Figure 11.16 Example of Buffer Operation (1)
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(b)
Section 11 16-Bit Timer Pulse Unit (TPU)
When TGR is an input capture register
Figure 11.17 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges
have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 11.17 Example of Buffer Operation (2)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock
at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to
TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, 4, 7, or 10, the counter clock setting is
invalid and the counter operates independently in phase counting mode.
Table 11.30 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Channels 4 and 5
TCNT_4
TCNT_5
Channels 7 and 8
TCNT_7
TCNT_8
Channels 10 and 11
TCNT_10
TCNT_11
(1)
Example of Cascaded Operation Setting Procedure
Figure 11.18 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Figure 11.18 Cascaded Operation Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation
Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the
TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1
clock
TCNT_1
H'03A1
H'03A2
TCNT_2
clock
TCNT_2
H'FFFF
H'0000
H'0001
TIOCA1,
TIOCA2
TGRA_1
H'03A2
TGRA_2
H'0000
Figure 11.19 Example of Cascaded Operation (1)
Figure 11.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
FFFD
TCNT_1
FFFE
0000
FFFF
0000
0001
0002
0001
0000
0001
FFFF
0000
Figure 11.20 Example of Cascaded Operation (2)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.5
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PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR
are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The
outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare
matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If
the set values of paired TGRs are identical, the output value does not change when a compare
match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a synchronization register compare match, the output value of each pin is
the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,
the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 11.31.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.31 PWM Output Registers and Output Pins
Output Pins
Unit
Channel
Registers
PWM Mode 1
PWM Mode 2
0
0
TIOCA0
3
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
4
TGRB_3
TGRC_3
TGRD_3
TGRA_4
1
2
5
1
6
7
8
9
10
11
TGRB_4
TGRA_5
TGRB_5
TGRA_6
TGRB_6
TGRC_6
TGRD_6
TGRA_7
TGRB_7
TGRA_8
TGRB_8
TGRA_9
TGRB_9
TGRC_9
TGRD_9
TGRA_10
TGRB_10
TGRA_11
TGRB_11
TIOCC0
TIOCA1
TIOCA2
TIOCA3
TIOCC3
TIOCA4
TIOCA5
TIOCA6
TIOCC6
TIOCA7
TIOCA8
TIOCA9
TIOCC9
TIOCA10
TIOCA11
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
TIOCA6
TIOCB6
TIOCC6
TIOCD6
TIOCA7
TIOCB7
TIOCA8
TIOCB8
TIOCA9
TIOCB9
TIOCC9
TIOCD9
TIOCA10
TIOCB10
TIOCA11
TIOCB11
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
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Section 11 16-Bit Timer Pulse Unit (TPU)
(1)
Example of PWM Mode Setting Procedure
Figure 11.21 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Select counter clearing source
Select waveform output level
Set TGR
[2]
[3]
[4]
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and
set the duty in the other TGRs.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set PWM mode
[5]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the count
operation.
Figure 11.21 Example of PWM Mode Setting Procedure
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Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of PWM Mode Operation
Figure 11.22 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as
the duty cycle.
TCNT value
Counter cleared by
TGRA compare match
TGRA
TGRB
H'0000
Time
TIOCA
Figure 11.22 Example of PWM Mode Operation (1)
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Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.23 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as
the duty cycle.
TCNT value
Counter cleared by
TGRB_1 compare match
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 11.23 Example of PWM Mode Operation (2)
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Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle
in PWM mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB rewritten
TGRB
rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 11.24 Example of PWM Mode Operation (3)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.6
H8S/2456, H8S/2456R, H8S/2454 Group
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, 5, 7, 8,
10, and 11.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 11.32 shows the correspondence between external clock pins and channels.
Table 11.32 Clock Input Pins in Phase Counting Mode
External Clock Pins
Unit
Channels
A-Phase
B-Phase
0
When channel 1 or 5 is set to phase counting mode
TCLKA
TCLKB
When channel 2 or 4 is set to phase counting mode
TCLKC
TCLKD
When channel 7 or 11 is set to phase counting mode
TCLKE
TCLKF
When channel 8 or 10 is set to phase counting mode
TCLKG
TCLKH
1
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(1)
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Phase Counting Mode Setting Procedure
Figure 11.25 shows an example of the phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
Figure 11.25 Example of Phase Counting Mode Setting Procedure
(2)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two
external clocks. There are four modes, according to the count conditions.
a. Phase counting mode 1
Figure 11.26 shows an example of phase counting mode 1 operation, and table 11.33
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.26 Example of Phase Counting Mode 1 Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKE (Channels 7 and 11)
TCLKG (Channels 8 and 10)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
TCLKF (Channels 7 and 11)
TCLKH (Channels 8 and 10)
Operation
Up-count
High level
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
[Legend]
:
Rising edge
:
Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
b. Phase counting mode 2
Figure 11.27 shows an example of phase counting mode 2 operation, and table 11.34
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.27 Example of Phase Counting Mode 2 Operation
Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKE (Channels 7 and 11)
TCLKG (Channels 8 and 10)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
TCLKF (Channels 7 and 11)
TCLKH (Channels 8 and 10)
Operation
Don't care
High level
Low level
Don't care
Low level
Don't care
High level
Up-count
High level
Don't care
Low level
Don't care
High level
Don't care
Low level
Down-count
Legend]
:
Rising edge
:
Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
c. Phase counting mode 3
Figure 11.28 shows an example of phase counting mode 3 operation, and table 11.35
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 11.28 Example of Phase Counting Mode 3 Operation
Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKE (Channels 7 and 11)
TCLKG (Channels 8 and 10)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
TCLKF (Channels 7 and 11)
TCLKH (Channels 8 and 10)
Operation
High level
Don't care
Low level
Don't care
Low level
Don't care
High level
Up-count
High level
Down-count
Low level
Don't care
High level
Don't care
Low level
Don't care
[Legend]
:
Rising edge
:
Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
d. Phase counting mode 4
Figure 11.29 shows an example of phase counting mode 4 operation, and table 11.36
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 11.29 Example of Phase Counting Mode 4 Operation
Table 11.36 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKE (Channels 7 and 11)
TCLKG (Channels 8 and 10)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
TCLKF (Channels 7 and 11)
TCLKH (Channels 8 and 10)
Operation
Up-count
High level
Low level
Low level
Don't care
High level
High level
Down-count
Low level
High level
Don't care
Low level
[Legend]
:
Rising edge
:
Falling edge
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Section 11 16-Bit Timer Pulse Unit (TPU)
(3)
H8S/2456, H8S/2456R, H8S/2454 Group
Phase Counting Mode Application Example
Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and
channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect
the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function, and are set with the speed control cycle and
position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source, and the up/down-counter
values for the control cycles are stored.
This procedure enables accurate position/speed detection to be achieved.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT_1
TGRA_1
(speed cycle capture)
TGRB_1
(position cycle capture)
TCNT_0
TGRA_0
(speed control cycle)
+
-
TGRC_0
(position control cycle)
+
-
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 11.30 Phase Counting Mode Application Example
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.5
H8S/2456, H8S/2456R, H8S/2454 Group
Interrupt Sources
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 11.37 lists the TPU interrupt sources.
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Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.37 TPU Interrupts
Unit Channel
Name
Interrupt Source
Interrupt
Flag
DTC
Activation
DMAC
Activation
0
TGI0A
TGRA_0 input capture/compare match
TGFA_0
Possible
Possible
TGI0B
TGRB_0 input capture/compare match
TGFB_0
Possible
Not possible
TGI0C
TGRC_0 input capture/compare match
TGFC_0
Possible
Not possible
TGI0D
TGRD_0 input capture/compare match
TGFD_0
Possible
Not possible
TCI0V
TCNT_0 overflow
TCFV_0
Not possible
Not possible
TGI1A
TGRA_1 input capture/compare match
TGFA_1
Possible
Possible
0
1
2
3
4
5
TGI1B
TGRB_1 input capture/compare match
TGFB_1
Possible
Not possible
TCI1V
TCNT_1 overflow
TCFV_1
Not possible
Not possible
TCI1U
TCNT_1 underflow
TCFU_1
Not possible
Not possible
TGI2A
TGRA_2 input capture/compare match
TGFA_2
Possible
Possible
TGI2B
TGRB_2 input capture/compare match
TGFB_2
Possible
Not possible
TCI2V
TCNT_2 overflow
TCFV_2
Not possible
Not possible
TCI2U
TCNT_2 underflow
TCFU_2
Not possible
Not possible
TGI3A
TGRA_3 input capture/compare match
TGFA_3
Possible
Possible
TGI3B
TGRB_3 input capture/compare match
TGFB_3
Possible
Not possible
TGI3C
TGRC_3 input capture/compare match
TGFC_3
Possible
Not possible
TGI3D
TGRD_3 input capture/compare match
TGFD_3
Possible
Not possible
TCI3V
TCNT_3 overflow
TCFV_3
Not possible
Not possible
TGI4A
TGRA_4 input capture/compare match
TGFA_4
Possible
Possible
TGI4B
TGRB_4 input capture/compare match
TGFB_4
Possible
Not possible
TCI4V
TCNT_4 overflow
TCFV_4
Not possible
Not possible
TCI4U
TCNT_4 underflow
TCFU_4
Not possible
Not possible
TGI5A
TGRA_5 input capture/compare match
TGFA_5
Possible
Possible
TGI5B
TGRB_5 input capture/compare match
TGFB_5
Possible
Not possible
TCI5V
TCNT_5 overflow
TCFV_5
Not possible
Not possible
TCI5U
TCNT_5 underflow
TCFU_5
Not possible
Not possible
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Section 11 16-Bit Timer Pulse Unit (TPU)
H8S/2456, H8S/2456R, H8S/2454 Group
Unit Channel
Name
Interrupt Source
Interrupt
Flag
DTC
Activation
DMAC
Activation
1
TGI6A
TGRA_6 input capture/compare match
TGFA_6
Possible
Not possible
TGI6B
TGRB_6 input capture/compare match
TGFB_6
Possible
Not possible
TGI6C
TGRC_6 input capture/compare match
TGFC_6
Possible
Not possible
TGI6D
TGRD_6 input capture/compare match
TGFD_6
Possible
Not possible
6
7
8
9
10
11
Note:
TCI6V
TCNT_6 overflow
TCFV_6
Not possible
Not possible
TGI7A
TGRA_7 input capture/compare match
TGFA_7
Possible
Not possible
TGI7B
TGRB_7 input capture/compare match
TGFB_7
Possible
Not possible
TCI7V
TCNT_7 overflow
TCFV_7
Not possible
Not possible
TCI7U
TCNT_7 underflow
TCFU_7
Not possible
Not possible
TGI8A
TGRA_8 input capture/compare match
TGFA_8
Possible
Not possible
TGI8B
TGRB_8 input capture/compare match
TGFB_8
Possible
Not possible
TCI8V
TCNT_8 overflow
TCFV_8
Not possible
Not possible
TCI8U
TCNT_8 underflow
TCFU_8
Not possible
Not possible
TGI9A
TGRA_9 input capture/compare match
TGFA_9
Possible
Not possible
TGI9B
TGRB_9 input capture/compare match
TGFB_9
Possible
Not possible
TGI9C
TGRC_9 input capture/compare match
TGFC_9
Possible
Not possible
TGI9D
TGRD_9 input capture/compare match
TGFD_9
Possible
Not possible
TCI9V
TCNT_9 overflow
TCFV_9
Not possible
Not possible
TGI10A
TGRA_10 input capture/compare match
TGFA_10 Possible
Not possible
TGI10B
TGRB_10 input capture/compare match
TGFB_10 Possible
Not possible
TCI10V
TCNT_10 overflow
TCFV_10 Not possible
Not possible
TCI10U
TCNT_10 underflow
TCFU_10 Not possible
Not possible
TGI11A
TGRA_11 input capture/compare match
TGFA_11 Possible
Not possible
TGI11B
TGRB_11 input capture/compare match
TGFB_11 Possible
Not possible
TCI11V
TCNT_11 overflow
TCFV_11 Not possible
Not possible
TCI11U
TCNT_11 underflow
TCFU_11 Not possible
Not possible
This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
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(1)
Section 11 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1
by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt
request is cleared by clearing the TGF flag to 0. The TPU has 32 input capture/compare match
interrupts, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and
11.
(2)
Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to
1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing
the TCFV flag to 0. The TPU has 12 overflow interrupts, one for each channel.
(3)
Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to
1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing
the TCFU flag to 0. The TPU has eight underflow interrupts, one each for channels 1, 2, 4, 5, 7, 8,
10, and 11.
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.6
H8S/2456, H8S/2456R, H8S/2454 Group
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 9, Data Transfer Controller (DTC).
A total of 32 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11.
11.7
DMAC Activation
In unit 0 of the TPU, the DMAC can be activated by the TGRA input capture/compare match
interrupt for a channel. For details, see section 7, DMA Controller (DMAC). (The DMAC cannot
be activated by unit 1.)
In unit 0 of the TPU, a total of six TGRA input capture/compare match interrupts can be used as
DMAC activation sources, one for each channel.
11.8
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
In the TPU, a total of 12 TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
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11.9
Operation Timing
11.9.1
Input/Output Timing
(1)
Section 11 16-Bit Timer Pulse Unit (TPU)
TCNT Count Timing
Figure 11.31 shows TCNT count timing in internal clock operation, and figure 11.32 shows TCNT
count timing in external clock operation.
φ
Internal clock
Falling edge
Rising edge
TCNT
input clock
N–1
TCNT
N
N+1
N+2
Figure 11.31 Count Timing in Internal Clock Operation
φ
External clock
Falling edge
Rising edge
Falling edge
TCNT
input clock
N–1
TCNT
N
N+1
N+2
Figure 11.32 Count Timing in External Clock Operation
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Section 11 16-Bit Timer Pulse Unit (TPU)
(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin. After a match
between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT
input clock is generated.
Figure 11.33 shows output compare output timing.
φ
TCNT
input clock
TCNT
TGR
N
N+1
N
Compare
match signal
TIOC pin
Figure 11.33 Output Compare Output Timing
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(3)
Section 11 16-Bit Timer Pulse Unit (TPU)
Input Capture Signal Timing
Figure 11.34 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
N+1
N
TCNT
N+2
N
TGR
N+2
Figure 11.34 Input Capture Input Signal Timing
(4)
Timing for Counter Clearing by Compare Match/Input Capture
Figure 11.35 shows the timing when counter clearing by compare match occurrence is specified,
and figure 11.36 shows the timing when counter clearing by input capture occurrence is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 11.35 Counter Clear Timing (Compare Match)
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Section 11 16-Bit Timer Pulse Unit (TPU)
φ
Input capture
signal
Counter clear
signal
TCNT
TGR
N
H'0000
N
Figure 11.36 Counter Clear Timing (Input Capture)
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(5)
Section 11 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing
Figures 11.37 and 11.38 show the timings in buffer operation.
φ
TCNT
n
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 11.37 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 11.38 Buffer Operation Timing (Input Capture)
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.9.2
(1)
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match
Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence,
and the TGI interrupt request signal timing.
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 11.39 TGI Interrupt Timing (Compare Match)
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(2)
Section 11 16-Bit Timer Pulse Unit (TPU)
TGF Flag Setting Timing in Case of Input Capture
Figure 11.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and
the TGI interrupt request signal timing.
φ
Input capture
signal
N
TCNT
TGR
N
TGF flag
TGI interrupt
Figure 11.40 TGI Interrupt Timing (Input Capture)
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Section 11 16-Bit Timer Pulse Unit (TPU)
(3)
TCFV Flag/TCFU Flag Setting Timing
Figure 11.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and
the TCIV interrupt request signal timing.
Figure 11.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 11.41 TCIV Interrupt Setting Timing
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 11.42 TCIU Interrupt Setting Timing
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(4)
Section 11 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or
DMAC is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag
clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or
DMAC.
TSR write cycle
T1
T2
φ
TSR address
Address
Write signal
Status flag
Interrupt
request
signal
Figure 11.43 Timing for Status Flag Clearing by CPU
DTC/DMAC
read cycle
T1
T2
DTC/DMAC
write cycle
T1
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC Activation
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10
Usage Notes
11.10.1 Module Stop Function Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing the module stop
state. For details, refer to section 24, Power-Down Modes.
11.10.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.45 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
diffediffeOverlap
rence
rence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.3 Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f=
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
11.10.4 Contention between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 11.46 shows the timing in this
case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
Counter clearing
signal
TCNT
N
H'0000
Figure 11.46 Contention between TCNT Write and Clear Operations
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 11.47 shows the timing in this case.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 11.47 Contention between TCNT Write and Increment Operations
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 11.48 shows the timing in this case.
TGR write cycle
T2
T1
φ
TGR address
Address
Write signal
Compare
match signal
Disabled
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 11.48 Contention between TGR Write and Compare Match
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 11.49 shows the timing in this case.
TGR write cycle
T2
T1
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 11.49 Contention between Buffer Register Write and Compare Match
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 11.50 shows the timing in this case.
TGR read cycle
T1
T2
φ
TGR address
Address
Read signal
Input capture
signal
TGR
X
Internal
data bus
M
M
Figure 11.50 Contention between TGR Read and Input Capture
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.51 shows the timing in this case.
TGR write cycle
T2
T1
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
TGR
M
M
Figure 11.51 Contention between TGR Write and Input Capture
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.52 shows the timing in this case.
Buffer register write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
N
M
N
M
Figure 11.52 Contention between Buffer Register Write and Input Capture
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clearing signal
TGF
Disabled
TCFV
Figure 11.53 Contention between Overflow and Counter Clearing
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Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.54 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
TCFV flag
Figure 11.54 Contention between TCNT Write and Overflow
11.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, the TCLKD input pin
with the TIOCB2 I/O pin, the TCLKE input pin with the TIOCC6 I/O pin, the TCLKF input pin
with the TIOCD6 I/O pin, the TCLKG input pin with the TIOCB7 I/O pin, and the TCLKH input
pin with the TIOCB8 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
11.10.14 Interrupts and Module Stop State
If a transition is made to the module stop state when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts
should therefore be disabled before entering the module stop state.
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Section 12 Programmable Pulse Generator (PPG)
Section 12 Programmable Pulse Generator (PPG)
The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse
unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that
can operate both simultaneously and independently. The block diagram of PPG is shown in figure
12.1.
12.1
•
•
•
•
•
•
•
Features
16-bit output data
Four output groups
Selectable output trigger signals
Non-overlap mode
Can operate together with the data transfer controller (DTC) and the DMA controller (DMAC)
Settable inverted output
Module stop state can be set.
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Section 12 Programmable Pulse Generator (PPG)
Compare match signals
Control logic
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
[Legend]
PMR:
PCR:
NDERH:
NDERL:
NDRH:
NDRL:
PODRH:
PODRL:
NDERH
NDERL
PMR
PCR
Pulse output
pins, group 3
PODRH
NDRH
(NDRHH,
NDRHL)
PODRL
NDRL
(NDRLH,
NDRLL)
Pulse output
pins, group 2
Internal
data bus
Pulse output
pins, group 1
Pulse output
pins, group 0
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Next data register H
Next data register L
Output data register H
Output data register L
Figure 12.1 Block Diagram of PPG
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12.2
Section 12 Programmable Pulse Generator (PPG)
Input/Output Pins
Table 12.1 shows the PPG pin configuration.
Table 12.1 Pin Configuration
Pin Name
I/O
Function
PO15
Output
Group 3 pulse output
PO14
Output
PO13
Output
PO12
Output
PO11
Output
PO10
Output
PO9
Output
PO8
Output
PO7
Output
PO6
Output
PO5
Output
PO4
Output
PO3
Output
PO2
Output
PO1
Output
PO0
Output
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Group 2 pulse output
Group 1 pulse output
Group 0 pulse output
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Section 12 Programmable Pulse Generator (PPG)
12.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The PPG has the following registers.
•
•
•
•
•
•
•
•
Next data enable register H (NDERH)
Next data enable register L (NDERL)
Output data register H (PODRH)
Output data register L (PODRL)
Next data register H (NDRH)
Next data register L (NDRL)
PPG output control register (PCR)
PPG output mode register (PMR)
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12.3.1
Section 12 Programmable Pulse Generator (PPG)
Next Data Enable Registers H and L (NDERH, NDERL)
NDERH and NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by
the PPG, set the corresponding DDR to 1.
•
NDERH
Bit
Bit Name
Initial Value
R/W
Description
7
NDER15
0
R/W
Next Data Enable 15 to 8
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
When a bit is set to 1, the value in the
corresponding NDRH bit is transferred to the
PODRH bit by the selected output trigger. Values
are not transferred from NDRH to PODRH for
cleared bits.
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
0
R/W
•
NDERL
Bit
Bit Name
Initial Value
R/W
Description
7
NDER7
0
R/W
Next Data Enable 7 to 0
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
When a bit is set to 1, the value in the
corresponding NDRL bit is transferred to the
PODRL bit by the selected output trigger. Values
are not transferred from NDRL to PODRL for
cleared bits.
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
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Section 12 Programmable Pulse Generator (PPG)
12.3.2
Output Data Registers H and L (PODRH, PODRL)
PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse
output by NDER is read-only and cannot be modified.
•
PODRH
Bit
Bit Name
Initial Value
R/W
Description
7
POD15
0
R/W
Output Data Register 15 to 8
6
POD14
0
R/W
5
POD13
0
R/W
4
POD12
0
R/W
3
POD11
0
R/W
2
POD10
0
R/W
For bits which have been set to pulse output by
NDERH, the output trigger transfers NDRH values
to this register during PPG operation. While
NDERH is set to 1, the CPU cannot write to this
register. While NDERH is cleared, the initial output
value of the pulse can be set.
1
POD9
0
R/W
0
POD8
0
R/W
•
PODRL
Bit
Bit Name
Initial Value
R/W
Description
7
POD7
0
R/W
Output Data Register 7 to 0
6
POD6
0
R/W
5
POD5
0
R/W
4
POD4
0
R/W
3
POD3
0
R/W
2
POD2
0
R/W
For bits which have been set to pulse output by
NDERL, the output trigger transfers NDRL values
to this register during PPG operation. While
NDERL is set to 1, the CPU cannot write to this
register. While NDERL is cleared, the initial output
value of the pulse can be set.
1
POD1
0
R/W
0
POD0
0
R/W
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12.3.3
Section 12 Programmable Pulse Generator (PPG)
Next Data Registers H and L (NDRH, NDRL)
NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on
whether pulse output groups have the same output trigger or different output triggers.
•
NDRH (NDRHH, NDRHL)*
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 8
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
•
NDRHH*
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 12
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3 to 0
⎯
All 1
⎯
Reserved
1 is always read and write is disabled.
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Section 12 Programmable Pulse Generator (PPG)
•
NDRHL*
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 1
⎯
Reserved
1 is always read and write is disabled.
3
NDR11
0
R/W
Next Data Register 11 to 8
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
•
NDRL (NDRLH, NDRLL)*
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 0
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
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•
Section 12 Programmable Pulse Generator (PPG)
NDRLH*
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 4
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3 to 0
⎯
All 1
⎯
Reserved
1 is always read and write is disabled.
•
NDRLL*
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 1
⎯
Reserved
1 is always read and write is disabled.
3
NDR3
0
R/W
Next Data Register 3 to 0
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Note: * When pulse output groups 2 and 3 have the same output trigger by PCR settings, the
NDRH address is H'FF4C. When they have different output triggers, the NDRL
address corresponding to the group 2 is NDRHH (H'FF4E) and the NDRH address
corresponding to the group 3 is NDRHL (H'FF4C). Also, when pulse output groups 0
and 1 have the same output trigger by PCR settings, the NDRL address is H'FF4D.
When they have different output triggers, the NDRL addresses corresponding to the
groups 0 and 1 are NDRLL (H'FF4F) and NDRLH (H'FF4D), respectively.
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Section 12 Programmable Pulse Generator (PPG)
12.3.4
PPG Output Control Register (PCR)
PCR selects output trigger signals on a group-by-group basis. For details on output trigger
selection, refer to section 12.3.5, PPG Output Mode Register (PMR).
Bit
Bit Name
Initial Value
R/W
Description
7
G3CMS1
1
R/W
Group 3 Compare Match Select 1 and 0
6
G3CMS0
1
R/W
Select output trigger of pulse output group 3.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
5
G2CMS1
1
R/W
Group 2 Compare Match Select 1 and 0
4
G2CMS0
1
R/W
Select output trigger of pulse output group 2.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
3
G1CMS1
1
R/W
Group 1 Compare Match Select 1 and 0
2
G1CMS0
1
R/W
Select output trigger of pulse output group 1.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
1
G0CMS1
1
R/W
Group 0 Compare Match Select 1 and 0
0
G0CMS0
1
R/W
Select output trigger of pulse output group 0.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
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12.3.5
Section 12 Programmable Pulse Generator (PPG)
PPG Output Mode Register (PMR)
PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a
low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If
non-overlapping operation is selected, PPG updates its output values at compare match A or B of
the TPU that becomes the output trigger. For details, refer to section 12.4.4, Non-Overlapping
Pulse Output.
Bit
Bit Name
Initial Value
R/W
Description
7
G3INV
1
R/W
Group 3 Inversion
Selects direct output or inverted output for pulse
output group 3.
0: Inverted output
1: Direct output
6
G2INV
1
R/W
Group 2 Inversion
Selects direct output or inverted output for pulse
output group 2.
0: Inverted output
1: Direct output
5
G1INV
1
R/W
Group 1 Inversion
Selects direct output or inverted output for pulse
output group 1.
0: Inverted output
1: Direct output
4
G0INV
1
R/W
Group 0 Inversion
Selects direct output or inverted output for pulse
output group 0.
0: Inverted output
1: Direct output
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Section 12 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
3
G3NOV
0
R/W
Group 3 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 3.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
2
G2NOV
0
R/W
Group 2 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 2.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
1
G1NOV
0
R/W
Group 1 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 1.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
0
G0NOV
0
R/W
Group 0 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 0.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the
selected TPU channel)
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12.4
Section 12 Programmable Pulse Generator (PPG)
Operation
Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
DDR
NDER
Q
Output trigger signal
C
Q PODR D
Q NDR D
Internal data bus
Pulse output pin
Normal output/inverted output
Figure 12.2 Overview Diagram of PPG
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Section 12 Programmable Pulse Generator (PPG)
12.4.1
Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 12.3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
TGRA
N+1
N
Compare match
A signal
n
NDRH
PODRH
PO8 to PO15
m
n
m
n
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)
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12.4.2
Section 12 Programmable Pulse Generator (PPG)
Sample Setup Procedure for Normal Pulse Output
Figure 12.4 shows a sample procedure for setting up normal pulse output.
Normal PPG output
Select TGR functions
[1]
Set TGRA value
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
[1] Set TIOR to make TGRA an output
compare register (with output
disabled).
[2] Set the PPG output trigger period.
TPU setup
Port and
PPG setup
TPU setup
Set next pulse
output data
[8]
Start counter
[9]
Compare match?
No
[3] Select the counter clock source with
bits TPSC2 to TPSC0 in TCR.
Select the counter clear source with
bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to 1.
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
[8] Set the next pulse output values in
NDR.
Yes
Set next pulse
output data
[10]
[9] Set the CST bit in TSTR to 1 to start
the TCNT counter.
[10] At each TGIA interrupt, set the next
output values in NDR.
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.4.3
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
TGRA
H'0000
Time
80
NDRH
PODRH
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
PO15
PO14
PO13
PO12
PO11
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)
1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
a cycle in TGRA so that the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by
writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts.
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
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12.4.4
Section 12 Programmable Pulse Generator (PPG)
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
•
•
NDR bits are always transferred to PODR bits at compare match A.
At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 12.6 illustrates the non-overlapping pulse output operation.
DDR
NDER
Q
Compare match A
Compare match B
Pulse
output
pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 12.6 Non-Overlapping Pulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 12.7 shows the timing of this operation.
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Section 12 Programmable Pulse Generator (PPG)
Compare match A
Compare match B
Write to NDR
Write to NDR
NDR
PODR
0 output
0/1 output
Write to NDR
Do not write here
to NDR here
0 output 0/1 output
Do not write
to NDR here
Write to NDR
here
Figure 12.7 Non-Overlapping Operation and NDR Write Timing
Page 814 of 1408
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12.4.5
Section 12 Programmable Pulse Generator (PPG)
Sample Setup Procedure for Non-Overlapping Pulse Output
Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
Non-overlapping
pulse output
Select TGR functions
[1]
Set TGR values
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
Set non-overlapping groups
[8]
Set next pulse
output data
[9]
Start counter
[10]
TPU setup
PPG setup
TPU setup
Compare match A?
[2] Set the pulse output trigger period
in TGRB and the non-overlap
period in TGRA.
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
No
[8] In PMR, select the groups that will
operate in non-overlap mode.
Yes
Set next pulse
output data
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled).
[11]
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.4.6
Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output)
Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRH
Time
65
95
00
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
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Section 12 Programmable Pulse Generator (PPG)
1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59, H'56, H'95... at successive TGIA interrupts.
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
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Section 12 Programmable Pulse Generator (PPG)
12.4.7
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 12.9.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRL
Time
65
95
00
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.10 Inverted Pulse Output (Example)
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12.4.8
Section 12 Programmable Pulse Generator (PPG)
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 12.11 shows the timing of this output.
φ
TIOC pin
Input capture
signal
NDR
N
PODR
M
PO
M
N
N
Figure 12.11 Pulse Output Triggered by Input Capture (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.5
Usage Notes
12.5.1
Module Stop Function Setting
H8S/2456, H8S/2456R, H8S/2454 Group
PPG operation can be disabled or enabled using the module stop control register. The initial value
is for PPG operation to be halted. Register access is enabled by clearing the module stop state. For
details, refer to section 24, Power-Down Modes.
12.5.2
Operation of Pulse Output Pins
Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by
another peripheral function is enabled, the corresponding pins cannot be used for pulse output.
Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage
of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
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Section 13 8-Bit Timers (TMR)
Section 13 8-Bit Timers (TMR)
This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit
counter. The 8-bit timer module can be used to count external events and be used as a
multifunction timer in a variety of applications, such as generation of counter reset, interrupt
requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two
registers.
13.1
Features
• Selection of seven clock sources
The counters can be driven by one of six internal clock signals (φ/2, φ/8, φ/32, φ/64, φ/1024, or
φ/8192) or an external clock input
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal (rising
edge, rising and falling edges, falling edge, low level, or high level)
• Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output
• Provision for cascading of two channels (TMR_0 and TMR_1)
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode)
TMR_1 can be used to count TMR_0 compare matches (compare match count mode)
• Three independent interrupts
Compare match A and B and overflow interrupts can be requested independently
• A/D converter conversion start trigger can be generated
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Section 13 8-Bit Timers (TMR)
Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
Internal clock sources
φ/2
φ/8
φ/32
φ/64
φ/1024
φ/8192
Counter clock 1
Counter clock 0
TMCI0
TMCI1
Compare match A1
Compare match A0
Overflow 1
Overflow 0
TMO0
TMRI0
TCORA_0
TCORA_1
Comparator A_0
Comparator A_1
TCNT_0
TCNT_1
Comparator B_0
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
TCCR_0
TCCR_1
Channel 0
(TMR_0)
Channel 1
(TMR_1)
Counter clear 0
Counter clear 1
Control logic
TMO1
TMRI1
Compare match B1
Compare match B0
A/D
conversion
start request
signal
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
[Legend]
TCORA_0:
TCNT_0:
TCORB_0:
TCSR_0:
TCR_0:
TCCR_0:
Time constant register A_0
Timer counter_0
Time constant register B_0
Timer control/status register_0
Timer control register_0
Timer counter control register_0
TCORA_1:
TCNT_1:
TCORB_1:
TCSR_1:
TCR_1:
TCCR_1:
Internal bus
Clock select
Time constant register A_1
Timer counter_1
Time constant register B_1
Timer control/status register_1
Timer control register_1
Timer counter control register_1
Figure 13.1 Block Diagram of 8-Bit Timer Module
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13.2
Section 13 8-Bit Timers (TMR)
Input/Output Pins
Table 13.1 shows the pin configuration of the 8-bit timer module.
Table 13.1 Pin Configuration
Channel
0
1
Name
Symbol
I/O
Function
Timer output pin
TMO0
Output
Outputs at compare match
Timer clock input pin
TMCI0
Input
Inputs external clock for counter
Timer reset input pin
TMRI0
Input
Inputs external reset to counter
Timer output pin
TMO1
Output
Outputs at compare match
Timer clock input pin
TMCI1
Input
Inputs external clock for counter
Timer reset input pin
TMRI1
Input
Inputs external reset to counter
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Section 13 8-Bit Timers (TMR)
13.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The 8-bit timer module has the following registers. For details on the module stop control register,
see section 24.1.2, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).
•
•
•
•
•
•
•
•
•
•
•
•
Timer counter_0 (TCNT_0)
Time constant register A_0 (TCORA_0)
Time constant register B_0 (TCORB_0)
Timer control register_0 (TCR_0)
Timer control/status register_0 (TCSR_0)
Timer counter control register_0 (TCCR_0)
Timer counter_1 (TCNT_1)
Time constant register A_1 (TCORA_1)
Time constant register B_1 (TCORB_1)
Timer control register_1 (TCR_1)
Timer control/status register_1 (TCSR_1)
Timer counter control register_1 (TCCR_1)
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13.3.1
Section 13 8-Bit Timers (TMR)
Timer Counter (TCNT)
TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be
accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a
clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.
Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When
TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.
13.3.2
Time Constant Register A (TCORA)
TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. The value in TCORA is
continually compared with the value in TCNT. When a match is detected, the corresponding
CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a
TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare
match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is
initialized to H'FF.
13.3.3
Time Constant Register B (TCORB)
TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. TCORB is continually
compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in
TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOBR write
cycle. The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.
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Section 13 8-Bit Timers (TMR)
13.3.4
Timer Control Register (TCR)
TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts.
Bit
Bit Name
Initial Value
R/W
Description
7
CMIEB
0
R/W
Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests (CMIB)
are enabled or disabled when the CMFB flag in
TCSR is set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
6
CMIEA
0
R/W
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA)
are enabled or disabled when the CMFA flag in
TCSR is set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI)
are enabled or disabled when the OVF flag in
TCSR is set to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4
CCLR1
0
R/W
Counter Clear 1 and 0
3
CCLR0
0
R/W
These bits select the method by which TCNT is
cleared, in combination with the TMRIS bit in
TCCR. See table 13.2.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the clock input to TCNT and
the count condition, in combination with the
ICKS1 and ICKS0 bits in TCCR. See table 13.3.
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13.3.5
Section 13 8-Bit Timers (TMR)
Timer Counter Control Register (TCCR)
TCCR selects the TCNT internal clock source and controls the external reset input.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
3
TMRIS
0
R/W
Timer Reset Input Select
Selects the external reset input, in combination
with the CCLR1 and CCLR0 bits in TCR. See
table 13.2.
2
⎯
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
1
ICKS1
0
R/W
Internal Clock Select 1, 0
0
ICKS0
0
R/W
These bits select the internal clock source, in
combination with the CKS2 to CKS0 bits in TCR.
See table 13.3.
Table 13.2 Reset Input to TCNT and Clearing Condition
TCR
TCCR
Bit 1
CCLR1
Bit 0
CCLR0
Bit 3
TMRIS
Description
0
0
0
Clearing is disabled
0
1
0
Clear by compare match A
1
0
0
Clear by compare match B
1
1
0
Clear by rising edge of external reset input
0
0
1
Clear by both rising and falling edges of external reset input
0
1
1
Clear by falling edge of external reset input
1
0
1
Clear by low level of external reset input
1
1
1
Clear by high level of external reset input
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Section 13 8-Bit Timers (TMR)
Table 13.3 Clock Input to TCNT and Count Condition
TCR
TCCR
Channel
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Bit 1
ICKS1
Bit 0
ICKS0
Description
TMR_0
0
0
0
⎯
⎯
Clock input disabled
0
0
1
0
0
Internal clock, counted at rising edge of φ/8
0
1
Internal clock, counted at rising edge of φ/2
1
0
Internal clock, counted at falling edge of φ/8
1
1
Internal clock, counted at falling edge of φ/2
0
0
Internal clock, counted at rising edge of φ/64
0
1
Internal clock, counted at rising edge of φ/32
1
0
Internal clock, counted at falling edge of φ/64
1
1
Internal clock, counted at falling edge of φ/32
0
0
Internal clock, counted at rising edge of φ/8192
0
1
Internal clock, counted at rising edge of φ/1024
1
0
Internal clock, counted at falling edge of φ/8192
1
1
Internal clock, counted at falling edge of φ/1024
⎯
⎯
Counted at TCNT_1 overflow signal*
0
0
1
TMR_1
1
1
0
0
1
0
0
0
0
⎯
⎯
Clock input disabled
0
0
1
0
0
Internal clock, counted at rising edge of φ/8
0
1
Internal clock, counted at rising edge of φ/2
1
0
Internal clock, counted at falling edge of φ/8
1
1
Internal clock, counted at falling edge of φ/2
0
0
Internal clock, counted at rising edge of φ/64
0
1
Internal clock, counted at rising edge of φ/32
1
0
Internal clock, counted at falling edge of φ/64
0
0
1
Page 828 of 1408
1
1
0
0
1
0
1
1
Internal clock, counted at falling edge of φ/32
0
0
Internal clock, counted at rising edge of φ/8192
0
1
Internal clock, counted at rising edge of φ/1024
1
0
Internal clock, counted at falling edge of φ/8192
1
1
Internal clock, counted at falling edge of φ/1024
⎯
⎯
Counted at TCNT_0 compare match A*
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Section 13 8-Bit Timers (TMR)
TCR
TCCR
Channel
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Bit 1
ICKS1
Bit 0
ICKS0
Description
All
1
0
1
⎯
⎯
External clock, counted at rising edge
1
0
⎯
⎯
External clock, counted at falling edge
1
1
⎯
⎯
External clock, counted at both rising and falling
edges
Note:
13.3.6
*
If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
•
TCSR_0
Bit
Bit Name
Initial Value
R/W
Description
7
CMFB
0
R/(W)*
Compare Match Flag B
[Setting condition]
•
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt while
DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
•
Set when TCNT matches TCORA
[Clearing conditions]
R01UH0309EJ0500 Rev. 5.00
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•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt while
DISEL bit of MRB in DTC is 0
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Section 13 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
5
OVF
0
R/(W)*
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4
ADTE
0
R/W
A/D Trigger Enable
Selects enabling or disabling of A/D converter
start requests by compare match A.
0: A/D converter start requests by compare match
A are disabled
1: A/D converter start requests by compare match
A are enabled
3
OS3
0
R/W
Output Select 3 and 2
2
OS2
0
R/W
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
OS1
0
R/W
Output Select 1 and 0
0
OS0
0
R/W
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note: Only 0 can be written to, to clear these flags.
Page 830 of 1408
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•
Section 13 8-Bit Timers (TMR)
TCSR_1
Bit
Bit Name
Initial Value
R/W
Description
7
CMFB
0
R/(W)*
Compare Match Flag B
[Setting condition]
•
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt while
DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
•
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt while
DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
•
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
•
4
⎯
1
R
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
Reserved
This bit is always read as 1 and cannot be
modified.
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Section 13 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
3
OS3
0
R/W
Output Select 3 and 2
2
OS2
0
R/W
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
OS1
0
R/W
Output Select 1 and 0
0
OS0
0
R/W
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to, to clear these flags.
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13.4
Operation
13.4.1
Pulse Output
Section 13 8-Bit Timers (TMR)
Figure 13.2 shows an example in which the 8-bit timer is used to generate a pulse output with a
selected duty cycle. The control bits are set as follows:
[1] In TCR, the CCLR1 bit is cleared to 0 and the CCLR0 bit is set to 1 so that TCNT is cleared at
a TCORA compare match.
[2] In TCSR, the OS3 to OS0 bits are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 13.2 Example of Pulse Output
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Section 13 8-Bit Timers (TMR)
13.4.2
Reset Input
Figure 13.3 shows an example in which the 8-bit timer is used to generate a pulse output with a
selected delay in response to the TMRI input. The control bits are set as follows:
[1] The CCLR0 bit in TCR is set to 1 and the TMRIS bit in TCCR is set to 1 so that TCNT is
cleared at the high level of the TMRI input.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses whose delay from the TMRI input is
determined by TCORA and the pulse width determined by (TCORB − TCORA).
TCORB
TCORA
TCNT
H'00
TMRI
TMO
Figure 13.3 Example of Reset Input
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13.5
Operation Timing
13.5.1
TCNT Incrementation Timing
Section 13 8-Bit Timers (TMR)
Figure 13.4 shows the count timing for internal clock input. Figure 13.5 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 13.4 Count Timing for Internal Clock Input
φ
External clock
input pin
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 13.5 Count Timing for External Clock Input
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Section 13 8-Bit Timers (TMR)
13.5.2
Timing of CMFA and CMFB Setting when Compare-Match Occurs
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input. Figure
13.6 shows this timing.
φ
TCNT
N
TCOR
N
N+1
Compare match
signal
CMF
Figure 13.6 Timing of CMF Setting
13.5.3
Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 13.7 Timing of Timer Output
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13.5.4
Section 13 8-Bit Timers (TMR)
Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1
and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this
operation.
φ
Compare match
signal
TCNT
N
H'00
Figure 13.8 Timing of Compare Match Clear
13.5.5
Timing of TCNT External Reset
TCNT is cleared at the rising edge, falling edge, low level, or high level of an external reset input,
depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR.
The clear pulse width must be at least 1.5 states for a single edge and at least 2.5 states for both
edges. Figure 13.9 shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 13.9 Timing of Clearance by External Reset
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Section 13 8-Bit Timers (TMR)
13.5.6
Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.10
shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 13.10 Timing of OVF Setting
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13.6
Section 13 8-Bit Timers (TMR)
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
13.6.1
16-Bit Counter Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
[1] Setting of compare match flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
[2] Counter clear specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
[3] Pin output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare match conditions.
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare match conditions.
13.6.2
Compare Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A's for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
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Section 13 8-Bit Timers (TMR)
13.7
Interrupt Sources
13.7.1
Interrupt Sources and DTC Activation
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are
shown in table 13.4. Each interrupt source is set as enabled or disabled by the corresponding
interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the
interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB
interrupts.
Table 13.4 8-Bit Timer Interrupt Sources
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
CMIA0
TCORA_0 compare match
CMFA
Possible
High
CMIB0
TCORB_0 compare match
CMFB
Possible
OVI0
TCNT_0 overflow
OVF
Not possible
Low
CMIA1
TCORA_1 compare match
CMFA
Possible
High
CMIB1
TCORB_1 compare match
CMFB
Possible
OVI1
TCNT_1 overflow
OVF
Not possible
13.7.2
Low
A/D Converter Activation
The A/D converter can be activated only by TMR_0 compare match A. If the ADTE bit in TCSR0
is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0 compare match A, a
request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start
trigger has been selected on the A/D converter side at this time, A/D conversion is started.
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Section 13 8-Bit Timers (TMR)
13.8
Usage Notes
13.8.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 13.11 shows
this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 13.11 Contention between TCNT Write and Clear
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Section 13 8-Bit Timers (TMR)
13.8.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 13.12 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.12 Contention between TCNT Write and Increment
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13.8.3
Section 13 8-Bit Timers (TMR)
Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 13.13.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare match signal
Inhibited
Figure 13.13 Contention between TCOR Write and Compare Match
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Section 13 8-Bit Timers (TMR)
13.8.4
H8S/2456, H8S/2456R, H8S/2454 Group
Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 13.5.
Table 13.5 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
13.8.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 13.6 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1,
CKS0, ICKS1, and ICKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the rising edge or falling edge of the
internal clock pulse is detected. Therefore, when the falling edge is selected, if clock switching
causes a change from high to low level, as shown in case 3 in table 13.6, a TCNT clock pulse is
generated and the TCNT incremented on the assumption that the switchover is a falling edge. This
is the same as when the rising edge is selected.
The erroneous incrementation can also happen when switching between the rising edge and falling
edge of an internal clock or switching between internal and external clocks.
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Section 13 8-Bit Timers (TMR)
Table 13.6 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of Modifying
CKS1, CKS0, ICKS1,
and ICKS0 Bits
TCNT Clock Operation
Switching from
low to low*1
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
CKS bit write
2
Switching from
low to high*2
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
3
Switching from
high to low*3
Clock before
swichover
Clock after
swichover
*4
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
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Section 13 8-Bit Timers (TMR)
No.
4
Timing of Switchover
by Means of Modifying
CKS1, CKS0, ICKS1,
and ICKS0 Bits
TCNT Clock Operation
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
Notes: 1.
2.
3.
4.
13.8.6
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
and compare match count modes simultaneously.
13.8.7
Module Stop Function Setting
Operation of the TMR can be disabled or enabled using the module stop control register. The
initial setting is for operation of the TMR to be halted. Register access is enabled by clearing the
module stop state. For details, refer to section 24, Power-Down Modes.
13.8.8
Interrupts in Module Stop State
If a transition is made to the module stop state when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts
should therefore be disabled before entering the module stop state.
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Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At
the same time, the WDT can also generate an internal reset signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 14.1.
14.1
Features
• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode
• If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not
the entire chip is reset at the same time.
Interval Timer Mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
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Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Clock
WDTOVF
Internal reset signal*
Clock
select
Reset
control
RSTCSR
TCNT
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
TSCR
Module bus
Bus
interface
Internal bus
Section 14 Watchdog Timer (WDT)
WDT
[Legend]
Timer control/status register
TCSR:
Timer counter
TCNT:
RSTCSR: Reset control/status register
Note: * An internal reset signal can be generated by the register setting.
Figure 14.1 Block Diagram of WDT
14.2
Input/Output Pin
Table 14.1 shows the WDT pin configuration.
Table 14.1 Pin Configuration
Name
Symbol
I/O
Function
Watchdog timer overflow
WDTOVF
Output
Outputs counter overflow signal in watchdog
timer mode
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14.3
Section 14 Watchdog Timer (WDT)
Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 14.6.1, Notes on Register Access.
•
•
•
Timer counter (TCNT)
Timer control/status register (TCSR)
Reset control/status register (RSTCSR)
14.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
14.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
7
Bit Name
OVF
Initial Value
R/W
Description
0
R/(W)*
Overflow Flag
Indicates that TCNT has overflowed in interval
timer mode. Only a write of 0 is permitted, to clear
the flag.
[Setting condition]
When TCNT overflows in interval timer mode
(changes from H'FF to H'00)
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
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Section 14 Watchdog Timer (WDT)
Bit
Bit Name
Initial Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
1: Watchdog timer mode
When TCNT overflows, the WDTOVF signal is
output.
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
4, 3
⎯
All 1
⎯
Reserved
These bits are always read as 1 and cannot be
modified.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
Selects the clock source to be input to TCNT. The
overflow frequency for φ = 20 MHz is enclosed in
parentheses.
000: Clock φ/2 (frequency: 25.6 μs)
001: Clock φ/64 (frequency: 819.2 μs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)
Note:
*
Only a write of 0 is permitted, to clear the flag.
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14.3.3
Section 14 Watchdog Timer (WDT)
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Bit
Bit Name
Initial Value
R/W
Description
7
WOVF
0
R/(W)*
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
6
RSTE
0
R/W
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR
in WDT are reset)
1: Reset signal is generated if TCNT overflows
⎯
5
0
R/W
Reserved
Can be read and written, but does not affect
operation.
⎯
4 to 0
All 1
⎯
Reserved
These bits are always read as 1 and cannot be
modified.
Note:
*
Only a write of 0 is permitted, to clear the flag.
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Section 14 Watchdog Timer (WDT)
14.4
Operation
14.4.1
Watchdog Timer Mode
H8S/2456, H8S/2456R, H8S/2454 Group
To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1.
If TCNT overflows without being rewritten because of a system crash or other error, the
WDTOVF signal is output.
This ensures that TCNT does not overflow while the system is operating normally. Software must
prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer
mode.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI
internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input
to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
The internal reset signal is output for 518 states.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the
entire chip.
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Section 14 Watchdog Timer (WDT)
TCNT count
Overflow
H'FF
Time
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WOVF=1
WDTOVF and
internal reset are
generated
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal
132 states*2
Internal reset signal*1
518 states
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Figure 14.2 Operation in Watchdog Timer Mode
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Section 14 Watchdog Timer (WDT)
14.4.2
Interval Timer Mode
To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1.
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the same time the OVF bit in the TCSR is set to 1.
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT=0
TME=1
WOVI
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 14.3 Operation in Interval Timer Mode
14.5
Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 14.2 WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Impossible
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14.6
Usage Notes
14.6.1
Notes on Register Access
Section 14 Watchdog Timer (WDT)
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
(1)
Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte
data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer
instruction cannot perform writing to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0
to the WOVF bit, satisfy the lower condition shown in figure 14.4.
If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit.
To write to the RSTE bit, satisfy the above condition shown in figure 14.4. If satisfied, the transfer
instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the
WOVF bit.
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Section 14 Watchdog Timer (WDT)
TCNT write or
Writing to RSTE bit in RSTCSR
15
Address: H'FFBC (TCNT)
H'FFBE (RSTCSR)
8
7
H'5A
0
Write data
TCSR write
Address: H'FFBC (TCSR)
15
8
7
H'A5
0
Write data
Writing 0 to WOVF bit in RSTCSR
Address: H'FFBE (RSTCSR)
15
8
7
H'A5
0
H'00
Writing to RSTE bit in RSTCSR
Address: H'FFBE (RSTCSR)
15
8
H'5A
7
0
Write data
Figure 14.4 Writing to TCNT, TCSR, and RSTCSR
(2)
Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.
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14.6.2
Section 14 Watchdog Timer (WDT)
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write
cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this
operation.
TCNT write cycle
T1
T2
Next cycle
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 14.5 Contention between TCNT Write and Increment
14.6.3
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
14.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
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Section 14 Watchdog Timer (WDT)
14.6.5
H8S/2456, H8S/2456R, H8S/2454 Group
Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
14.6.6
System Reset by WDTOVF Signal
If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly.
Make sure that the WDTOVF signal is not input logically to the RES pin.
To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6.
This LSI
Reset input
Reset signal to entire system
RES
WDTOVF
Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example)
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Section 15 Serial Communication Interface (SCI, IrDA)
Section 15 Serial Communication Interface (SCI, IrDA)
This LSI has five independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface
Adapter (ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function) in asynchronous mode. The SCI also supports an IC
card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an
asynchronous serial communication interface extension function. One of the five SCI channels
(SCI_0) can generate an IrDA communication waveform conforming to IrDA specification
version 1.0.
Figure 15.1 shows a block diagram of the SCI.
15.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources ⎯ transmit-end, transmit-data-empty, receive-data-full, and receive
error ⎯ that can issue requests. The transmit-data-empty interrupt and receive data full
interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC).
• Module stop state can be set.
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Section 15 Serial Communication Interface (SCI, IrDA)
H8S/2456, H8S/2456R, H8S/2454 Group
Asynchronous Mode
•
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
• Average transfer rate generator (SCI_2 only):
115.152, or 460.606 kbps at 10.667-MHz operation
115.196, 460.784, or 720 kbps at 16-MHz operation
720 kbps at 32-MHz operation
Clocked Synchronous Mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
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Bus interface
Section 15 Serial Communication Interface (SCI, IrDA)
Module data bus
RxD
RDR
TDR
RSR
TSR
SCMR
SSR
SCR
SMR
SEMR
BRR
φ
Baud rate
generator
Transmission/
reception control
TxD
Parity generation
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
Internal
data bus
[Legend]
RSR:
Receive shift register
RDR:
Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
SCR:
Serial control register
SSR:
Serial status register
SCMR: Smart card mode register
BRR:
Bit rate register
SEMR: Serial extension mode register (only in SCI_2)
TEI
TXI
RXI
ERI
Average transfer
rate generator
(SCI_2)
10.667 MHz operation
• 115.152 kbps
• 460.606 kbps
16 MHz operation
• 115.196 kbps
• 460.784 kbps
• 720 kbps
32 MHz operation
• 720 kbps
Figure 15.1 Block Diagram of SCI
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Section 15 Serial Communication Interface (SCI, IrDA)
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the serial communication interface.
Table 15.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
Channel 0 clock input/output
RxD0/IrRxD
Input
Channel 0 receive data input (normal/IrDA)
TxD0/IrTxD
Output
Channel 0 transmit data output (normal/IrDA)
SCK1
I/O
Channel 1 clock input/output
1
2
3
4
Note:
*
RxD1
Input
Channel 1 receive data input
TxD1
Output
Channel 1 transmit data output
SCK2
I/O
Channel 2 clock input/output
RxD2
Input
Channel 2 receive data input
TxD2
Output
Channel 2 transmit data output
SCK3
I/O
Channel 3 clock input/output
RxD3
Input
Channel 3 receive data input
TxD3
Output
Channel 3 transmit data output
SCK4
I/O
Channel 4 clock input/output
RxD4
Input
Channel 4 receive data input
TxD4
Output
Channel 4 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
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15.3
Section 15 Serial Communication Interface (SCI, IrDA)
Register Descriptions
The SCI has the following registers. The serial mode register (SMR), serial status register (SSR),
and serial control register (SCR) are described separately for normal serial communication
interface mode and Smart Card interface mode because their bit functions partially differ.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Receive shift register_0 (RSR_0)
Transmit shift register_0 (TSR_0)
Receive data register_0 (RDR_0)
Transmit data register_0 (TDR_0)
Serial mode register_0 (SMR_0)
Serial control register_0 (SCR_0)
Serial status register_0 (SSR_0)
Smart card mode register_0 (SCMR_0)
Bit rate register_0 (BRR_0)
IrDA control register_0 (IrCR_0)
Receive shift register_1 (RSR_1)
Transmit shift register_1 (TSR_1)
Receive data register_1 (RDR_1)
Transmit data register_1 (TDR_1)
Serial mode register_1 (SMR_1)
Serial control register_1 (SCR_1)
Serial status register_1 (SSR_1)
Smart card mode register_1 (SCMR_1)
Bit rate register_1 (BRR_1)
Receive shift register_2 (RSR_2)
Transmit shift register_2 (TSR_2)
Receive data register_2 (RDR_2)
Transmit data register_2 (TDR_2)
Serial mode register_2 (SMR_2)
Serial control register_2 (SCR_2)
Serial status register_2 (SSR_2)
Smart card mode register_2 (SCMR_2)
Bit rate register_2 (BRR_2)
Serial extension mode register_2 (SEMR_2)
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Section 15 Serial Communication Interface (SCI, IrDA)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H8S/2456, H8S/2456R, H8S/2454 Group
Receive shift register_3 (RSR_3)
Transmit shift register_3 (TSR_3)
Receive data register_3 (RDR_3)
Transmit data register_3 (TDR_3)
Serial mode register_3 (SMR_3)
Serial control register_3 (SCR_3)
Serial status register_3 (SSR_3)
Smart card mode register_3 (SCMR_3)
Bit rate register_3 (BRR_3)
Receive shift register_4 (RSR_4)
Transmit shift register_4 (TSR_4)
Receive data register_4 (RDR_4)
Transmit data register_4 (TDR_4)
Serial mode register_4 (SMR_4)
Serial control register_4 (SCR_4)
Serial status register_4 (SSR_4)
Smart card mode register_4 (SCMR_4)
Bit rate register_4 (BRR_4)
15.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
15.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is
receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous
receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU.
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15.3.3
Section 15 Serial Communication Interface (SCI, IrDA)
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR for only once after confirming that
the TDRE bit in SSR is set to 1.
15.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot
be directly accessed by the CPU.
15.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock
source. Some bit functions of SMR differ in normal serial communication interface mode and
Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
C/A
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is
fixed and the MSB (bit 7) of TDR is not
transmitted in transmission.
In clocked synchronous mode, a fixed data length
of 8 bits is used.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
5
PE
0
R/W
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. For a multiprocessor
format, parity bit addition and checking are not
performed regardless of the PE bit setting.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked
regardless of the STOP bit setting. If the second
stop bit is 0, it is treated as the start bit of the next
transmit character.
2
MP
0
R/W
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/E bit settings are invalid in multiprocessor
mode.
1
CKS1
0
R/W
Clock Select 1 and 0:
0
CKS0
0
R/W
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).
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Section 15 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF bit in SCMR is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
GM
0
R/W
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of 1 bit), and clock
output control mode addition is performed. For
details, refer to section 15.7.8, Clock Output
Control.
6
BLK
0
R/W
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 15.7.3, Block Transfer Mode.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. In Smart Card interface
mode, this bit must be set to 1.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card
interface mode, refer to section 15.7.2, Data
Format (Except for Block Transfer Mode).
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
3
BCP1
0
R/W
Basic Clock Pulse 1 and 0
2
BCP0
0
R/W
These bits, in combination with the BCP2 bit in
SCMR, select the number of basic clock cycles in
a 1-bit transfer interval in Smart Card interface
mode.
BCP2 to BCP0 Settings:
000: 93 clock cycles (S = 93)
001: 128 clock cycles (S = 128)
010: 186 clock cycles (S = 186)
011: 512 clock cycles (S = 512)
100: 32 clock cycles (S = 32) (initial value)
101: 64 clock cycles (S = 64)
110: 372 clock cycles (S = 372)
111: 256 clock cycles (S = 256)
For details, refer to section 15.7.4, Receive Data
Sampling Timing and Reception Margin. S stands
for the value of S in BRR (see section 15.3.9, Bit
Rate Register (BRR)).
1
CKS1
0
R/W
Clock Select 1 and 0
0
CKS0
0
R/W
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).
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15.3.6
Section 15 Serial Communication Interface (SCI, IrDA)
Serial Control Register (SCR)
SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
15.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication
interface mode and Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
5
TE
0
R/W
Transmit Enable
When this bit s set to 1, transmission is enabled. In
this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 15.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is
received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF,
FER, and ORER flags in SSR , is not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
is enabled.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled. TEI cancellation can be performed by
reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or
by clearing the TEIE bit to 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
1
CKE1
0
R/W
Clock Enable 1 and 0
0
CKE0
0
R/W
Selects the clock source and SCK pin function.
Asynchronous mode
00: On-chip baud rate generator
SCK pin functions as I/O port
01: On-chip baud rate generator
(Outputs a clock of the same frequency as the
bit rate from the SCK pin.)
1x: External clock
(Inputs a clock with a frequency 16 times the
bit rate from the SCK pin.)
Clocked synchronous mode
0x: Internal clock (SCK pin functions as clock
output)
1x: External clock (SCK pin functions as clock
input)
[Legend]
x:
Don't care
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Section 15 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF bit in SCMR is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled. TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
Write 0 to this bit in Smart Card interface mode.
Page 872 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
TEIE
0
R/W
Transmit End Interrupt Enable
Write 0 to this bit in Smart Card interface mode.
1
CKE1
0
R/W
Clock Enable 1 and 0
0
CKE0
0
R/W
Enables or disables clock output from the SCK
pin. The clock output can be dynamically switched
in GSM mode. For details, refer to section 15.7.8,
Clock Output Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an
I/O port pin)
01: Clock output
1x: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
[Legend]
x:
Don't care
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Bit
7
Bit Name
TDRE
Initial Value
R/W
Description
1
R/(W)*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR,
and data writing to TDR is enabled.
[Clearing conditions]
6
RDRF
0
R/(W)*
•
When 0 is written to TDRE after reading TDRE
=1
•
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF
=1
•
When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the
next data is completed while the RDRF flag is set
to 1, an overrun error occurs and receive data will
be lost.
Page 874 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
5
ORER
0
R/(W)*
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended abnormally.
[Setting condition]
•
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued,
either.
[Clearing condition]
•
When 0 is written to ORER after reading
ORER = 1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
4
FER
0
R/(W)*
Framing Error
Indicates that a framing error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is
checked for a value of 0; the second stop bit is
not checked. If a framing error occurs, the
receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial
reception cannot be continued while the FER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued,
either.
[Clearing condition]
•
When 0 is written to FER after reading FER =
1
The FER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
3
PER
0
R/(W)*
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
When a parity error is detected during
reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot
be continued while the PER flag is set to 1. In
clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
•
When 0 is written to PER after reading PER =
1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
Page 876 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
TEND
1
R
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TDRE after reading TDRE
=1
•
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
Note:
*
Only 0 can be written, to clear the flag.
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF bit in SCMR is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
TDRE
1
R/(W)*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR,
and data writing to TDR is enabled.
[Clearing conditions]
6
RDRF
0
R/(W)*
•
When 0 is written to TDRE after reading TDRE
=1
•
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF
=1
•
When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the
next data is completed while the RDRF flag is set
to 1, an overrun error occurs and receive data will
be lost.
Page 878 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
5
ORER
0
R/(W)*
Overrun Error
Indicates that an overrun error occurred while
receiving and the reception has ended abnormally.
[Setting condition]
•
When the next serial reception is completed
while RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER
flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued,
either.
[Clearing condition]
•
When 0 is written to ORER after reading
ORER = 1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
4
ERS
0
R/(W)*
Error Signal Status
[Setting condition]
•
When the low level of the error signal is
sampled
[Clearing conditions]
•
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
When 0 is written to ERS after reading ERS =
1
Page 879 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
3
PER
0
R/(W)*
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
When a parity error is detected during
reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot
be continued while the PER flag is set to 1. In
clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
•
When 0 is written to PER after reading PER =
1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
Page 880 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
TEND
1
R
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
When the TE bit in SCR is 0 and the ERS bit is
also 0
•
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1byte data
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 12.5 etu after transmission
GM = 0, BLK = 1: 11.5 etu after transmission
GM = 1, BLK = 0: 11.0 etu after transmission
GM = 1, BLK = 1: 11.0 etu after transmission
[Clearing conditions]
•
When 0 is written to TEND after reading TEND
=1
•
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
1
MPB
0
R
Multiprocessor Bit
0
MPBT
0
R/W
Multiprocessor Bit Transfer
This bit is not used in Smart Card interface mode.
Write 0 to this bit in Smart Card interface mode.
Note:
*
Only 0 can be written, to clear the flag.
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.8
Smart Card Mode Register (SCMR)
SCMR selects Smart Card interface mode and its format.
Bit
Bit Name
Initial Value
R/W
Description
7
BCP2
1
R/W
Basic Clock Pulse 2
Selects, in combination with the BCP1 and BCP0
bits in SMR, the number of basic clock cycles in a
1-bit transfer interval in Smart Card interface
mode.
For the settings, refer to section 15.3.5, Serial
Mode Register (SMR).
6 to 4
⎯
All 1
⎯
Reserved
These bits are always read as 1.
3
SDIR
0
R/W
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
2
SINV
0
R/W
Smart Card Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the parity
bit. To invert the parity bit, invert the O/E bit in
SMR.
0: TDR contents are transmitted as they are.
Receive data is stored as it is in RDR.
1: TDR contents are inverted before being
transmitted. Receive data is stored in inverted
form in RDR.
1
⎯
1
⎯
Reserved
This bit is always read as 1.
0
SMIF
0
R/W
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
synchronous mode
1: Smart Card interface mode
Page 882 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
15.3.9
Section 15 Serial Communication Interface (SCI, IrDA)
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode
ABCS
Bit
Asynchronous 0
Mode
Bit Rate
N=
1
N=
Clocked Synchronous
Mode
N=
Smart Card Interface
Mode
N=
Error
φ × 106
64 × 2
2n−1
×B
φ × 106
32 × 2 2n−1 × B
φ × 106
8 × 2 2n−1 × B
φ × 106
S × 2 2n+1 × B
− 1 Error (%) = {
− 1 Error (%) = {
φ × 106
B × 64 × 2 2n−1 × (N + 1)
φ × 106
B × 32 × 2 2n−1 × (N + 1)
− 1 } × 100
− 1 } × 100
−1
− 1 Error (%) = {
φ × 106
B × S × 2 2n+1 × (N + 1)
− 1 } × 100
Note: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
SCMR Setting
SMR Setting
CKS1
CKS0
n
BCP2
BCP1
BCP0
S
0
0
0
0
0
0
93
0
1
1
0
0
1
128
1
0
2
0
1
0
186
1
1
3
0
1
1
512
1
0
0
32
1
0
1
64
1
1
0
372
1
1
1
256
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N
settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock cycles in
a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data
Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with
external clock input.
The bit rate should be twice the value in table 15.3 when the ABCS bit in the serial expansion
mode register of the SCI_2 (SEMR_2) is 1 in asynchronous mode.
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
8
9.8304
10
12
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
141
0.03
2
174
–0.26
2
177
–0.25
2
212
0.03
150
2
103
0.16
2
127
0.00
2
129
0.16
2
155
0.16
300
1
207
0.16
1
255
0.00
2
64
0.16
2
77
0.16
600
1
103
0.16
1
127
0.00
1
129
0.16
1
155
0.16
1200
0
207
0.16
0
255
0.00
1
64
0.16
1
77
0.16
2400
0
103
0.16
0
127
0.00
0
129
0.16
0
155
0.16
4800
0
51
0.16
0
63
0.00
0
64
0.16
0
77
0.16
9600
0
25
0.16
0
31
0.00
0
32
–1.36
0
38
0.16
19200
0
12
0.16
0
15
0.00
0
15
1.73
0
19
–2.34
31250
0
7
0.00
0
9
–1.70
0
9
0.00
0
11
0.00
38400
⎯
⎯
⎯
0
7
0.00
0
7
1.73
0
9
–2.34
Page 884 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Operating Frequency φ (MHz)
12.288
14
14.7456
16
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
217
0.08
2
248
–0.17
3
64
0.69
3
70
0.03
150
2
159
0.00
2
181
0.16
2
191
0.00
2
207
0.16
300
2
79
0.00
2
90
0.16
2
95
0.00
2
103
0.16
600
1
159
0.00
1
181
0.16
1
191
0.00
1
207
0.16
1200
1
79
0.00
1
90
0.16
1
95
0.00
1
103
0.16
2400
0
159
0.00
0
181
0.16
0
191
0.00
0
207
0.16
4800
0
79
0.00
0
90
0.16
0
95
0.00
0
103
0.16
9600
0
39
0.00
0
45
1.73
0
47
0.00
0
51
0.16
19200
0
19
0.00
0
22
1.73
0
23
0.00
0
25
0.16
31250
0
11
2.40
0
13
0.00
0
14
–1.70
0
15
0.00
38400
0
9
0.00
⎯
⎯
⎯
0
11
0.00
0
12
0.16
Operating Frequency φ (MHz)
17.2032
18
19.6608
20
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
75
0.48
3
79
–0.12
3
86
0.31
3
88
–0.25
150
2
223
0.00
2
233
0.16
2
255
0.00
3
64
0.16
300
2
111
0.00
2
116
0.16
2
127
0.00
2
129
0.16
600
1
223
0.00
1
233
0.16
1
255
0.00
2
64
0.16
1200
1
111
0.00
1
116
0.16
1
127
0.00
1
129
0.16
2400
0
223
0.00
0
233
0.16
0
255
0.00
1
64
0.16
4800
0
111
0.00
0
116
0.16
0
127
0.00
0
129
0.16
9600
0
55
0.00
0
58
–0.69
0
63
0.00
0
64
0.16
19200
0
27
0.00
0
28
1.01
0
31
0.00
0
32
–1.36
31250
0
16
1.20
0
17
0.00
0
19
–1.70
0
19
0.00
38400
0
13
0.00
0
14
–2.34
0
15
0.00
0
15
1.73
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Section 15 Serial Communication Interface (SCI, IrDA)
Operating Frequency φ (MHz)
25
30
33
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
110
–0.02
3
132
0.13
3
145
0.33
150
3
80
0.47
3
97
–0.35
3
106
0.39
300
2
162
–0.15
2
194
0.16
2
214
–0.07
600
2
80
0.47
2
97
–0.35
2
106
0.39
1200
1
162
–0.15
1
194
0.16
1
214
–0.07
2400
1
80
0.47
1
97
–0.35
1
106
0.39
4800
0
162
–0.15
0
194
0.16
0
214
–0.07
9600
0
80
0.47
0
97
–0.35
0
106
0.39
19200
0
40
–0.76
0
48
–0.35
0
53
–0.54
31250
0
24
0.00
0
29
0.00
0
32
0.00
38400
0
19
1.73
0
23
1.73
0
26
–0.54
Note: For the SCI_2, values in the table are the examples with ABCS = 0 in SEMR_2. When
ABCS = 1, the bit rates should be twice the values given above.
Page 886 of 1408
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
19.6608
614400
0
0
20
625000
0
0
25
781250
0
0
30
937500
0
0
33
1031250
0
0
Note: For the SCI_2, values in the table are the examples with ABCS = 0 in SEMR_2. When
ABCS = 1, the bit rates should be twice the values given above.
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Sep 24, 2012
Page 887 of 1408
Section 15 Serial Communication Interface (SCI, IrDA)
H8S/2456, H8S/2456R, H8S/2454 Group
Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bit/s)
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
19.6608
4.9152
307200
20
5.0000
312500
25
6.2500
390625
30
7.5000
468750
33
8.2500
515625
Note: For the SCI_2, values in the table are the examples with ABCS = 0 in SEMR_2. When
ABCS = 1, the bit rates should be twice the values given above.
Page 888 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
Bit
Rate
(bit/s) n
8
10
16
N
n
N
n
N
20
n
N
25
n
N
30
n
N
3
233
33
n
N
110
250
3
124
⎯
⎯
3
249
500
2
249
⎯
⎯
3
124
⎯
⎯
1k
2
124
⎯
⎯
2
249
⎯
⎯
3
97
3
116
3
128
2.5 k
1
199
1
249
2
99
2
124
2
155
2
187
2
205
5k
1
99
1
124
1
199
1
249
2
77
2
93
2
102
10 k
0
199
0
249
1
99
1
124
1
155
1
187
1
205
25 k
0
79
0
99
0
159
0
199
0
249
1
74
1
82
50 k
0
39
0
49
0
79
0
99
0
124
0
149
0
164
100 k
0
19
0
24
0
39
0
49
0
62
0
74
0
82
250 k
0
7
0
9
0
15
0
19
0
24
0
29
0
32
500 k
0
3
0
4
0
7
0
9
⎯
⎯
0
14
⎯
⎯
1M
0
1
0
3
0
4
⎯
⎯
⎯
⎯
⎯
⎯
0
0*
0
1
⎯
⎯
0
2
⎯
⎯
0
0*
⎯
⎯
⎯
⎯
⎯
⎯
2.5 M
5M
[Legend]
Blank: Cannot be set.
⎯:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
8
1.3333
1333333.3
18
3.0000
3000000.0
10
1.6667
1666666.7
20
3.3333
3333333.3
12
2.0000
2000000.0
25
4.1667
4166666.7
14
2.3333
2333333.3
30
5.0000
5000000.0
16
2.6667
2666666.7
33
5.5000
5500000.0
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372)
Operating Frequency φ (MHz)
10.00
10.7136
13.00
14.2848
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
1
30.00
0
1
25.00
0
1
8.99
0
1
0.00
Operating Frequency φ (MHz)
16.00
18.00
20.00
25.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
1
12.01
0
2
15.99
0
2
6.66
0
3
12.49
Operating Frequency φ (MHz)
30.00
33.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
9600
0
3
5.01
0
4
7.59
Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
10.00
13441
0
0
18.00
24194
0
0
10.7136
14400
0
0
20.00
26882
0
0
13.00
17473
0
0
25.00
33602
0
0
14.2848
19200
0
0
30.00
40323
0
0
16.00
21505
0
0
33.00
44355
0
0
Page 890 of 1408
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 15 Serial Communication Interface (SCI, IrDA)
15.3.10 IrDA Control Register (IrCR)
IrCR selects the function of SCI_0.
Bit
Bit Name
Initial Value
R/W
Description
7
IrE
0
R/W
IrDA Enable
Specifies normal SCI mode or IrDA mode for
SCI_0 input/output.
0: Pins TxD0/IrTxD and RxD0/IrRxD function as
TxD0 and RxD0
1: Pins TxD0/IrTxD and RxD0/IrRxD function as
IrTxD and IrRxD
6
IrCKS2
0
R/W
IrDA Clock Select 2 to 0
5
IrCKS1
0
R/W
4
IrCKS0
0
R/W
Specifies the high pulse width in IrTxD output
pulse encoding when the IrDA function is enabled.
000: Pulse width = B × 3/16 (3/16 of bit rate)
001: Pulse width = φ/2
010: Pulse width = φ/4
011: Pulse width = φ/8
100: Pulse width = φ/16
101: Pulse width = φ/32
110: Pulse width = φ/64
111: Pulse width = φ/128
3
IrTxINV
0
R/W
IrTx Data Invert
Specifies the logic level of the IrTxD output to be
inverted. When inversion is performed, the high
pulse width specified by bits 6 to 4 becomes the
low pulse width.
0: Transmit data is used as IrTxD output without
change
1: Transmit data is inverted before used as IrTxD
output
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
IrRxINV
0
R/W
IrRx Data Invert
Specifies the logic level of the IrRxD output to be
inverted. When inversion is performed, the high
pulse width specified by bits 6 to 4 becomes the
low pulse width.
0: Transmit data is used as IrRxD output without
change
1: Transmit data is inverted before used as IrRxD
output
1, 0
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
15.3.11 SCI_2 Serial Extension Mode Register (SEMR)
SEMR selects the clock source in asynchronous mode for the SCI_2. The basic clock can be
automatically set by selecting the average transfer rate.
Bit
Bit Name
7 to 4 ⎯
Initial Value
R/W
Description
Undefined
⎯
Reserved
If these bits are read, an undefined value will be
returned and cannot be modified.
3
ABCS
0
R/W
Asynchronous basic clock selection (valid only in
asynchronous mode)
Selects the basic clock for 1-bit period in
asynchronous mode.
0: Operates on a basic clock with a frequency of
16 times the transfer rate.
1: Operates on a basic clock with a frequency of 8
times the transfer rate.
Page 892 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
ACS2
0
R/W
1
ACS1
0
R/W
Asynchronous clock source selection (valid when
CKE1 = 1 in asynchronous mode)
0
ACS0
0
R/W
Selects the clock source for the average transfer
rate.
The basic clock can be automatically set by
selecting the average transfer rate in spite of the
value of ABCS.
000: External clock input
001: Selects 115.152 kbps which is the average
transfer rate dedicated for φ= 10.667 MHz.
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
010: Selects 460.606 kbps which is the average
transfer rate dedicated for φ= 10.667 MHz.
(Operates on a basic clock with a frequency
of 8 times the transfer rate.)
011: Selects 720 kbps which is the average
transfer rate dedicated for φ = 32 MHz.
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
100: Reserved
101: Selects 115.196 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
110: Selects 460.784 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
111: Selects 720 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a frequency
of 8 times the transfer rate.)
Note that the average transfer rate does not
correspond to the frequency other than 10.667,
16, or 32 MHz.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4
Operation in Asynchronous Mode
Figure 15.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. In asynchronous serial communication, the
communication line is usually held in the mark state (high level). The SCI monitors the
communication line, and when it goes to the space state (low level), recognizes a start bit and
starts serial communication. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication. Both the transmitter and the receiver also have a doublebuffered structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer.
Idle state
(mark state)
LSB
1
Serial
data
0
D0
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity Stop bit(s)
bit
1 bit,
or none
1 or
2 bits
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
15.4.1
Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 15.5, Multiprocessor Communication Function.
Page 894 of 1408
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
R01UH0309EJ0500 Rev. 5.00
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
M = { (0.5 –
1
⏐D – 0.5⏐
) – (L – 0.5) F –
(1 + F) } × 100 [%]
2N
N
... Formula (1)
Where M: Reception Margin
N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
7
0
15 0
7
15 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
Page 896 of 1408
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15.4.3
Section 15 Serial Communication Interface (SCI, IrDA)
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4.
SCK
TxD
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 15.4 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is
cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external
clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start of initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. (Not necessary if
an external clock is used.)
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
Figure 15.5 Sample SCI Initialization Flowchart
Page 898 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
15.4.5
Section 15 Serial Communication Interface (SCI, IrDA)
Data Transmission (Asynchronous Mode)
Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Because the TXI interrupt routine writes the next transmit data to TDR before
transmission of the current transmit data has finished, continuous transmission can be enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 15.7 shows a sample flowchart for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1?
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or DTC
is activated by a transmit-dataempty interrupt (TXI) request, and
data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
Figure 15.7 Sample Serial Transmission Flowchart
Page 900 of 1408
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15.4.6
Section 15 Serial Communication Interface (SCI, IrDA)
Serial Data Reception (Asynchronous Mode)
Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
ERI interrupt request
generated by framing
error
1 frame
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
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Sep 24, 2012
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Section 15 Serial Communication Interface (SCI, IrDA)
H8S/2456, H8S/2456R, H8S/2454 Group
Table 15.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample
flowchart for serial data reception.
Table 15.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
ORER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains its state before data reception.
Page 902 of 1408
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Initialization
Section 15 Serial Communication Interface (SCI, IrDA)
[1]
Start of reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling and
break detection:
Read ORER, PER, and
If a receive error occurs, read the
[2]
FER flags in SSR
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
processing, ensure that the
PER ∨ FER ∨ ORER = 1?
ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot
No
Error handling
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
No
RDRF = 1?
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DMAC or DTC is
activated by an RXI interrupt and
the RDR value is read.
Figure 15.9 Sample Serial Reception Data Flowchart (1)
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Section 15 Serial Communication Interface (SCI, IrDA)
[3]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags in SSR to 0
Figure 15.9 Sample Serial Reception Data Flowchart (2)
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15.5
Section 15 Serial Communication Interface (SCI, IrDA)
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component cycles:
an ID transmission cycle which specifies the receiving station, and a data transmission cycle to the
specified receiving station. The multiprocessor bit is used to differentiate between the ID
transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID
transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure
15.10 shows an example of inter-processor communication using the multiprocessor format. The
transmitting station first sends communication data with a 1 multiprocessor bit added to the ID
code of the receiving station. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On
reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB= 1)
ID transmission cycle =
receiving station
specification
(MPB= 0)
Data transmission cycle =
data transmission to
receiving station specified by ID
Legend:
MPB: Multiprocessor bit
Figure 15.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
15.5.1
Multiprocessor Serial Data Transmission
Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
[1] [1] SCI initialization:
Initialization
Start of transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1,
a frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC is activated by a
transmit-data-empty interrupt
(TXI) request, and data is written
to TDR.
TEND = 1?
Yes
No
Break output?
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Yes
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.5.2
H8S/2456, H8S/2456R, H8S/2454 Group
Multiprocessor Serial Data Reception
Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
15.12 shows an example of SCI operation for multiprocessor format reception.
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1
Start
bit
0
Section 15 Serial Communication Interface (SCI, IrDA)
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data2)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
Data2
ID2
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt handling routine
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 15.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2]
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
Start of reception
Set MPIE bit in SCR to 1
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
[3] SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1?
Yes
[4] SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Read receive data in RDR
No
This station's ID?
Yes
[5] Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
Yes
No
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR
No
All data received?
[5]
Error handling
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
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[5]
Section 15 Serial Communication Interface (SCI, IrDA)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6
Operation in Clocked Synchronous Mode
Figure 15.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character of communication data consists of 8-bit data. In clocked synchronous serial
communication, data on the transmission line is output from one falling edge of the serial clock to
the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising
edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In
clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex communication by use of a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that
data can be read or written during transmission or reception, enabling continuous data transfer.
One unit of transfer data (character or frame)
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First)
15.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and
CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed the clock is fixed high.
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15.6.2
Section 15 Serial Communication Interface (SCI, IrDA)
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to
0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start of initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
[3] Write a value corresponding to the bit
rate to BRR. (Not necessary if an
external clock is used.)
[4] Wait at least one bit interval, then set
the TE and RE bits in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enable the
TxD and RxD pins to be used.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
Note: In simultaneous transmit and receive operations, the TE and RE bits should
both be cleared to 0 or set to 1 simultaneously.
Figure 15.15 Sample SCI Initialization Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6.3
H8S/2456, H8S/2456R, H8S/2454 Group
Serial Data Transmission (Clocked Synchronous Mode)
Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
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Section 15 Serial Communication Interface (SCI, IrDA)
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
TXI interrupt
and TDRE flag
request generated
cleared to 0 in TXI
interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit-dataempty interrupt (TXI) request and data
is written to TDR.
No
TEND = 1?
Yes
Clear TE bit in SCR to 0
Figure 15.17 Sample Serial Transmission Flowchart
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15.6.4
Section 15 Serial Communication Interface (SCI, IrDA)
Serial Data Reception (Clocked Synchronous Mode)
Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the received data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 15.18 Example of SCI Operation in Reception
Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart
for serial data reception.
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1?
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC is activated by a receivedata-full interrupt (RXI) request
and the RDR value is read.
[3]
Error handling
Overrun error handling
Clear ORER flag in SSR to 0
Figure 15.19 Sample Serial Reception Flowchart
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15.6.5
Section 15 Serial Communication Interface (SCI, IrDA)
Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode)
Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.
To switch from receive mode to simultaneous transmit and receive mode, after checking that the
SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error
flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single
instruction.
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start of transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
Read ORER flag in SSR
ORER = 1?
No
Read RDRF flag in SSR
Yes
[3]
Error handling
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[4]
No
RDRF = 1?
[5] Serial transmission/reception
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE and RE bits to 0,
then set both these bits to 1 simultaneously.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit-dataempty interrupt (TXI) request and
data is written to TDR. Also, the
RDRF flag is cleared automatically
when the DMAC or DTC is activated
by a receive-data-full interrupt (RXI)
request and the RDR value is read.
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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15.7
Section 15 Serial Communication Interface (SCI, IrDA)
Operation in Smart Card Interface Mode
The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification
Card) as a serial communication interface extension function. Switching between the normal serial
communication interface and the Smart Card interface is carried out by means of a register setting.
15.7.1
Pin Connection Example
Figure 15.21 shows an example of connection with the Smart Card. In communication with an IC
card, since both transmission and reception are carried out on a single data transmission line, the
TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be
pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and
RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be
carried out. When the clock generated on the SCI is used by an IC card, the SCK pin output is
input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
VCC
TxD
RxD
SCK
Rx (port)
This LSI
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Connected equipment
Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections
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Section 15 Serial Communication Interface (SCI, IrDA)
15.7.2
Data Format (Except for Block Transfer Mode)
Figure 15.22 shows the transfer data format in Smart Card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit)
is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If an error signal is sampled during transmission, the same data is retransmitted automatically
after the elapse of 2 etu or longer.
When there is no parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Transmitting station output
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Transmitting station output
Receiving station
output
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Figure 15.22 Normal Smart Card Interface Data Format
Data transfer with the types of IC cards (direct convention and inverse convention) are performed
as described in the following.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)
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Section 15 Serial Communication Interface (SCI, IrDA)
As in the above sample start character, with the direct convention type, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to
select even parity mode.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For
the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart
Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to
invert the parity bit for both transmission and reception.
15.7.3
Block Transfer Mode
Operation in block transfer mode is the same as that in normal Smart Card interface, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.7.4
H8S/2456, H8S/2456R, H8S/2454 Group
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive
clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in
normal asynchronous mode) as determined by bits BCP2 to BCP0. In reception, the SCI samples
the falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, 128th,
46th, 64th, 93rd, or 256th pulse of the basic clock, data can be latched at the middle of the bit. The
reception margin is given by the following formula.
M = ⏐ (0.5 –
1
⏐D – 0.5⏐
) – (L – 0.5) F –
(1 + F) ⏐ × 100 [%]
2N
N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256, 93, 128, 186, or 512)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
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Section 15 Serial Communication Interface (SCI, IrDA)
372 clocks
186 clocks
0
185
185
371 0
371 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.7.5
H8S/2456, H8S/2456R, H8S/2454 Group
Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also
necessary when switching from transmit mode to receive mode, or vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ERS, PER, and ORER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and the BCP2 bit in
SCMR. Set the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
To switch from receive mode to transmit mode, after checking that the SCI has finished reception,
initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be
checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode,
after checking that the SCI has finished transmission, initialize the SCI, and clear TE to 0 and set
RE to 1. Whether SCI has finished transmission can be checked with the TEND flag.
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15.7.6
Section 15 Serial Communication Interface (SCI, IrDA)
Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sampled from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next parity
bit is sampled.
2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is
retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
4. Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is
generated. Writing transmit data to TDR transfers the next transmit data.
Figure 15.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt
source. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in
SSR, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI
request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will
be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE
and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or
DMAC. In the event of an error, the SCI retransmits the same data automatically. During this
period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the
SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of
an error, including retransmission. However, the ERS flag is not cleared automatically when an
error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or
DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,
refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).
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Section 15 Serial Communication Interface (SCI, IrDA)
Transfer
frame n+1
Retransferred frame
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer to TSR from TDR
Transfer to TSR
from TDR
Transfer to TSR from TDR
TEND
[2]
[4]
FER/ERS
[1]
[3]
Figure 15.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
generation timing is shown in figure 15.27.
I/O data
Ds
TXI
(TEND interrupt)
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard
time
12.5 etu
When GM = 0
11.0 etu
When GM = 1
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
Figure 15.27 TEND Flag Generation Timing in Transmission Operation
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Section 15 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start transmission
ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Write data to TDR,
and clear TDRE flag
in SSR to 0
No
All data transmitted ?
Yes
No
ERS = 0?
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit to 0
End
Figure 15.28 Example of Transmission Processing Flow
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Section 15 Serial Communication Interface (SCI, IrDA)
15.7.7
H8S/2456, H8S/2456R, H8S/2454 Group
Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled.
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
4. The receive operation is judged to have been completed normally, and the RDRF flag in SSR
is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is
generated.
Figure 15.30 shows a flowchart for reception. The sequence of receive operations can be
performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt
source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR
is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the
DTC or DMAC will be activated by the RXI request, and transfer of the receive data will be
carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the
DTC or DMAC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a
transfer error interrupt (ERI) request will be generated, and so the error flag must be cleared to 0.
In the event of an error, the DTC or DMAC is not activated and receive data is skipped. Therefore,
receive data is transferred for only the specified number of bytes in the event of an error. Even
when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been
received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, refer to section 15.4, Operation in
Asynchronous Mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
nth transfer frame
Transfer
frame n+1
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
[1]
[3]
PER
Figure 15.29 Retransfer Operation in SCI Receive Mode
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Section 15 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start reception
ORER = 0 and
PER = 0
No
Yes
Error processing
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit to 0
Figure 15.30 Example of Reception Processing Flow
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15.7.8
Section 15 Serial Communication Interface (SCI, IrDA)
Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and
CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 15.31 Timing for Fixing Clock Output Level
When turning on the power or switching between Smart Card interface mode and software
standby mode, the following procedures should be followed in order to maintain the clock duty
cycle.
Powering On: To secure the clock duty cycle from power-on, the following switching procedure
should be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to Smart Card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
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Section 15 Serial Communication Interface (SCI, IrDA)
When Changing from Smart Card Interface Mode to Software Standby Mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
the value for the fixed output state in software standby mode.
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
operation. At the same time, set the CKE1 bit to the value for the fixed output state in software
standby mode.
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock cycle.
During this interval, clock output is fixed at the specified level, with the duty cycle preserved.
5. Make the transition to the software standby state.
When Returning to Smart Card Interface Mode from Software Standby Mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty cycle.
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
Normal operation
[6] [7]
Figure 15.32 Clock Halt and Restart Procedure
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15.8
Section 15 Serial Communication Interface (SCI, IrDA)
IrDA Operation
When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are
subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD
and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to
implement infrared transmission/reception conforming to the IrDA specification version 1.0
system.
In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600
bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this
LSI does not include a function for varying the transfer rate automatically, the transfer rate setting
must be changed by software.
Figure 15.33 shows a block diagram of the IrDA function.
SCI0
IrDA
TxD0/IrTxD
Pulse encoder
RxD0/IrRxD
Pulse decoder
TxD
RxD
IrCR
Figure 15.33 Block Diagram of IrDA
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Section 15 Serial Communication Interface (SCI, IrDA)
(1)
Transmission
In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the
IrDA interface (see figure 15.34).
When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one
bit) is output (initial value). The high-level pulse can be varied according to the setting of bits
IrCKS2 to IrCKS0 in IrCR.
In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of
(3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can
be set for a high pulse width with a minimum value of 1.41 µs.
When the serial data is 1, no pulse is output.
UART frame
Stop
bit
Data
Start
bit
0
1
0
1
0
0
1
Transmit
1
0
1
Receive
IR frame
Data
Start
bit
0
Bit
cycle
1
0
1
0
Stop
bit
0
1
1
0
1
Pulse width
1.6 μs to 3/16 bit cycle
Figure 15.34 IrDA Transmit/Receive Operations
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(2)
Section 15 Serial Communication Interface (SCI, IrDA)
Reception
In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the
SCI.
When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1
data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified
as a 0 signal.
(3)
High Pulse Width Selection
Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and
operating frequencies of this LSI and bit rates, for making the pulse width shorter than 3/16 times
the bit rate in transmission.
Table 15.12 Settings of IrCKS2 to IrCKS0 Bits
Operating
Frequency
φ (MHz)
Bit Rate (bps) (Above)/Bit Period × 3/16 (µs) (Below)
2400
9600
19200
38400
57600
115200
78.13
19.53
9.77
4.88
3.26
1.63
8
100
100
100
100
100
100
9.8304
100
100
100
100
100
100
10
100
100
100
100
100
100
12
101
101
101
101
101
101
12.288
101
101
101
101
101
101
14
101
101
101
101
101
101
14.7456
101
101
101
101
101
101
16
101
101
101
101
101
101
16.9344
101
101
101
101
101
101
17.2032
101
101
101
101
101
101
18
101
101
101
101
101
101
19.6608
101
101
101
101
101
101
20
101
101
101
101
101
101
25
110
110
110
110
110
⎯
30
110
110
110
110
110
⎯
33
110
110
110
110
110
⎯
[Legend]
⎯:
A bit rate setting cannot be made on the SCI side.
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Section 15 Serial Communication Interface (SCI, IrDA)
H8S/2456, H8S/2456R, H8S/2454 Group
15.9
Interrupt Sources
15.9.1
Interrupts in Normal Serial Communication Interface Mode
Table 15.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC or
DMAC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC or DMAC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0
automatically when data transfer is performed by the DTC or DMAC.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.13 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC
Activation
DMAC
Activation
Priority
0
ERI0
Receive Error
ORER, FER, PER
Not possible
Not possible
High
RXI0
Receive Data Full
RDRF
Possible
Possible
TXI0
Transmit Data Empty
TDRE
Possible
Possible
TEI0
Transmission End
TEND
Not possible
Not possible
ERI1
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI1
Receive Data Full
RDRF
Possible
Possible
TXI1
Transmit Data Empty
TDRE
Possible
Possible
TEI1
Transmission End
TEND
Not possible
Not possible
ERI2
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI2
Receive Data Full
RDRF
Possible
Not possible
TXI2
Transmit Data Empty
TDRE
Possible
Not possible
TEI2
Transmission End
TEND
Not possible
Not possible
ERI3
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI3
Receive Data Full
RDRF
Possible
Not possible
TXI3
Transmit Data Empty
TDRE
Possible
Not possible
TEI3
Transmission End
TEND
Not possible
Not possible
ERI4
Receive Error
ORER, FER, PER
Not possible
Not possible
RXI4
Receive Data Full
RDRF
Possible
Not possible
TXI4
Transmit Data Empty
TDRE
Possible
Not possible
TEI4
Transmission End
TEND
Not possible
Not possible
1
2
3
4
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Section 15 Serial Communication Interface (SCI, IrDA)
15.9.2
Interrupts in Smart Card Interface Mode
Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt
(TEI) request cannot be used in this mode.
Table 15.14 Interrupt Sources
Channel
0
1
2
3
4
Name
Interrupt Source
Interrupt Flag
DTC
Activation
DMAC
Activation
Priority
High
ERI0
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI0
Receive Data Full
RDRF
Possible
Possible
TXI0
Transmit Data Empty
TEND
Possible
Possible
ERI1
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI1
Receive Data Full
RDRF
Possible
Possible
TXI1
Transmit Data Empty
TEND
Possible
Possible
ERI2
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI2
Receive Data Full
RDRF
Possible
Not possible
TXI2
Transmit Data Empty
TEND
Possible
Not possible
ERI3
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI3
Receive Data Full
RDRF
Possible
Not possible
TXI3
Transmit Data Empty
TEND
Possible
Not possible
ERI4
Receive Error, detection
ORER, PER, ERS
Not possible
Not possible
RXI4
Receive Data Full
RDRF
Possible
Not possible
TXI4
Transmit Data Empty
TEND
Possible
Not possible
Low
In Smart Card interface mode, as in normal serial communication interface mode, transfer can be
carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the
same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is
designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be
activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and
TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC.
In the event of an error, the SCI retransmits the same data automatically. During this period, the
TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and
DTC or DMAC will automatically transmit the specified number of bytes in the event of an error,
including retransmission. However, the ERS flag is not cleared automatically when an error
occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in
the event of an error, and the ERS flag will be cleared.
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Section 15 Serial Communication Interface (SCI, IrDA)
When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or
DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,
refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).
In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or
DMAC will be activated by the RXI request, and transfer of the receive data will be carried out.
The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or
DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or
DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the
error flag should be cleared.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.10
H8S/2456, H8S/2456R, H8S/2454 Group
Usage Notes
15.10.1 Module Stop Function Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing the module stop state. For
details, refer to section 24, Power-Down Modes.
15.10.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a
break, even if the FER flag is cleared to 0, it will be set to 1 again.
15.10.3 Mark State and Break Sending
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break
during serial data transmission. To maintain the communication line at mark state until TE is set to
1, set both DDR and DR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an I/O
port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR
to 1 and clear DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.10.5 Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
15.10.6 Restrictions on Use of DMAC or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Incorrect
operation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.
(Figure 15.35)
• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
SCI receive-data-full interrupt (RXI).
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4 clocks.
Figure 15.35 Example of Synchronous Transmission Using DTC
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Section 15 Serial Communication Interface (SCI, IrDA)
H8S/2456, H8S/2456R, H8S/2454 Group
15.10.7 Operation in Case of Mode Transition
(1)
Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before setting the module stop
state or making a transition to software standby mode. TSR, TDR, and SSR are reset. The output
pin states in the module stop state or software standby mode depend on the port settings, and
become high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined.
When transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence: SSR
read → TDR write → TDRE clearance. To transmit with a different transmit mode after clearing
the relevant mode, the procedure must be started again from initialization.
Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states
during mode transition are shown in figures 15.37 and 15.38.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition
from transmission by DTC transfer to module stop state setting or software standby mode
transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE
and TIE to 1 will set the TXI flag and start DTC transmission.
(2)
Reception
Receive operation should be stopped (by clearing RE to 0) before setting the module stop state or
making a transition to software standby mode. RSR, RDR, and SSR are reset. If a transition is
made during reception, the data being received will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared, set
RE to 1 before starting reception. To receive with a different receive mode, the procedure must be
started again from initialization.
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Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.39 shows a sample flowchart for mode transition during reception.
All data
transmitted?
No
[1]
Yes
Read TEND flag in SSR
TEND = 1
No
Yes
TE = 0
[2]
Transition to software
standby mode
[3]
[1] Data being transmitted is interrupted.
After exiting software standby mode,
normal CPU transmission is possible
by setting TE to 1, reading SSR,
writing TDR, and clearing TDRE to 0,
but note that if the DTC has been
activated, the remaining data in
DTCRAM will be transmitted when
TE and TIE are set to 1.
[2] If TIE and TEIE are set to 1, clear
them to 0 in the same way.
[3] Includes setting of module stop state.
Exit from software
standby mode
Change
operating mode?
No
Yes
Initialization
TE = 1
Figure 15.36 Sample Flowchart for Mode Transition during Transmission
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Section 15 Serial Communication Interface (SCI, IrDA)
End of
transmission
Start of transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin
Port input/output
High output
Port
Start
Stop
Port input/output
SCI TxD output
High output
SCI TxD
output
Port
Figure 15.37 Port Pin States during Mode Transition
(Internal Clock, Asynchronous Transmission)
Start of transmission
End of
transmission
Exit from
software
standby
Transition
to software
standby
TE bit
Port input/output
SCK output pin
TxD output pin Port input/output
Last TxD bit held
Marking output
Port
SCI TxD output
Port input/output
Port
High output*
SCI TxD
output
Note: * Initialized by software standby.
Figure 15.38 Port Pin States during Mode Transition
(Internal Clock, Synchronous Transmission)
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Section 15 Serial Communication Interface (SCI, IrDA)
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Receive data being received
becomes invalid.
[2]
[2] Includes setting of module
stop state.
Yes
Read receive data in RDR
RE = 0
Transition to software
standby mode
Exit from software
standby mode
Change
operating mode?
No
Yes
Initialization
RE = 1
Figure 15.39 Sample Flowchart for Mode Transition during Reception
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Section 15 Serial Communication Interface (SCI, IrDA)
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Section 16 USB Function Module (USB)
Section 16 USB Function Module (USB)
This LSI incorporates a USB function module (USB).
16.1
Features
• The protocol block conforming to USB2.0 and transceiver process USB protocol
automatically.
Automatic processing of USB standard commands for endpoint 0 (some commands and
class/vendor commands require decoding and processing by firmware)
• Transfer speed: Supports full-speed (12 Mbps)
• Endpoint configuration:
Endpoint
Name
Maximum
FIFO Buffer
Abbreviation Transfer Type Packet Size Capacity (Byte)
Endpoint 0
EP0s
Setup
8
8
⎯
EP0i
Control-in
16
16
⎯
EP0o
Control-out
16
16
⎯
Endpoint 1
EP1
Bulk-out
64
128
Possible
Endpoint 2
EP2
Bulk-in
64
128
Possible
Endpoint 3
EP3
Interrupt-in
16
16
⎯
Configuration1-Interface0 to 3-AlternateSetting0-
DMA Transfer
EndPoint1 to 3
• Interrupt requests: Generates various interrupt signals necessary for USB
transmission/reception
• Power mode: Self power mode or bus power mode can be selected by the power mode bit
(PWMD) in the control register (CTLR).
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Section 16 USB Function Module (USB)
Figure 16.1 shows the block diagram of the USB.
Peripheral bus
USB function module
Status/control
registers
Interrupt requests
Protocol
processing
block
D+
Transceiver
D-
FIFO
Clock for USB
(48 MHz)
Figure 16.1 Block Diagram of USB
16.2
Input/Output Pins
Table 16.1 shows the USB pin configuration.
Table 16.1 Pin Configuration
Pin Name
I/O
Function
VBUS
Input
USB cable connection monitor pin
USD+
I/O
USB data I/O pin
USD-
I/O
USB data I/O pin
DrVcc
Input
Power supply pin for USB on-chip transceiver
DrVss
Input
Ground pin for USB on-chip transceiver
PUPD+
Output
USD+ signal pull-up control pin
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16.3
Section 16 USB Function Module (USB)
Register Descriptions
The USB has following registers. For the information on the addresses of these registers and the
state of the register in each processing condition, see section 25, List of Registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interrupt flag register 0 (IFR0)
Interrupt flag register 1 (IFR1)
Interrupt flag register 2 (IFR2)
Interrupt enable register 0 (IER0)
Interrupt enable register 1 (IER1)
Interrupt enable register 2 (IER2)
Interrupt select register 0 (ISR0)
Interrupt select register 1 (ISR1)
Interrupt select register 2 (ISR2)
EP0i data register (EPDR0i)
EP0o data register (EPDR0o)
EP0s data register (EPDR0s)
EP1 data register (EPDR1)
EP2 data register (EPDR2)
EP3 data register (EPDR3)
EP0o receive data size register (EPSZ0o)
EP1 receive data size register (EPSZ1)
Data status register 0 (DASTS0)
Data status register 1 (DASTS1)
Trigger register 0 (TRG0)
Trigger register 1 (TRG1)
FIFO clear register 0 (FCLR0)
FIFO clear register 1 (FCLR1)
Endpoint stall register 0 (EPSTL0)
Endpoint stall register 1 (EPSTL1)
Stall status register 1 (STLSR1)
DMA transfer setting register (DMAR)
Configuration value register (CVR)
Control register (CTLR)
Endpoint information register (EPIR)
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Section 16 USB Function Module (USB)
• Transceiver test register 0 (TRNTREG0)
• Transceiver test register 1 (TRNTREG1)
16.3.1
Interrupt Flag Register 0 (IFR0)
IFR0, together with interrupt flag registers 1 and 2 (IFR1 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since SURSS and VBUSMN are status bits, these bits cannot be cleared.
Bit
Bit Name
Initial
Value
R/W
Description
7
BRST
0
R/W
Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
6
CFDN
0
R/W
End Point Information Load End
This bit is set to 1 when writing data in the endpoint
information register to the EPIR register ends (load end).
This module starts the USB operation after the endpoint
information is completely set.
5
SURSS
0
R
Suspend/Resume Status
This is a status bit that describes bus state.
0: Normal state
1: Suspended state
This is a status bit and cannot be cleared. It generates
no interrupt request.
4
SURSF
0
R/W
Suspend/Resume Detection
This bit is set to 1 when the state changed from normal
to suspended state or vice versa. The corresponding
interrupt output is RESUME, USBINTN2, and
USBINTN3.
3
SETC
0
R/W
Set_Configuration Command Detection
When the Set_Configuration command is detected, this
bit is set to 1.
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Section 16 USB Function Module (USB)
Bit
Bit Name
Initial
Value
R/W
Description
2
SETI
0
R/W
Set_Interface Command Detection
When the Set_Interface command is detected, this bit is
set to 1.
1
VBUSMN
0
R
VBUS Pin State Monitor
This is a status bit that monitors the state of the VBUS
pin.
0: VBUS pin = 0
1: VUBS pin = 1
This is a status bit and cannot be cleared. It generates
no interrupt request.
This bit is always 0 when the PULLUPE bit in CTLR is 0.
0
VBUSF
0
R/W
USB BUS Connection/Disconnection Detection
When the function is connected to the USB bus or
disconnected from it, this bit is set to 1. The VBUS pin of
this module is used for detecting connection or
disconnection.
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Section 16 USB Function Module (USB)
16.3.2
Interrupt Flag Register 1 (IFR1)
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
SOF
0
R/W
SOF Packet Detection
This bit is set to 1 when the Start Of Frame (SOF)
packet is detected.
3
SETUP TS
0
R/W
Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives
successfully a setup command requiring decoding on
the application side, and returns an ACK handshake to
the host.
2
EP0o TS
0
R/W
EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host successfully, stores the data in the FIFO
buffer, and returns an ACK handshake to the host.
1
EP0i TR
0
R/W
EP0i Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
0
EP0i TS
0
R/W
EP0i Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.
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16.3.3
Section 16 USB Function Module (USB)
Interrupt Flag Register 2 (IFR2)
IFR2, together with interrupt flag registers 0 and 1, (IFR0 and IFR1), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since EP2 EMPTY, EP2 ALLEMP, and EP1 FULL are status bits, these bits cannot be
cleared.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
5
EP3 TR
0
R/W
EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
4
EP3 TS
0
R/W
EP3 Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 3 and an ACK handshake is returned.
3
EP2 TR
0
R/W
EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
2
EP2 EMPTY 1
R
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit and cannot be cleared.
1
EP2
ALLEMP
1
R
EP2 FIFO All Empty
This bit is set when both of the dual endpoint 2 transmit
FIFO buffers are empty.
This is a status bit and cannot be cleared.
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Section 16 USB Function Module (USB)
Bit
Bit Name
Initial
Value
R/W
Description
0
EP1 FULL
0
R
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1
as long as there is valid data in the FIFO buffer.
This is a status bit and cannot be cleared.
16.3.4
Interrupt Enable Register 0 (IER0)
IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 0
(ISR0).
Bit
Bit Name
Initial
Value
R/W
Description
7
BRSTE
0
R/W
Bus Reset
6
CFDNE
0
R/W
End Point Information Load End
5
SSRSME
0
R/W
Resume Detection for Software Standby Cancel
For details of the operation, see section 16.5.4,
Suspend and Resume Operations.
4
SURSFE
0
R/W
Suspend/Resume Detection
For details of the operation, see section 16.5.4,
Suspend and Resume Operations.
3
SETCE
0
R/W
Set_Configuration Command Detection
2
SETIE
0
R/W
Set_Interface Command Detection
1
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
0
VBUSFE
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0
R/W
USB Bus Connection/Disconnection
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16.3.5
Section 16 USB Function Module (USB)
Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 1
(ISR1).
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
SOFE
0
R/W
SOF Packet Detection
3
SETUP TSE
0
R/W
Setup Command Receive Complete
2
EP0o TSE
0
R/W
EP0o Receive Complete
1
EP0i TRE
0
R/W
EP0i Transfer Request
0
EP0i TSE
0
R/W
EP0i Transmission Complete
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Section 16 USB Function Module (USB)
16.3.6
Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 2
(ISR2).
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
5
EP3 TRE
0
R/W
EP3 Transfer Request
4
EP3 TSE
0
R/W
EP3 Transmission Complete
3
EP2 TRE
0
R/W
EP2 Transfer Request
2
EP2
EMPTYE
0
R/W
EP2 FIFO Empty
1
EP2
ALLEMPE
0
R/W
EP2 FIFO All Empty
0
EP1 FULLE
0
R/W
EP1 FIFO Full
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16.3.7
Section 16 USB Function Module (USB)
Interrupt Select Register 0 (ISR0)
ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0
(IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the
interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the
INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
Bit
Bit Name
Initial
Value
R/W
Description
7
BRSTS
0
R/W
Bus Reset
6
CFDNS
0
R/W
End Point Information Load End
5
⎯
0
⎯
Reserved
This bit is always read as 1. The write value should
always be 1.
4
SURSFS
0
R/W
Suspend/Resume Detection
3
SETCS
0
R/W
Set_Configuration Command Detection
2
SETIS
0
R/W
Set_Interface Command Detection
1
⎯
0
⎯
Reserved
This bit is always read as 1. The write value should
always be 1.
0
VBUSFS
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1
R/W
USB Bus Connection/Disconnection
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Section 16 USB Function Module (USB)
16.3.8
Interrupt Select Register 1 (ISR1)
ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1
(IFR1). If the USB issues an interrupt request to the INTC when a bit in ISR1 is cleared to 0, the
interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the
INTC when a bit in ISR1 is set to 1, the corresponding interrupt will be USBINTN3.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
SOFS
0
R/W
SOF Packet Detection
3
SETUP TSS 0
R/W
Setup Command Receive Complete
2
EP0o TSS
0
R/W
EP0o Receive Complete
1
EP0i TRS
0
R/W
EP0i Transfer Request
0
EP0i TSS
0
R/W
EP0i Transmission Complete
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16.3.9
Section 16 USB Function Module (USB)
Interrupt Select Register 2 (ISR2)
ISR2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2
(IFR2). If the USB issues an interrupt request to the INTC when a bit in ISR2 is cleared to 0, the
interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the
INTC when a bit in ISR2 is set to 1, the corresponding interrupt will be USBINTN3.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
5
EP3 TRS
0
R/W
EP3 Transfer Request
4
EP3 TSS
0
R/W
EP3 Transmission Complete
3
EP2 TRS
0
R/W
EP2 Transfer Request
2
EP2
EMPTYS
0
R/W
EP2 FIFO Empty
1
EP2
ALLEMPS
0
R/W
EP2 FIFO All Empty
0
EP1 FULLS 0
R/W
EP1 FIFO Full
16.3.10 EP0i Data Register (EPDR0i)
EPDR0i is a 16-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit
data for control-in. Transmit data is fixed by writing one packet of data and setting EP0i PKTE in
trigger register 0. When an ACK handshake is returned from the host after the data has been
transmitted, EP0i TS in interrupt flag register 1 is set. This FIFO buffer can be initialized by
means of EP0i CLR in FCLR register 0.
Bit
Bit Name
Initial
Value
7 to 0
D7 to D0
Undefined W
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R/W
Description
Data register for control-in transfer
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Section 16 USB Function Module (USB)
16.3.11 EP0o Data Register (EPDR0o)
EPDR0o is a 16-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data
other than setup commands. When data is received successfully, EP0o TS in interrupt flag register
1 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After
the data has been read, setting EP0o RDFN in trigger register 0 enables the next packet to be
received. This FIFO buffer can be initialized by means of EP0o CLR in FCLR register 0.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
All 0
R
Data register for control-out transfer
16.3.12 EP0s Data Register (EPDR0s)
EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the
setup command to be processed by the application is received. When command data is received
successfully, the SETUPTS bit in interrupt flag register 1 is set.
As a latest setup command must be received in high priority, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority, the read by the application is forcibly stopped, and
the read data is invalid.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
All 0
R
Data register for storing the setup command at the
control-out transfer
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Section 16 USB Function Module (USB)
16.3.13 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When one packet of data is received
successfully, EP1 FULL in interrupt flag register 2 is set, and the number of receive bytes is
indicated in the EP1 receive data size register. After the data has been read, the buffer that was
read is enabled to receive data again by writing 1 to the EP1 RDFN bit in trigger register 1. The
receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized
by means of EP1 CLR in FCLR register 1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
All 0
R
Data register for endpoint 1 transfer
16.3.14 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2 PKTE in trigger register 1 is set, one packet of transmit data is fixed, and the dualFIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by DMA.
This FIFO buffer can be initialized by means of EP2 CLR in FCLR register 1.
Bit
Bit Name
Initial
Value
7 to 0
D7 to D0
Undefined W
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R/W
Description
Data register for endpoint 2 transfer
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Section 16 USB Function Module (USB)
16.3.15 EP3 Data Register (EPDR3)
EPDR3 is a 16-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data
for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and
setting EP3 PKTE in trigger register 1. This FIFO buffer can be initialized by means of EP3 CLR
in FCLR register 1.
Bit
Bit Name
Initial
Value
7 to 0
D7 to D0
Undefined W
R/W
Description
Data register for endpoint 3 transfer
16.3.16 EP0o Receive Data Size Register (EPSZ0o)
EPSZ0o indicates the number of bytes received at endpoint 0 from the host.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
⎯
All 0
⎯
Reserved
These bits are always read as 0.
4 to 0
D4 to D0
All 0
R
Number of receive data for endpoint 0
16.3.17 EP1 Receive Data Size Register (EPSZ1)
EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received
from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received
data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
This bit is always read as 0.
6 to 0
D6 to D0
Page 964 of 1408
All 0
R
Number of received bytes for endpoint 1
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Section 16 USB Function Module (USB)
16.3.18 Data Status Register 0 (DASTS0)
DASTS0 indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is
written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all
data has been transmitted to the host.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
⎯
0
⎯
3
⎯
0
⎯
2
⎯
0
⎯
1
⎯
0
⎯
0
EP0i DE
0
R
EP0i Data Present
This bit is set when the endpoint 0i FIFO buffer
contains valid data.
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Section 16 USB Function Module (USB)
16.3.19 Data Status Register 1 (DASTS1)
DASTS1 indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is
written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all
data has been transmitted to the host.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
⎯
0
⎯
3
⎯
0
⎯
2
EP3 DE
0
R
EP3 Data Present
This bit is set when the endpoint 3 FIFO buffer
contains valid data.
1
EP2 DE
0
R
EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data.
0
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
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Section 16 USB Function Module (USB)
16.3.20 Trigger Register 0 (TRG0)
TRG0 generates one-shot triggers to control the transfer sequence for endpoint 0.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
⎯
0
⎯
3
⎯
0
⎯
2
EP0s RDFN 0
W
EP0s Read Complete
Write 1 to this bit after data for the EP0s command
FIFO has been read. Writing 1 to this bit enables
transfer of data in the following data stage. A NAK
handshake is returned in response to transfer
requests from the host in the data stage until 1 is
written to this bit.
1
EP0o RDFN 0
W
EP0o Read Complete
Writing 1 to this bit after one packet of data has been
read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet to
be received.
0
EP0i PKTE
0
W
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
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Section 16 USB Function Module (USB)
16.3.21 Trigger Register 1 (TRG1)
TRG1 generates one-shot triggers to control the transfer sequence for each endpoint.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
⎯
0
⎯
3
⎯
0
⎯
2
EP3 PKTE
0
W
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
1
EP2 PKTE
0
W
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
0
EP1 RDFN
0
W
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-buffer configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
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Section 16 USB Function Module (USB)
16.3.22 FIFO Clear Register 0 (FCLR0)
FCLR0 is a register to initialize the FIFO buffers for endpoint 0. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
The write value should always be 0.
5
⎯
0
⎯
4
⎯
0
⎯
3
⎯
0
⎯
2
⎯
0
⎯
1
EP0o CLR
0
W
EP0o Clear
Writing 1 to this bit initializes the endpoint 0 receive
FIFO buffer.
0
EP0i CLR
0
W
EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.
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Section 16 USB Function Module (USB)
16.3.23 FIFO Clear Register 1 (FCLR1)
FCLR1 is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
The write value should always be 0.
5
⎯
0
⎯
4
⎯
0
⎯
3
⎯
0
⎯
2
EP3 CLR
0
W
EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
1
EP2 CLR
0
W
EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
0
EP1 CLR
0
W
EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
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Section 16 USB Function Module (USB)
16.3.24 Endpoint Stall Register 0 (EPSTL0)
Bit 0 in EPSTL0 is used to forcibly stall endpoint 0 on the application side. While the bit is set to
1, the corresponding endpoint returns a stall handshake to the host. Bit 4 is used to clear the stall
setting in bit 0. Writing 1 to the EP0 stall setting bit and stall clear bit at the same time is
prohibited.
The stall bit for endpoint 0 is cleared automatically on reception of 8-byte setup command data for
which decoding is performed by firmware the EP0 STLS bit is cleared. When the SETUPTS flag
in the IFR1 is set to 1, writing 1 to the EP0 STLS bit is ignored. For detailed operation, see section
16.7, Stall Operations.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
EP0 STLC
0
W
EP0 Stall Clear
Writing 1 to this bit clears the EP0 STLS bit to 0.
Writing 0 is ignored.
3
⎯
0
⎯
Reserved
2
⎯
0
⎯
1
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
0
EP0 STLS
0
R/W
EP0 Stall Setting
Writing 1 to this bit specifies a stall for EP0. Writing 0
is ignored.
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Section 16 USB Function Module (USB)
16.3.25 Endpoint Stall Register 1 (EPSTL1)
Bits 2 to 0 in EPSTL1 are used to forcibly stall the corresponding endpoints on the application
side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. Bits 6
to 4 are used to clear the stall settings for the endpoints (bits 2 to 0). Writing 1 to the stall setting
bit and stall clear bit for an endpoint at the same time is prohibited.
For detailed operation, see section 16.7, Stall Operations.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
6
EP3 STLC
0
W
EP3 Stall Clear
Writing 1 to this bit clears the EP3 STLS bit to 0.
Writing 0 is ignored.
5
EP2 STLC
0
W
EP2 Stall Clear
Writing 1 to this bit clears the EP2 STLS bit to 0.
Writing 0 is ignored.
4
EP1 STLC
0
W
EP1 Stall Clear
Writing 1 to this bit clears the EP1 STLS bit to 0.
Writing 0 is ignored.
3
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
2
EP3 STLS
0
R/W
EP3 Stall Setting
Writing 1 to this bit specifies a stall for EP3. Writing 0
is ignored.
1
EP2 STLS
0
R/W
EP2 Stall Setting
Writing 1 to this bit specifies a stall for EP2. Writing 0
is ignored.
0
EP1 STLS
0
R/W
EP1 Stall Setting
Writing 1 to this bit specifies a stall for EP1. Writing 0
is ignored.
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Section 16 USB Function Module (USB)
16.3.26 Stall Status Register 1 (STLSR1)
Bits 2 to 0 in STLSR1 are status bits that indicate the internal stall state of each endpoint (internal
status bits shown in figures 16.19 and 16.20). When a bit is 1, the corresponding endpoint is in
stall state. When a bit is 0, the corresponding endpoint is in normal operation state. Since these
bits are status bits, they cannot be cleared.
Bits 6 to 4 in STLSR1 are used to enable automatic stall clear for each endpoint.
Bit
Bit Name
7
⎯
Initial
Value
R/W
Description
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
6
EP3 ASCE
0
R/W
EP3 Automatic Stall Clear Enable
Setting the EP3 ASCE bit to 1 automatically clears the
EP3 stall setting bit (the EP3 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP3 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP3 ASCE bit should be set to 1
before the EP3 STLS bit in EPSTL1 is set to 1.
5
EP2 ASCE
0
R/W
EP2 Automatic Stall Clear Enable
Setting the EP2 ASCE bit to 1 automatically clears the
EP2 stall setting bit (the EP2 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP2 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP2 ASCE bit should be set to 1
before the EP2 STLS bit in EPSTL1 is set to 1.
4
EP1 ASCE
0
R/W
EP1 Automatic Stall Clear Enable
Setting the EP1 ASCE bit to 1 automatically clears the
EP1 stall setting bit (the EP1 STLS bit in EPSTL1)
after the stall handshake is returned to the host.
When the EP1 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP1 ASCE bit should be set to 1
before the EP1 STLS bit in EPSTL1 is set to 1.
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Section 16 USB Function Module (USB)
Bit
Bit Name
Initial
Value
R/W
Description
3
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
2
EP3 STLST 0
R
EP3 internal stall state
1
EP2 STLST 0
R
EP2 internal stall state
0
EP1 STLST 0
R
EP1 internal stall state
16.3.27 DMA Transfer Setting Register (DMAR)
DMA transfer can be carried out between the data registers for endpoints 1 and 2 and memory by
means of the on-chip direct memory access controller (DMAC). Dual address transfer is
performed in bytes. To start DMA transfer, DMAC settings must be made in addition to the
settings in this register.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
6
⎯
0
⎯
5
⎯
0
⎯
These bits are always read as 0. The write value
should always be 0.
4
⎯
0
R/W
Reserved
The write value should always be 0.
3
⎯
0
R/W
2
⎯
0
⎯
Reserved
The write value should always be 0.
Reserved
This bit is always read as 0. The write value should
always be 0.
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Section 16 USB Function Module (USB)
Bit
Bit Name
Initial
Value
R/W
Description
1
EP2 DMAE
0
R/W
EP2 DMA Transfer Enable
When this bit is set, DMA transfer is enabled from
memory to the endpoint 2 transmit FIFO buffer. If
there is at least one byte of open space in the FIFO
buffer, a DMA transfer request signal (USB INTN1) is
asserted. In DMA transfer, when 64 bytes are written
to the FIFO buffer the EP2 packet enable bit is set
automatically, allowing 64 bytes of data to be
transferred, and if there is still space in the other side
of the two FIFOs, the DMA transfer request signal
(USB INTN1) is asserted again. However, if the size
of the data packet to be transmitted is less than 64
bytes, the EP2 packet enable bit is not set
automatically, and so should be set by the CPU with a
DMA transfer end interrupt.
As EP2-related interrupt requests to the CPU are not
automatically masked, interrupt requests should be
masked as necessary in the interrupt enable register.
•
Operating procedure
1. Write of 1 to the EP2 DMAE bit in DMAR
2. Set the DMAC to activate through DREQ1
(USB INTN1)
3. Transfer count setting in the DMAC
4. DMAC activation
5. DMA transfer
6. DMA transfer end interrupt generated
See section 16.8.4, DMA Transfer for Endpoints 2.
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Section 16 USB Function Module (USB)
Bit
Bit Name
Initial
Value
R/W
Description
0
EP1 DMAE
0
R/W
EP1 DMA Transfer Enable
When this bit is set, a DMA transfer request (USB
INTN0) is asserted and DMA transfer is enabled from
the endpoint 1 receive FIFO buffer to memory. If there is
at least one byte of receive data in the FIFO buffer, the
DMA transfer request (USB INTN0) is asserted. In DMA
transfer, when all the received data is read, EP1 is
automatically read and the completion trigger operates.
EP1-related interrupt requests to the CPU are not
automatically masked.
•
Operating procedure:
1. Write of 1 to the EP1 DMAE bit in DMA
2. Set the DMAC to activate through DREQ0
(USB INTN0)
3. Transfer count setting in the DMAC
4. DMAC activation
5. DMA transfer
6. DMA transfer end interrupt generated
See section 16.8.3, DMA Transfer for Endpoints 1and 4.
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Section 16 USB Function Module (USB)
16.3.28 Configuration Value Register (CVR)
This register stores the Configuration, Interface, or Alternate set value when the Set Configuration
or Set Interface command from the host is correctly received.
Bit
Bit Name
Initial
Value
R/W
Description
7
CNFV1
All 0
R
6
CNFV0
These bits store Configuration Setting value when
they receive Set Configuration command. CNFV is
updated when the SETC bit in IFR0 is set to 1.
5
INTV1
All 0
R
4
INTV0
These bits store Interface Setting value when they
receive Set Interface command. INTV is updated
when the SETI bit in IFR0 is set to 1.
3
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
2
ALTV2
0
R
1
ALTV1
0
R
0
ALTV0
0
R
These bits store Alternate Setting value when they
receive Set Interface command. ALTV2 to ALTV0 are
updated when the SETI bit in IFR0 is set to 1.
16.3.29 Control Register (CTLR)
This register sets functions for bits PRTRST, ASCE, PWMD, RSME, PWUPS, and PULLUP_E.
Bit
Bit Name
7
PULLUPE
Initial
Value
R/W
Description
0
R/W
Pull-up Enable
This bit controls whether to pull up the D+ pin. P20 is
used as the pull-up control pin.
0: D+ is not pulled up.
1: D+ is pulled up.
6, 5
⎯
0
R/W
Reserved
The write value should always be 0.
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Section 16 USB Function Module (USB)
Bit
Bit Name
Initial
Value
R/W
Description
4
RWUPS
0
R
Remote Wakeup Status
This status bit indicates remote wakeup command
from USB host is enabled or disabled.
This bit is set to 0 when remote wakeup command
from UBM host is disabled by
Device_Remote_Wakeup due to Set Feature or Clear
Feature request. This bit is set to 1 when remote
wakeup command is enabled.
3
RSME
0
R/W
Resume Enable
This bit releases the suspend state (or executes
remote wakeup). When RSME is set to 1, resume
request starts. If RSME is once set to 1, clear this bit
to 0 again afterwards. In this case, the value 1 set to
RSME must be kept for at least one clock period of
12-MHz clock.
2
PWMD
0
R/W
Bus Power Mode
This bit specifies the USB power mode. When PWMD
is set to 0, the self-power mode is selected for this
module. When set to 1, the bus-power mode is
selected.
1
EP0 ASCE
0
R/W
EP0 Automatic Stall Clear Enable
Setting the EP0 ASCE bit to 1 automatically clears the
EP0 stall setting bit (the EP0 STLS bit in EPSTL0)
after the stall handshake is returned to the host.
When the EP0 ASCE bit is set to 0, the stall setting bit
is not automatically cleared and must be cleared by
the users. To enable the automatic stall clear function,
make sure that the EP0 ASCE bit should be set to 1
before the EP0 STLS bit in EPSTL0 is set to 1.
0
PRTRST
1
R/W
Protocol Processing Block Reset
0: The protocol processing block is placed in
operation state.
1: The protocol processing block is placed in reset
state.
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Section 16 USB Function Module (USB)
16.3.30 Endpoint Information Register (EPIR)
This register sets the information for each endpoint. Each endpoint needs five bytes to store the
information. Writing data should be done in sequence starting at logical endpoint 0. Make sure to
write data of 20 bytes (five bytes multiplied by four endpoints) to this register. The information
should be written to this register only once at a power-on reset and no data should be written after
that. Description of writing data for one endpoint is shown below.
Although this register consists of one register to which data is written sequentially for one address,
the write data for the endpoint 0 is described as EPIR00 to EPIR04 (EPIR endpoint number in
write order) to make the explanation understood easier. Write should start at EPIR00.
The endpoint numbers should not be overlapped except the one not in use.
• EPIR00
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
D7 to D4
Undefined
W
Endpoint Number
[Enable setting range]
0 to 3
3, 2
D3, D2
Undefined
W
Endpoint Configuration Number
[Enable setting range]
0 or 1
1, 0
D1, D0
Undefined
W
Endpoint Interface Number
[Enable setting range]
0 to 3
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Section 16 USB Function Module (USB)
• EPIR01
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
D7, D6
Undefined
W
Endpoint Alternate Number
[Possible setting range]
0
5, 4
D5, D4
Undefined
W
Endpoint Transmission
[Possible setting range]
0: Control
1: Setting prohibited
2: Bulk
3: Interrupt
3
D3
Undefined
W
Endpoint Transmission Direction
[Possible setting range]
0: Out
1: In
2 to 0
D2 to D0
Undefined
W
Reserved
[Possible setting range]
Fixed to 0.
• EPIR02
Bit
Bit Name
Initial
Value
R/W
7 to 1
D7 to D1
Undefined
W
Description
Endpoint Maximum Packet Size
[Possible setting range]
0 to 64
0
D0
Undefined
W
Reserved
[Possible setting range]
Fixed to 0.
• EPIR03
Bit
Bit Name
Initial
Value
R/W
7 to 0
D7 to D0
Undefined
W
Description
Reserved
[Possible setting range]
Fixed to 0.
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Section 16 USB Function Module (USB)
• EPIR04
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
Undefined
W
Endpoint FIFO Number
[Possible setting range]
0 to 3
The endpoint number is the endpoint number the USB host uses. The endpoint FIFO number
corresponds to the endpoint number described in this manual. Thus data transfer between the USB
host and the endpoint FIFO can be enabled by putting the endpoint number and the endpoint FIFO
number in one-to-one correspondence. Note that the setting value is subject to a limitation
described below.
Since each endpoint FIFO number is optimized by the exclusive software that corresponds to the
transfer system, direction, and the maximum packet size, make sure to set the endpoint FIFO
number to the data described in table 16.2.
1. Endpoint number 0 and endpoint FIFO number 0 must have one-on-one relationship.
2. The maximum packet size for endpoint FIFO number 0 is limited to 16 bytes.
3. For endpoint FIFO number 0, only the maximum packet size can be specified and the data for
the rest should be all 0.
4. The maximum packet size for endpoint FIFO numbers 1 and 2 is limited to 64 bytes.
5. Only the bulk transfer method and out transfer direction can be specified for endpoint FIFO
numbers 1.
6. Only the bulk transfer method and in transfer direction can be specified for endpoint FIFO
numbers 2.
7. The maximum packet size for endpoint FIFO numbers 3 is limited to 16 bytes.
8. Only the interrupt transfer method and in transfer direction can be specified for endpoint FIFO
numbers 3.
9. The maximum number of endpoint information settings is four.
10. Four endpoint information settings should be made.
11. Write 0 to the endpoints not in use.
Table 16.2 shows the limitations for the maximum packet size, the transfer method, and the
transfer direction.
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Section 16 USB Function Module (USB)
Table 16.2 Limitations for Setting Values
Endpoint FIFO Number
Maximum Packet Size
Transfer Method
Transfer Direction
0
16 bytes
Control
In/Out
1
64 bytes
Bulk
Out
2
64 bytes
Bulk
In
3
16 bytes
Interrupt
In
Table 16.3 shows a specific example of setting.
Table 16.3 Example of Setting
Endpoint
Number Conf.
Int.
Alt.
Transfer
Method
Transfer
Direction
Maximum
Packet Size
Endpoint
FIFO Number
0
⎯
⎯
⎯
Control
In/Out
16 bytes
0
1
1
0
0
Bulk
Out
64 bytes
1
2
1
0
0
Bulk
In
64 bytes
2
3
1
0
0
Interrupt
In
16 bytes
3
N
EPIR[N]0
EPIR[N]1
EPIR[N]2
EPIR[N]3
EPIR[N]4
0
00
00
20
00
00
1
14
20
80
00
01
2
24
28
80
00
02
3
34
38
20
00
03
Page 982 of 1408
Configuration
Interface
Alternate
Setting
Endpoint
Number
Endpoint
FIFO Number
Attribute
⎯
⎯
⎯
0
0
Control
1
0
0
1
1
Bulk-Out
2
2
Bulk-In
3
3
Interrupt-In
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16.3.31
Section 16 USB Function Module (USB)
Transceiver Test Register 0 (TRNTREG0)
TRNTREG0 controls the on-chip transceiver output signals. Setting the PTSTE bit to 1 specifies
the transceiver output signals (USD+ and USD-) arbitrarily. Table 16.4 shows the relationship
between TRNTREG0 setting and pin output.
Bit
Bit Name
Initial
Value
R/W
Description
7
PTSTE
0
R/W
Pin Test Enable
Enables the test control for the on-chip transceiver
output pins (USD+ and USD-).
6 to 4
⎯
⎯
All 0
Reserved
These bits are always read as 0. The write value
should always be 0.
3
SUSPEND
0
R/W
On-Chip Transceiver Output Signal Setting
2
txenl
0
R/W
1
txse0
0
R/W
SUSPEND: Sets the (SUSPEND) signal of the on-chip
transceiver.
0
txdata
0
R/W
txenl:
Sets the output enable (txenl) signal of the
on-chip transceiver.
txse0:
Sets the Signal-ended 0 (txse0) signal of
the on-chip transceiver.
txdata:
Sets the (txdata) signal of the on-chip
transceiver.
Table 16.4 Relationship between TRNTREG0 Setting and Pin Output
Register Setting
PTSTE
txenl
txse0
Pin Output
txdata
USD+
USD-
0
X
X
X
⎯
⎯
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
X
0
0
1
1
X
X
Hi-Z
Hi-Z
[Legend]
X:
Don't care.
⎯:
Cannot be controlled. Indicates state in normal operation according to the USB operation
and port settings.
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Section 16 USB Function Module (USB)
16.3.32 Transceiver Test Register 1 (TRNTREG1)
TRNTREG1 is a test register that can monitor the on-chip transceiver input signal.
Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the on-chip transceiver input
signal. Table 16.5 shows the relationship between pin input and TRNTREG1 monitoring value.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
⎯
All 0
⎯
Reserved
These bits are always read as 0. The write value should
always be 0.
2
xver_data
0
R
On-Chip Transceiver Input Signal Monitor
1
dpls
0
R
0
dmns
0
R
xver_data: Monitors the differential input level
(xver_data) signal of the on-chip
transceiver.
Page 984 of 1408
dpls:
Monitors the USD+ (dpls) signal of the onchip transceiver.
dmns:
Monitors the USD- (dmns) signal of the onchip transceiver.
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Section 16 USB Function Module (USB)
Table 16.5 Relationship between Pin Input and TRNTREG1 Monitoring Value
Register Setting
TRNTREG1
Monitoring Value
Pin Input
PTSTE
SUSPEND
USD+
USD-
xver_data dpls
dmns
Remarks
0
X
X
X
0
0
0
Cannot be monitored when
VBUS = 0 or PTSTE = 0
(initial value)
1
0
0
0
X
0
0
1
0
0
1
0
0
1
Can be monitored when
VBUS = 1 and PTSTE = 1
1
0
1
0
1
1
0
1
0
1
1
X
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
0
0
1
0
1
1
1
1
0
1
1
[Legend]
X:
Don't care.
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Section 16 USB Function Module (USB)
16.4
Interrupt Sources
This module has five interrupt signals. Table 16.6 shows the interrupt sources and their
corresponding interrupt request signals. The USBINTN interrupt signals are activated at low level.
The USBINTN interrupt requests can only be detected at low level (specified as level sensitive).
Table 16.6 Interrupt Sources
Register
Bit
Transfer
Mode
Interrupt
Source
IFR0
0
Status
VBUSF
USB bus connection/ USBINTN2 or USBINTN3 x
disconnection
detection
1
VBUSMN
VBUS connection
status
⎯
2
SETI
Set_Interface
command detection
USBINTN2 or USBINTN3 x
3
SETC
Set_Configuration
command detection
USBINTN2 or USBINTN3 x
4
SURSF
Suspend/resume
detection
USBINTN2, USBINTN3
or RESUME
x
5
SURSS
Suspend/resume
status
⎯
x
6
CFDN
Endpoint information
load end
USBINTN2 or USBINTN3 x
7
BRST
Bus reset
USBINTN2 or USBINTN3 x
EP0i_TS*
EP0i transmission
complete
USBINTN2 or USBINTN3 x
EP0i_TR*
EP0i transfer request USBINTN2 or USBINTN3 x
2
EP0o_TS*
EP0o receive
complete
USBINTN2 or USBINTN3 x
3
SETUP_TS*
Setup command
receive complete
USBINTN2 or USBINTN3 x
IFR1
0
1
Control
transfer
(EP0)
Description
Interrupt
Request Signal
DMAC
Activation
x
4
Status
SOF
SOF packet detection USBINTN2 or USBINTN3 x
5
⎯
Reserved
⎯
⎯
⎯
6
⎯
Reserved
⎯
⎯
⎯
7
⎯
Reserved
⎯
⎯
⎯
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Transfer
Mode
Interrupt
Source
Description
0
Bulk_out
transfer
(EP1)
EP1_FULL
EP1 FIFO full
USBINTN2 or USBINTN3 USBINTN0
(DREQ0)
1
Bulk_in
transfer
(EP2)
EP2_ALLEMP
EP2 FIFO all empty
USBINTN2 or USBINTN3 x
EP2_EMPTY
EP2 FIFO empty
USBINTN2 or USBINTN3 USBINTN1
(DREQ1)
3
EP2_TR
EP2 transfer request
USBINTN2 or USBINTN3 x
4
EP3 transmission
complete
USBINTN2 or USBINTN3 x
5
Interrupt_in EP3_TS
transfer
(EP3)
EP3_TR
EP3 transfer request
USBINTN2 or USBINTN3 x
6
⎯
Reserved
⎯
⎯
⎯
7
⎯
Reserved
⎯
⎯
⎯
Register
Bit
IFR2
2
Note:
*
Section 16 USB Function Module (USB)
Interrupt
Request Signal
DMAC
Activation
EP0 interrupts must be assigned to the same interrupt request signal.
• USB INTN0 signal
DMA transfer request signal only for EP1. See section 16.8, DMA Transfer.
• USB INTN1 signal
DMA transfer request signal only for EP2. See section 16.8, DMA Transfer.
• USB INTN2 signal
The USB INTN2 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 and 2 (ISR0 and ISR2) are cleared to 0. The USB INTN2 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
• USB INTN3 signal
The USBINTN3 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 2 (ISR0 and ISR2) are cleared to 0. The USB INTN3 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
• RESUME signal
The RESUME signal is a resume interrupt signal for canceling software standby mode. The
RESUME signal is driven low at the transition to the resume state for canceling software
standby mode.
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Section 16 USB Function Module (USB)
16.5
Operation
16.5.1
Initial Settings
USB function
H8S/2456, H8S/2456R, H8S/2454 Group
Application
Power-on reset state canceled
48-MHz USB clock
supply started
Set the multiplication ratio for the USB
PLL frequency.
(USSTC1 and USSTC0 in USPLLCR)
With a software timer, and so on, wait for
48-MHz USB clock oscillation to be
settled. (tUSOSC)
Cancel 48-MHz USB clock module
stop mode.
(Clear MSTP17 in EXMSTPCRL to 0.)
Cancel USB system clock module
stop mode.
(Clear MSTP18 in EXMSTPCRL to 0.)
Insert a 26-state dummy cycle.
Set the endpoint information to
endpoint information register (EPIR).
Cancel reset state in the protocol
processing block.
(Clear PRTRST in CTLR to 0.)
Wait for USB cable connection.
Figure 16.2 Initial Setting Operation
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16.5.2
Section 16 USB Function Module (USB)
Cable Connection
USB function
Application
Cable disconnected
VBUS pin = 0 V
Protocol processing block reset
USB module interrupt
setting
Initial
settings
As soon as preparations are
completed, enable D+ pull-up.
USB cable connection
No
General output port
D+ pull-up enabled?
Yes
Interrupt request
IFR0.VBUSF = 1
USB bus connection interrupt
Firmware preparations for
start of USB communication
Protocol processing block
reset release
Bus reset reception
IFR0.BRST = 1
Bus reset interrupt
Wait for setup command
reception complete interrupt
Clear VBUSF flag.
(IFR0.VBUSF)
Interrupt request
Clear bus reset flag.
(IFR0.BRST)
Clear FIFOs.
(EP0 to EP3)
Wait for setup command
reception complete interrupt
Figure 16.3 Cable Connection Operation
The above flowchart shows the operation in the case of in section 16.9, Example of USB External
Circuitry.
In applications that do not require USB cable connection to be detected, processing by the USB
bus connection interrupt is not necessary. Preparations should be made with the bus-reset
interrupt.
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Section 16 USB Function Module (USB)
16.5.3
H8S/2456, H8S/2456R, H8S/2454 Group
Cable Disconnection
USB function
Application
Cable connected
VBUS pin = 1
USB cable disconnection
VBUS pin = 0
Protocol processing block
reset
End
Figure 16.4 Cable Disconnection Operation
The above flowchart shows the operation in section 16.9, Example of USB External Circuitry.
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16.5.4
(1)
Section 16 USB Function Module (USB)
Suspend and Resume Operations
Suspend Operation
If the USB bus enters the suspend state from the non-suspend state, perform the operation as
shown in figure 16.5.
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Section 16 USB Function Module (USB)
Application
USB function
USB cable connected
Bus idle of 3 ms or
more occurs
Suspend/resume
interrupt occurs.
(IFR0/SURSF = 1)
USBINTN2 or
USBINTN3
Clear SURSF in IFR0 to 0.
Check if SURSS in IFR0
is set to 1.
Remote
wakeup enabled?
(CTLR/RWUPS = 1?)
N
Y
Check remote-wakeup
function enabled.
Check remote-wakeup
function disabled.
System needs to
enter power-down
mode?
N
Y
Need to enter
software standby
mode?
N
Y
Set standby timer select.
SBYCR/STS3 to STS0
Clear SURSFE in IER0 to 0.
Set SURSFE in IER0 to 1.
Set SSRSME in IER0 to 1. Clear SSRSME in IER0 to 0.
Module stop
(set MSTP17 in
EXMSTPCRL to 1.)
Enter software
standby mode
Wait for suspend/
resume interrupt
Figure 16.5 Suspend Operation
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(2)
Section 16 USB Function Module (USB)
Resume Operation from Up-Stream
If the USB bus enters the non-suspend state from the suspend state by resume signal output from
up-stream, perform the operation as shown in figure 16.6.
Application
USB function
USB cable connected
USB bus in suspend state
Resume interrupt is
requested from the
up-stream.
Suspend/resume
interrupt occurs.
(IFR0/SURSF = 1)
48-MHz USB clock
oscillation started
RESUME
USBINTN2 or
USBINTN3
Cancel software standby mode.
Wait for system clock oscillation
to be settled.
Wait for 48-MHz USB clock
oscillation to be settled.
Cancel 48-MHz USB clock
module stop.
(EXMSTPCRL/MSTP17 = 0)
Clear SURSF in IFR0 to 0.
Check if SURSS in IFR0 is 0.
Set SURSFE in IER0 to 1.
Clear SSRSME IN IER0 to 0.
Return to normal state.
Figure 16.6 Resume Operation from Up-Stream
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Section 16 USB Function Module (USB)
(3)
Transition from Suspend State to Software Standby Mode and Canceling Software
Standby Mode
If the USB bus enters from the suspend state to software standby mode, perform the operation as
shown in figure 16.7. When canceling software standby mode, ensure enough time for the system
clock oscillation to be settled.
Canceling software standby mode
Transition from suspend state to
software standby mode
(1)
Detect that USB bus is in suspend state.
(2)
Set SURSF in IFR0 to 1.
(3)
USBINTN interrupt
(4)
Clear SURSF in IFR0 to 0.
Check if SURSS in IFR0 is set to 1.
(5)
(6)
(7)
(8)
Clear SURSFE in IER0 to 0.
Set SSRSME in IER0 to 1.
(10)
(11)
(13)
Clear MSTP17 in EXMATPCRL to 0.
(14)
Supply 48-MHz USB clock.
(15)
Clear SURSF in IFR0 to 0.
Check if SURSS in IFR0 is cleared to 0.
(16)
Set SURSFE in IER0 to 1.
Clear SSRSME in IER0 to 0.
Shift to software standby mode.
(Execute SLEEP instruction.)
(17)
(9)
RESUME interrupt
Cancel software standby mode
(12) Wait for system clock oscillation to be settled.
Wait for 48-MHz USB clock oscillation to be
settled.
Set MSTP17 in EXMSTPCRL to 1.
Stop 48-MHz USB clock.
Detect that USB bus is in resume state.
USB communications can be resumed
through USB registers.
Stop all clocks of LSI.
Denotation of figures
: Operation by firmware setting
: Automatic operation by LSI hardware
Figure 16.7 Flow of Transition to and Canceling Software Standby Mode
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Section 16 USB Function Module (USB)
(10)
(1)
USB bus state
Normal
Resume → Normal
Suspend
(3)
USBINTN
interrupt
IFR0/SURSF
IFR0/SURSS
(2)
(4)
(15)
(4)
(15)
IER0/SURSFE
(5)
(16)
IER0/SSRSME
(5)
(16)
RESUME
interrupt
EXMSTPCRL/
MSTP17
Software
standby
(11)
(6)
(13)
(12)
(8)
Oscillator
(9)
Software standby
Oscillation
settling
time
(tOSC2)
(9)
System clock (φ)
(9)
PLL USB clock
Two cycles of
48-MHz USB clock
48-MHz USB
clock (cku)
(7)
Two cycles of
48-MHz USB clock
(14)
Figure 16.8 Timing of Transition to and Canceling Software Standby Mode
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Section 16 USB Function Module (USB)
(4)
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Remote-Wakeup Operation
If the USB bus enters the non-suspend (resume) state from the suspend state by the remotewakeup signal output from this function, perform the operation as shown in figure 16.9.
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Section 16 USB Function Module (USB)
Application
USB function
USB cable connected
USB bus in suspend state
Remote
wakeup enabled?
(CTLR/RWUPS = 1?)
N
Y
Bus wakeup source
generated
Wait for resume
from up-stream
Y
Software standby
mode ?
Cancel software
standby mode
N
Oscillation
stabilization time
has passed?
N
Y
48-MHz USB clock
supply started
Cancel 48-MHz USB clock module
stop.
(Clear MSTP17 in EXMSTPCRL to 0)
Set SURSFE in IER0 to 1.
Clear SSRSME in IER0 to 0.
Resume signal output
Suspend/resume
interrupt occurs.
(IFR0/SURSF = 1)
Remote wakeup execution.
(CTLR/RSME= 1)
USBININ2 or
USBININ3
Clear SURSF in IFR0 to 0.
Check if SURSS in IFR0 is
cleared to 0.
Return to normal state.
Figure 16.9 Remote-Wakeup
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Section 16 USB Function Module (USB)
16.5.5
Control Transfer
Control transfer consists of three stages: setup, data (not always included), and status (figure
16.10). The data stage comprises a number of bus transactions. Operation flowcharts for each
stage are shown below.
Setup stage
Control-in
Control-out
No data
Data stage
SETUP(0)
IN(1)
IN(0)
DATA0
DATA1
DATA0
SETUP(0)
OUT(1)
OUT(0)
DATA0
DATA1
DATA0
Status stage
...
...
IN(0/1)
OUT(1)
DATA0/1
DATA1
OUT(0/1)
IN(1)
DATA0/1
DATA1
SETUP(0)
IN(1)
DATA0
DATA1
Figure 16.10 Transfer Stages in Control Transfer
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(1)
Section 16 USB Function Module (USB)
Setup Stage
Application
USB function
SETUP token reception
Receive 8-byte command
data in EP0s
Command
to be processed by
application?
No
Automatic
processing by
this module
Yes
Set setup command
reception complete flag.
(IFR1.SETUP TS = 1)
To data stage
Interrupt request
Clear SETUP TS flag.
(IFR1.SETUP TS = 0)
Clear EP0i FIFO. (FCLR0.EP0iCLR = 1)
Clear EP0o FIFO..(FCLR0.EP0oCLR = 1)
Read 8-byte data from EP0s.
Decode command data.
Determine data stage direction.*1
Write 1 to EP0s read complete bit.
(TRG0.EP0s RDFN = 1)
*2
To control-in
data stage
To control-out
data stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by
the application, and determines the subsequent processing (for example, data stage direction, etc.).
2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status
stage should be enabled here. When the transfer direction is control-in, this interrupt is not required
and should be disabled.
Figure 16.11 Setup Stage Operation
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Section 16 USB Function Module (USB)
(2)
Data Stage (Control-In)
USB function
Application
IN token reception
From setup stage
1 written
to TRG0.EP0s
RDFN?
No
NAK
Yes
Valid data
in EP0i FIFO?
Write data to EP0i
data register (EPDR0i).
No
Write 1 to EP0i packet
enable bit.
(TRG0.EP0i PKTE = 1)
NAK
Yes
Data transmission to host
ACK
Set EP0i transmission
complete flag.
(IFR1.EP0i TS = 1)
Interrupt
request
Clear EP0i transmission
complete flag.
(IFR1.EP0i TS = 0)
Write data to EP0i
data register (EPDR0i).
Write 1 to EP0i packet
enable bit.
(TRG0.EP0i PKTE = 1)
Figure 16.12 Data Stage (Control-In) Operation
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be
sent, this data is written to the FIFO after the data written first has been sent to the host (EP0i TS
bit in IFR1 = 1).
The end of the data stage is identified when the host transmits an OUT token and the status stage
is entered.
Note: If the size of the data transmitted by the function is smaller than the data size requested by
the host, the function indicates the end of the data stage by returning to the host a packet
shorter than the maximum packet size. If the size of the data transmitted by the function is
an integral multiple of the maximum packet size, the function indicates the end of the data
stage by transmitting a zero-length packet.
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Section 16 USB Function Module (USB)
Data Stage (Control-Out)
USB function
Application
OUT token reception
1 written
to TRG0.EP0s
RDFN?
No
NAK
Yes
Data reception from host
ACK
Set EP0o reception
complete flag.
(IFR1.EP0o TS = 1)
Interrupt request
Read data from EP0o
receive data size register
(EPSZ0o).
OUT token reception
1 written
to TRG0.EP0o
RDFN?
Clear EP0o reception
complete flag.
(IFR1.EP0o TS = 0)
No
NAK
Read data from EP0o
data register (EPDR0o).
Yes
Write 1 to EP0o read
complete bit.
(TRG0.EP0o RDFN = 1)
Figure 16.13 Data Stage (Control-Out) Operation
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (EP0o TS bit in
IFR1 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit,
empties the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
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Section 16 USB Function Module (USB)
(4)
Status Stage (Control-In)
USB function
Application
OUT token reception
0-byte reception from host
ACK
Set EP0o reception
complete flag
(IFR1.EP0o TS = 1)
End of control transfer
Interrupt request
Clear EP0o reception
complete flag
(IFR1.EP0o TS = 0)
Write 1 to EP0o read
complete bit
(TRG0.EP0o RDFN = 1)
End of control transfer
Figure 16.14 Status Stage (Control-In) Operation
The control-in status stage starts with an OUT token from the host. The application receives 0byte data from the host, and ends control transfer.
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(5)
Section 16 USB Function Module (USB)
Status Stage (Control-Out)
USB function
Application
IN token reception
Valid data
in EP0i FIFO?
No
Interrupt request
NAK
Clear EP0i transfer
request flag.
(IFR1.EP0i TR = 0)
Yes
Write 1 to EP0i packet
enable bit.
(TRG0.EP0i PKTE = 1)
0-byte transmission to host
ACK
Set EP0i transmission
complete flag.
(IFR1.EP0i TS = 1)
End of control transfer
Interrupt request
Clear EP0i transmission
complete flag.
(IFR1.EP0i TS = 0)
End of control transfer
Figure 16.15 Status Stage (Control-Out) Operation
The control-out status stage starts with an IN token from the host. When an IN-token is received at
the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer
request interrupt is generated. The application recognizes from this interrupt that the status stage
has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable
bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be
transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
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Section 16 USB Function Module (USB)
16.5.6
EP1 Bulk-Out Transfer
USB function
Application
OUT token reception
Space
in EP1 FIFO?
No
NAK
Yes
Data reception from host
Read EP1 receive data
size register (EPSZ1).
ACK
Set EP1 FIFO full status.
(IFR2.EP1 FULL = 1)
Interrupt
request
Read data from EP1
data register (EPDR1).
Write 1 to EP1 read
complete bit.
(TRG1.EP1 RDFN = 1)
No Interrupt request
Yes
Clear EP1 FIFO full status.
(IFR2.EP1 FULL = 0)
Figure 16.16 EP1 Bulk-Out Transfer Operation
•
Dual FIFOs (EP1)
EP1 has two 64-byte FIFOs, but the user can receive data and read receive data without being
aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the EP1 FULL bit in IFR2 is set. After the
first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty,
and so the next packet can be received immediately. When both FIFOs are full, NAK is returned
to the host automatically. When reading of the receive data is completed following data reception,
1 is written to the EP1 RDFN bit in TRG1. This operation empties the FIFO that has just been
read, and makes it ready to receive the next packet.
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16.5.7
Section 16 USB Function Module (USB)
EP2 Bulk-In Transfer
USB function
Application
IN token reception
Valid data
in EP2 FIFO?
No
NAK
Interrupt
Set EP2 transfer
request
request flag.
(IFR2.EP2TR = 1)
Clear EP2 transfer
request flag.
(IFR2.EP2 TR = 0)
Yes
Write 1 to EP2 FIFO
empty interrupt bit.
(IER2.EP2 EMPTY = 1)
Data transmission to host
ACK
Space
in EP2 FIFO?
Yes
Set EP2
empty status.
(IFR2.EP2
EMPTY = 1)
Interrupt
request
IFR2.EP2 EMPTY interrupt
No
Clear EP2 empty status.
(IFR2.EP2 EMPTY = 0)
Write one packet of data
to EP2 data register.
(EPDR2)
Write 1 to EP2 packet
enable bit.
(TRG1.EP2 PKTE = 1)
Figure 16.17 EP2 Bulk-In Transfer Operation
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Section 16 USB Function Module (USB)
(1)
H8S/2456, H8S/2456R, H8S/2454 Group
Dual FIFOs (EP2)
EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being
aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For
example, even if both FIFOs are empty, it is not possible to perform EP2 PKTE at one time after
consecutively writing 128 bytes of data. EP2 PKTE must be performed for each 64-byte write.
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first
IN token, an EP2 TR bit interrupts in IFR2 is requested. With this interrupt, 1 is written to the EP2
EMPTYE bit in IER2, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are
empty, and so an EP2 FIFO empty interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2 EMPTYE is cleared to 0. If at least
one FIFO is empty, the EP2 EMPTY bit in IFR2 is set to 1. When ACK is returned from the host
after data transmission is completed, the FIFO used in the data transmission becomes empty. If the
other FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to the EP2 EMPTYE bit in IER2 and
disable interrupt requests.
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16.5.8
Section 16 USB Function Module (USB)
EP3 Interrupt-In Transfer
USB function
Application
Is there data
for transmission
to host?
No
Yes
IN token reception
Write data to EP3 data
register (EPDR3).
Valid data
in EP3FIFO?
No
NAK
Yes
Write 1 to EP3 packet
enable bit.
(TRG1.EP3 PKTE = 1)
Data transmission to host
ACK
Set EP3 transmission
complete flag.
(IFR2.EP3 TS = 1)
Interrupt request
Clear EP3 transmission
complete flag.
(IFR2.EP3 TS = 0)
Is there data
for transmission
to host?
No
Yes
Write data to EP3 data
register (EPDR3).
Write 1 to EP3 packet
enable bit.
(TRG1.EP3 PKTE = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is
referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 16.18 Operation of EP3 Interrupt-In Transfer
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Section 16 USB Function Module (USB)
16.6
Processing of USB Standard Commands and Class/
Vendor Commands
16.6.1
Processing of Commands Transmitted by Control Transfer
A command transmitted from the host by control transfer may require decoding and execution of
command processing on the application side. Whether command decoding is required on the
application side is indicated in table 16.7 below.
Table 16.7 Command Decoding on Application Side
Decoding not Necessary on Application Side
Decoding Necessary on Application Side
Clear Feature
Get Descriptor
Get Configuration
Class/Vendor command
Get Interface
Set Descriptor
Get Status
Sync Frame
Set Address
Set Configuration
Set Feature
Set Interface
If decoding is not necessary on the application side, command decoding and data stage and status
stage processing are performed automatically. No processing is necessary by the user. An interrupt
is not generated in this case.
If decoding is necessary on the application side, this module stores the command in the EP0s
FIFO. After reception is completed successfully, the IFR1/SETUP TS flag is set and an interrupt
request is generated. In the interrupt routine, eight bytes of data must be read from the EP0s data
register (EPDR0s) and decoded by firmware. The necessary data stage and status stage processing
should then be carried out according to the result of the decoding operation.
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16.7
Stall Operations
16.7.1
Overview
Section 16 USB Function Module (USB)
This section describes stall operations in this module. There are two cases in which the USB
function module stall function is used:
• When the application forcibly stalls an endpoint for some reason
• When a stall is performed automatically within the USB function module due to a USB
specification violation
The USB function module has internal status bits that hold the status (stall or non-stall) of each
endpoint. When a transaction is sent from the host, the module references these internal status bits
and determines whether to return a stall to the host. These bits cannot be cleared by the
application; they must be cleared with a Clear Feature command from the host.
However, the internal status bit for EP0 is automatically cleared only when the setup command is
received.
16.7.2
Forcible Stall by Application
The application uses the EPSTL register to issue a stall request for the USB function module.
When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (11 in figure 16.19). The internal status bits are not changed at this time. When a transaction is sent
from the host for the endpoint for which the EPSTL bit was set, the USB function module
references the internal status bit, and if this is not set, references the corresponding bit in EPSTL
(1-2 in figure 16.19). If the corresponding bit in EPSTL is set, the USB function module sets the
internal status bit and returns a stall handshake to the host (1-3 in figure 16.19). If the
corresponding bit in EPSTL is not set, the internal status bit is not changed and the transaction is
accepted.
Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the
host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature
command (3-1 in figure 16.19), the USB function module continues to return a stall handshake
while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed
for the corresponding endpoint (1-2 in figure 16.19). To clear a stall, therefore, it is necessary for
the corresponding bit in EPSTL to be cleared by the application, and also for the internal status bit
to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 16.19).
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Section 16 USB Function Module (USB)
(1) Transition from normal operation to stall
(1-1)
USB
EPSTL
0→1
Internal status bit
0
1. 1 written to EPSTL
by application
(1-2)
Reference
Transaction request
EPSTL
1
Internal status bit
0
(1-3)
Stall
STALL handshake
EPSTL
1
Internal status bit
0→1
1. IN/OUT token
received from host
2. EPSTL referenced
1. 1 set in EPSTL
2. Internal status bit
set to 1
3. Transmission of
STALL handshake
To (2-1) or (3-1)
(2) When Clear Feature is sent after EPSTL is cleared
(2-1)
Transaction request
1. EPSTL cleared to 0
by application
2. IN/OUT token
received from host
3. Internal status bit
already set to 1
4. EPSTL not
referenced
5. Internal status bit
not changed
Internal status bit
1
EPSTL
1→0
Internal status bit
1
EPSTL
0
1. Transmission of
STALL handshake
Internal status bit
1→0
EPSTL
0
1. Internal status bit
cleared to 0
(2-2)
STALL handshake
(2-3)
Clear Feature command
Normal status restored
(3) When Clear Feature is sent before EPSTL is cleared to 0
(3-1)
Clear Feature command
EPSTL
1
Internal status bit
1→0
1. Internal status bit
cleared to 0
2. EPSTL not changed
To (1-2)
Figure 16.19 Forcible Stall by Application
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16.7.3
Section 16 USB Function Module (USB)
Automatic Stall by USB Function Module
When a stall setting is made with the Set Feature command, or in the event of a USB specification
violation, the USB function module automatically sets the internal status bit for the relevant
endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 16.20).
Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the
host, without regard to the EPSTL register. After a bit is cleared by the Clear Feature command,
EPSTL is referenced (3-1 in figure 16.20). The USB function module continues to return a stall
handshake while the internal status bit is set, since the internal status bit is set even if a transaction
is executed for the corresponding endpoint (2-1 and 2-2 in figure 16.20). To clear a stall, therefore,
the internal status bit must be cleared with a Clear Feature command (3-1 in figure 16.20). If set
by the application, EPSTL should also be cleared (2-1 in figure 16.20).
(1) Transition from normal operation to stall
(1-1)
STALL handshake
Internal status bit
0→1
EPSTL
0
To (2-1) or (3-1)
1. In case of USB
specification
violation, etc., USB
function module
stalls endpoint
automatically
(2) When transaction is performed when internal status bit is set, and Clear Feature is sent
(2-1)
Transaction request
Internal status bit
1
EPSTL
0
Internal status bit
1
EPSTL
0
1. EPSTL cleared to 0
by application
2. IN/OUT token
received from host
3. Internal status bit
already set to 1
4. EPSTL not
referenced
5. Internal status bit
not changed
(2-2)
STALL handshake
1. Transmission of
STALL handshake
Stall status maintained
(3) When Clear Feature is sent before transaction is performed
(3-1)
Clear Feature command
Internal status bit
1→0
EPSTL
0
1. Internal status bit
cleared to 0
2. EPSTL not changed
Normal status restored
Figure 16.20 Automatic Stall by USB Function Module
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Section 16 USB Function Module (USB)
16.8
DMA Transfer
16.8.1
Overview
H8S/2456, H8S/2456R, H8S/2454 Group
DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword
data cannot be transferred.
When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is
generated. When endpoint 2 holds no valid data, a DMA request for endpoint 2 is generated.
If the DMA transfer is enabled by setting the EP1 DMAE bit in the DMA transfer setting register
to 1, zero-length data reception at endpoint 1 is ignored. When the DMA transfer is enabled, the
EP1 RDFN bit and EP2 PKTE bit do not need to be set to 1 in TRG1. (Note that the PKTE bit in
TRG1 must be set to 1 when the transfer data is less than the maximum number of bytes). When
all the data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the
maximum number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters
the FULL state, and the data in the FIFO can be transmitted (see figures 16.21 and 16.22).
16.8.2
Setting for the On-chip DMAC
The on-chip DMAC should be set for USB requests (using the DREQ signal), low-level input
activation, byte size, full-address mode transfer, and the DTA bit = 1 in the DMABCR register.
The on-chip DMAC will then be stopped after transfer has been completed the specified number
of times. However, note that the DREQ signal continues to be asserted (held at the low level)
regardless of the state of the DMAC when the DMA transfer requests still remains in this module.
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16.8.3
Section 16 USB Function Module (USB)
DMA Transfer for Endpoints 1 and 4
When the data received at EP1 is transferred by the DMAC, the USB function module
automatically performs the same processing as writing 1 to the RDFN bit in TRG1 if the currently
selected FIFO becomes empty. Accordingly, in DMA transfer, do not write 1 to the RDFN bit in
TRG1. If the user writes 1 to the RDFN bit in DMA transfer, correct operation cannot be
guaranteed.
Figure 16.21 shows an example of receiving 150 bytes of data from the host. In this case, internal
processing which is the same as writing 1 to the RDFN bit in TRG1 is automatically performed
three times. This internal processing is performed when the currently selected data FIFO becomes
empty. Accordingly, this processing is automatically performed both when 64-byte data is sent
and when data less than 64 bytes is sent.
64 bytes
64 bytes
RDFN
(Automatically
performed)
22 bytes
RDFN
RDFN
(Automatically (Automatically
performed)
performed)
Figure 16.21 RDFN Bit Operation for EP1
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Section 16 USB Function Module (USB)
16.8.4
DMA Transfer for Endpoints 2
When the transmit data at EP2 is transferred by the DMAC, the USB function module
automatically performs the same processing as writing 1 to the PKTE bit in TRG1 if the currently
selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the
user need not write 1 to the PKTE bit in TRG1. To transfer data of less than 64 bytes, the user
must write 1 to the PKTE bit using the DMA transfer end interrupt of the on-chip DMAC. If the
user writes 1 to the PKTE bit in TRG1 when the maximum number of bytes (64 bytes) are
transferred, correct operation cannot be guaranteed.
Figure 16.22 shows an example for transmitting 150 bytes of data to the host. In this case, internal
processing which is the same as writing 1 to the PKTE bit in TRG1 is automatically performed
twice. This internal processing is performed when the currently selected data FIFO becomes full.
Accordingly, this processing is automatically performed only when 64-byte data is sent.
When the last 22 bytes are sent, the internal processing for writing 1 to the PKTE bit in TRG1 is
not performed, and the user must write 1 to the PKTE bit by software. In this case, the application
has no more data to transfer but the USB function module continues to output DMA requests for
EP2 as long as the FIFO has an empty space. When all data has been transferred, write 0 to the
EP2 DMAE bit in DMAR to cancel DMA requests for EP2.
64 bytes
64 bytes
PKTE
(Automatically
performed)
22 bytes
PKTE is
PKTE
(Automatically not performed
performed)
Execute by DMA transfer
end interrupt (user)
Figure 16.22 PKTE Bit Operation for EP2
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16.9
Section 16 USB Function Module (USB)
Example of USB External Circuitry
1. USB Transceiver
This module supports the on-chip transceiver only, not the external transceiver.
2. D+ Pull-Up Control
The general output port (P20) is used for D+ pull-up control pin. The P20 pin is driven high by
the PULLUP_E bit of CTLR when the USB cable VBUS is connected.
Thus, USB host/hub connection notification (D+ pill-up) is enabled.
3. Detection of USB Cable Connection/Disconnection
As USB states, etc., are managed by hardware in this module, a VBUS signal that recognizes
connection/disconnection is necessary. The power supply signal (VBUS) in the USB cable is
used for this purpose. However, if the cable is connected to the USB host/hub when the
function (system installing this LSI) power is off, a voltage (5 V) will be applied from the USB
host/hub. Therefore, an IC (such as an HD74LV1G08A or 2G08A) that allows voltage
application when the system power is off should be connected externally.
USB
Vcc
PULLUP_E
On-chip transceiver
Vcc
(3.3 V)
P20
VBUS*3
DrVCC
(3.3 V)
USD+
USD-
DrVSS
Vss
Vcc
(3.3 V)
Regulator*1
Vcc
*2
External pull-up
control circuit
supporting full-speed
Notes:
1.5 kΩ
VBUS
(5 V)
D+
D-
GND
USB connector
1. Reduce voltage to the operating voltage of this LSI (3.3 V).
2. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can
be applied voltage even when the system power is turned off.
3. Prevent noise from the VBUS pin while the USB is performing communication.
Figure 16.23 Example of Circuitry in Bus Power Mode
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Section 16 USB Function Module (USB)
USB
Vcc
PULLUP_E
On-chip transceiver
Vcc
(3.3 V)
P20
VBUS*2
DrVCC
(3.3 V)
USD+
USD-
DrVSS
Vss
3.3 V
Vcc
*1
Vcc
*1
1.5 kΩ
External pull-up
control circuit
supporting full-speed
VBUS
(5 V)
D+
D-
GND
USB connector
Notes:
1. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can
be applied voltage even when the system power is turned off.
2. Prevent noise from the VBUS pin while the USB is performing communication.
Figure 16.24 Example of Circuitry in Self Power Mode
Page 1016 of 1408
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16.10
Section 16 USB Function Module (USB)
Usage Notes
16.10.1 Receiving Setup Data
Note the following for EPDR0s that receives 8-byte setup data:
1. As a latest setup command must be received in high priority, the write from the USB bus takes
priority over the read from the CPU. If the next setup command reception is started while the
CPU is reading data after the data is received, the read from the CPU is forcibly terminated.
Therefore, the data read after reception is started becomes invalid.
2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data
received at the next setup cannot be read correctly.
16.10.2 Clearing the FIFO
If a USB cable is disconnected during data transfer, the data being received or transmitted may
remain in the FIFO. When disconnecting a USB cable, clear the FIFO.
While a FIFO is transferring data, it must not be cleared.
16.10.3 Overreading and Overwriting the Data Registers
Note the following when reading or writing to a data register of this module.
(1)
Receive data registers
The receive data registers must not be read exceeding the valid amount of receive data, that is, the
number of bytes indicated by the receive data size register. Even for EPDR1, which has double
FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the
current valid FIFO buffer, be sure to write 1 to EPx RDFN in TRGx, which switches the valid
buffer, updates the receive data size to the new number of bytes, and enables the next data to be
received.
(2)
Transmit data registers
The transmit data registers must not be written to exceeding the maximum packet size. Even for
EPDR2, which has double FIFO buffers, write data within the maximum packet size at one time.
After the data is written, write 1 to EPx PKTE in TRGx to switch the valid buffer and enable the
next data to be written. Data must not be continuously written to the two FIFO buffers.
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Section 16 USB Function Module (USB)
16.10.4 Assigning Interrupt Sources to EP0
The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must
be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.
16.10.5 Clearing the FIFO When DMA Transfer is Enabled
EPDR1 cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1DMAE in DMAR =
1). Cancel DMA transfer before clearing the register.
16.10.6 Notes on TR Interrupt
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP2, and EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 16.25, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note: This module determines whether to return NAK if the FIFO of the target EP has no data
when receiving the IN token, but the TR interrupt flag is set after a NAK handshake is
sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is
set again.
TR interrupt routine
TR interrupt routine
Clear
Writes
TRG.
TR flag transmit data PKTE
CPU
Host
IN token
IN token
USB
Determines whether
to return NAK.
NAK
Determines whether
to return NAK.
NAK
Sets TR flag
IN token
Transmits data
Sets TR flag
(Sets the flag again)
ACK
Figure 16.25 TR Interrupt Flag Set Timing
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Section 16 USB Function Module (USB)
16.10.7 Module Stop Function Setting
Operation of the USB function module can be disabled or enabled using the module stop control
register. The initial setting is for operation of the USB function module to be halted. Register
access is enabled by clearing the module stop state. After clearing the module stop state, set the
register after executing a 26-state dummy read. For details of the module stop control register, see
section 24, Power-Down Modes.
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Section 16 USB Function Module (USB)
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Section 17 I2C Bus Interface 2 (IIC2)
Section 17 I2C Bus Interface 2 (IIC2)
This LSI has a four-channel I2C bus interface.
The I2C bus interface conforms to and provides a subset of the NXP I2C bus (inter-IC bus)
interface functions (Rev. 0.3) for standard-mode and fast-mode. The register configuration that
controls the I2C bus differs partly from the NXP configuration, however.
Figure 17.1 shows a block diagram of the I2C bus interface 2. Figure 17.2 shows an example of
I/O pin connections to external circuits.
17.1
•
•
•
•
•
•
•
Features
Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
Start and stop conditions generated automatically in master mode
Selection of acknowledge output levels when receiving
Automatic loading of acknowledge bit when transmitting
Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
Six interrupt sources
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
Direct bus drive
Two pins, SCL and SDA pins function as NMOS open-drain outputs.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Transfer clock
generation
circuit
Transmission/
reception
control circuit
Output
control
SCL
ICCRA
ICCRB
ICMR
Internal data bus
Noise canceler
ICDRT
Output
control
SDA
ICDRS
SAR
Address
comparator
Noise canceler
ICDRR
Bus state
decision circuit
Arbitration
decision circuit
ICSR
ICEIR
Interrupt
generator
[Legend]
ICCRA:
ICCRB:
ICMR:
ICSR:
ICIER:
ICDRT:
ICDRR:
ICDRS:
SAR:
Interrupt request
2
I C bus control register A
I2C bus control register B
I2C mode register
I2C status register
I2C interrupt permission register
I2C transmission data register
I2C reception data register
I2C bus shift register
Slave address register
Figure 17.1 Block Diagram of I2C Bus Interface 2
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Vcc
SCL in
Vcc
SCL
SCL
SDA
SDA
SCL out
SDA in
SCL in
SCL
SDA
(Master)
SCL
SDA
SDA out
SCL in
SCL out
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
(Slave 2)
Figure 17.2 External Circuit Connections of I/O Pins
17.2
Input/Output Pins
Table 17.1 shows the pin configuration of the I2C bus interface 2.
Table 17.1 Pin Configuration
Name
Abbreviation
I/O
Function
Serial clock pin
SCL0
I/O
IIC2_0 serial clock input/output
Serial data pin
SDA0
I/O
IIC2_0 serial data input/output
Serial clock pin
SCL1
I/O
IIC2_1 serial clock input/output
Serial data pin
SDA1
I/O
IIC2_1 serial data input/output
Serial clock pin
SCL2
I/O
IIC2_2 serial clock input/output
Serial data pin
SDA2
I/O
IIC2_2 serial data input/output
Serial clock pin
SCL3
I/O
IIC2_3 serial clock input/output
Serial data pin
SDA3
I/O
IIC2_3 serial data input/output
Note: The pin symbols are represented as SCL and SDA; channel numbers are omitted in this
manual.
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Page 1023 of 1408
Section 17 I2C Bus Interface 2 (IIC2)
17.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The I2C bus interface has the following registers.
Channel 0
•
•
•
•
•
•
•
•
•
I2C bus control register A_0 (ICCRA_0)
I2C bus control register B_0 (ICCRB_0)
I2C bus mode register_0 (ICMR_0)
I2C bus interrupt enable register_0 (ICIER_0)
I2C bus status register_0 (ICSR_0)
Slave address register_0 (SAR_0)
I2C bus transmit data register_0 (ICDRT_0)
I2C bus receive data register_0 (ICDRR_0)
I2C bus shift register_0 (ICDRS_0)
Channel 1
•
•
•
•
•
•
•
•
•
I2C bus control register A_1 (ICCRA_1)
I2C bus control register B_1 (ICCRB_1)
I2C bus mode register_1 (ICMR_1)
I2C bus interrupt enable register_1 (ICIER_1)
I2C bus status register_1 (ICSR_1)
Slave address register_1 (SAR_1)
I2C bus transmit data register_1 (ICDRT_1)
I2C bus receive data register_1 (ICDRR_1)
I2C bus shift register_1 (ICDRS_1)
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Section 17 I2C Bus Interface 2 (IIC2)
Channel 2
•
•
•
•
•
•
•
•
•
I2C bus control register A_2 (ICCRA_2)
I2C bus control register B_2 (ICCRB_2)
I2C bus mode register_2 (ICMR_2)
I2C bus interrupt enable register_2 (ICIER_2)
I2C bus status register_2 (ICSR_2)
Slave address register_2 (SAR_2)
I2C bus transmit data register_2 (ICDRT_2)
I2C bus receive data register_2 (ICDRR_2)
I2C bus shift register_2 (ICDRS_2)
Channel 3
•
•
•
•
•
•
•
•
•
I2C bus control register A_3 (ICCRA_3)
I2C bus control register B_3 (ICCRB_3)
I2C bus mode register_3 (ICMR_3)
I2C bus interrupt enable register_3 (ICIER_3)
I2C bus status register_3 (ICSR_3)
Slave address register_3 (SAR_3)
I2C bus transmit data register_3 (ICDRT_3)
I2C bus receive data register_3 (ICDRR_3)
I2C bus shift register_3 (ICDRS_3)
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Section 17 I2C Bus Interface 2 (IIC2)
17.3.1
H8S/2456, H8S/2456R, H8S/2454 Group
I2C Bus Control Register A (ICCRA)
ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ICE
0
R/W
I2C Bus Interface Enable
0: Disables SCL/SDA outputs. (Inputs to SCL/SDA
are available.)
1: This module is enabled for transfer operations.
(SCL and SDA pins are bus drive state.)
6
RCVD
0
R/W
Reception Disable
This bit enables or disables the next operation
when TRS is 0 and ICDRR is read.
0: Enables next reception.
1: Disables next reception.
5
MST
0
R/W
Master/Slave Select
4
TRS
0
R/W
Transmit/Receive Select
When arbitration is lost in master mode, MST and
TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of
the TRS bit should be made between transfer
frames. In addition, TRS is set to 1 automatically
in slave receive mode if the seventh bit of the start
condition matches the slave address set in SAR
and the eighth bit is set to 1.
Operating modes are described below according
to MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
CKS3
0
R/W
Transfer Clock Select 3 to 0
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
In the master mode, these bits should be set
according to the necessary transfer rate (see table
17.2). In the slave mode, they are used to secure
the data setup time in transmit mode. The data
setup time is 10 tcyc if CKS3 is cleared to 0 and
20 tcyc if CKS3 is set to 1.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Table 17.2 Transfer Rate
Transfer Rate
Bit 3
Bit 2
Bit 1
Bit 0
CKS3
CKS2
CKS1
CKS0
Clock
φ = 8 MHz
φ = 10 MHz φ = 20 MHz φ = 25 MHz φ = 33 MHz
0
0
0
0
φ/28
286 kHz
357 kHz
714 kHz*
893 kHz*
1179 kHz*
1
φ/40
200 kHz
250 kHz
500 kHz*
625 kHz*
825 kHz*
1
1
0
1
1
0
0
1
1
0
1
Note:
*
0
φ/48
167 kHz
208 kHz
417 kHz*
521 kHz*
688 kHz*
1
φ/64
125 kHz
156 kHz
313 kHz
391 kHz
516 kHz*
0
φ/168
47.6 kHz
59.5 kHz
119 kHz
149 kHz
196 kHz
1
φ/100
80.0 kHz
100 kHz
200 kHz
250 kHz
330 kHz
0
φ/112
71.4 kHz
89.3 kHz
179 kHz
223 kHz
295 kHz
1
φ/128
62.5 kHz
78.1 kHz
156 kHz
195 kHz
258 kHz
0
φ/56
143 kHz
179 kHz
357 kHz
446 kHz*
589 kHz*
1
φ/80
100 kHz
125 kHz
250 kHz
313 kHz
413 kHz*
0
φ/96
83.3 kHz
104 kHz
208 kHz
260 kHz
344 kHz
1
φ/128
62.5 kHz
78.1 kHz
156 kHz
195 kHz
258 kHz
0
φ/336
23.8 kHz
29.8 kHz
59.5 kHz
74.4 kHz
98.2 kHz
1
φ/200
40.0 kHz
50.0 kHz
100 kHz
125 kHz
165 kHz
0
φ/224
35.7 kHz
44.6 kHz
89.3 kHz
112 kHz
147 kHz
1
φ/256
31.3 kHz
39.1 kHz
78.1 kHz
97.7 kHz
129 kHz
Correct operation cannot be guaranteed since the transfer rate is beyond the I2C bus
interface specification (normal mode: maximum 100 kHz, high-speed mode: maximum
400 kHz).
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Section 17 I2C Bus Interface 2 (IIC2)
17.3.2
H8S/2456, H8S/2456R, H8S/2454 Group
I2C Bus Control Register B (ICCRB)
ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in I2C control.
Bit
Bit Name
Initial Value
R/W
Description
7
BBSY
0
R/W
Bus Busy
2
This bit enables to confirm whether the I C bus is
occupied or released and to issue start and stop
conditions in master mode. This bit is set to 1
when the SDA level changes from high to low
under the condition of SCL = high, assuming that
the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low
to high under the condition of SCL = high,
assuming that the stop condition has been issued.
Write 1 to BBSY and 0 to SCP to issue a start
condition. Follow this procedure when also retransmitting a start condition. Write 0 to BBSY and
0 to SCP to issue a stop condition. To issue a
start/stop condition, use the MOV instruction.
6
SCP
1
R/W
Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop
conditions in master mode.
To issue a start condition, write 1 in BBSY and 0
in SCP. A retransmit start condition is issued in
the same way. To issue a stop condition, write 0 in
BBSY and 0 in SCP. This bit is always read as 1.
If 1 is written, the data is not stored.
5
SDAO
1
R
This bit monitors SDA output level. When reading
and SDA0 is 1, the SDA pin outputs high. When
reading and SDA0 is 0, the SDA pin outputs low.
The write value should always be 1.
4
⎯
1
R/W
Reserved
The write value should always be 1.
3
SCLO
1
R
This bit monitors SCL output level. When reading
and SCLO is 1, the SCL pin outputs high. When
reading and SCLO is 0, the SCL pin outputs low.
2
⎯
1
⎯
Reserved
This bit is always read as 1.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial Value
R/W
Description
1
IICRST
0
R/W
IIC Control Part Reset
2
This bit resets control parts except for I C
registers. If this bit is set to 1 when hang-up is
occurred because of communication failure during
2
2
I C operation, I C control part can be reset without
setting ports and initializing registers.
0
⎯
1
⎯
Reserved
This bit is always read as 1.
17.3.3
I2C Bus Mode Register (ICMR)
ICMR controls the master mode wait and selects the number of transfer bits.
Bit
Bit Name
Initial Value
R/W
Description
7
⎯
0
⎯
Reserved
The write value should always be 0.
6
WAIT
0
R/W
Wait Insertion
This bit selects whether to insert a wait after data
transfer except for the acknowledge bit. When
WAIT is set to 1, after the fall of the clock for the
final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively
with no wait inserted.
The setting of this bit is invalid in slave mode.
5, 4
⎯
All 1
⎯
3
BCWP
1
R/W
Reserved
These bits are always read as 1.
BC Write Protect
This bit controls the BC2 to BC0 modifications.
When modifying BC2 to BC0, this bit should be
cleared to 0 and use the MOV instruction.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are
invalid.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial Value
R/W
Description
2
BC2
0
R/W
Bit Counter 2 to 0
1
BC1
0
R/W
0
BC0
0
R/W
These bits specify the number of bits to be
transferred next. When read, the remaining
number of transfer bits is indicated. The data is
transferred with one addition acknowledge bit. Bit
BC2 to BC0 settings should be made during an
interval between transfer frames. If bits BC2 to
BC0 are set to a value other than 000, the setting
should be made while the SCL line is low. The
value returns to 000 at the end of a data transfer,
including the acknowledge bit.
000: 9 bits
001: 2 bits
010: 3 bits
011: 4 bits
100: 5 bits
101: 6 bits
110: 7 bits
111: 8 bits
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
17.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be
received.
Bit
Bit Name
Initial Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit
enables or disables the transmit data empty
interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6
TEIE
0
R/W
Transmit End Interrupt Enable
This bit enables or disables the transmit end
interrupt (TEI) at the rising of the ninth clock while
the TDRE bit in ICSR is 1. TEI can be canceled by
clearing the TEND bit or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5
RIE
0
R/W
Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (RXI) when a received data is
transferred from ICDRS to ICDRR and the RDRF
bit in ICSR is set to 1. RXI can be canceled by
clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) is
disabled.
1: Receive data full interrupt request (RXI) is
enabled.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial Value
R/W
Description
4
NAKIE
0
R/W
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive
interrupt request (NAKI) when the NACKF and AL
bits in ICSR are set to 1. NAKI can be canceled by
clearing the NACKF, AL, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is
disabled.
1: NACK receive interrupt request (NAKI) is
enabled.
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable
0: Stop condition detection interrupt request
(STPI) is disabled.
1: Stop condition detection interrupt request
(STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgement Select
0: The value of the acknowledge bit is ignored,
and continuous transfer is performed.
1: If the acknowledge bit is 1, continuous transfer
is interrupted.
1
ACKBR
0
R
Receive Acknowledge
In transmit mode, this bit stores the acknowledge
data that are returned by the receive device. This
bit cannot be modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent
at the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
17.3.5
I2C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit
Bit Name
Initial Value
R/W
7
TDRE
0
R/W
Description
Transmit Data Register Empty
[Setting condition]
•
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty.
•
When TRS has been set.
•
When a start condition (including retransmission)
has been issued.
•
When a transition from the receive mode to the
transmit mode has been made in the slave mode.
[Clearing conditions]
• When 0 is written in TDRE after reading
TDRE = 1.
• When data is written in ICDRT.
6
TEND
0
R/W
Transmit End
[Setting conditions]
• When the ninth clock of SCL is rose while the
TDRE flag is 1.
[Clearing conditions]
• When 0 is written in TEND after reading TEND =
1.
• When data is written in ICDRT.
5
RDRF
0
R/W
Receive Data Register Full
[Setting condition]
• When a received data is transferred from ICDRS
to ICDRR.
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF =
1.
• When data is read from ICDRR.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial Value
R/W
Description
4
NACKF
0
R/W
No Acknowledge Detection Flag
[Setting condition]
•
When no acknowledge is detected from the
receive device in transmission while the ACKE bit
in ICIER is 1.
[Clearing condition]
•
3
STOP
0
R/W
When 0 is written in NACKF after reading NACKF
= 1.
Stop Condition Detection Flag
[Setting condition]
• When a stop condition is detected after frame
transfer.
[Clearing condition]
• When 0 is written in STOP after reading STOP =
1.
2
AL
0
R/W
Arbitration Lost Flag
This flag indicates that arbitration was lost in master
mode.
When two or more master devices attempt to seize
the bus at nearly the same time, if the I2C bus
interface detects data differing from the data it sent,
it sets AL to 1 to indicate that the bus has been taken
by another master.
[Setting conditions]
• If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode.
• When the SDA pin outputs high in master mode
while a start condition is detected.
[Clearing condition]
• When 0 is written in AL after reading AL =1.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial Value
R/W
Description
1
AAS
0
R/W
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA6
to SVA0 in SAR.
[Setting condition]
•
When the slave address is detected in slave
receive mode.
•
When the general call address is detected in
slave receive mode.
[Clearing condition]
•
0
ADZ
0
R/W
When 0 is written in AAS after reading AAS=1
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
•
When the general call address is detected in
slave receive mode.
[Clearing conditions]
• When 0 is written in ADZ after reading ADZ=1.
17.3.6
Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
Bit
Bit Name
Initial Value
R/W
Description
7 to 1
SVA6 to
SVA0
All 0
R/W
Slave Address 6 to 0
⎯
0
0
These bits set a unique address in bits SVA6 to
SVA0, differing from the addresses of other slave
2
devices connected to the I C bus.
R/W
Reserved
This bit is readable/writable. The write value
should always be 0.
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Section 17 I2C Bus Interface 2 (IIC2)
17.3.7
H8S/2456, H8S/2456R, H8S/2454 Group
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in
ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. The initial value of ICDRT is H'FF.
17.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot be written to this register. The initial value of
ICDRR is H'FF.
17.3.9
I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read from the CPU.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
17.4
Operation
17.4.1
I2C Bus Format
Figure 17.3 shows the I2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I2C bus format
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
m
(b) I2C bus format (start condition retransmission)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
m1
1
m2
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
Figure 17.3 I2C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
DATA
8
9
A
1-7
DATA
8
9
A
P
Figure 17.4 I2C Bus Timing
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Legend:
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA:
Slave address
R/W:
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receiving device drives SDA to low.
DATA: Transferred data
P:
17.4.2
Stop condition. The master device drives SDA from low to high while SCL is high.
Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations in master transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in
ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in
ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. After this, when TDRE is cleared to 0, data is
transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT, and clear TDRE and
TEND. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop
condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL
is fixed low until the transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set, thus
clearing TDRE.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
SCL
(master output)
1
2
3
4
5
6
SDA
(master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
7
8
Bit 1
Slave address
9
1
Bit 0
Bit 7
2
Bit 6
R/W
SDA
(slave output)
A
TDRE
TEND
Address + R/W
ICDRT
ICDRS
Data 1
Address + R/W
User
[2] Instruction of start
processing
condition issuance
Data 2
Data 1
[4] Write data to ICDRT (second byte).
[3] Write data to ICDRT (first byte).
[5] Write data to ICDRT (third byte).
Figure 17.5 Master Transmit Mode Operation Timing 1
SCL
(master output)
9
SDA
(master output)
SDA
(slave output)
1
2
3
4
5
6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
A
7
Bit 1
8
9
Bit 0
A/A
TDRE
TEND
Data n
ICDRT
ICDRS
Data n
User
[5] Write data to ICDRT.
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 17.6 Master Transmit Mode Operation Timing 2
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Section 17 I2C Bus Interface 2 (IIC2)
17.4.3
H8S/2456, H8S/2456R, H8S/2454 Group
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. The reception procedure and operations in master
receive mode are shown below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
of 9th receive clock pulse. At this time, the received data is read by reading ICDRR.
4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time
RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while
RDRF is 1, SCL is fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, read ICDRR. Then, clear
RCVD.
7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the
RCVD bit to 0.
8. The operation returns to the slave receive mode.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Master transmit mode
SCL
(master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
SDA
(slave output)
9
1
A
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User
processing
Data 1
[3] Read ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
Figure 17.7 Master Receive Mode Operation Timing 1
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Section 17 I2C Bus Interface 2 (IIC2)
SCL
(master output)
9
SDA
(master output)
A
SDA
(slave output)
1
H8S/2456, H8S/2456R, H8S/2454 Group
2
3
4
5
6
7
8
9
A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS
Data n
Data n-1
ICDRR
User
processing
Data n
Data n-1
[5] Read ICDRR after setting RCVD.
[6] Issue stop
condition
[7] Read ICDRR and clear RCVD
[8] Set slave
receive mode
Figure 17.8 Master Receive Mode Operation Timing 2
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H8S/2456, H8S/2456R, H8S/2454 Group
17.4.4
Section 17 I2C Bus Interface 2 (IIC2)
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS in ICCRA and TDRE in ICSR
are set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by clearing TDRE after writing transmit data to ICDRT every time
TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
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Section 17 I2C Bus Interface 2 (IIC2)
Slave receive mode
SCL
(master output)
H8S/2456, H8S/2456R, H8S/2454 Group
Slave transmit mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
9
1
A
SCL
(slave output)
SDA
(slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 7
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data 1
Data 2
Data 1
Data 3
Data 2
ICDRR
User
processing
[2] Write data to ICDRT (data 1).
[2] Write data to ICDRT (data 2).
[2] Write data to ICDRT (data 3).
Figure 17.9 Slave Transmit Mode Operation Timing 1
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Slave receive
mode
Slave transmit mode
SCL
(master output)
9
SDA
(master output)
A
1
2
3
4
5
6
7
8
9
A/A
SCL
(slave output)
SDA
(slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User
processing
[3] Clear TEND
[4] Read ICDRR (dummy read)
after clearing TRS
[5] Clear TDRE
Figure 17.10 Slave Transmit Mode Operation Timing 2
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Section 17 I2C Bus Interface 2 (IIC2)
17.4.5
H8S/2456, H8S/2456R, H8S/2454 Group
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCRA to 1. (Initial setting) Set the MST and TRS bits in ICCRA to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read) and RDRF
is cleared. (Since the read data show the slave address and R/W, it is not used.)
3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls
while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge
before reading ICDRR, to be returned to the master device, is reflected to the next transmit
frame.
4. The last byte data is read by reading ICDRR.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
SCL
(master output)
9
SDA
(master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
Bit 7
SCL
(slave output)
SDA
(slave output)
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[7] Read ICDRR.
[4] Read ICDRR (dummy read).
Figure 17.11 Slave Receive Mode Operation Timing 1
SCL
(master output)
9
SDA
(master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(slave output)
SDA
(slave output)
A
A
RDRF
ICDRS
Data 2
Data 1
ICDRR
Data 1
User
processing
[8] Set ACKBT
[9] Read ICDRR.
[11] Read ICDRR.
Figure 17.12 Slave Receive Mode Operation Timing 2
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Section 17 I2C Bus Interface 2 (IIC2)
17.4.6
H8S/2456, H8S/2456R, H8S/2454 Group
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 17.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or SDA
input signal
D
C
Q
Latch
Q
D
Latch
March detector
Internal
SCL or SDA
signal
System clock
period
Sampling
clock
Figure 17.13 Block Diagram of Noise Canceler
17.4.7
Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 17.14 to 17.17.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Start
Initialize
Read BBSY in ICCRB
[1]
Test the status of the SCL and SDA lines.
[2]
Select master transmit mode.
[3]
Start condition issuance.
[4]
Select transmit data for the first byte (slave address + R/W).
[5]
Wait for 1 byte to be transmitted.
[6]
Test the acknowledge bit, transferred from the specified slave device.
[7]
Set transmit data for the second and subsequent data (except for the final byte).
[8]
Wait for ICDRT empty.
[9]
Set the final byte of transmit data.
[1]
No
BBSY=0 ?
Yes
Set MST = 1 and TRS
= 1 in ICCRA.
[2]
Write BBSY = 1
and SCP = 0.
[3]
Write transmit data
in ICDRT
[4]
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Read ACKBR in ICIER
[6]
ACKBR=0 ?
No
[10] Wait for the completion of transmission for the final byte.
Yes
Transmit
mode?
Yes
[11] Clear TEND flag.
No
Write transmit data in ICDRT
Master receive mode
[12] Clear STOP flag.
[7]
[13] Stop condition issuance.
Read TDRE in ICSR
No
[8]
[14] Wait for the generation of the stop condition.
TDRE=1 ?
[15] Set slave receive mode. Clear TDRE.
Yes
No
Final byte?
[9]
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No
[10]
TEND=1 ?
Yes
Clear TEND in ICSR
[11]
Clear STOP in ICSR
[12]
Write BBSY = 0
and SCP = 0
[13]
Read STOP in ICSR
No
[14]
STOP=1 ?
Yes
Set MST = 0 and TRS
= 0 in ICCRA
[15]
Clear TDRE in ICSR
End
Figure 17.14 Sample Flowchart for Master Transmit Mode
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Mater receive mode
[1]
Clear TEND, select master receive mode, and then clear TDRE.*
[2]
Set acknowledge to the transmitting device.*
[3]
Dummy read ICDDR.*
[4]
Wait for 1 byte to be received.
[5]
Check if the (last receive - 1).
[6]
Read the receive data.
[7]
Set acknowledge of the final byte. Disable continuous receive (RCVD = 1).
[8]
Read receive data of (final byte - 1).
[9]
Wait for the final byte to be received.
Clear TEND in ICSR
Set TRS = 0 (ICCRA)
[1]
Clear TDRE of ICSR
Set ACKBT = 0 (ICIER)
[2]
Dummy read ICDRR
[3]
Read RDRF in ICSR
No
[4]
RDRF=1 ?
Yes
Last receive
- 1?
No
Read ICDRR
Yes
[5]
[10] Clear STOP flag.
[6]
[11] Stop condition issuance.
[12] Wait for the generation of stop condition.
Set ACKBT = 1 (ICIER)
[7]
Set RCVD = 1 (ICCRA)
Read ICDRR
[13] Read the receive data of the final byte.
[14] Clear RCVD to 0.
[8]
[15] Set slave receive mode.
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Clear STOP in ICSR
Write BBSY = 0
and SCP = 0
[9]
[10]
[11]
Read STOP of ICSR
No
[12]
STOP=1 ?
Yes
Read ICDRR
[13]
Set RCVD = 0 (ICCRA)
[14]
Set MST = 0 (ICCRA)
[15]
End
Note: * Ensure that no interrupts are received while steps [1] through [3] are being processed.
Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1],
and processing jumps to step [7]. Step [8] is ICDDR dummy read.
Figure 17.15 Sample Flowchart for Master Receive Mode
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
[1] Clear the flag AAS.
Slave transmit mode
Clear AAS in ICSR
[1]
Write transmit data
in ICDRT
[2]
[3] Wait for ICDRT empty.
[4] Set the last byte of the transmit data.
Read TDRE in ICSR
No
[5] Wait the transmission end of the last byte.
[3]
TDRE=1 ?
Yes
No
[6] Clear the flag TEND.
[7] Set slave receive mode.
End of
transmission?
Yes
[2] Set transmit data for ICDRT (except for the last data).
[8] Dummy read ICDRR to release the SCL line.
[4]
[9] Clear the flag TDRE.
Write transmit data
in ICDRT
Read TEND in ICSR
No
[5]
TEND=1 ?
Yes
Clear TEND in ICSR
[6]
Set TRS=0 in ICCRA
[7]
Dummy read ICDRR
[8]
Clear TDRE in ICSR
[9]
End
Figure 17.16 Sample Flowchart for Slave Transmit Mode
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
Slave receive mode
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Read AAS in ICSR
No
Set RIE = 0 in ICIER
AAS=1 ?
[2] Clear the flag AAS.
Yes
Clear AAS in ICSR
[12]
Read STOP in ICSR
No
[1]
[1] Determination of slave address*
Use receive-data-full interrupts to determine
whether the slave address matches.
• If the slave address did match (AAS = 1),
execute steps [2] to [11].
• If the slave address did not match (AAS = 0),
execute steps [12] to [15].
[3] Set the acknowledge for the transmit device.
Set ACKBT=0 in ICIER
[2]
[4] Dummy read ICDRR.
Dummy read ICDRR
[3]
[5] Wait the reception end of 1 byte.
[13]
STOP=1 ?
Yes
Clear RDRF in ICSR
[6] Check if the (last receive - 1).
Read RDRF in ICSR
[14]
No
Clear STOP in ICSR
[4]
RDRF=1 ?
Set RIE = 1 in ICIER
[7] Read the received data.
[8] Set the acknowledge for the last byte.
[15]
Yes
Last receive
- 1?
No
Read ICDRR
Yes
[9] Read the received data of the (last byte - 1).
[5]
[10] Wait the reception end of the last byte.
[6]
[11] Read the received data of the last byte.
[12] Receive-data-full interrupt requests
are disabled.
Set ACKBT=1 in ICIER
Read ICDRR
[7]
[13] Determined by the stop condition
detection flag.
[8]
[14] Clear the RDRF and STOP flags.
Read RDRF in ICSR
No
[9]
RDRF=1 ?
[15] Receive-data-full interrupt requests
are enabled.
Yes
Read ICDRR
[10]
End
Additional information: If only one byte is received, steps [2] through [6] are omitted following step [1],
and processing jumps to step [7]. Step [8] is ICDRR dummy read.
Note: *
In slave receiver mode, even if the actual and received slave addresses did not match,
received data are stored in ICDRR, after which the RDRF in ICSR is set.
Checking whether or not the addresses matched is thus required.
Figure 17.17 Sample Flowchart for Slave Receive Mode
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
17.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost. Table 17.3 shows the contents of each
interrupt request.
Table 17.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Transmit Data Empty
TXI
(TDRE=1) • (TIE=1)
Transmit End
TEI
(TEND=1) • (TEIE=1)
Receive Data Full
RXI
(RDRF=1) • (RIE=1)
STOP Recognition
STPI
(STOP=1) • (STIE=1)
NACK Detection
NAKI
{(NACKF=1)+(AL=1)} • (NAKIE=1)
Arbitration Lost
Interrupt exception handling is performed when the interrupt conditions listed in table 17.3 are set
to 1 and the CPU is ready to accept interrupts. During exception handling, the interrupt sources
should be cleared. Note, however, that TDRE and TEND are automatically cleared by writing
transmit data to ICDRT, and RDRF is automatically cleared by reading data from ICDRR. In
particular, if TDRE is set at the same time transmit data is written to ICDRT, and then TDRE is
cleared again, an extra byte of data may be transmitted.
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Section 17 I2C Bus Interface 2 (IIC2)
17.6
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Synchronous Circuit
In master mode,
•
•
When SCL is driven to low by the slave device
When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pullup resistance)
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 17.18
shows the timing of the bit synchronous circuit and table 17.4 shows the time when SCL output
changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
VIH
SCL
Internal SCL
Figure 17.18 Timing of the Bit Synchronous Circuit
Table 17.4 Time for monitoring SCL
CKS3
CKS2
CSK1
CSK0
Time for monitoring SCL
0
0
*
*
7.5 tcyc
1
0
0
41.5 tcyc
1
19.5 tcyc
1
1
*
0
*
*
17.5 tcyc
1
0
0
85.5 tcyc
1
1
Page 1054 of 1408
*
41.5 tcyc
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17.7
Section 17 I2C Bus Interface 2 (IIC2)
Usage Notes
1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
Check SCLO in the I2C control register B (IICRB) to confirm the fall of the ninth clock.
When the start/stop conditions are issued (retransmitted) at the specific timing under the
following condition (i) or (ii), such conditions may not be output successfully. This does not
occur in other cases.
(i) When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
(ii) When the bit synchronous circuit is activated by extending the low period of eighth and
ninth clocks, that is driven by the slave device
2. Control WAIT in the I2C bus mode register (ICMR) to be set to 0.
When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave
device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This
does not occur in other cases.
3. In slave receive mode, even if a slave address does not match, received data is stored in
ICDRR, and then the RDRF bit in ICSR is set. To confirm whether or not the addresses
matched, see the AAS bit in the I2C bus status register (ICSR). (See figure 17.17, Sample
Flowchart for Slave Receive Mode.)
4. If 0 is written to the ICE bit in ICCRA or 1 is written to the IICRST bit in ICCRB in one of the
following four states, the BBSY bit in ICCRB and STOP bit in ICSR are undefined.
(1) This module is the bus master of the I2C in master transmission mode (MST = 1 and TRS
= 1 in ICCRA).
(2) This module is the bus master of the I2C in master reception mode (MST = 1 and TRS = 0
in ICCRA).
(3) This module is transmitting data in slave transmission mode (MST = 0 and TRS = 1 in
ICCRA).
(4) This module is transmitting an acknowledgment in slave reception mode (MST = 0 and
TRS = 0 in ICCRA).
The undefined state of BBSY in ICCRB can be exited in one of the following ways:
⎯ Input the start condition (SCL = high and SDA falling) to set BBSY to 1.
⎯ Input the stop condition (SCL = high and SDA rising) to clear BBSY to 0.
⎯ Write 1 to BBSY and 0 to SCP in ICCRB to issue the start condition with SCL = high and
SDA = high in master transmission mode. BBSY is set to 1 when the start condition (SCL
= high and SDA falling) is output.
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Section 17 I2C Bus Interface 2 (IIC2)
H8S/2456, H8S/2456R, H8S/2454 Group
⎯ Write 0 to BBSY and SCP in ICCRB to issue the stop condition when SDA = low in
master transmission or master reception mode and this module is the only module which
pulls SCL low. BBSY is cleared to 0 when the stop condition (SCL = high and SDA rising)
is output.
5. Restriction on Setting Transfer Rate in Use of Multi-Master
In multi-master usage when I2C transfer rate setting of this LSI is lower than those of the other
masters, unexpected length of SCL may occasionally be output. To avoid this, the specified
value must be greater than or equal to the value produced by multiplying the fastest transfer
rate among the other masters by 1/1.8. For example, when the transfer rate of the fastest bus
master among the other bus masters is 400 kbps, the transfer rate of the I2C of this LSI must
be set to at least 223 kbps (= 400/1.8).
6. Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in Use of MultiMaster
When master transmission is selected by consecutively manipulating the MST and TRS bits in
multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for
TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode (MST
= 1, TRS = 1).
Ways to avoid this effect are listed below.
⎯ Use the MOV instruction to set MST and TRS in multi-master usage.
⎯ When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and
TRS = 0 is not confirmed, set MST = 0 and TRS = 0 again.
7. Note on Master Receive Mode
In master receive mode, when SCL is fixed low on the falling edge of the 8th clock while the
RDRF bit is set to 1 and ICDRR is read around the falling edge of the 8th clock, the clock is
only fixed low in the 8th clock of the next round of data reception. The SCL is then released
from its fixed state without reading ICDRR and the 9th clock is output. As a result, some
receive data is lost.
Ways to avoid this phenomenon are listed below.
⎯ Read ICDRR in master receive mode before the rising edge of the 8th clock.
⎯ Set RCVD to 1 in master receive mode and perform communication in units of one byte.
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Section 17 I2C Bus Interface 2 (IIC2)
8. Notes on Changing from Master Transmit Mode to Master Receive Mode
If TRS is cleared to 0 before the falling edge of the 9th clock in master transmit mode when
master transmit mode is changed to master receive mode, this module outputs the receive clock
in synchronization with the internal clock whether ICDRR is read (dummy read) or not.
At that time, if ICDRR is read (dummy read) at or after the 9th receive clock pulse due to
DMAC transfer or DTC transfer, the output of the next receive clock is not triggered even if
ICDRR is read (dummy read). This module stops outputting the receive clock.
Then, the communication hangs up with SCL fixed low.
Ways to avoid this phenomenon are listed below.
(1) Design the timing so that ICDRR is read (dummy read) before the 9th receive clock pulse
when master transmit mode is changed to master receive mode.
(2) Clear TRS to 0 at or after the falling edge of the 9th transmit clock when master transmit
mode is changed to master receive mode.
In way (2), before clearing TRS to 0 at or after the falling edge of the 9th transmit clock,
confirm the SCLO bit (SCL monitor flag) in ICCR2 has been set to 0 (the SCL pin outputs
low).
Also in way (2), reading ICDRR (dummy read) triggers the output of the first receive clock in
master receive mode. No problem occurs even if reading ICDRR (dummy read) is delayed due
to DMAC or DTC transfer or by interrupt processing. Steps (1) through (3) (no interrupts are
received during these steps) in figure 17.15, Sample Flowchart for Master Receive Mode, are
unnecessary.
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Section 17 I2C Bus Interface 2 (IIC2)
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H8S/2456, H8S/2456R, H8S/2454 Group
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 18 A/D Converter
Section 18 A/D Converter
This LSI includes two units (units 0 and 1) of successive approximation type 10-bit A/D
converter. In the H8S/2456 group and H8S/2456R group, the A/D converter units 0 and 1 allow up
to eight analog input channels to be selected. In the H8S/2454 group, unit 0 allows up to eight
analog input channels to be selected while unit 1 allows up to two channels.
Figures 18.1 and 18.2 show block diagrams of the A/D converter units 0 and 1, respectively.
18.1
Features
• 10-bit resolution
• Input channels:
H8S/2456 group and H8S/2456R group: Eight channels (total of 16 channels for the two units)
H8S/2454 group: Eight channels for unit 0 and two channels for unit 1 (total of 10 channels for
the two units)
• Conversion cycle: 64 cycles or 40 cycles (A/D conversion clock)
• Two kinds of operating modes
⎯ Single mode: Single-channel A/D conversion
⎯ Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels*1
• Separate A/D conversion clock specifiable for each unit (φ, φ/2, or φ/4)
• Eight data registers for A/D converter unit 0 and eight data registers for unit 1*2 (total of 16
data registers for the two units)
Results of A/D conversion are held in a 16-bit data register for each channel.
• Sample and hold functionality
• Three types of conversion start
Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit
(TPU) or 8-bit timer (TMR), or an external trigger signal.
• Interrupt source
A/D conversion end interrupt (ADI) request can be generated.
• Module stop state specifiable
Notes: 1. Continuous A/D conversion on 1 to 2 channels in the H8S/2454 group.
2. Two data registers for unit 1 (total of ten data registers for the two units) in the
H8S/2454 group.
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Section 18 A/D Converter
Internal
data bus
AVSS
Bus interface
ADCR_0
ADCSR_0
ADDRH_0
ADDRG_0
ADDRF_0
ADDRE_0
ADDRD_0
ADDRC_0
ADDRB_0
10-bit A/D
Vref
ADDRA_0
AVCC
Successive approximation
register
Module data bus
AN0
+
AN1
AN2
Multiplexer
–
AN3
AN4
AN5
AN6
Comparator
Control circuit
Sample-andhold circuit
AN7
ADI0 interrupt
signal
ADTRG0-A
ADTRG0-B
[Legend]
ADCR_0:
ADCSR_0:
ADDRA_0:
ADDRB_0:
ADDRC_0:
Conversion start
trigger from
TPU (units 0, 1) or TMR
A/D control register_0
A/D control/status register_0
A/D data register A_0
A/D data register B_0
A/D data register C_0
ADDRD_0:
ADDRE_0:
ADDRF_0:
ADDRG_0:
ADDRH_0:
A/D data register D_0
A/D data register E_0
A/D data register F_0
A/D data register G_0
A/D data register H_0
Figure 18.1 Block Diagram of A/D Converter Unit 0 (AD_0)
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Section 18 A/D Converter
Internal
data bus
AVSS
Bus interface
ADCR_1
ADCSR_1
ADDRH_1
ADDRG_1
ADDRF_1
ADDRE_1
ADDRD_1
ADDRC_1
ADDRB_1
10-bit A/D
Vref
ADDRA_1
AVCC
Successive approximation
register
Module data bus
AN8*
+
AN9*
–
Multiplexer
AN10*
AN11*
AN12
AN13
Comparator
Control circuit
Sample-andhold circuit
AN14*
AN15*
ADI1 interrupt
signal
ADTRG1
[Legend]
ADCR_1:
ADCSR_1:
ADDRA_1:
ADDRB_1:
ADDRC_1:
Conversion start
trigger from
TPU (units 0, 1)
A/D control register_1
A/D control/status register_1
A/D data register A_1
A/D data register B_1
A/D data register C_1
ADDRD_0:
ADDRE_0:
ADDRF_0:
ADDRG_0:
ADDRH_0:
A/D data register D_1
A/D data register E_1
A/D data register F_1
A/D data register G_1
A/D data register H_1
Note: * The H8S/2454 group does not have these pins.
Figure 18.2 Block Diagram of A/D Converter Unit 1 (AD_1)
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Section 18 A/D Converter
18.2
Input/Output Pins
Tables 18.1 and 18.2 show the pin configuration of the A/D converter.
Table 18.1 Pin Configuration (H8S/2456 Group and H8S/2456R Group)
Unit
Symbol Pin Name
0
AD_0
1
AD_1
Common
Note:
*
Symbol
I/O
Function
Analog inputs
Analog input pin 0
AN0
Input
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger
input pin 0_A
ADTRG0-A
Input
External trigger input pin 0_A
for starting A/D conversion*
A/D external trigger
input pin 0_B
ADTRG0-B
Input
External trigger input pin 0_B
for starting A/D conversion*
Analog input pin 8
AN8
Input
Analog inputs
Analog input pin 9
AN9
Input
Analog input pin 10
AN10
Input
Analog input pin 11
AN11
Input
Analog input pin 12
AN12
Input
Analog input pin 13
AN13
Input
Analog input pin 14
AN14
Input
Analog input pin 15
AN15
Input
A/D external trigger
input pin 1
ADTRG1
Input
External trigger input pin A for
starting A/D conversion
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground
Reference voltage pin
Vref
Input
A/D conversion reference
voltage
Selectable by setting of the TRGS1, TRGS0, and EXTRGS bits in ADCR.
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Section 18 A/D Converter
Table 18.2 Pin Configuration (H8S/2454 Group)
Unit
Abbr.
Pin Name
Symbol
I/O
Function
0
AD_0
Analog input pin 0
AN0
Input
Analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger
input pin 0_A
ADTRG0-A
Input
External trigger input pin 0_A
for starting A/D conversion*
A/D external trigger
input pin 0_B
ADTRG0-B
Input
External trigger input pin 0_B
for starting A/D conversion*
Analog input pin 12
AN12
Input
Analog inputs
Analog input pin 13
AN13
Input
A/D external trigger
input pin 1
ADTRG1
Input
External trigger input pin A for
starting A/D conversion
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground
Reference voltage pin
Vref
Input
A/D conversion reference
voltage
1
AD_1
Common
Note:
*
Selectable by setting of the TRGS1, TRGS0, and EXTRGS bits in ADCR.
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Section 18 A/D Converter
18.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The A/D converter has the following registers.
Unit 0 (A/D_0) registers:
•
•
•
•
•
•
•
•
•
•
A/D data register A_0 (ADDRA_0)
A/D data register B_0 (ADDRB_0)
A/D data register C_0 (ADDRC_0)
A/D data register D_0 (ADDRD_0)
A/D data register E_0 (ADDRE_0)
A/D data register F_0 (ADDRF_0)
A/D data register G_0 (ADDRG_0)
A/D data register H_0 (ADDRH_0)
A/D control/status register_0 (ADCSR_0)
A/D control register_0 (ADCR_0)
Unit 1 (A/D_1) registers:
•
•
•
•
•
•
•
•
•
•
A/D data register A_1 (ADDRA_1)
A/D data register B_1 (ADDRB_1)
A/D data register C_1 (ADDRC_1)
A/D data register D_1 (ADDRD_1)
A/D data register E_1 (ADDRE_1)
A/D data register F_1 (ADDRF_1)
A/D data register G_1 (ADDRG_1)
A/D data register H_1 (ADDRH_1)
A/D control/status register_1 (ADCSR_1)
A/D control register_1 (ADCR_1)
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18.3.1
Section 18 A/D Converter
A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in tables 18.3 and 18.4.
The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read
directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit
units.
Table 18.3 Analog Input Channels and Corresponding ADDR Registers
(H8S/2456 Group and H8S/2456R Group)
Analog Input Channel
Channel Set 0
(CH3 = 0)
AN0
Analog Input Channel
Data Register Storing Channel Set 1
Data Register Storing
Conversion Result
Conversion Result
(CH3 = 1)
ADDRA_0
AN8
ADDRA_1
AN1
ADDRB_0
AN9
ADDRB_1
AN2
ADDRC_0
AN10
ADDRC_1
AN3
ADDRD_0
AN11
ADDRD_1
AN4
ADDRE_0
AN12
ADDRE_1
AN5
ADDRF_0
AN13
ADDRF_1
AN6
ADDRG_0
AN14
ADDRG_1
AN7
ADDRH_0
AN15
ADDRH_1
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Section 18 A/D Converter
Table 18.4 Analog Input Channels and Corresponding ADDR Registers (H8S/2454 Group)
Analog Input Channel
Analog Input Channel
Channel Set 0
(CH3 = 0)
Data Register Storing Channel Set 1
Conversion Result
(CH3 = 1)
AN0
ADDRA_0
⎯
⎯
AN1
ADDRB_0
⎯
⎯
AN2
ADDRC_0
⎯
⎯
AN3
ADDRD_0
⎯
⎯
AN4
ADDRE_0
AN12
ADDRE_1
AN5
ADDRF_0
AN13
ADDRF_1
AN6
ADDRG_0
⎯
⎯
AN7
ADDRH_0
⎯
⎯
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Data Register Storing
Conversion Result
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18.3.2
Section 18 A/D Converter
A/D Control/Status Register for Unit 0 (ADCSR_0)
ADCSR_0 controls A/D conversion operations.
Bit
Bit Name
Initial
Value
7
ADF
0
R/W
Description
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• Completion of A/D conversion in single mode
•
Completion of A/D conversion on all specified
channels in scan mode
[Clearing conditions]
• Writing of 0 after reading ADF = 1
•
6
ADIE
0
R/W
5
ADST
0
R/W
Reading from ADDR after activation of the DMAC or
DTC by an ADI interrupt
A/D Interrupt Enable
Setting this bit to 1 enables ADI interrupts by ADF.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when A/D conversion
on the specified channel ends. In scan mode, A/D
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or hardware standby mode. While the ADSTCLR bit in
ADCR is set to 1, the ADST bit is cleared to 0
automatically when A/D conversion on all selected
channels ends, and then A/D conversion stops.
The timing to clear the ADST bit automatically differs
from that of ADF setting; the ADST bit is cleared before
the ADF bit is set.
4
EXCKS
0
R/W
Clock Extension Select
Specifies the A/D conversion time in combination with
the CKS1 and CKS0 bits in ADCR. Be sure to set these
three bits at one time. For details, see the description of
the ADCR resisters.
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Section 18 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
3
2
1
0
CH3
CH2
CH1
CH0
0
0
0
0
R/W
R/W
R/W
R/W
Channel Select 3 to 0
Selects analog input together with bits SCANE and
SCANS in ADCR.
• When SCANE = 0 and SCANS = x
0000: AN0
0001: AN1
0010: AN2
0011: AN3
0100: AN4
0101: AN5
0110: AN6
0111: AN7
1xxx: Setting prohibited
• When SCANE = 1 and SCANS = 0
0000: AN0
0001: AN0 and AN1
0010: AN0 to AN2
0011: AN0 to AN3
0100: AN4
0101: AN4 and AN5
0110: AN4 to AN6
0111: AN4 to AN7
1xxx: Setting prohibited
• When SCANE = 1 and SCANS = 1
0000: AN0
0001: AN0 and AN1
0010: AN0 to AN2
0011: AN0 to AN3
0100: AN0 to AN4
0101: AN0 to AN5
0110: AN0 to AN6
0111: AN0 to AN7
1xxx: Setting prohibited
[Legend]
x:
Don't care
Note: * Only 0 can be written to this bit, to clear the flag.
Page 1068 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
18.3.3
Section 18 A/D Converter
A/D Control/Status Register for Unit 1 (ADCSR_1)
ADCSR_1 controls A/D conversion operations.
Bit
Bit Name
Initial
Value
7
ADF
0
R/W
Description
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• Completion of A/D conversion in single mode
•
Completion of A/D conversion on all specified
channels in scan mode
[Clearing conditions]
• Writing of 0 after reading ADF = 1
•
6
ADIE
0
R/W
5
ADST
0
R/W
Reading from ADDR after activation of the DTC by an
ADI interrupt
A/D Interrupt Enable
Setting this bit to 1 enables ADI interrupts by ADF.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when A/D conversion
on the specified channel ends. In scan mode, A/D
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or hardware standby mode. While the ADSTCLR bit in
ADCR is set to 1, the ADST bit is cleared to 0
automatically when A/D conversion on all selected
channels ends, and then A/D conversion stops.
The timing to clear the ADST bit automatically differs from
that of ADF setting; the ADST bit is cleared before the
ADF bit is set.
4
EXCKS
0
R/W
Clock Extension Select
Specifies the A/D conversion time in combination with the
CKS1 and CKS0 bits in ADCR. Be sure to set these three
bits at one time. For details, see the description of the
ADCR resisters.
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Section 18 A/D Converter
•
H8S/2456 Group and H8S/2456R Group
Bit
Bit Name
Initial
Value
R/W
Description
3
2
1
0
CH3
CH2
CH1
CH0
0
0
0
0
R/W
R/W
R/W
R/W
Channel Select 3 to 0
Selects analog input together with bits SCANE and
SCANS in ADCR.
• When SCANE = 0 and SCANS = x
0xxx: Setting prohibited
1000: AN8
1001: AN9
1010: AN10
1011: AN11
1100: AN12
1101: AN13
1110: AN14
1111: AN15
• When SCANE = 1 and SCANS = 0
0xxx: Setting prohibited
1000: AN8
1001: AN8 and AN9
1010: AN8 to AN10
1011: AN8 to AN11
1100: AN12
1101: AN12 and AN13
1110: AN12 to AN14
1111: AN12 to AN15
• When SCANE = 1 and SCANS = 1
0xxx: Setting prohibited
1000: AN8
1001: AN8 and AN9
1010: AN8 to AN10
1011: AN8 to AN11
1100: AN8 to AN12
1101: AN8 to AN13
1110: AN8 to AN14
1111: AN8 to AN15
[Legend]
x:
Don't care
Note: * Only 0 can be written to this bit, to clear the flag.
Page 1070 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
•
Section 18 A/D Converter
H8S/2454 Group
Bit
Bit Name
Initial
Value
R/W
Description
3
2
1
0
CH3
CH2
CH1
CH0
0
0
0
0
R/W
R/W
R/W
R/W
Channel Select 3 to 0
Selects analog input together with bits SCANE and
SCANS in ADCR.
• When SCANE = 0 and SCANS = x
0xxx: Setting prohibited
10xx: Setting prohibited
1100: AN12
1101: AN13
111x: Setting prohibited
• When SCANE = 1 and SCANS = 0
0xxx: Setting prohibited
10xx: Setting prohibited
1100: AN12
1101: AN12 and AN13
111x: Setting prohibited
• Setting SCANE = 1 and SCANS = 1 are prohibited.
[Legend]
x:
Don't care
Note: * Only 0 can be written to this bit, to clear the flag.
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Section 18 A/D Converter
18.3.4
A/D Control Register (ADCR_0) Unit 0
ADCR enables A/D conversion to be started by an external trigger input.
Bit
Bit Name
Initial
Value
R/W
Description
7
TRGS1
0
R/W
Timer Trigger Select 1 and 0 and Extended Trigger Select
6
TRGS0
0
R/W
0
EXTRGS
0
R/W
These bits enable or disable the start of A/D conversion by a
trigger signal.
000: Disables A/D conversion start by external trigger
010: Enables A/D conversion start by external trigger from
TPU (units 0 and 1)*
100: Enables A/D conversion start by external trigger from
TMR
110: Enables A/D conversion start by the ADTRG0-A pin
001: Enables A/D conversion start by the ADTRG0-B pin
011: Enables simultaneous A/D conversion start in multiple
units by external trigger from TPU (units 0 and 1)
101: Enables simultaneous A/D conversion start in multiple
units by external trigger from TMR
111: Enables simultaneous A/D conversion start in multiple
units by the ADTRG0-B pin
Page 1072 of 1408
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Section 18 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
5
SCANE
0
R/W
Scan Mode
4
SCANS
0
R/W
These bits select the A/D conversion operating mode.
0x: Single mode
10: Scan mode. A/D conversion is performed continuously for
channels 1 to 4.
11: Scan mode. A/D conversion is performed continuously for
channels 1 to 8.
3
CKS1
0
R/W
Clock Select 1 and 0
2
CKS0
0
R/W
These bits select the A/D conversion clock (ADCLK) and
specify the A/D conversion time in combination with the
EXCKS bit.
First select the A/D conversion time while ADST = 0 in
ADCSR and then set the mode of A/D conversion. Before
entering software standby mode or module stop state, set
these bits to B'11.
Set CKS1 and CKS0 bits appropriately so that the ADCLK
satisfies the conversion time.
EXCKS, CKS1, and CKS0
000: Setting prohibited
001: A/D conversion time = 268 states (max.) at ADCLK = φ/4
010: A/D conversion time = 138 states (max.) at ADCLK = φ/2
011: A/D conversion time = 73 states (max.) at ADCLK = φ
100: Setting prohibited
101: A/D conversion time = 172 states (max.) at ADCLK = φ/4
110: A/D conversion time = 90 states (max.) at ADCLK = φ/2
111: A/D conversion time = 49 states (max.) at ADCLK = φ
1
ADSTCLR 0
R/W
A/D Start Clear
This bit enables or disables automatic clearing of the ADST bit
in scan mode.
0: The ADST bit is not automatically cleared to 0 in scan
mode.
1: The ADST bit is cleared to 0 upon completion of the A/D
conversion for all of the selected channels in scan mode.
[Legend]
x:
Don't care
Note: * If this bit is set the same as the TRGS_1, TRGS0, and EXTRGS bits in ADCR_1, the
A/D converter units 0 and 1 start A/D conversion by conversion start trigger from TPU
(units 0 and 1).
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Section 18 A/D Converter
18.3.5
A/D Control Register (ADCR_1) Unit 1
ADCR enables A/D conversion to be started by an external trigger input.
Bit
Bit Name
Initial
Value
R/W
Description
7
TRGS1
0
R/W
Timer Trigger Select 1 and 0 and Extended Trigger Select
6
TRGS0
0
R/W
0
EXTRGS
0
R/W
These bits enable or disable the start of A/D conversion by a
trigger signal.
000: Disables A/D conversion start by external trigger
010: Enables A/D conversion start by external trigger from
1
TPU (units 0 and 1)*
100: Enables A/D conversion start by external trigger from
TMR
110: Enables A/D conversion start by the ADTRG1 pin
001: Setting prohibited
011: Enables simultaneous A/D conversion start in multiple
units by external trigger from TPU (units 0 and 1)
101: Enables simultaneous A/D conversion start in multiple
units by external trigger from TMR
111: Enables simultaneous A/D conversion start in multiple
units by the ADTRG0-B pin
5
SCANE
0
R/W
Scan Mode
4
SCANS
0
R/W
These bits select the A/D conversion operating mode.
0x: Single mode
10: Scan mode. A/D conversion is performed continuously for
channels 1 to 4.
11: Scan mode. A/D conversion is performed continuously for
2
channels 1 to 8.*
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Section 18 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
3
CKS1
0
R/W
Clock Select 1 and 0
2
CKS0
0
R/W
These bits select the A/D conversion clock (ADCLK) and
specify the A/D conversion time in combination with the
EXCKS bit.
First select the A/D conversion time while ADST = 0 in
ADCSR and then set the mode of A/D conversion. Before
entering software standby mode or module stop state, set
these bits to B'11.
Set CKS1 and CKS0 bits appropriately so that the ADCLK
satisfies the conversion time.
EXCKS, CKS1, and CKS0
000: Setting prohibited
001: A/D conversion time = 268 states (max.) at ADCLK = φ/4
010: A/D conversion time = 138 states (max.) at ADCLK = φ/2
011: A/D conversion time = 73 states (max.) at ADCLK = φ
100: Setting prohibited
101: A/D conversion time = 172 states (max.) at ADCLK = φ/4
110: A/D conversion time = 90 states (max.) at ADCLK = φ/2
111: A/D conversion time = 49 states (max.) at ADCLK = φ
1
ADSTCLR 0
R/W
A/D Start Clear
This bit enables or disables automatic clearing of the ADST
bit in scan mode.
0: The ADST bit is not automatically cleared to 0 in scan
mode.
1: The ADST bit is cleared to 0 upon completion of the A/D
conversion for all of the selected channels in scan mode.
[Legend]
x:
Don't care
Notes: 1. If this bit is set the same as the TRGS_1, TRGS0, and EXTRGS bits in ADCR_0, the
A/D converter units 0 and 1 start A/D conversion by conversion start trigger from TPU
(units 0 and 1).
2. Setting prohibited in the H8S/2454 Group.
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Page 1075 of 1408
Section 18 A/D Converter
18.4
H8S/2456, H8S/2456R, H8S/2454 Group
Operation
The A/D converter has two operating modes: single mode and scan mode. First select the clock for
A/D conversion (ADCLK). When changing the operating mode or analog input channel, to
prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set to 1
at the same time as the operating mode or analog input channel is changed.
18.4.1
Single Mode
In single mode, A/D conversion is to be performed only once on the analog input of the specified
single channel.
1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by
software, TPU, TMR, or an external trigger input.
2. When A/D conversion is completed, the A/D conversion result is transferred to the
corresponding A/D data register of the channel.
3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set
to 1 at this time, an ADI interrupt request is generated.
4. The ADST bit remains at 1 during A/D conversion, and is automatically cleared to 0 when
A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0
during A/D conversion, A/D conversion stops and the A/D converter enters a wait state.
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Section 18 A/D Converter
Set*
ADIE
Set*
ADST
Set*
A/D conversion start
Clear*
Clear*
ADF
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Waiting for conversion
Waiting for
conversion
A/D conversion 1
Channel 2 (AN2)
operation state
Waiting for conversion
Channel 3 (AN3)
operation state
Waiting for conversion
Waiting for conversion
A/D conversion 2
Waiting for conversion
ADDRA
Reading A/D conversion result
A/D conversion result 1
ADDRB
Reading A/D conversion result
A/D conversion result 2
ADDRC
ADDRD
Note: * ↓ indicates the timing of instruction execution by software.
Figure 18.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
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Section 18 A/D Converter
18.4.2
H8S/2456, H8S/2456R, H8S/2454 Group
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified
channels up to four or eight* channels. Two types of scan mode are provided, that is, continuous
scan mode where A/D conversion is repeatedly performed and one-cycle scan mode where A/D
conversion is performed for the specified channels for one cycle.
(1)
Continuous Scan Mode
1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
input, A/D conversion starts on the first channel in the specified channel group. Consecutive
A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a
maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive
A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and
CH2 of unit 0 = B'00, on AN4 when CH3 and CH2 of unit 1 = B'01, on AN8* when CH3 and
CH2 of unit 1 = B'10, or on AN12 when CH3 and CH2 of unit 1= B'11. When consecutive
A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 =
B'0 or on AN8* when CH3 = B'1.
2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
transferred to the corresponding ADDR of each channel.
3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of
the first channel in the group starts again.
4. The ADST bit is not cleared automatically, and steps 2 to 3 are repeated as long as the ADST
bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D
converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from
the first channel in the group.
Note: * Only possible in the H8S/2456 group and H8S/2456R group.
Page 1078 of 1408
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Section 18 A/D Converter
A/D conversion consecutive execution
Clear*1
Set*1
ADST
Clear*1
ADF
Channel 0 (AN0)
operation state
Waiting for
conversion
A/D
conversion 1
Channel 1 (AN1)
operation state
Waiting for conversion
Channel 2 (AN2)
operation state
Waiting for conversion
Channel 3 (AN3)
operation state
Waiting for conversion
A/D conversion time
Waiting for conversion
A/D
conversion 2
A/D
conversion 4
Waiting for conversion
A/D
conversion 3
Waiting for conversion
A/D
conversion 5
*2
Waiting for
conversion
Waiting for conversion
Transfer
ADDRA
A/D conversion result 1
ADDRB
A/D conversion result 4
A/D conversion result 2
ADDRC
A/D conversion result 3
ADDRD
Notes: 1. ↓ indicates the timing of instruction execution by software.
2. Data being converted is ignored.
Figure 18.4 Example of A/D Conversion
(Continuous Scan Mode, Three Channels (AN0 to AN2) Selected)
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Section 18 A/D Converter
(2)
H8S/2456, H8S/2456R, H8S/2454 Group
One-Cycle Scan Mode
1. Set the ADSTCLR bit in ADCR to 1.
2. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
input, A/D conversion starts on the first channel in the specified channel group. Consecutive
A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a
maximum of eight channels (SCANE and SCANS = B'11) can be selected. Four-channel
consecutive A/D conversion starts on AN0 when CH3 and CH2 = B'00 of unit 0, on AN4
when CH3 and CH2 = B'01, on AN8* when CH3 and CH2 of unit 1 = B'10, or on AN12 when
CH3 and CH2 of unit 1= B'11. Eight-channel consecutive A/D conversion starts on AN0 when
CH3 = B'0 or on AN8* when CH3 = B'1.
3. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
transferred to the corresponding ADDR of each channel.
4. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated.
5. The ADST bit is automatically cleared when A/D conversion is completed for all of the
channels that have been selected. A/D conversion stops and the A/D converter enters a wait
state.
Note: * Only possible in the H8S/2456 group and H8S/2456R group.
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Section 18 A/D Converter
A/D conversion one-cycle execution
Set *
ADST
Clear*
ADF
A/D conversion time
Channel 4 (AN4) Waiting for conversion
operation state
Channel5 (AN5)
operation state
Channel 6 (AN6)
operation state
Waiting for conversion
A/D conversion 1
Waiting for conversion
Waiting for conversion
A/D conversion 2
Waiting for conversion
Waiting for conversion
A/D conversion 3
Channel 7 (AN7)
operation state
Waiting for conversion
Transfer
ADDRE
A/D conversion result 1
ADDRF
A/D conversion result 2
ADDRG
A/D conversion result 3
ADDRH
Note: * ↓ indicates the timing of instruction execution by software.
Figure 18.5 Example of A/D Conversion
(One-Cycle Scan Mode, Three Channels (AN4 to AN6) Selected)
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Section 18 A/D Converter
18.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 18.6 shows the A/D conversion timing. Tables 18.5 and 18.6
show the A/D conversion time.
As shown in figure 18.6, the A/D conversion time (tCONV) includes the A/D conversion start delay
time (tD) and the input sampling time (tSPL). The length of tD varies depending on the timing of the
write access to ADCSR. The total conversion time therefore varies within the ranges indicated in
tables 18.5 and 18.6.
In scan mode, the values given in tables 18.5 and 18.6 apply to the first conversion time. The
values given in table 18.7 apply to the second and subsequent conversions. In either case, bit
EXCKS in ADCSR, and bits CKS1 and CKS0 in ADCR should be set so that the conversion time
is within the ranges indicated by the A/D conversion characteristics.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
[Legend]
(1):
ADCSR write cycle
(2):
ADCSR address
tD:
A/D conversion start delay time
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 18.6 A/D Conversion Timing
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Section 18 A/D Converter
Table 18.5 A/D Conversion Characteristics (EXCKS = 0)
CKS1 = 0
CKS1 = 1
CKS = 1
CKS = 0
CKS = 1
Item
Symbol Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
A/D conversion start
tD
4
⎯
10
4
⎯
8
3
⎯
7
Input sampling time
tSPL
⎯
156
⎯
⎯
78
⎯
⎯
39
⎯
A/D conversion time
tCONV
262
⎯
268
134
⎯
138
69
⎯
73
delay time
Note: Values in the table are the number of states.
Table 18.6 A/D Conversion Characteristics (EXCKS = 1)
CKS1 = 0
CKS1 = 1
CKS = 1
CKS = 0
CKS = 1
Item
Symbol Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
A/D conversion start
tD
4
⎯
10
4
⎯
8
3
⎯
7
Input sampling time
tSPL
⎯
60
⎯
⎯
30
⎯
⎯
15
⎯
A/D conversion time
tCONV
166
⎯
172
86
⎯
90
45
⎯
49
delay time
Note: Values in the table are the number of states.
Table 18.7 A/D Conversion Time (Scan Mode)
EXCKS
CKS1
CKS0
Conversion Time (Number of States)
0
0
0
Setting prohibited
1
256 (fixed)
0
128 (fixed)
1
64 (fixed)
0
Setting prohibited
1
160 (fixed)
0
80 (fixed)
1
40 (fixed)
1
1
0
1
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Section 18 A/D Converter
18.4.4
H8S/2456, H8S/2456R, H8S/2454 Group
External Trigger Input Timing
A/D conversion can be externally triggered. For unit 0, an external trigger is input from the
ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 or B'001 in ADCR_0.
For unit 1, an external trigger is input from the ADTRG1 pin when the TRGS1, TRGS0, and
EXTRGS bits are set to B'110 in ADCR_1. For multiple-unit simultaneous start, an external
trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to
B'111 in ADCR. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling
edge of the ADTRG0 pin. Other operations, in both single and scan modes, are the same as when
the ADST bit has been set to 1 by software. Figure 18.7 shows the timing. Figure 18.8 shows the
timing of multiple-unit simultaneous start.
φ
ADTRG0
Internal trigger
signal
ADST
A/D conversion
Figure 18.7 External Trigger Input Timing (TRGS1, TRGS0, and EXTRGS ≠ B'111)
Page 1084 of 1408
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Section 18 A/D Converter
φ
ADTRG0
Internal trigger
signal
ADST
A/D conversion
Figure 18.8 External Trigger Input Timing when Multiple Units Start Simultaneously
(TRSG1, TRGS0, and EXTRGS = B'111)
18.5
Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is
completed enables ADI interrupt requests. The data transfer controller (DTC) and DMA controller
(DMAC) * can be activated by an ADI interrupt. Having the converted data read by the DTC or
DMAC* in response to an ADI interrupt enables continuous conversion to be achieved without
imposing a load on software.
Note: * Only possible in unit 0.
Table 18.8 A/D Converter Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
DMAC Activation
ADI0
A/D conversion end
ADF
Possible*
Possible
Note:
*
Only possible in unit 0.
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Section 18 A/D Converter
18.6
H8S/2456, H8S/2456R, H8S/2454 Group
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes.
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.9).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 18.10).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 18.10).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error
(see figure 18.10).
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
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Section 18 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
2
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 18.9 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 18.10 A/D Conversion Accuracy Definitions
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Section 18 A/D Converter
18.7
Usage Notes
18.7.1
Module Stop Function Setting
H8S/2456, H8S/2456R, H8S/2454 Group
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing the module stop state. Set the CKS1 and CKS2 bits to 1 to set ADCLK to φ, and clear the
ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion when entering
module stop state after operation of the A/D converter. After that, set the module stop control
register after executing a dummy read by one word. For details, see section 24, Power-Down
Modes.
18.7.2
A/D Input Hold Function in Software Standby Mode
When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are
retained, and the analog power supply current is equal to as during A/D conversion. If the analog
power supply current needs to be reduced in software standby mode, set the CKS1 and CKS2 bits
to 1 to set ADCLK to φ, and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to
disable A/D conversion. After that, enter software standby mode after executing a dummy read by
one word.
18.7.3
Restarting the A/D Converter
When the ADST bit has been cleared to 0, A/D converter stops in synchronization with the
ADCLK and then enters the standby sate. After the ADST bit has been cleared, the converter may
not actually make the transition to the standby state for up to 10 cycles (φ), so do not change the
channels of the ADCLK, motion mode, or analog input at this time.
When restarting the A/D converter right after the ADST bit has been cleared to 0, read the 16
bytes from ADDRA to ADDRH and then start the A/D converter by setting the ADST bit to 1. If
the converter is in single mode or one-cycle scan mode, however, the ADST bit can be set to 1 by
clearing the ADF bit to 0 after confirming that the ADF bit had been set to 1 on completion of the
previous round of conversion.
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18.7.4
Section 18 A/D Converter
Permissible Signal Source Impedance
This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input
signal for which the signal source impedance is 5 kΩ or less. This specification is provided to
enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
provided externally for conversion in single mode, the input load will essentially comprise only
the internal input resistance of 5 kΩ, and the signal source impedance is ignored. However, since a
low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with
a large differential coefficient (e.g., 5 mV/μs or greater) (see figure 18.11). When converting a
high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted.
This LSI
Equivalent circuit of the A/D converter
Sensor output
impedance
R ≤ 5 kΩ
10 kΩ
Sensor input
Low-pass
filter
C ≤ 0.1 μF
Cin =
15 pF
7 pF
Figure 18.11 Example of Analog Input Circuit
18.7.5
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, acting as antennas.
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Section 18 A/D Converter
18.7.6
H8S/2456, H8S/2456R, H8S/2454 Group
Setting Range of Analog Power Supply and Other Pins
If the conditions shown below are not met, the reliability of the LSI may be adversely affected.
• Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ VAN ≤ Vref.
• Relation between AVss and Vss, and AVcc and Vcc
As the relationship between AVss and Vss, set AVss = Vss. If the A/D converter is not used,
set AVcc = Vcc and AVss = Vss.
• Vref setting range
The reference voltage at the Vref pin should be set in the range Vref ≤ AVcc.
18.7.7
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Digital circuitry must be isolated from the analog input pins (AN0 to AN15*), analog reference
power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss). Also, the
analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board.
Note: * In the H8S/2454 group, only AN0 to AN7, AN12, and AN13 are available as analog
input pins.
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18.7.8
Section 18 A/D Converter
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN15*) should be connected between AVcc and AVss as
shown in figure 18.12. Also, the bypass capacitors connected to AVcc and the filter capacitor
connected to the AN0 to AN11 pins must be connected to AVss.
If a filter capacitor is connected, the input currents at the AN0 to AN15* pins are averaged, and so
an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the
current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D
converter exceeds the current input via the input impedance (Rin), an error will arise in the analog
input pin voltage. Careful consideration is therefore required when deciding the circuit constants.
Note: * In the H8S/2454 group, only AN0 to AN7, AN11, and AN12 are available as analog
input pins.
AVCC
Vref
100 Ω
Rin* 2
*1
AN0 to AN15* 3
*1
0.1 µF
AVSS
Notes:
Values are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
3. The H8S/2454 Group has only AN0 to AN7, AN11, and AN12 as analog input pins.
Figure 18.12 Example of Analog Input Protection Circuit
Table 18.9 Analog Pin Specifications
Item
Min.
Max.
Unit
Analog input capacitance
⎯
15
pF
Permissible signal source impedance
⎯
5
kΩ
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Section 18 A/D Converter
18.7.9
Concurrent Operation of Two A/D Converters
When operating two A/D converters concurrently, if conversion by the two converters starts at
different times, the accuracy of conversion may be affected by crosstalk between the two
converters.
When converter Y starts A/D conversion during the period indicated by TX-Y in figure 18.13 below
after the start of A/D conversion by converter X, and conversion by converter X is completed
while conversion by converter Y is still in progress, the accuracy of A/D conversion may not be
guaranteed.
When operating two A/D converters concurrently, be sure to conduct adequate evaluation in
advance.
Note: X and Y in "converter X" and "converter Y" indicate either pair of 0 and 1.
Converter X
ADST
Converter Y
ADST
ANn
in operation
Wait for conversion
tSPL
A/D conversion
Wait for conversion
TX-Y
[Legend]
ANn: Operating channel of converter Y
TX-Y: Difference in time when A/D conversion starts
tSPL: Input sampling time
Figure 18.13 An Example of Timing Where Accuracy of A/D Conversion is not Guaranteed
Table 18.10 Difference in Time When A/D Conversion Starts (TX-Y) in Figure 18.13
TX-Y
Unit
0 to 10
ADCLK cycles
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Section 18 A/D Converter
18.7.10 Notes on Start of A/D Conversion by Conversion Start Trigger from TPU (Units 0
and 1)
When A/D conversion starts by a conversion start trigger from the TPU, the register settings of the
TPU and A/D converters must be checked so that A/D conversion does not start at unintended
timing.
When the TTGE bit in multiple channels of the TPU (units 0 and 1) is set to 1 and the TRGS1,
TRGS0, and EXTRGS bits in ADCR_0 and ADCR_1 are set to b’010 at the start of A/D
conversion by a conversion start trigger from the TPU, the A/D converter units 0 and 1 start A/D
conversion by the trigger accepted first regardless of the number of the TPU unit which has issued
the trigger. The trigger requested during A/D conversion is ignored. Figure 18.14 shows an
example of the operation timing when A/D conversion starts by the trigger from the TPU (units 0
and 1).
Conversion start trigger from
TPU (unit 0: channels 0 to 5)
A conversion start trigger during A/D conversion
is ignored.
Conversion start trigger from
TPU (unit 1: channels 6 to 11)
A/D converter
unit 0
ADST in
operation
A/D converter
unit 1
ADST in
operation
Wait for conversion
A/D conversion 1
Wait for conversion A/D conversion 2
Wait for conversion
A/D conversion 1
Wait for conversion A/D conversion 2
Figure 18.14 Example of Operation Timing when A/D Conversion Starts by Conversion
Start Trigger from TPU (Units 0 and 1)
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Section 18 A/D Converter
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Section 19 D/A Converter
Section 19 D/A Converter
19.1
Features
D/A converter features are listed below.
•
•
•
•
•
•
8-bit resolution
Output channels: Two channels
Maximum conversion time of 10 µs (with 20 pF load)
Output voltage of 0 V to Vref
D/A output hold function in software standby mode
Module stop state can be set.
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Module data bus
Bus interface
H8S/2456, H8S/2456R, H8S/2454 Group
Section 19 D/A Converter
Internal data bus
DA2
D/A
DACR23
8-bit
DA3
DADR3
AVcc
DADR2
Vref
AVss
Control circuit
[Legend]
DADR2: D/A data register 2
DADR3: D/A data register 3
DACR23: D/A control register 23
Figure 19.1 Block Diagram of D/A Converter
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19.2
Section 19 D/A Converter
Input/Output Pins
Table 19.1 shows the pin configuration of the D/A converter.
Table 19.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power pin
Analog ground pin
AVCC
Input
Analog power
AVSS
Input
Analog ground
Reference voltage pin
Vref
Input
Reference voltage of D/A converter
Analog output pin 2
DA2
Output
Channel 2 analog output
Analog output pin 3
DA3
Output
Channel 3 analog output
19.3
Register Descriptions
The D/A converter has the following registers.
•
•
•
D/A data register 2 (DADR2)
D/A data register 3 (DADR3)
D/A control register 23 (DACR23)
19.3.1
D/A Data Registers 2 and 3 (DADR2 and DADR3)
DADR2 and DADR3 are 8-bit readable/writable registers that store data for conversion.
Whenever analog output is enabled, the values in DADR are converted and output to the analog
output pins.
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Section 19 D/A Converter
19.3.2
D/A Control Register 23 (DACR23)
DACR23 controls the operation of channels 2 and 3 in the D/A converter.
Bit
Bit Name
Initial
Value
R/W
Description
7
DAOE3
0
R/W
D/A Output Enable 3
Controls D/A conversion and analog output.
0: Channel 3 analog output (DA3) is disabled.
1: Channel 3 D/A conversion is enabled; channel 3
analog output (DA3) is enabled.
6
DAOE2
0
R/W
D/A Output Enable 2
Controls D/A conversion and analog output.
0: Channel 2 analog output (DA2) is disabled.
1: Channel 2 D/A conversion is enabled; channel 2
analog output (DA2) is enabled.
5
DAE
0
R/W
D/A Enable
This bit is used together with the DAOE2 and DAOE3
bits to control D/A conversion. When the DAE bit is
cleared to 0, channel 2 and 3 D/A conversions are
controlled independently. When the DAE bit is set to 1,
channel 2 and 3 D/A conversions are controlled
together.
Output of conversion results is always controlled
independently by the DAOE2 and DAOE3 bits. For
details, see table 19.2.
4 to 0
⎯
All 1
⎯
Reserved
These bits are always read as 1 and cannot be
modified.
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Section 19 D/A Converter
Table 19.2 Control of D/A Conversion
Bit 5
DAE
Bit 7
Bit 6
DAOE3 DAOE2
Description
0
0
0
D/A conversion disabled
1
Channel 2 D/A conversion enabled, and channel 3 D/A conversion
disabled.
Channel 2 analog output (DA2) enabled, and channel 3 analog output
(DA3) disabled.
1
0
Channel 2 D/A conversion disabled, and channel 3 D/A conversion
enabled.
Channel 2 analog output (DA2) disabled, channel 3 analog output
(DA3) enabled.
1
Channel 2 and 3 D/A conversions enabled.
Channel 2 and 3 analog outputs (DA2 and DA3) enabled.
1
0
0
Channel 2 and 3 D/A conversions enabled.
Channel 2 and 3 analog outputs (DA2 and DA3) disabled.
1
Channel 2 and 3 D/A conversions enabled.
Channel 2 analog output (DA2) enabled, and channel 3 analog output
(DA3) disabled.
1
0
Channel 2 and 3 D/A conversions enabled.
Channel 2 analog output (DA2) disabled, and channel 3 analog output
(DA3) enabled.
1
Channel 2 and 3 D/A conversions enabled.
Channel 2 and 3 analog outputs (DA2 and DA3) enabled.
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Section 19 D/A Converter
19.4
H8S/2456, H8S/2456R, H8S/2454 Group
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate
independently. When DAOE bit in DACR23 is set to 1, D/A conversion is enabled and the
conversion result is output. The following shows an example of D/A conversion on channel 2.
Figure 19.2 shows the timing of this operation.
1. Write the conversion data to DADR2.
2. Set the DAOE2 bit in DACR23 to 1. D/A conversion is started. The conversion result is output
from the analog output pin DA2 after the conversion time tDCONV has elapsed. The conversion
result is continued to output until DADR2 is written to again or the DAOE2 bit is cleared to 0.
The output value is expressed by the following formula:
DADR contents × Vref
256
3. If DADR2 is written to again, the conversion is immediately started. The conversion result is
output after the conversion time tDCONV has elapsed.
4. If the DAOE2 bit is cleared to 0, analog output is disabled.
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DADR2
write cycle
Section 19 D/A Converter
DADR2
write cycle
DACR23
write cycle
DACR23
write cycle
φ
Address
DADR2
Conversion data 1
Conversion data 2
DAOE2
DA2
Conversion
result 2
Conversion
result 1
High-impedance state
tDCONV
tDCONV
Legend:
tDCONV: D/A conversion time
Figure 19.2 Example of D/A Converter Operation
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Section 19 D/A Converter
19.5
Usage Notes
19.5.1
Module Stop Function Setting
H8S/2456, H8S/2456R, H8S/2454 Group
D/A converter operation can be disabled or enabled using the module stop control register. The
initial setting is for the D/A converter to be halted. Register access is enabled by clearing the
module stop state. For details, see section 24, Power-Down Modes.
19.5.2
D/A Output Hold Function in Software Standby Mode
If D/A conversion is enabled and this LSI enters software standby mode, D/A output is held and
analog power supply current remains at the same level during D/A conversion. When the analog
power supply current is required to go low in software standby mode, bits DAOE and DAE should
be cleared to 0, and D/A output should be disabled.
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Section 20 Synchronous Serial Communication Unit (SSU)
Section 20 Synchronous Serial Communication Unit (SSU)
This LSI has one channel of synchronous serial communication unit (SSU). The SSU has master
mode in which this LSI outputs clocks as a master device for synchronous serial communication
and slave mode in which clocks are input from an external device for synchronous serial
communication. Synchronous serial communication can be performed with devices having
different clock polarity and clock phase. Figure 20.1 is a block diagram of the SSU.
20.1
•
•
•
•
•
•
•
•
•
•
•
Features
Choice of SSU mode and clock synchronous mode
Choice of master mode and slave mode
Choice of standard mode and bidirectional mode
Synchronous serial communication with devices with different clock polarity and clock phase
Choice of 8/16/24/32-bit width of transmit/receive data
Full-duplex communication capability
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
Consecutive serial communication
Choice of LSB-first or MSB-first transfer
Choice of a clock source
Seven internal clocks (φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256) or an external clock
Five interrupt sources
Transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error
Module stop state can be set.
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Section 20 Synchronous Serial Communication Unit (SSU)
Module data bus
SSCRH
Bus interface
Figure 20.1 shows a block diagram of the SSU.
Internal data bus
SSTDR 0
SSRDR 0
SSCRL
OEI
SSTDR 1
SSRDR 1
SSMR
CEI
SSTDR 2
SSRDR 2
SSER
RXI
SSTDR 3
SSRDR 3
SSSR
TXI
Control circuit
TEI
Clock
Clock
selector
Shiftin
Shiftout
SSTRSR
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
Selector
SSI
[Legend]
SSCRH:
SSCRL:
SSCR2:
SSMR:
SSER:
SSSR:
SSTDR0 to SSTDR3:
SSRDR0 to SSRDR3:
SSTRSR:
SSO
SCS
SSCK (External clock)
SS control register H
SS control register L
SS control register 2
SS mode register
SS enable register
SS status register
SS transmit data registers 0 to 3
SS receive data registers 0 to 3
SS shift register
Figure 20.1 Block Diagram of SSU
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20.2
Section 20 Synchronous Serial Communication Unit (SSU)
Input/Output Pins
Table 20.1 shows the SSU pin configuration.
Table 20.1 Pin Configuration
Channel
Symbol
I/O
Function
0
SSCK0
I/O
SSU clock input/output
SSI0
I/O
SSU data input/output
SSO0
I/O
SSU data input/output
SCS0
I/O
SSU chip select input/output
Note:
*
Because channel numbers are omitted in later descriptions, these are shown SSCK,
SSI, SSO, and SCS.
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Section 20 Synchronous Serial Communication Unit (SSU)
20.3
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The SSU has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SS control register H_0 (SSCRH_0)
SS control register L_0 (SSCRL_0)
SS mode register_0 (SSMR_0)
SS enable register_0 (SSER_0)
SS status register_0 (SSSR_0)
SS control register 2_0 (SSCR2_0)
SS transmit data register 0_0 (SSTDR0_0)
SS transmit data register 1_0 (SSTDR1_0)
SS transmit data register 2_0 (SSTDR2_0)
SS transmit data register 3_0 (SSTDR3_0)
SS receive data register 0_0 (SSRDR0_0)
SS receive data register 1_0 (SSRDR1_0)
SS receive data register 2_0 (SSRDR2_0)
SS receive data register 3_0 (SSRDR3_0)
SS shift register_0 (SSTRSR_0)
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20.3.1
Section 20 Synchronous Serial Communication Unit (SSU)
SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSS
0
R/W
Master/Slave Device Select
Selects that this module is used in master mode or
slave mode. When master mode is selected, transfer
clocks are output from the SSCK pin. When the CE bit
in SSSR is set, this bit is automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
6
BIDE
0
R/W
Bidirectional Mode Enable
Selects that both serial data input pin and output pin are
used or one of them is used. However, transmission
and reception are not performed simultaneously when
bidirectional mode is selected. For details, section
20.4.3, Relationship between Data Input/Output Pins
and Shift Register.
0: Standard mode (two pins are used for data input and
output)
1: Bidirectional mode (one pin is used for data input and
output)
5
⎯
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
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Section 20 Synchronous Serial Communication Unit (SSU)
H8S/2456, H8S/2456R, H8S/2454 Group
Bit
Bit Name
Initial
Value
R/W
Description
4
SOL
0
R/W
Serial Data Output Value Select
The serial data output retains its level of the last bit
after completion of transmission. The output level
before or after transmission can be specified by setting
this bit. When specifying the output level, use the MOV
instruction after clearing the SOLP bit to 0. Since writing
to this bit during data transmission causes malfunctions,
this bit should not be changed.
0: Serial data output is changed to low.
1: Serial data output is changed to high.
3
SOLP
1
R/W
SOL Bit Write Protect
When changing the output level of serial data, set the
SOL bit to 1 or clear the SOL bit to 0 after clearing the
SOLP bit to 0 using the MOV instruction.
0: Output level can be changed by the SOL bit
1: Output level cannot be changed by the SOL bit. This
bit is always read as 1.
2
SCKS
0
R/W
SSCK Pin Select
Selects that the SSCK pin functions as a port or a serial
clock pin. When the SSCK pin is used as a serial clock
pin, this bit must be set to 1.
0: Functions as an I/O port.
1: Functions as a serial clock.
1
CSS1
0
R/W
SCS Pin Select
0
CSS0
0
R/W
Select that the SCS pin functions as a port or SCS input
or output. However, when MSS = 0, the SCS pin
functions as an input pin regardless of the CSS1 and
CSS0 settings.
00: I/O port
01: Function as SCS input
10: Function as SCS automatic input/output (function as
SCS input before and after transfer and output a
low level during transfer)
11: Function as SCS automatic output (outputs a high
level before and after transfer and outputs a low
level during transfer)
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20.3.2
Section 20 Synchronous Serial Communication Unit (SSU)
SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
6
SSUMS
0
R/W
Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
5
SRES
0
R/W
Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
4 to 2
⎯
All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
1
DATS1
0
R/W
Transmit/Receive Data Length Select
0
DATS0
0
R/W
Select serial data length.
00: 8 bits
01: 16 bits
10: 32 bits
11: 24 bits
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Section 20 Synchronous Serial Communication Unit (SSU)
20.3.3
H8S/2456, H8S/2456R, H8S/2454 Group
SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
6
CPOS
0
R/W
MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
mode
1: Low output in idle mode, and high output in active
mode
5
CPHS
0
R/W
4, 3
⎯
All 0
R/W
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Page 1110 of 1408
Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
Reserved
These bits are always read as 0. The write value should
always be 0.
Transfer Clock Rate Select
Select the transfer clock rate when an internal clock is
selected.
000: Reserved
100: φ/32
001: φ/4
101: φ/64
010: φ/8
110: φ/128
011: φ/16
111: φ/256
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20.3.4
Section 20 Synchronous Serial Communication Unit (SSU)
SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit
Bit Name
Initial
Value
R/W
Description
7
TE
0
R/W
Transmit Enable
6
RE
0
R/W
Receive Enable
When this bit is set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
5, 4
⎯
All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
3
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an RXI interrupt request and
an OEI interrupt request are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
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Section 20 Synchronous Serial Communication Unit (SSU)
20.3.5
H8S/2456, H8S/2456R, H8S/2454 Group
SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
6
ORER
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While
ORER = 1, consecutive serial reception cannot be
continued. Serial transmission cannot be continued,
either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
5, 4
⎯
All 0
R/W
3
TEND
1
R
Page 1112 of 1408
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit End
[Setting condition]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR
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Section 20 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
2
TDRE
1
R/W
1
RDRF
0
R/W
0
CE
0
R/W
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master device).
If the SCS pin level changes to 1 with SSUMS = 0
(SSU mode) and MSS = 0 (slave device), an
incomplete error occurs because it is determined that a
master device has terminated the transfer. Data
reception does not continue while the CE bit is set to 1.
Serial transmission also does not continue. Reset the
SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting condition]
• When a low level is input to the SCS pin in master
device (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave device (the MSS bit in SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1
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Section 20 Synchronous Serial Communication Unit (SSU)
20.3.6
H8S/2456, H8S/2456R, H8S/2454 Group
SS Control Register 2 (SSCR2)
SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS
pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of
the TEND bit.
Bit
Bit Name
Initial
Value
R/W
Description
7
SDOS
0
R/W
Serial Data Pin Open Drain Select
Selects whether the serial data output pin is used as a
CMOS or an NMOS open drain output. Pins to output
serial data differ according to the register setting. For
details, 20.4.3, Relationship between Data Input/Output
Pins and Shift Register.
0: CMOS output
1: NMOS open drain output
6
SSCKOS
0
R/W
SSCK Pin Open Drain Select
Selects whether the SSCK pin is used as a CMOS or
an NMOS open drain output.
0: CMOS output
1: NMOS open drain output
5
SCSOS
0
R/W
SCS Pin Open Drain Select
Selects whether the SCS pin is used as a CMOS or an
NMOS open drain output.
0: CMOS output
1: NMOS open drain output
4
TENDSTS 0
R/W
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
transmitted
1: Sets the TEND bit after the last bit is transmitted
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Section 20 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
SCSATS
0
R/W
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc
1: Min. values of tLEAD and tLAG are 3/2 × tSUcyc
2
SSODTS
0
R/W
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
1, 0
⎯
All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 20 Synchronous Serial Communication Unit (SSU)
20.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 24-bit data length is selected, SSTDR0, SSTDR1, and SSTDR2 are
valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Be sure not to access to
invalid SSTDRs.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Table 20.2 Correspondence Between DATS Bit Setting and SSTDR
DATS[1:0] (SSCRL[1:0])
SSTDR
00
0
Valid
Valid
Valid
Valid
1
Invalid
Valid
Valid
Valid
2
Invalid
Invalid
Valid
Valid
3
Invalid
Invalid
Valid
Invalid
Page 1116 of 1408
01
10
11 (Setting Invalid)
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20.3.8
Section 20 Synchronous Serial Communication Unit (SSU)
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 24-bit data length is selected, SSRDR0, SSRDR1, and SSRDR2 are
valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Be sure not to access to
invalid SSRDR.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR
function as a double buffer in this way, consecutive receive operations can be performed.
Read SSRDR after confirming that the RDRF bit in SSSR is set to 1.
SSRDR is a read-only register, therefore, cannot be written to by the CPU.
Table 20.3 Correspondence Between DATS Bit Setting and SSRDR
DATS[1:0] (SSCRL[1:0])
SSRDR
00
01
10
11 (Setting Invalid)
0
Valid
Valid
Valid
Valid
1
Invalid
Valid
Valid
Valid
2
Invalid
Invalid
Valid
Valid
3
Invalid
Invalid
Valid
Invalid
20.3.9
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR
contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB
first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to
perform serial data transmission.
In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB
(bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to
SSRDR. SSTRSR cannot be directly accessed by the CPU.
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Section 20 Synchronous Serial Communication Unit (SSU)
20.4
Operation
20.4.1
Transfer Clock
A transfer clock can be selected from eight internal clocks and an external clock. When using this
module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS
bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When
transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output
from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an
input pin.
20.4.2
Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of the
CPOS and CPHS bits in SSMR. Figure 20.2 shows the relationship. When SSUMS = 1, the CPHS
setting is invalid although the CPOS setting is valid.
Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data
is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the
LSB.
(1) When CPHS = 0
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 1
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 20.2 Relationship of Clock Phase, Polarity, and Data
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20.4.3
Section 20 Synchronous Serial Communication Unit (SSU)
Relationship between Data Input/Output Pins and Shift Register
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 20.3
shows the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 20.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 20.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 20.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 20.3 (5) and (6)).
(1) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 1, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSO
(2) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 0, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSI
SSI
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 1, and either TE or RE = 1
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 0, and either TE or RE = 1
SSCK
SSCK
Shift register
(SSTRSR)
SSO
Shift register
(SSTRSR)
(6) When SSUMS = 1 and MSS = 0
SSCK
SSCK
Shift register
(SSTRSR)
SSO
SSI
SSI
(5) When SSUMS = 1 and MSS = 1
SSO
SSO
SSI
Shift register
(SSTRSR)
SSO
SSI
Figure 20.3 Relationship between Data Input/Output Pins and the Shift Register
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Section 20 Synchronous Serial Communication Unit (SSU)
20.4.4
Communication Modes and Pin Functions
The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the
communication modes and register settings. When a pin is used as an input pin, clear the
corresponding bit in each data direction register (DDR) to 0. The relationship of communication
modes and input/output pin functions are shown in tables 20.4 to 20.6.
Table 20.4 Communication Modes and Pin States of SSI and SSO Pins
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
BIDE
MSS
TE
RE
SSI
SSO
0
0
0
0
1
⎯
Input
1
0
Output
⎯
1
Output
Input
1
SSU (bidirectional)
0
communication mode
1
0
1
Clock synchronous
1
communication mode
0
0
0
1
Input
⎯
1
0
⎯
Output
1
Input
Output
0
1
⎯
Input
1
0
⎯
Output
0
1
⎯
Input
1
0
⎯
Output
0
1
Input
⎯
0
⎯
Output
1
Input
Output
0
1
Input
⎯
1
0
⎯
Output
1
Input
Output
1
1
[Legend]
⎯:
Not used as SSU pin (can be used as I/O port)
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Section 20 Synchronous Serial Communication Unit (SSU)
Table 20.5 Communication Modes and Pin States of SSCK Pin
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
MSS
SCKS
SSCK
0
0
0
⎯
1
Input
0
⎯
1
Output
0
⎯
1
Input
0
⎯
1
Output
1
Clock synchronous
1
communication mode
0
1
[Legend]
⎯:
Not used as SSU pin
Table 20.6 Communication Modes and Pin States of SCS Pin
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
MSS
CSS1
CSS0
SCS
0
0
×
×
Input
1
0
0
⎯
0
1
Input
1
0
Automatic
input/output
Clock synchronous
1
communication mode
×
1
1
Output
×
×
⎯
[Legend]
×:
Don't care
⎯:
Not used as SSU pin
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Section 20 Synchronous Serial Communication Unit (SSU)
20.4.5
H8S/2456, H8S/2456R, H8S/2454 Group
SSU Mode
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1)
Initial Settings in SSU Mode
Figure 20.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1] When the pin is used as an input.
[2] Specify master/slave mode selection, bidirectional mode enable,
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
[1]
Clear a bit in DDR to 0
[2]
Specify MSS, BIDE, SOL, SCKS, CSS1,
and CSS0 bits in SSCRH
[3] Selects SSU mode and specify transmit/receive data length.
[3]
Clear SSUMS in SSCRL to 0 and
specify bits DATS1 and DATS0
[4] Specify MSB first/LSB first selection, clock polarity selection,
clock phase selection, and transfer clock rate selection.
[4]
Specify MLS, CPOS, CPHS, CKS2,
CKS1, and CKS0 bits in SSMR
[5] Enables/disables interrupt request to the CPU.
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS and SSODTS
bits in SSCR2
[5]
Specify TE, RE, TEIE, TIE, RIE,
and CEIE bits in SSER smulataneously
End
Figure 20.4 Example of Initial Settings in SSU Mode
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(2)
Section 20 Synchronous Serial Communication Unit (SSU)
Data Transmission
Figure 20.5 shows an example of transmission operation, and figure 20.6 shows a flowchart
example of data transmission.
When transmitting data, the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal
is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in
synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the
SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
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Section 20 Synchronous Serial Communication Unit (SSU)
1 frame
SCS
1 frame
SSCK
SSO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
7
SSTDR0
(LSB first transmission)
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SSTDR0
(MSB first transmission)
TDRE
TEND
LSI operation
User operation
TXI interrupt
generated
TEI interrupt
generated
TXI interrupt
generated
TEI interrupt
generated
Data written to SSTDR0
Data written to SSTDR0
Figure 20.5 (1) Example of Transmission Operation (SSU Mode)
When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
SSTDR1
SSO
(MSB first)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
2
Bit
1
Bit
0
SSTDR0
Bit
2
Bit
1
Bit
0
SSTDR0
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
SSTDR1
TDRE
TEND
LSI operation
User operation
TXI interrupt generated
TEI interrupt generated
Data written to SSTDR0 and SSTDR1
Figure 20.5 (2) Example of Transmission Operation (SSU Mode) When 16-bit data length is
selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
Page 1124 of 1408
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Section 20 Synchronous Serial Communication Unit (SSU)
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
Bit
1
SSO
(MSB first)
Bit
7
Bit
6
Bit
6
to
Bit
7
Bit
0
Bit
1
Bit
0
Bit
7
Bit
6
SSTDR2
Bit
1
to
to
Bit
6
Bit
7
Bit
0
Bit
1
Bit
0
Bit
7
Bit
6
SSTDR1
SSTDR0
to
to
Bit
6
Bit
7
Bit
1
Bit
0
SSTDR0
Bit
1
SSTDR1
to
SSTDR2
TDRE
TEND
TXI interrupt generated
LSI operation
User operation
TEI interrupt generated
Data written to SSTDR0, SSTDR1, and SSTDR2
Figure 20.5 (3) Example of Transmission Operation (SSU Mode) When 24-bit data length is
selected (SSTDR0, SSTDR1, and SSTDR2 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
SSO
(MSB first)
Bit
7
to
Bit
7
SSTDR3
to
Bit
0
SSTDR0
Bit
0
to
Bit
7
SSTDR2
Bit
7
to
Bit
0
SSTDR1
Bit
0
to
Bit
7
Bit
0
SSTDR1
Bit
7
to
Bit
0
SSTDR2
to
Bit
7
SSTDR0
Bit
7
to
Bit
0
SSTDR3
TDRE
TEND
LSI operation
User operation
TXI interrupt generated TEI interrupt generated
Data written to SSTDR0, SSTDR1, SSTDR2 and SSTDR3
Figure 20.5 (4) Example of Transmission Operation (SSU Mode)
When 32-bit data length is selected (SSTDR0, SSTDR1, SSTDR2 and SSTDR3 are valid)
with CPOS = 0 and CPHS = 0
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Section 20 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
TDRE = 1?
[1] Initial setting:
Specify the transmit data format.
No
Write transmit data to SSTDR
TDRE automatically cleared
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
Consecutive data transmission?
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
Yes
[3]
H8S/2456, H8S/2456R, H8S/2454 Group
Yes
No
Read TEND in SSSR
TEND = 1?
No
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
[4]
One bit time
quantum elapsed?
Yes
No
Clear TE in SSER to 0
End transmission
Note: Hatching boxes represent SSU internal operations.
Figure 20.6 Flowchart Example of Data Transmission (SSU Mode)
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(3)
Section 20 Synchronous Serial Communication Unit (SSU)
Data Reception
Figure 20.7 shows an example of reception operation, and figure 20.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
1 frame
SCS
1 frame
SSCK
SSI
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
7
SSRDR0
(LSB first transmission)
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SSRDR0
(MSB first transmission)
RDRF
REI interrupt
generated
LSI operation
User operation
Dummy-read SSRDR0
REI interrupt
generated
Read SSRDR0
Figure 20.7 (1) Example of Reception Operation (SSU Mode)
When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
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Section 20 Synchronous Serial Communication Unit (SSU)
1 frame
SCS
SSCK
SSI
(LSB first)
Bit
0
Bit
1
Bit
2
SSO
(MSB first)
Bit
7
Bit
6
Bit
5
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
2
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
3
SSRDR1
Bit
4
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
2
Bit
1
Bit
0
SSRDR0
SSRDR0
Bit
4
Bit
3
SSRDR1
RDRF
RXI interrupt
generated
LSI operation
User operation
Dummy-read SSRDR0 and SSRDR1
Figure 20.7 (2) Example of Reception Operation (SSU Mode) When 16-bit data length is
selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSI
(LSB first)
Bit
0
Bit
1
SSI
(MSB first)
Bit
7
Bit
6
to
Bit
6
Bit
7
Bit
0
Bit
1
Bit
0
Bit
7
Bit
6
SSRDR2
to
Bit
1
SSRDR0
to
Bit
6
Bit
7
Bit
0
Bit
1
Bit
0
Bit
7
Bit
6
SSRDR1
to
Bit
1
SSRDR1
to
Bit
6
Bit
7
SSRDR0
to
Bit
1
Bit
0
SSRDR2
RDRF
RXI interrupt
generated
LSI operation
User operation
Dummy-read SSRDR0,
SSRDR1, and SSRDR2
Figure 20.7 Example of Reception Operation (SSU Mode) When 24-bit data length is
selected (SSRDR0, SSRDR1, and SSRDR2 are valid) with CPOS = 0 and CPHS = 0 (3)
Page 1128 of 1408
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Section 20 Synchronous Serial Communication Unit (SSU)
1 frame
SCS
SSCK
SSI
(LSB first)
Bit
0
SSI
(MSB first)
Bit
7
to
Bit
7
SSRDR3
to
Bit
0
SSRDR0
Bit
0
to
Bit
7
Bit
0
SSRDR2
Bit
7
to
Bit
0
to
Bit
7
SSRDR1
Bit
7
SSRDR1
to
Bit
0
SSRDR2
Bit
0
to
Bit
7
SSRDR0
Bit
7
to
Bit
0
SSRDR3
RDRF
LSI operation
User operation
RXI interrupt
generated
Dummy-read SSRDR0, SSRDR1,
SSRDR2 and SSRDR3
Figure 20.7 Example of Reception Operation (SSU Mode)
When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2 and SSRDR3 are valid)
with CPOS = 0 and CPHS = 0 (4)
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Section 20 Synchronous Serial Communication Unit (SSU)
H8S/2456, H8S/2456R, H8S/2454 Group
Start
[1]
Initial setting
[2]
Dummy-read SSRDR
[1]
Initial setting:
Specify the receive data format.
[2]
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Yes
No
Consecutive data
reception?
Yes
[4]
[3]
[3], [6] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
[4]
To continue single reception:
When continuing single reception, wait for time of tSUcyc
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
[5]
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
No
Read received data in SSRDR
RDRF automatically cleared
[5]
RE = 0
Read receive data in SSRDR
End reception
[6]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 20.8 Flowchart Example of Data Reception (SSU Mode)
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(4)
Section 20 Synchronous Serial Communication Unit (SSU)
Data Transmission/Reception
Figure 20.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
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Section 20 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
[1] Initial setting:
Specify the transmit/receive data format.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
TDRE set to 1 to start transmission
Read SSSR
[3]
No
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
RDRF = 1?
Yes
Yes [4]
ORER = 1?
No
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Yes [5]
Read TEND in SSSR
No
TEND = 1?
Yes
Clear TEND in SSSR to 0
Error processing
No
Has the 1 bit transfer
period elapsed?
Yes
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 20.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
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Section 20 Synchronous Serial Communication Unit (SSU)
SCS Pin Control and Conflict Error
20.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect conflict error. The conflict
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
Data written
to SSTDR
CE
SCS output
(Hi-Z)
Conflict error
detection period
Maximum time for
internally clocking SCS
Figure 20.10 Conflict Error Detection Timing (Before Transfer)
φ
SCS
(Hi-Z)
MSS
Internal signal for
transfer enable
Transfer
end
CE
Conflict error detection period
Figure 20.11 Conflict Error Detection Timing (After Transfer End)
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Section 20 Synchronous Serial Communication Unit (SSU)
20.4.7
Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Initial Settings in Clock Synchronous Communication Mode
Figure 20.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1]
Clear a bit in DDR to 0
[2]
Specify MSS and SCKS in SSCRH
[3]
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
[4]
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
selection.
[3] Selects clock synchronous communication mode and
specify transmit/receive data length.
[4] Specify clock polarity selection and transfer clock rate
selection.
[5] Enables/disables interrupt request to the CPU.
Specify CPOS, CKS2, CKS1, and
CKS0 bits in SSMR
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS, and
SSODTS bits in SSCR2
[5]
Specify TE, RE, TEIE, TIE, RIE, and
CEIE bits in SSER simultaneously
End
Figure 20.12 Example of Initial Settings in Clock Synchronous Communication Mode
Page 1134 of 1408
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(2)
Section 20 Synchronous Serial Communication Unit (SSU)
Data Transmission
Figure 20.13 shows an example of transmission operation, and figure 20.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is
input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0.
SSCK
SSO
Bit 0
Bit 1
Bit 7
Bit 0
1 frame
Bit 1
Bit 7
1 frame
TDRE
TEND
LSI operation
User operation
TXI interrupt
generated
Data written
to SSTDR
TXI interrupt
generated
TEI interrupt
generated
Data written
to SSTDR
Figure 20.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)
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Page 1135 of 1408
Section 20 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
TDRE = 1?
[4][1] Initial setting:
Specify the transmit data format.
No
Write transmit data to SSTDR
TDRE automatically cleared
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
Consecutive data transmission?
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
Yes
[3]
H8S/2456, H8S/2456R, H8S/2454 Group
Yes
No
Read TEND in SSSR
TEND = 1?
No
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
[4]
One bit time
quantum elapsed?
Yes
No
Clear TE in SSER to 0
End transmission
Note: Hatching boxes represent SSU internal operations.
Figure 20.14 Flowchart Example of Transmission Operation
(Clock Synchronous Communication Mode)
Page 1136 of 1408
R01UH0309EJ0500 Rev. 5.00
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(3)
Section 20 Synchronous Serial Communication Unit (SSU)
Data Reception
Figure 20.15 shows an example of reception operation, and figure 20.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
SSCK
SSI
Bit 0
Bit 7
Bit 0
1 frame
Bit 7
Bit 0
Bit 7
1 frame
RDRF
LSI operation
RXI interrupt
generated
User operation Dummy-read SSRDR
RXI interrupt
generated
Read data from SSRDR
RXI interrupt
generated
Read data from SSRDR
Figure 20.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
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Page 1137 of 1408
Section 20 Synchronous Serial Communication Unit (SSU)
[1]
Start
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Initial setting:
Specify the receive data format.
[2], [4] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
Initial setting
[1]
H8S/2456, H8S/2456R, H8S/2454 Group
[3]
Yes [2]
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
No
Consecutive data reception?
No
Yes
Read received data in SSRDR
RDRF automatically cleared
[3]
RE = 0
Read receive data in SSRDR
End reception
[4]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 20.16 Flowchart Example of Data Reception
(Clock Synchronous Communication Mode)
Page 1138 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
(4)
Section 20 Synchronous Serial Communication Unit (SSU)
Data Transmission/Reception
Figure 20.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bits to 1.
R01UH0309EJ0500 Rev. 5.00
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Page 1139 of 1408
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Section 20 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
[1] Initial setting:
Specify the transmit/receive data format.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE bit
is automatically cleared to 0 and transmission is started
by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
TDRE automatically cleared
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Read SSSR
[3]
No
RDRF = 1?
Yes
ORER = 1?
Yes [4]
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
No
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Yes [5]
Read TEND in SSSR
No
TEND = 1?
Yes
Clear TEND in SSSR to 0
Has the 1 bit transfer
period elapsed?
Error processing
No
Yes
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 20.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode)
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20.5
Section 20 Synchronous Serial Communication Unit (SSU)
Interrupt Requests
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 20.7 lists the
interrupt sources.
When an interrupt condition shown in table 20.7 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DMAC data transfer.
Table 20.7 Interrupt Sources
DMAC
Activation
Channel Abbreviation Interrupt Source
Symbol Interrupt Condition
0
Overrun error
OEI0
(RIE = 1) • (ORER = 1)
⎯
Conflict error
CEI0
(CEIE = 1) • (CE = 1)
⎯
SSRXI0
Receive data register full
RXI0
(RIE = 1) • (RDRF = 1)
⎯
SSTXI0
Transmit data register empty
TXI0
(TIE = 1) • (TDRE = 1)
⎯
Transmit end
TEI0
(TEIE = 1) • (TEND = 1)
⎯
SSERI0
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Section 20 Synchronous Serial Communication Unit (SSU)
20.6
Usage Note
20.6.1
Module Stop Function Setting
H8S/2456, H8S/2456R, H8S/2454 Group
SSU operation can be disabled or enabled using the module stop control register. The initial
setting is for the SSU operation is to be halted. Register access is enabled by clearing the module
stop state. For details, see section 24, Power-Down Modes.
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Section 21 RAM
Section 21 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), see section 3.2.2, System
Control Register (SYSCR).
Product Type
H8S/24569
R4F24569
H8S/24569R
R4F24569R
H8S/24549
R4F24549
H8S/24568
R4F24568
H8S/24568R
R4F24568R
H8S/24565
R4F24565
H8S/24565R
R4F24565R
H8S/24548
R4F24548
H8S/24545
R4F24545
H8S/24562
R4S24562
H8S/24562R
R4S24562R
H8S/24542
R4S24542
H8S/24561
R4S24561
H8S/24561R
R4S24561R
H8S/24541
R4S24541
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ROM Type
RAM
Capacity
RAM Address
Flash memory version
64 Kbytes
H'FEC000 to H'FFBFFF
48 Kbytes
H'FF0000 to H'FFBFFF
64 Kbytes
H'FEC000 to H'FFBFFF
48 Kbytes
H'FF0000 to H'FFBFFF
ROM-less version
Page 1143 of 1408
Section 21 RAM
Page 1144 of 1408
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Section 22 Flash Memory
Section 22 Flash Memory
The flash memory in this LSI can be accessed in three programming modes: user programming
mode, boot mode, and programmer mode.
Table 22.1 gives an overview of the flash memory specifications (see section 1, Overview, for
items that are not shown in table 22.1).
Table 22.1 Overview of Flash Memory Specifications
Item
Description
Flash memory programming modes
Three modes (user programming mode, boot mode,
and programmer mode)
Erase block division
See figure 22.1.
User ROM
Data flash
Programming method
Word units*1
Erase method
Block units
Programming and erase control method
Programming and erasure are controlled by
software commands
Commands
Six commands
Programming and erase count
1,000 times/10,000 times*1*2
Data retention
Ten years
Notes: 1. The programming and erase count determine the number of times the erase operation
can be performed in each block.
For example, if 1-word programming is done 2,048 times, each at a different address in
a 4-Kbyte block and then the block is erased, this is counted as one erase count. If the
allowed programming and erase count are 1,000 times, each block can be erased
1,000 times.
2. 10,000 times for the data flash and 1,000 times for other blocks.
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Section 22 Flash Memory
Table 22.2 Overview of Flash Memory Programming Modes
On-board Programming Mode
Item
Functional
overview
Off-board Mode
User Programming
Mode
Boot Mode
The user ROM is
programmed by the CPU
through execution of
software commands.
The user ROM is programmed The user ROM is
through the on-chip SCI
programmed through a
interface.
dedicated parallel
programmer.
Standard serial I/O mode 1:
Programmer Mode
EW0 mode:
Clock-synchronous serial I/O
Programming can be
Standard serial I/O mode 2:
done from outside of the Asynchronous serial I/O
flash memory.
Programmable User ROM, data flash
area
User ROM, data flash
User ROM, data flash
Operating
mode
Single-chip mode, onchip ROM enabled
expanded mode (EW0
mode)
Boot mode
Programmer mode
ROM
programmer
⎯
⎯
Parallel programmer
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22.1
Section 22 Flash Memory
Memory Map
This ROM is divided into the user ROM and the data flash.
Figure 22.1 shows a block diagram of the flash memory.
The user ROM and data flash are divided into multiple blocks. The user ROM can be programmed
in user programming mode, boot mode, or programmer mode.
128-Kbyte version
256-Kbyte version
H'000000
Block 0: 64K
H'00FFFF
H'010000
Block 1: 64K
H'01FFFF
H'020000
User ROM
Block 2: 64K
H'02FFFF
H'030000
Block 3: 64K
H'03FFFF
H'F00000
H'F00FFF
H'F01000
H'F01FFF
Block A
Data flash
Block B
Notes: 1. To specify a block, use an even address in the block.
2. This is a block diagram in ROM-enabled mode.
Figure 22.1 Block Diagram of Flash Memory
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Section 22 Flash Memory
22.2
H8S/2456, H8S/2456R, H8S/2454 Group
Register Descriptions
The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory data block protect register (FLMDBPR)
• Flash memory status register (FLMSTR)
Note: When the FLSHE bit in SYSCR is 0, the read values are undefined and registers cannot be
modified.
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Section 22 Flash Memory
22.2.1
Flash Memory Control Register 1 (FLMCR1)
Bit
Bit Name
Initial
Value
R/W
7
⎯
0
⎯
Description
Reserved
The initial value should not be changed.
6
CBIDB
1
R/W
CPU Programming Mode Select
Setting this bit to 0 (CPU programming mode) enables
command acceptance.
0: CPU programming mode enabled
1: CPU programming mode disabled
5
⎯
0
⎯
Reserved
The initial value should not be changed.
4
⎯
0
⎯
Reserved
The initial value should not be changed.
3
⎯
0
⎯
Reserved
The initial value should not be changed.
2
⎯
1
⎯
Reserved
The initial value should not be changed.
1
⎯
0
⎯
Reserved
The initial value should not be changed.
0
FMCMDEN 0
R/W
Flash Memory Software Command Enable
Setting this bit to 1 (CPU programming mode) enables
command acceptance.
0: Flash memory software commands disabled
1: Flash memory software commands enabled
To set this bit to 1, be sure to write 0 and then write 1 in a
row.
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Section 22 Flash Memory
22.2.2
Flash Memory Data Block Protect Register (FLMDBPR)
Bit
Bit Name
Initial
Value
R/W
7
⎯
0
⎯
Description
Reserved
The initial value should not be changed.
⎯
6
0
⎯
Reserved
The initial value should not be changed.
5
⎯
0
⎯
4
⎯
0
⎯
Reserved
The initial value should not be changed.
Reserved
The initial value should not be changed.
⎯
3
0
⎯
Reserved
The initial value should not be changed.
⎯
2
0
⎯
Reserved
The initial value should not be changed.
⎯
1
0
⎯
Reserved
The initial value should not be changed.
0
FMDBPT0
0
R/W
Data Flash E/W Protect*
0: Data flash E/W disabled
1: Data flash E/W enabled
To clear this bit to 0, be sure to write 1 and then write 0 in
a row.
Note:
*
This bit is set to 1 simultaneously when the FMCMDEN bit in FLMCR1 is set to 1. To
clear this bit to 0, be sure to write 1 and then write 0 in a row.
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Section 22 Flash Memory
22.2.3
Flash Memory Status Register (FLMSTR)
Bit
Bit Name
Initial
Value
R/W
7
⎯
0
⎯
Description
Reserved
The initial value should not be changed.
⎯
6
0
⎯
Reserved
The initial value should not be changed.
5
FMERSF*
0
R
Erase or Blank Check Status Flag
0: Successfully completed
1: Ended with an error
⎯
4
0
⎯
Reserved
The initial value should not be changed.
3
FMPRSF*
0
R
Program Status Flag
0: Successfully completed
1: Ended with an error
⎯
2
0
⎯
Reserved
The initial value should not be changed.
1
⎯
1
⎯
0
FMRDY
1
R
Reserved
The initial value should not be set.
Flash Memory Ready/Busy Status
0: Busy (Interrupt processing or erasure is in progress.)
1: Ready
Note:
*
The FMERSF and FMPRSF bits are cleared to 0 by a clear status command.
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Section 22 Flash Memory
22.3
On-Board Programming Mode
When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset
start is executed, a transition is made to on-board programming mode in which the on-chip flash
memory can be programmed/erased. On-board programming mode has three operating modes:
SCI boot mode by P27 and P26 settings, USB boot mode, and user programming mode.
Table 22.3 shows the pin setting for each operating mode.
Table 22.3 On-Board Programming Mode Setting
Input clock frequencies
for oscillators
Mode Setting
EMLE MD2
MD1
MD0 P27
P26
SCI boot mode
0
0
1
1
0
0
0
1
1
0
1
16MHz
0
1
1
1
0
12 MHz
0
1
1
1
1
8 MHz
⎯
⎯
USB boot mode
User programming mode
Page 1152 of 1408
Single-chip mode,
on-chip ROM
enabled expanded
mode
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22.3.1
Section 22 Flash Memory
User Programming Mode
In the user programming mode, the flash memory can be programmed by the CPU through
execution of software commands. In this mode, the user ROM and data flash can be programmed
without using a ROM programmer with the microcomputer mounted on a system board.
The programming and block erase commands should be executed only in each block area of the
user ROM and data flash.
The user programming mode provides the erase/write 0 mode (EW0 mode). Table 22.4 gives an
overview of the EW0 mode specifications.
Table 22.4 EW0 Mode Specifications
Item
Description
Operating mode
•
Single-chip mode
•
On-chip ROM enabled expanded mode
Area for storing the programming User ROM
control program
Area for executing the
programming control program
The programming control program should be transferred to an
area outside the flash memory (such as RAM) before
execution*2
Programmable area
User ROM, data flash
Limitations on software
commands
None
Mode after programming or
erasure
Read status register mode
CPU state during automatic
programming or erasure
Operating*1
Flash memory status detection
•
Reading the FMPRSF and FMERSF bits in FLMSTR by a
program.
•
Executing a read status register command to read the SR7,
SR5, and SR4 bits in the status register.
Notes: 1. Make sure that no interrupt (except NMI) or DMA transfer is generated.
2. In the user programming mode, the programming control program should be executed
in the on-chip RAM or an external area.
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Section 22 Flash Memory
22.3.2
EW0 Mode
Setting the FMCMDEN bit in FLMCR1 to 1 shifts the flash memory into the user programming
mode, in which commands can be accepted. Figure 22.2 shows how to set and clear the EW0
mode.
Programming and erasure are controlled through software commands. The flash memory state
after programming or erasure can be checked through FLMSTR or the status register.
EW0 mode processing procedures
Programming control program*3
Single-chip mode or
on-chip ROM enabled expanded mode
Transfer the programming control program
to an area outside the flash memory. *3
Set the FLSHE in SYSCR.
Jump to the programming control program transferred
to an area outside the flash memory.
(The subsequent processing should be done by
the transferred programming control program.)
Notes: 1.
2.
3.
Write 0 to the FMCMDEN bit and then write 1
to it (user program mode enabled).*1
Clear CBIDB to 0.
Execute software commands.
Execute a read array command.*2
Write 1 to the CBIDB bit (user program mode
disabled).
Jump to a desired address in the flash memory.
To set the FMCMDEN bit to 1, write 0 to the bit and then write 1 to it in a row.
Write to the FMCMDEN bit from an area outside the on-chip flash memory.
After a read array command, disable user programming mode.
In user program mode, execute the programming control program in
the on-chip RAM or external area.
Figure 22.2 Setting and Clearing EW0 Mode
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22.4
Section 22 Flash Memory
Software Commands
The following describes the software commands. A command or data should be read or written in
16-bit units at an even address in the user ROM or data flash area. When a command code is
written, the lower eight bits (D7 to D0) are ignored.
Table 22.5 List of Software Commands
First Bus Cycle
Second Bus Cycle
Third Bus Cycle
Software
Command
Data
Data
Data
(D15 to
(D15 to
(D15 to
Mode Address D0)
Mode Address D0)
Mode Address D0)
Read array
Write
x
H'FFxx
Read status
register
Write
x
H'70xx
Clear status
register
Write
x
H'50xx
Program
Write
WA0
Block erase
Write
Block blank
check
Write
Read
x
SRD
H'41xx
Write
WA0
WD0
x
H'20xx
Write
BA
H'D0xx
x
H'25xx
Write
BA
H'D0xx
Write
WA1
WD1
[Legend]
SRD: Status register data (D7 to D0)
WA0: Address to write the lower word (the address for the first bus cycle must be the same even
address as that for the second bus cycle).
WA1: Address to write the upper word
WD0: Lower word of write data (16 bits)
WD1: Upper word of write data (16 bits)
BA:
Lowest address of the block (note that this should be an even address).
(i.e. H'0000 0000 for block 0, H'0001 0000 for block 1)
x:
A desired even address in user ROM, data flash, or user boot ROM.
xx:
Lower eight bits of command code (ignored)
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Section 22 Flash Memory
22.4.1
H8S/2456, H8S/2456R, H8S/2454 Group
Read Array
This command reads the flash memory.
Write H'FFxx in the first bus cycle to shift the flash memory into the read array mode. Specify the
target read address in the next bus cycle after setting the CBIDB bit in FLMCR1 to 1, and data is
read from the address in 16-bit units.
As the flash memory stays in the read array mode until another command is issued, multiple
addresses can be read in sequence.
22.4.2
Read Status Register
This command reads the status register.
Write H'70xx in the first bus cycle, and the status register can be read in the second bus cycle (see
section 22.5, Status Register). Specify an even address in the user ROM, data flash, or user boot
ROM to read the status register.
Do not issue this command in the EW1 mode.
22.4.3
Clear Status Register
This command clears the status register.
Write H'50xx in the first bus cycle, and the FMERSF and FMPRSF bits in FLMSTR are cleared to
0.
22.4.4
Program
This command writes data to the flash memory in 2-word units.
Write H'41xx in the first bus cycle and write data to the target address in the second and third bus
cycles; the flash memory starts automatic writing (programming and verifying data). The address
value specified in the first bus cycle should be the same even address as that specified in the
second bus cycle.
Completion of automatic writing can be checked through the FMRDY bit in FLMSTR. The
FMRDY bit is 0 (busy) during automatic writing and becomes 1 (ready) when writing is
completed.
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Section 22 Flash Memory
After automatic writing is completed, the result can be checked through the FMPRSF bit in
FMRSTR (see section 22.6, Full Status Check).
Once an address is programmed, no additional data can be written to the address. Figure 22.3
shows a flowchart of the program command processing.
In the EW0 mode, the read status register mode is entered as soon as automatic writing starts, and
the status register can be read. The SR7 bit in the status register becomes 0 when automatic
writing starts and returns to 1 when writing is completed. In this case, the flash memory stays in
the read status register mode until a read array command is issued. After automatic writing is
completed, the result of writing can be checked by reading the status register.
Start
Write command code "H'41xx"
to the target write address.
Write data to
the target write address.
FMRDY = 1?
NO
YES
Full status check
End of programming
Note: Write the command code and data to even addresses.
Figure 22.3 Flowchart of Program Command Processing
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Section 22 Flash Memory
22.4.5
H8S/2456, H8S/2456R, H8S/2454 Group
Block Erase
Write H'20xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the
target block in the second cycle; automatic erasure (erasing data and verifying the erased status)
starts in the specified block.
Completion of automatic erasure can be checked through the FMRDY bit in FLMSTR.
The FMRDY bit is 0 (busy) during automatic erasure and becomes 1 (ready) when erasure is
completed.
After automatic erasure is completed, the result can be checked through the FMERSF bit in
FLMSTR (see section 22.6, Full Status Check).
Figure 22.4 shows a flowchart of the block erase command processing.
In the EW0 mode, the read status register mode is entered as soon as automatic erasure starts, and
the status register can be read. The SR7 bit in the status register becomes 0 when automatic
erasure starts and returns to 1 when erasure is completed. In this case, the flash memory stays in
the read status register mode until a read array command is issued. If an erase error occurs, repeat
a sequence of the clear status register command to block erase command at least three times until
no erase error occurs.
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Section 22 Flash Memory
Start
Write command code "H'20xx"*1
Write "H'D0xx" to the lowest
address of the block.
NO
FMRDY = 1?
YES
Full status check *2*3
End of block erase
Notes:1. Write the command code and data to even addresses.
2. See figure 22.8.
3. If an erase error occurs, repeat a sequence of the clear
status register command -> block erase command at least
three times until no erase error occurs.
Figure 22.4 Flowchart of Block Erase Command Processing
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Section 22 Flash Memory
22.4.6
Block Blank Check
This command checks if a block is blank (the erased state).
Write H'25xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the
target block in the second cycle; the check result will be stored in the FMERSF bit in FLMSTR.
After the FMRDY bit in FLMSTR has become 1 (ready), read the FMERSF bit.
Figure 22.5 shows a flowchart of the block blank check command processing.
Start
Write command code "H'25xx".
Write "H'D0xx" to the lowest
address of the block.
NO
FMRDY = 1?
YES
FMERSF = 0?
NO
YES
Blank
Not blank
Note: Write the command code and data to even addresses.
Figure 22.5 Flowchart of Block Blank Check Command Processing
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22.5
Section 22 Flash Memory
Status Register
The status register indicates the state of flash memory operation and whether erasure or
programming has ended successfully or with an error. The status register contents can be read
through the FMRDY, FMPRSF, and FMERSF bits in FLMSTR.
Table 22.6 shows the status register.
In the EW0 mode, the status register can be read with the following timing.
• When a read status register command is issued and then an even address in the user ROM or
data flash is read
• When a program command, a block erase command, or a block blank check command is
issued and then an even address in the user ROM or data flash is read before a read array
command is issued
Table 22.6 Status Register
Status
Bits in Status
Register
Bits in
FMLSTR
Status Name
0
1
Value after
Reset
SR0 (D0)
⎯
Reserved
⎯
⎯
⎯
SR1 (D1)
⎯
Reserved
⎯
⎯
⎯
SR2 (D2)
⎯
Reserved
⎯
⎯
⎯
SR3 (D3)
⎯
Reserved
⎯
⎯
⎯
SR4 (D4)
FMPRSF
Programming
status
Completed
successfully
Ended with
error
0
SR5 (D5)
FMERSF
Erase status
Completed
successfully
Ended with
error
0
SR6 (D6)
⎯
Reserved
⎯
⎯
SR7 (D7)
FMRDY
Sequencer status Busy
Ready
1
[Legend]
SR0 to SR7: Status register data
D0 to D7:
Data bus from which the bit is read when a read status register command is issued.
Note: The FMERSF (SR5) and FMPRSF (SR4) bits are cleared to 0 by a clear status register
command.
When the FMERSF (SR5) or FMPRSF (SR4) bit is 1, the program, block erase, and block
blank check commands are not accepted.
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Section 22 Flash Memory
22.5.1
H8S/2456, H8S/2456R, H8S/2454 Group
Sequencer Status (FMRDY Bit)
The sequencer status bit indicates the state of flash memory operation. Its value is 0 during
execution of a program, block erase, or block blank check, and 1 in other cases.
22.5.2
Erase Status (FMERSF Bit)
See section 22.6, Full Status Check.
22.5.3
Programming Status (FMPRSF Bit)
See section 22.6, Full Status Check.
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22.6
Section 22 Flash Memory
Full Status Check
When an error occurs, the FMERSF or FMPRSF bit in FLMSTR becomes 1 to indicate
occurrence of the error. Read these status bits (full status check) to check the operation results.
Table 22.7 shows the errors and FLMSTR status and figure 22.6 shows a flowchart of full status
check processing and corrective actions for each error.
Table 22.7 Errors and Register Status
State of FLMSTR
(Status Register)
FMERSF Bit
(SR5)
FMPRSF Bit
(SR4)
1
1
1
0
0
Note:
1
*
Error
Error Conditions
Command
sequence error
•
When a command is not issued correctly
•
When an invalid value (a value other than
H'D0xx or H'FFxx) is written in the second
bus cycle of a block erase command*
Erase error
•
When a block erase command is issued but
the block is not erased correctly
•
When a block blank check command is
issued and the checked block is not blank
•
When a program command is issued but
automatic writing is not done correctly
Programming
error
When H'FFxx is written in the second bus cycle of this command, the flash memory
enters the read array mode and the command code written in the first bus cycle is
ignored.
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Section 22 Flash Memory
Full status check
FMPRSF = 1
and
FMERSF =1 ?
YES
Command sequence
error
. . . (1) Execute a clear status register command to clear the FMPRSF and
FMERSF bits to 0 (successfully completed state).
(2) Check if the command was input correctly, and execute it again.
NO
FMERSF = 0?
NO
Erase error
. . . (1) Execute a clear stats register command to clear the FMERSF bit
to 0 (successfully completed state).
(2) Execute a block erase command.
Repeat steps (1) and (2) at least three times until no block erase
error occurs.
Note: If an error still occurs, the block cannot be used.
Programming error
. . . [During program execution]
(1) Execute a clear stats register command to clear the FMPRSF bit
to 0 (successfully completed state).
(2) Execute a block erase command again.
Note: If an error still occurs, the block cannot be used.
YES
FMPRSF = 0?
NO
YES
End of
full status check
Note:
When either the FMPRSF or FMERSF bit is 1 (ended with error), the program, block erase, and block blank check
commands are not accepted. Execute a clear status register command and then execute a desired command again.
Figure 22.6 Flowchart of Full Status Check Processing and Corrective Actions
for Each Error
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22.7
Notes on User Programming Mode
22.7.1
Prohibited Interrupts (EW0 Mode)
Section 22 Flash Memory
The NMI and watchdog timer interrupts can be used because FLMCR1 is forcibly initialized when
an interrupt is generated; specify the destination address of each interrupt routine in the fixed
vector table. Flash memory programming is terminated when an NMI interrupt or a watchdog
timer interrupt occurs. In this case, reexecute the programming program after the interrupt routine
is completed.
22.7.2
Access Method
To set the FMCMDEN bit to 1, be sure to write 0 to the bit and then write 1 in a row. Make sure
that no interrupt, EXDMAC transfer, DTC transfer, or DMA transfer is generated between writing
0 and 1.
22.7.3
Programming (EW0 Mode)
If the power-supply voltage falls during programming of the block that stores the programming
control program, the programming control program cannot be correctly modified and the flash
memory may not be programmed after that. In this case, use the boot mode or programmer mode
instead.
22.7.4
Writing Commands or Data
The address to write a command code should be H'0, H'4, H'8, or H'C.
22.7.5
Software Standby Mode
Before entering the stop mode, set the FMCMDEN bit to 0 (CPU programming mode disabled),
disable the DMA transfer, and then make a transition to the software standby mode.
22.8
Boot Mode
Setting the mode pins to mode 3 and resetting the hardware shifts the flash memory into boot
mode. In this mode, the embedded standard program is executed.
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Section 22 Flash Memory
22.9
SCI Boot Mode
SCI boot mode executes programming/erasing of the user ROM by means of the control command
and program data transmitted from the externally connected host via the on-chip SCI_1.
In SCI boot mode, the tool for transmitting the control command and program data, and the
program data must be prepared in the host. The serial communication mode is set to asynchronous
mode. The system configuration in SCI boot mode is shown in figure 22.7. Interrupts are ignored
in SCI boot mode. Configure the user system so that interrupts do not occur.
This LSI P27 and P26
MD2 to MD0
Host
Programming
tool and program
data
Software for
analyzing
control
commands
(on-chip)
Flash
memory
RxD1
SCI_1
TxD1
On-chip
RAM
00
011
Control command,
program data
Response
Figure 22.7 System Configuration in SCI Boot Mode
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22.10
Section 22 Flash Memory
USB Boot Mode
USB boot mode executes programming/erasing of the user ROM by means of the control
command and program data transmitted from the externally connected host via the USB.
In USB boot mode, the tool for transmitting the control command and program data, and the
program data must be prepared in the host. The system configuration in USB boot mode is shown
in figure 22.8. Interrupts are ignored in USB boot mode. Configure the user system so that
interrupts do not occur.
Host or
self-power HUB
This LSI
P27 and P26
MD2 to MD0
P20
Software for
analyzing
control
commands
(on-chip)
01, 10, 11 (depending on the
input frequency)
011
Flash
memory
1.5 kΩ
Programming tool
and program data
Rs
USB+
Rs
USBUSB
Data transmission/
reception
On-chip
RAM
VBUS
P17
0: Self power setting
1: Bus power setting
Figure 22.8 System Configuration in USB Boot Mode
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Section 22 Flash Memory
(1)
Features
• Bus power mode and self-power mode are selectable.
• The P20 pin supports the D+ pull-up control connection.
• For enumeration information, refer to table 22.8.
Table 22.8 Enumeration Information
USB standard
Ver.2.0 (Full speed)
Transfer mode
Transfer mode Control (in, out), Bulk (in, out)
Maximum power consumption
For self power mode (P17 = 0)
100 mA
For bus power mode (P17 = 1)
500 mA
Endpoint configuration
EP0 Control (in out) 16 bytes
Configuration 1
InterfaceNumber0
AlternateSetting0
EP1 Bulk (out) 64 bytes
EP2 Bulk (in) 64 bytes
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(2)
Section 22 Flash Memory
State Transition Diagram
The state transition after USB boot mode is initiated is shown in figure 22.9.
Boot mode initiation
(reset by boot mode)
Enumeration
H'55
1.
n
eptio
rec
Inquiry command reception
2.
Wait for inquiry
setting command
Processing of inquiry
setting command
Inquiry command response
3.
4.
All user ROM erasure
Read/check command reception
Wait for inquiry
programming/erasing
command
Processing of
read/check command
Command response
(Er
com asure
sur
s
ma
e co
nd electio
mp
rec
letio
ept n
n)
ion
)
(Era
(Program selection
command reception)
(Programming
completion)
Wait for erasure block data
(Program data transmission)
Wait for program data
Figure 22.9 USB Boot Mode State Transition Diagram
1. After a transition to the USB boot mode is made, the boot program embedded in this LSI is
initialized. This LSI performs enumeration to the host after the USB boot program is
initialized.
2. Inquiry information about the size, configuration, start address, and support status of the user
ROM is transmitted to the host.
3. After inquiries have finished, all user ROMs are automatically erased.
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Section 22 Flash Memory
4.
(3)
H8S/2456, H8S/2456R, H8S/2454 Group
After all user ROMs are automatically erased, the state of waiting for programming/erasing
command is entered. When the programming command is received, the state shifts to the state
of waiting for programming data. The same applies to erasing. In addition to the commands
for programming/erasing, there are commands for performing sum check, blank check
(erasure check), and memory read of the user ROM, and acquiring the current status
information.
Notes on USB Boot Mode Execution
• The clock of 48 MHz needs to be supplied to the USB module. Set the external clock
frequency and clock pulse generator so as to supply 48 MHz as the clock for the USB (cku).
For details, refer to section 23, Clock Pulse Generator.
• Use the P20 pin for the D+ pull-up control connection.
• For the stable supply of the power during the flash memory programming and erasing, the
cable should not be connected via the bus powered HUB.
• If the bus powered HUB is disconnected during the flash memory programming and erasing,
permanent damage to the LSI may result.
• If the USB bus in the bus power mode enters the suspend mode, this does not make the
transition to the software standby mode of the power-down mode.
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22.11
Section 22 Flash Memory
Serial Communication Interface Specification for Boot Mode
Initiating boot mode enables the boot program to communicate with the host by using the on-chip
SCI_1. The serial communication interface specification is shown below.
(1)
Status
The boot program has three states.
1. Bit-Rate-Adjustment State
In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot
mode enables starting of the boot program and entry to the bit-rate-adjustment state. The
program receives the command from the host to adjust the bit rate. After adjusting the bit rate,
the program enters the inquiry/selection state.
2. Inquiry/Selection State
In this state, the boot program responds to inquiry commands from the host. The device name,
clock mode, and bit rate are selected. After selection of these settings, the program is made to
enter the programming/erasing state by the command for a transition to the
programming/erasing state. The program transfers the libraries required for erasure to the
RAM and erases the user ROMs before the transition.
3. Programming/erasing state
Programming and erasure by the boot program take place in this state. The boot program is
made to transfer the programming/erasing programs to the RAM by commands from the host.
Sum checks and blank checks are executed by sending these commands from the host.
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Section 22 Flash Memory
These boot program states are shown in figure 22.10.
Reset
Bit-rate-adjustment
state
Inquiry/response
wait
Response
Inquiry
Operations for
inquiry and selection
Transition to
programming/erasing
Operations for
response
Operations for erasing
user MATs
Programming/erasing
wait
Programming
Operations for
programming
Erasing
Operations for
erasing
Checking
Operations for
checking
Figure 22.10 Boot Program States
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(2)
Section 22 Flash Memory
Bit-Rate-Adjustment State
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment
sequence is shown in figure 22.11.
Host
Boot Program
H'00 (30 times maximum)
Measuring the
1-bit length
H'00 (Completion of adjustment)
H'55
H'E6 (Boot response)
H'FF (error)
Figure 22.11 Bit-Rate-Adjustment Sequence
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Section 22 Flash Memory
(3)
H8S/2456, H8S/2456R, H8S/2454 Group
Communications Protocol
After adjustment of the bit rate, the protocol for communications between the host and the boot
program is as shown below.
1. One-byte commands and one-byte responses
These commands and responses are comprised of a single byte. These are consists of the
inquiries and the ACK for successful completion.
2. n-byte commands or n-byte responses
These commands and responses are comprised of n bytes of data. These are selections and
responses to inquiries.
The amount of programming data is not included under this heading because it is determined
in another command.
3. Error response
The error response is a response to inquiries. It consists of an error response and an error code
and comes two bytes.
4. Programming of 128 bytes
The size is not specified in commands. The size of n is indicated in response to the
programming unit inquiry.
5. Memory read response
This response consists of 4 bytes of data.
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One-byte command
or one-byte response
Section 22 Flash Memory
Command or response
n-byte Command or
n-byte response
Data
Size
Checksum
Command or response
Error response
Error code
Error response
128-byte programming
Address
Data (n bytes)
Command
Memory read
response
Size
Checksum
Data
Response
Checksum
Figure 22.12 Communication Protocol Format
• Command (1 byte): Commands including inquiries, selection, programming, erasing, and
checking
• Response (1 byte): Response to an inquiry
• Size (1 byte): The amount of data for transmission excluding the command, data, and
checksum
• Data (n bytes): Detailed data of a command or response
• Checksum (1 byte): The checksum is calculated so that the total of all values from the
command byte to the SUM byte becomes H'00.
• Error response (1 byte): Error response to a command
• Error code (1 byte): Type of the error
• Address (4 bytes): Address for programming
• Data (n bytes): Data to be programmed (the size is indicated in the response to the
programming unit inquiry.)
• Size (4 bytes): 4-byte response to a memory read
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Section 22 Flash Memory
(4)
Inquiry/Selection State
The boot program returns information from the flash memory in response to the host’s inquiry
commands and sets the device code, clock mode, and bit rate in response to the host’s selection
command.
Inquiry and selection commands are listed below.
Table 22.9 Inquiry and Selection Commands
Command
Command Name
Description
H'20
Supported Device Inquiry
Inquiry regarding device codes and product
name
H'10
Device Selection
Selection of device code
H'21
Clock Mode Inquiry
Inquiry regarding numbers of clock modes and
values of each mode
H'11
Clock Mode Selection
Indication of the selected clock mode
H'22
Multiplication Ratio Inquiry
Inquiry regarding the number of frequencymultiplied clock types, the number of
multiplication ratios, and the values of each
multiple
H'23
Operating Clock Frequency
Inquiry
Inquiry regarding the maximum and minimum
values of the main clock and peripheral clocks
H'25
User ROM Information Inquiry
Inquiry regarding the number of user ROMs
and the start and last addresses of each ROM
H'26
Erased Block Information
Inquiry
Inquiry regarding the number of blocks and the
start and last addresses of each block
H'27
Programming Unit Inquiry
Inquiry regarding the unit of programming data
H'3F
New Bit Rate Selection
Selection of new bit rate
H'40
Transition to
Programming/Erasing State
Erasing of user ROM and entry to
programming/erasing state
H'4F
Boot Program Status Inquiry
Inquiry regarding the operated status of the
boot program
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Section 22 Flash Memory
The selection commands, which are device selection (H'10), clock mode selection (H'11), and new
bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly
be needed. When two or more selection commands are sent at once, the last command will be
valid.
All of these commands, except for the boot program status inquiry command (H'4F), will be valid
until the boot program receives the programming/erasing transition command (H'40). The host can
choose the needed commands out of the commands and inquiries listed above. The boot program
status inquiry command (H'4F) is valid even after the boot program has received the
programming/erasing transition command (H'40).
(a)
Supported Device Inquiry
The boot program will return the device codes of supported devices and the product name in
response to the supported device inquiry.
Command
H'20
• Command, H'20, (1 byte): Inquiry regarding supported devices
Response
H'30
Size
Number of
characters
Device code
Number of devices
Product name
···
SUM
• Response, H'30, (1 byte): Response to the supported device inquiry
• Size (1 byte): Number of bytes to be transmitted, excluding the command, size, and checksum,
that is, the amount of data contributes by the number of devices, characters, device codes and
product names
• Number of devices (1 byte): The number of device types supported by the boot program
• Number of characters (1 byte): The number of characters in the device codes and boot
program's name
• Device code (4 bytes): ASCII code of the supporting product
• Product name (n bytes): Type name of the boot program in ASCII-coded characters
• SUM (1 byte): Checksum
The checksum is calculated so that the total of all values from the command byte to the SUM
byte becomes H'00.
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Section 22 Flash Memory
(b)
Device Selection
The boot program will set the supported device to the specified device code. The program will
return the selected device code in response to the inquiry after this setting has been made.
Command
H'10
Size
Device code
SUM
• Command, H'10, (1 byte): Device selection
• Size (1 byte): Amount of device-code data
This is fixed at 2.
• Device code (4 bytes): Device code (ASCII code) returned in response to the supported device
inquiry
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to the device selection command
ACK will be returned when the device code matches.
Error response
H'90
ERROR
• Error response, H'90, (1 byte): Error response to the device selection command
ERROR: (1 byte): Error code
H'11: Sum check error
H'21: Device code mismatch error, that is, the device code does not match
(c)
Clock Mode Inquiry
The boot program will return the supported clock modes in response to the clock mode inquiry.
Command
H'21
• Command, H'21, (1 byte): Inquiry regarding clock mode
Response
•
•
•
•
H'31
Size
Mode
···
SUM
Response, H'31, (1 byte): Response to the clock-mode inquiry
Size (1 byte): Amount of data that represents modes
Mode (1 byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.)
SUM (1 byte): Checksum
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(d)
Section 22 Flash Memory
Clock Mode Selection
The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made.
The clock-mode selection command should be sent after the device-selection commands.
Command
H'11
Size
Mode
SUM
• Command, H'11, (1 byte): Selection of clock mode
• Size (1 byte): Amount of data that represents the modes
This is fixed at 1.
• Mode (1 byte): A clock mode returned in reply to the supported clock mode inquiry.
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to the clock mode selection command
ACK will be returned when the clock mode matches.
Error Response
H'91
ERROR
• Error response, H'91, (1 byte): Error response to the clock mode selection command
• ERROR, (1 byte): Error code
H'11: Sum check error
H'22: Clock mode mismatch error, that is, the clock mode does not match.
Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must
be selected using these respective values.
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Section 22 Flash Memory
(e)
Multiplication Ratio Inquiry
The boot program will return the supported multiplication and division ratios.
Command
H'22
• Command, H'22, (1 byte): Inquiry regarding multiplication ratio
Response
H'32
Size
Number of
Multiplicamultiplication ratios tion ratio
Number
of types
···
···
SUM
• Response, H'32, (1 byte): Response to the multiplication ratio inquiry
• Size (1 byte): The amount of data that represents the number of clock types and multiplication
ratios and the multiplication ratios
• Number of types (1 byte): The number of supported multiplied clock types
(e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the
number of types will be H'02.)
• Number of multiplication ratios (1 byte): The number of multiplication ratios for each type
(e.g. the number of multiplication ratios to which the main clock can be set and the peripheral
clock can be set.)
• Multiplication ratio (1 byte)
Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency
multiplier is four, the value of multiplication ratio will be H'04.)
Division ratio: The number of multiplication ratios returned is the same as the number of
multiplication ratios and as many groups of data are returned as there are types.
• SUM (1 byte): Checksum
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(f)
Section 22 Flash Memory
Operating Clock Frequency Inquiry
The boot program will return the number of operating clock frequencies, and the maximum and
minimum values.
Command
H'23
• Command, H'23, (1 byte): Inquiry regarding operating clock frequencies
Response
H'33
Size
Number of operating clock
frequencies
Minimum value of operating Maximum value of operating clock
clock frequency
frequency
···
SUM
• Response, H'33, (1 byte): Response to operating clock frequency inquiry
• Size (1 byte): The number of bytes that represents the minimum values, maximum values, and
the number of frequencies.
• Number of operating clock frequencies (1 byte): The number of supported operating clock
frequency types
(e.g. when there are two operating clock frequency types, which are the main and peripheral
clocks, the number of types will be H'02.)
• Minimum value of operating clock frequency (2 bytes): The minimum value of the multiplied
or divided clock frequency.
The minimum and maximum values represent the values in MHz, valid to the hundredths place
of MHz, and multiplied by 100 (e.g. when the value is 64 MHz, it will be 6400 and H'1900).
• Maximum value (2 bytes): Maximum value of the multiplied or divided clock frequencies.
There are as many pairs of minimum and maximum values as there are operating clock
frequency.
• SUM (1 byte): Checksum
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Section 22 Flash Memory
(g)
User ROM Information Inquiry
The boot program will return the number of user ROMs and their addresses.
Command
H'25
• Command, H'25, (1 byte): Inquiry regarding user ROM information
Response
H'35
Size
Number of areas
Area-start address
Area-last address
···
SUM
• Response, H'35, (1 byte): Response to the user ROM information inquiry
• Size (1 byte): The number of bytes that represents the number of areas, area-start address, and
area-last address
• Number of areas (1 byte): The number of consecutive user ROM areas
When the user ROM areas are consecutive, the number of areas returned is H'01.
• Area-start address (4 bytes): Start address of the area
• Area-last address (4 bytes): Last address of the area
There are as many groups of data representing the start and last addresses as there are areas.
• SUM (1 byte): Checksum
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(h)
Section 22 Flash Memory
Erased Block Information Inquiry
The boot program will return the number of erased blocks and their addresses.
Command
H'26
• Command, H'26, (1 byte): Inquiry regarding erased block information
Response
H'36
Size
Number of blocks
Block-start address
Block-last address
···
SUM
• Response, H'36, (1 byte): Response to the number of erased blocks and addresses
• Size (2 bytes): The number of bytes that represents the number of blocks, block-start
addresses, and block-last addresses.
• Number of blocks (1 byte): The number of erased blocks
• Block-start address (4 bytes): Start address of a block
• Block-last Address (4 bytes): Last address of a block
There are as many groups of data representing the start and last addresses as there are blocks.
• SUM (1 byte): Checksum
(i)
Programming Unit Inquiry
The boot program will return the programming unit used to program data.
Command
H'27
• Command, H'27, (1 byte): Inquiry regarding programming unit
Response
H'37
Size
Programming unit
SUM
• Response, H'37, (1 byte): Response to programming unit inquiry
• Size (1 byte): The number of bytes that indicate the programming unit, which is fixed to 2
• Programming unit (2 bytes): A unit for programming
This is the unit for reception of programming data.
• SUM (1 byte): Checksum
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Section 22 Flash Memory
(j)
New Bit-Rate Selection
The boot program will set a new bit rate and return the new bit rate.
This selection should be sent after sending the clock mode selection command.
Command
H'3F
Size
Bit rate
Number of
multiplication ratios
Multiplication
ratio 1
Multiplication
ratio 2
Input frequency
SUM
• Command, H'3F, (1 byte): Selection of new bit rate
• Size (1 byte): The number of bytes that represents the bit rate, input frequency, number of
multiplication ratios, and multiplication ratio
• Bit rate (2 bytes): New bit rate
One hundredth of the value (e.g. when the value is 19,200 bps, the bit rate is H'00C0, which is
192.)
• Input frequency (2 bytes): Frequency of the clock input to the boot program
This is valid to the hundredths place and represents the value in MHz multiplied by 100 (e.g.
when the value is 64 MHz, the input frequency is H'1900 (= 6400)).
• Number of multiplication ratios (1 byte): The number of multiplication ratios to which the
device can be set.
• Multiplication ratio 1 (1 byte): The value of multiplication or division ratios for the main
operating frequency
Multiplication ratio (1 byte): The value of the multiplication ratio (e.g. when the clock
frequency is multiplied by four, the multiplication ratio will be H'04.)
Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock
frequency is divided by two, the value of division ratio will be H'FE. H'FE = [-2])
• Multiplication ratio 2 (1 byte): The value of multiplication or division ratios for the peripheral
frequency
Multiplication ratio (1 byte): The value of the multiplication ratio (e.g. when the clock
frequency is multiplied by four, the multiplication ratio will be H'04.)
(Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock is
divided by two, the value of division ratio will be H'FE. H'FE = [-2])
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• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to selection of a new bit rate
When it is possible to set the bit rate, the response will be ACK.
Error Response
H'BF
ERROR
• Error response, H'BF, (1 byte): Error response to selection of new bit rate
• ERROR: (1 byte): Error code
H'11: Sum check error
H'24: Bit-rate selection disable error
The rate is not available.
H'25: Input frequency error
This input frequency is not within the specified range.
H'26: Multiplication-ratio error
The ratio does not match an available ratio.
H'27: Operating frequency error
The frequency is not within the specified range.
(5)
Received Data Check
The methods for checking of received data are listed below.
1. Input frequency
The received value of the input frequency is checked to ensure that it is within the range of
minimum to maximum frequencies which matches the clock modes of the specified device. When
the value is out of this range, an input-frequency error is generated.
2. Multiplication ratio
The received value of the multiplication ratio or division ratio is checked to ensure that it matches
a multiplication or division ratio for the clock modes of the specified device. When the value is
out of this range, an input-frequency error is generated.
3. Operating frequency error
The operating frequency is calculated from the received value of the input frequency and the
multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at
the operating frequency. The expression is given below.
Operating frequency = Input frequency × Multiplication ratio, or
Operating frequency = Input frequency ÷ Division ratio
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The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
4. Bit rate
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR),
and the value (N) in the bit rate register (BRR), which are found from the peripheral operating
clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than
4%. If the error is 4% or more, a bit rate error is generated. The error is calculated using the
following expression:
Error (%) = {[
φ × 106
(N + 1) × B × 64 × 2(2×n − 1)
] − 1} × 100
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation
H'06
• Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response
H'06
• Response, H'06, (1 byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 22.13.
Boot program
Host
Setting a new bit rate
Waiting for one-bit period
at the specified bit rate
H'06 (ACK)
Setting a new bit rate
Setting a new bit rate
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Figure 22.13 New Bit-Rate Selection Sequence
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Section 22 Flash Memory
Transition to Programming/Erasing State
The boot program will transfer the erasing program, and erase data of the user ROMs. On
completion of this erasure, ACK will be returned and the programming/erasing state will be
entered.
The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the
transition to programming/erasing state. These procedures should be carried out before sending of
the programming selection command or program data.
Command
H'40
• Command, H'40, (1 byte): Transition to programming/erasing state
Response
H'06
• Response, H'06, (1 byte): Response to transition to programming/erasing state
The boot program will send ACK when the user ROM has been erased by the transferred
erasing program.
Error Response
•
H'C0
H'51
Error code, H'51, (1 byte): Erasure error
An error occurred and erasure was not completed.
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(7)
Command Error
A command error will occur when a command is undefined, the order of commands is incorrect,
or a command is unacceptable. Issuing a clock-mode selection command before a device selection
or an inquiry command after the transition to programming/erasing state command, are examples.
Error Response
H'80
H'xx
• Error response, H'80, (1 byte): Command error
• Command, H'xx, (1 byte): Received command
(8)
Command Order
The order for commands in the inquiry/selection state is shown below.
1. A supported device inquiry (H'20) should be made to inquire about the supported devices.
2. The device should be selected from among those described by the returned information and set
with a device-selection (H'10) command.
3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes.
4. The clock mode should be selected from among those described by the returned information
and set.
5. After selection of the device and clock mode, inquiries for other required information should
be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23),
which are needed for a new bit-rate selection.
6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according
to the returned information on multiplication ratios and operating frequencies.
7. After selection of the device and clock mode, inquiries for the information of
programming/erasing to the user ROM should be made by the user ROMs information inquiry
(H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27).
8. After making inquiries and selecting a new bit rate, issue the transition to
programming/erasing state command (H'40). The boot program will then enter the
programming/erasing state.
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Section 22 Flash Memory
Programming/Erasing State
A programming selection command makes the boot program select the programming method, an
128-byte programming command makes it program the memory with data, and an erasing
selection command and block erasing command make it erase the block. The programming/
erasing commands are listed below.
Table 22.10 Programming/Erasing Commands
Command
Command Name
Description
H'43
User-program programming
selection
Transfers the user ROM programming
program
H'50
128-byte programming
Programs 128 bytes of data
H'48
Erasure selection
Transfers the erasing program
H'58
Block erasure
Erases a block of data
H'52
Memory read
Reads the contents of memory
H'4B
User ROM sum check
Executes sum checking of the user ROM area
H'61
Data flash sum check
Executes sum checking of the data flash area
H'4D
User ROM blank check
Executes blank checking of the user ROM
area
H'62
Data flash blank check
Executes blank checking of the data flash area
H'4F
Boot program status inquiry
Inquires into the boot program's status
• Programming
Programming is executed by a programming-selection command and a 128-byte programming
command.
Firstly, the host should send the programming-selection command and select the programming
method and programming ROMs. The programming selection command is user ROM
programming selection, regardless of the area and method for programming.
After issuing the programming selection command, the host should send the 128-byte
programming command. The 128-byte programming command that follows the selection
command represents the data programmed according to the method specified by the selection
command. When more than 128-byte data is programmed, 128-byte commands should repeatedly
be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will
stop the programming. On completion of programming, the boot program will wait for selection of
programming or erasing.
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Section 22 Flash Memory
Where the sequence of programming operations that is executed includes programming with
another method or of another ROM, the procedure must be repeated from the programming
selection command.
The sequence for programming-selection and 128-byte programming commands is shown in
figure 22.14.
Host
Boot program
Programming selection (H'42, H'43, H'44)
Transfer of the
programming
program
ACK
128-byte programming (address, data)
Repeat
Programming
ACK
128-byte programming (H'FFFFFFFF)
ACK
Figure 22.14 Programming Sequence
(a)
User-Program Programming Selection
The boot program will transfer a program for programming. The data is programmed to the user
ROMs by the transferred program for programming.
Command
H'43
• Command, H'43, (1 byte): User-program programming selection
Response
H'06
• Response, H'06, (1 byte): Response to user-program programming selection
When the programming program has been transferred, the boot program will return ACK.
Error response
H'C3
ERROR
• Error response, H'C3, (1 byte): Error response for user-program programming selection
• ERROR: (1 byte): Error code
H'54: Selection processing error (transfer error occurs and processing is not completed)
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(b)
Section 22 Flash Memory
128-Byte Programming
The boot program will use the programming program transferred by the programming selection to
program the user ROMs in response to 128-byte programming.
Command
H'50
Address
Data
···
···
SUM
• Command, H'50, (1 byte): 128-byte programming
• Programming address (4 bytes): Start address for programming
Multiple of the size specified in response to the programming unit inquiry
(i.e. H'00, H'01, H'00, H'00: H'0001 0000)
• Programming data (128 bytes): Data to be programmed
The size is specified in the response to the programming unit inquiry.
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to 128-byte programming
On completion of programming, the boot program will return ACK.
Error Response
H'D0
ERROR
• Error response, H'D0, (1 byte): Error response for 128-byte programming
• ERROR: (1 byte): Error code
H'11: Sum check error
H'2A: Address error
The address is not within the specified ROM.
H'53: Programming error
A programming error has occurred and programming cannot be continued.
The specified address should match the unit for programming of data. For example, when the
programming is in 128-byte units, the lower byte of the address should be H'00 or H'80.
When there are less than 128 bytes of data to be programmed, the host should fill the rest with
H'FF.
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Section 22 Flash Memory
(c)
Programming End
Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the
programming operation. The boot program will interpret this as the end of the programming and
wait for selection of programming or erasing.
Command
H'50
Address
SUM
• Command, H'50, (1 byte): 128-byte programming
• Programming address (4 bytes): End code is H'FF, H'FF, H'FF, H'FF.
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to 128-byte programming
On completion of programming, the boot program will return ACK.
Error Response
H'D0
ERROR
• Error Response, H'D0, (1 byte): Error response for 128-byte programming
• ERROR: (1 byte): Error code
H'11: Sum check error
H'53: Programming error
An error has occurred in programming and programming cannot be continued.
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Section 22 Flash Memory
(10) Erasure
Erasure is performed with the erasure selection and block erasure command.
Firstly, erasure is selected by the erasure selection command and the boot program then erases the
specified block. The command should be repeatedly executed if two or more blocks are to be
erased. Sending a block-erasure command from the host with the block number H'FF will stop the
erasure operating. On completion of erasing, the boot program will wait for selection of
programming or erasing.
The sequences of the issuing of erasure selection commands and the erasure of data are shown in
figure 22.15.
Host
Boot program
Preparation for erasure (H'48)
Transfer of erasure
program
ACK
Repeat
Erasure (Erasure block number)
Erasure
ACK
Erasure (H'FF)
ACK
Figure 22.15 Erasure Sequence
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Section 22 Flash Memory
(a)
Erasure Selection
The boot program will transfer the erasure program. User ROM data is erased by the transferred
erasure program.
Command
H'48
• Command, H'48, (1 byte): Erasure selection
Response
H'06
• Response, H'06, (1 byte): Response for erasure selection
After the erasure program has been transferred, the boot program will return ACK.
Error response
H'C8
ERROR
• Error response, H'C8, (1 byte): Response to erasure selection
• ERROR (1 byte): Error code
H'54:
Selection processing error (transfer error occurs and processing is not completed)
(b)
Block Erasure
The boot program will erase the contents of the specified block.
Command
H'58
Size
Block number
SUM
• Command, H'58, (1 byte): Block erasure
• Size (1 byte): The number of bytes that represents the erasure block number
This is fixed to 1.
• Block number (1 byte): Number of the block to be erased
• SUM (1 byte): Checksum
Response
H'06
• Response, H'06, (1 byte): Response to Erasure
After erasure has been completed, the boot program will return ACK.
Error Response
H'D8
ERROR
• Error Response, H'D8, (1 byte): Response to block erasure
• ERROR (1 byte): Error code
H'11: Sum check error
H'29: Block number error
Block number is incorrect.
H'51: Erasure error
An error has occurred during erasure.
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Section 22 Flash Memory
(11) Memory Read
The boot program will return the data stored in the specified address in response to a memory read
command.
Command
H'52
Size
Area
Read size
Read address
SUM
• Command, H'52, (1 byte): Memory read
• Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9)
• Area (1 byte):
H'01: User ROM area
An address error occurs when the area setting is incorrect.
• Read address (4 bytes): Start address to be read from
• Read size (4 bytes): Size of data to be read
• SUM (1 byte): Checksum
Response
H'52
Read size
Data
…
SUM
•
•
•
•
Response H'52 (1 byte): Response to memory read
Read size (4 bytes): Size of data to be read
Data (n bytes): Data for the read size from the read address
SUM (1 byte): Checksum
Error response
H'D2
ERROR
• Error response: H'D2 (1 byte): Error response to memory read
• ERROR: (1 byte): Error code
H'11: Sum check error
H'2A: Address error
The read address is not in the ROM.
H'2B: Data size error
The read size is greater than the size of the ROM.
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(12) User ROM Sum Check
The boot program will add all the data bytes in the user ROM area and return the result in
response to a user ROM sum check command.
Command
H'4B
• Command, H'4B, (1 byte): Sum check for user ROM
Response
H'5B
Size
Checksum of user ROM
SUM
• Response, H'5B, (1 byte): Response to the user ROM sum check
• Size (1 byte): The number of bytes that represents the checksum
This is fixed to 4.
• Checksum of user ROM (4 bytes): Result of checksum calculation for the user ROM area; the
total of all the data in the ROM, in byte units.
• SUM (1 byte): Sum check for data being transmitted
(13) Data Flash Sum Check
The boot program will add all the data bytes in the data flash area and return the result in response
to a data flash sum check command.
Command
H'61
• Command, H'61, (1 byte): Sum check for data flash
Response
H'71
Size
Checksum of data flash
SUM
• Response, H'71, (1 byte): Response to the data flash sum check
• Size (1 byte): The number of bytes that represents the checksum
This is fixed to 4.
• Checksum of data flash (4 bytes): Result of checksum calculation for the data flash area; the
total of all the data in the data flash, in byte units.
• SUM (1 byte): Checksum value that makes the sum of the bytes from the command to the
SUM byte become H'00.
(14) User ROM Blank Check
The boot program will check to see if the whole user ROM area is blank and return the result in
response to a user ROM blank check command.
Command
H'4D
• Command, H'4D, (1 byte): Blank check for user ROM
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Response
Section 22 Flash Memory
H'06
• Response, H'06, (1 byte): Response to the user ROM blank check
If all user ROM areas are blank (H'FF), the boot program will return ACK.
Error response
H'CD
H'52
• Error response, H'CD, (1 byte): Error response to blank check for user ROM
• Error code, H'52, (1 byte): Erasure incomplete error
(15) Data Flash Blank Check
The boot program will check to see if the whole data flash area is blank and return the result in
response to a data flash blank check command.
Command
H'62
• Command, H'62, (1 byte): Blank check for data flash
Response
H'06
• Response, H'06, (1 byte): Response to the data flash blank check
If all data flash areas are blank (H'FF), the boot program will return ACK.
Error response
H'E2
H'52
• Error response, H'E2, (1 byte): Error response to blank check for data flash
• Error code, H'52, (1 byte): Erasure incomplete error
(16) Boot Program Status Inquiry
The boot program will return indications of its present state and error condition in response to a
boot program status inquiry command. This inquiry can be made in the inquiry/selection state or
the programming/erasing state.
Command
H'4F
• Command, H'4F, (1 byte): Inquiry regarding boot program states
Response
H'5F
Size
STATUS ERROR
SUM
• Response, H'5F, (1 byte): Response to the boot program state inquiry
• Size (1 byte): The number of bytes. This is fixed to 2.
• STATUS (1 byte): State of the boot program
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Table 22.11 Status Code
Code
Description
H'11
Device selection wait
H'12
Clock mode selection wait
H'13
Bit rate selection wait
H'1F
Programming/erasing state transition wait (Bit rate selection is completed)
H'31
Programming state for erasure
H'3F
Programming/erasing selection wait (erasure completed)
H'4F
Programming data transmit wait (programming completed)
H'5F
Erasure block specification wait (erasure completed)
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Section 22 Flash Memory
• ERROR (1 byte): Error status
ERROR = 0 indicates normal operation.
ERROR = 1 indicates error has occurred.
Table 22.12 Error Code
Code
Description
H'00
No error
H'11
Sum check error
H'12
Program size error
H'21
Device code mismatch error
H'22
Clock mode mismatch error
H'24
Bit-rate selection disable error
H'25
Input frequency error
H'26
Multiplication ratio error
H'27
Operating frequency error
H'29
Block number error
H'2A
Address error
H'2B
Data size error
H'51
Erasure error
H'52
Erasure incomplete error
H'53
Programming error
H'54
Selection processing error
H'80
Command error
H'FF
Bit-rate-adjustment confirmation error
• SUM (1 byte): Sum check
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22.12
H8S/2456, H8S/2456R, H8S/2454 Group
Programmer Mode
Along with the on-board programming mode, this LSI also has a programmer mode as a further
mode for the writing and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer can be used to freely write programs to the on-chip ROM.
Program/erase is possible on the user ROM. The PROM programmer must support Renesas
microcomputers with 256-Kbyte flash memory as a device type.
A status-polling system is adopted for operation in automatic program, automatic erase, and
status-read modes. In the status-read mode, details of the system's internal signals are output after
execution of automatic programming or automatic erasure. In the PROM mode, provide a 12-MHz
input-clock signal.
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Section 23 Clock Pulse Generator
Section 23 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and
internal clocks. The clock pulse generator consists of an oscillator circuit, a system-clock PLL
circuit and a divider.
Figure 23.1 shows a block diagram of the clock pulse generator.
PLLCR
STC0, STC1
EXTAL
Oscillator
XTAL
System-clock
PLL circuit
(×1, 2)
Divider
USPLLCR
USSTC0, USSTC1
PLL circuit
for USB
(×3, 4, 6)
System clock
to φ pin
Internal clock
to peripheral
modules
USB dedicated clock to USB
[Legend]
PLLCR: PLL control register
USPLLCR: PLL control register for USB
Figure 23.1 Block Diagram of Clock Pulse Generator
The frequency of the system clock from the oscillator can be changed by means of the systemclock PLL circuit and divider. Frequency changes are made by software by means of settings in
the PLL control register (PLLCR).
The USB module requires a 48-MHz clock. Set the frequency of the USB dedicated clock (cku toe
48 MHz. Changes to the frequency of the USB dedicated clock are made by software by means of
settings in the USB PLL control register (USPLLCR).
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Section 23 Clock Pulse Generator
23.1
Register Descriptions
The clock pulse generator has the following registers.
• System clock control register (SCKCR)
• PLL control register (PLLCR)
• USB PLL control register (USPLLCR)
23.1.1
System Clock Control Register (SCKCR)
SCKCR controls φ clock output and selects operation when the PLLCR register setting is changed.
Bit
Bit Name
Initial Value
R/W
7
PSTOP
0
R/W
Description
φ Clock Output Disable
Controls φ output.
Normal Operation
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
All module clock stop mode
0: φ output
1: Fixed high
6
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
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Section 23 Clock Pulse Generator
Bit
Bit Name
Initial Value
R/W
Description
5
SDPSTP*
0
R/W
SDRAMφ Output Disable
Controls SDRAMφ.
0: SDRMφ output.
1: Can be used as PH1/CS5/RAS5.
When the SDRAMφ output is selected, the pin
functions as follows in each power-down mode.
Normal operation: SDRAMφ output
Sleep mode: SDRAMφ output
Software standby mode: Fixed at a low level
Hardware standby mode: High-impedance state
All module clock stop mode: SDRAMφ output
4
⎯
0
⎯
Reserved
This bit is always read as 0 and cannot be
modified.
3
STCS
0
R/W
Frequency Multiplication Factor Switching Mode
Select
Selects the operation when the PLLCR register
setting is changed.
0: Specified multiplication factor is valid after
transition to software standby mode.
1: Specified multiplication factor is valid
immediately after STC1 and STC0 bits are
rewritten.
2
⎯
0
R/W
Reserved
1
⎯
0
R/W
0
⎯
0
R/W
This bit can be read from or written to. However,
the write value should always be 0.
Note:
*
The H8S/2456 Group and H8S/2454 Group do not have this bit. The pin always
functions as an I/O port regardless of this bit setting.
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Section 23 Clock Pulse Generator
23.1.2
PLL Control Register (PLLCR)
PLLCR sets the frequency multiplication factor used by the system-clock PLL circuit.
Care must be taken when writing to this register. For details, see section 23.3, System-Clock PLL
Circuit and Divider.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
3
⎯
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
2
⎯
0
⎯
Reserved
This bit is always read as 0 and cannot be
modified.
1
STC1
0
R/W
0
STC0
0
R/W
Frequency Multiplication Factor for SystemClock PLL Circuit and System Clock Divider
Setting
The STC bits specify the frequency
multiplication factor and dividing ratio with
respect to the oscillator frequency.
00: × 1
01: × 2
10: Setting prohibited
11: divided by 2
Page 1204 of 1408
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23.1.3
Section 23 Clock Pulse Generator
USB PLL Control Register (USPLLCR)
USPLLCR selects multiplication factor used by the PLL circuit.
Bit
Bit Name
Initial Value
R/W
Description
7 to 2
⎯
All 0
⎯
Reserved
These bits are always read as 0 and cannot be
modified.
1
USSTC1
0
R/W
0
USSTC0
0
R/W
Frequency Multiplication Factor for USB PLL
Circuit Setting
The USSTC bits specify the frequency
multiplication factor for USB PLL circuit.
00: USB PLL circuit operation halted
01: USB PLL in operation with frequency × 3
10: USB PLL in operation with frequency × 4
11: USB PLL in operation with frequency × 6
R01UH0309EJ0500 Rev. 5.00
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Section 23 Clock Pulse Generator
23.2
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
23.2.1
Connecting a Crystal Resonator
A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping
resistance Rd according to table 23.1. When a crystal resonator is used, the range of its frequencies
is from 8 to 20 MHz.
Figure 23.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has
the characteristics shown in table 23.2.
CL1
EXTAL
XTAL
Rd
CL2
CL1 = CL2 = 10 to 22 pF
Figure 23.2 Connection of Crystal Resonator (Example)
Table 23.1 Damping Resistance Value
Frequency (MHz)
8
12
16
20
Rd (Ω)
200
0
0
0
CL
L
Rs
XTAL
EXTAL
C0
Figure 23.3 Crystal Resonator Equivalent Circuit
Page 1206 of 1408
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Section 23 Clock Pulse Generator
Table 23.2 Crystal Resonator Characteristics
Frequency (MHz)
8
12
16
20
RS max (Ω)
80
60
50
40
C0 max (pF)
7
7
7
7
23.2.2
External Clock Input
An external clock signal can be input as shown in the examples in figure 23.4. If the XTAL pin is
left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is
input to the XTAL pin, make sure that the external clock is held high in standby mode.
Table 23.3 shows the input conditions for the external clock. When an external clock is used, the
range of its frequencies is from 8 to 20 MHz.
EXTAL
XTAL
External clock input
Open state
(a) XTAL pin left open
EXTAL
External clock input
XTAL
(b) Counter clock input at XTAL pin
Figure 23.4 Connection of External Clock Input (Examples)
R01UH0309EJ0500 Rev. 5.00
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Section 23 Clock Pulse Generator
Table 23.3 External Clock Input Conditions
Vcc = 3.0 V to 3.6 V
Item
Symbol
Min
Max
Unit
Test Conditions
External clock input
low pulse width
tEXL
20
⎯
ns
Figure 23.5
External clock input
high pulse width
tEXH
20
⎯
ns
External clock rise time
tEXr
⎯
5
ns
External clock fall time
tEXf
⎯
5
ns
Clock low pulse width
tCL
0.4
0.6
tcyc
Clock high pulse width
tCH
0.4
0.6
tcyc
tEXH
tEXL
EXTAL
VCC × 0.5
tEXr
tEXf
Figure 23.5 External Clock Input Timing
Page 1208 of 1408
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23.3
Section 23 Clock Pulse Generator
System-Clock PLL Circuit and Divider
The system-clock PLL circuit and divider have the function of multiplying the frequency of the
clock from the oscillator by a factor of 1, 2, or dividing by 2. The system clock frequency is set
with the STC1 and STC0 bits in PLLCR. The phase of the rising edge of the internal clock is
controlled so as to match that of the rising edge of the EXTAL pin.
When the frequency is changed with the system-clock PLL circuit and divider, the operation
varies according to the setting of the STCS bit in SCKCR.
When STCS = 0, the setting of the changed frequency becomes valid after a transition to software
standby mode. The transition time count is performed in accordance with the setting of bits STS3
to STS0 in SBYCR. For details on SBYCR, see section 24.1.1, Standby Control Register
(SBYCR).
1. The initial PLL circuit multiplication factor is 1.
2. A value is set in bits STS3 to STS0 to give the specified transition time.
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
mode.
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
setting in STS3 to STS0.
6. After the set transition time has elapsed, this LSI resumes operation using the target
multiplication factor.
When STCS = 1, a change to the frequency setting becomes effective a maximum of four cycles
after the setting is changed. If the clock frequency is changed during access to an external address
space, correct operation cannot be guaranteed. Therefore, be sure to store instructions that change
the STC1 and STC0 bits and other instructions to be executed within a maximum of four cycles
after the change to the frequency setting in on-chip ROM or on-chip RAM, so that instructions do
not access an external address space before the frequency clock is switched over.
R01UH0309EJ0500 Rev. 5.00
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Section 23 Clock Pulse Generator
23.4
PLL Circuit for the USB Module
The PLL circuit for the USB module takes 8, 12, and 16 MHz clock signals from an oscillator and
generates the 48-MHz clock for the USB module through frequency-multiplication by 3, 4, or 6.
The frequency-multiplication factor is set by bits USSTC1 and USSTC0 in the USPLLCR. For
details on the USPLLCR, see section 23.1.3, USB PLL Control Register (USPLLCR).
When the USB is in use, make settings so that the system clock runs at or above 14 MHz. The
settings listed below (table 23.4) produce a USB dedicated clock at 48 MHz. Operation at other
frequencies cannot be guaranteed.
Table 23.4 Clock Selection when the USB is to be used
Input clock frequency
from the oscillator (MHz)
USB dedicated clock
(cku: 48 MHz)
System clock (φ)
8 MHz
EXTAL × 6
EXTAL × 2 (16MHz)
12 MHz
EXTAL × 4
EXTAL × 2 (24MHz)
16 MHz
EXTAL × 3
EXTAL × 2 (32MHz)
EXTAL × 1 (16MHz)
Page 1210 of 1408
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23.5
Usage Notes
23.5.1
Notes on Clock Pulse Generator
Section 23 Clock Pulse Generator
1. The following points should be noted since the frequency of φ changes according to the
settings of PLLCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of the Electrical Characteristics. In other words, φ must be set to
a value between 8 MHz (minimum) and 33 MHz (maximum). The setting of φ must not be less
than 8 MHz or greater than 33 MHz.
2. All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode in section 24.2.3, Software Standby Mode, for details.
3. Note that the frequency of φ will be changed when setting PLLCR while executing the external
bus cycle with the write-data-buffer function.
23.5.2
Notes on Resonator
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user's part, using the resonator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
floating capacitance of the resonator and the user board, the parameters should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the resonator pin.
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Section 23 Clock Pulse Generator
23.5.3
Notes on Board Design
When using the crystal resonator, place the crystal resonator and its load capacitors as close as
possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the
oscillation circuit to prevent induction from interfering with correct oscillation. See figure 23.6.
Prohibited
Signal A Signal B
This LSI
CL2
XTAL
EXTAL
CL1
Figure 23.6 Note on Board Design for Oscillation Circuit
Figure 23.7 shows the external circuitry recommended for the PLL circuit. Separate PLLVcc and
PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert
bypass capacitors CPB and CB close to the pins.
PLLVCC
CPB: 0.1 µF*
PLLVSS
VCC
CB: 0.1 µF*
VSS
Note: * CB and CPB are laminated ceramic capacitors.
Figure 23.7 Recommended External Circuitry for PLL Circuit
Page 1212 of 1408
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Section 24 Power-Down Modes
Section 24 Power-Down Modes
In addition to the normal program execution state, this LSI has power-down modes in which
operation of the CPU and oscillator is halted and power consumption is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and
so on.
This LSI's operating modes are high-speed mode and six power down modes:
•
•
•
•
•
•
Clock division mode
Sleep mode
Module stop function
All module clocks stop mode
Software standby mode
Hardware standby mode
Sleep mode is a CPU state, clock division mode is an on-chip peripheral function (including bus
masters and the CPU) state, and module stop function is an on-chip peripheral function (including
bus masters other than the CPU) state. A combination of these modes can be set.
After a reset, this LSI is in high-speed mode.
Table 24.1 shows the internal states of this LSI in each mode. Figure 24.1 shows the mode
transition diagram.
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Section 24 Power-Down Modes
Table 24.1 Operating Modes and Internal states of the LSI
Operating State
High
Speed
Mode
Clock
Division
Mode
Sleep
Mode
Module
Stop
Function
All Module Software
Clocks Stop Standby
Mode
Mode
Hardware
Standby
Mode
Clock pulse generator
Operating
Operating
Operating
Operating
Operating
Stopped
Stopped
CPU
Instruction
execution
Operating
Operating
Stopped
Operating
Stopped
Stopped
Stopped
Retained
Undefined
External
interrupts
NMI
Operating
Operating
Operating
Operating
Operating
Operating
Stopped
Peripheral WDT
functions
Operating
Operating
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Reset)
TMR
Operating
Operating
Operating
Stopped
(Retained)
Operating/
Stopped
2
(Retained)*
Stopped
(Retained)
Stopped
(Reset)
3
EXDMAC* Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
DMAC
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
DTC
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
TPU
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
PPG
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
D/A
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
A/D
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
SCI
Operating
Operating
Operating
4
Stopped*
(Reset/
retained)
4
Stopped*
(Reset/
retained)
4
Stopped*
(Reset/
retained)
Stopped
(Reset)
IIC2
Operating
Operating
Operating
Stopped*
(Reset/
retained)
5
Stopped*
(Reset/
retained)
Stopped*
(Reset/
retained)
Stopped
(Reset)
SSU
Operating
Operating
Operating
Stopped
(Reset)
Stopped
(Reset)
Stopped
(Reset)
Stopped
(Reset)
USB
Operating
Operating
Operating
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Retained)
Stopped
(Reset)
Register
Retained
IRQ0 to
1
15*
Page 1214 of 1408
5
5
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Operating State
Peripheral RAM
functions
I/O
Notes:
1.
2.
3.
4.
5.
6.
Section 24 Power-Down Modes
High
Speed
Mode
Clock
Division
Mode
Sleep
Mode
Module
Stop
Function
All Module Software
Clocks Stop Standby
Mode
Mode
Hardware
Standby
Mode
Operating
Operating
Operating
Stopped
(Retained)
Operating/
Stopped
6
(Retained)*
Retained
Retained
Operating
Operating
Operating
Operating
Retained
Retained
High
impedance
Stopped (Retained) in the table means that internal register values are retained and
internal operations are suspended.
Stopped (Reset) in the table means that internal register values and internal states are
initialized.
In module stop function, only modules for which a stop setting has been made are
stopped (reset or retained).
IRQ8 to IRQ15 are not supported by the H8S/2454 Group.
The active or stopped state can be selected by means of the MSTP0 bit in MSTPCR.
Not supported by the H8S/2454 Group.
TDR, SSR, and RDR are stopped (reset) and other registers are stopped (retained).
BC2 to BC0 are stopped (reset) and other registers are stopped (retained).
The active or stopped state can be selected by means of the bits in RMMSTPCR.
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Section 24 Power-Down Modes
STBY pin = low
Reset state
STBY pin = high
RES pin = low
Hardware
standby mode
RES pin = high
SSBY = 0
SLEEP
instruction
High-speed mode
(Internal clock is PLL
circuit output clock)
STC1,
STC0 ≠ 11
STC1,
STC0 = 11
Clock division
mode
SLEEP
instruction
MSTPCR =
H'FFFF (H'FFFE),
EXMSTPCR = H'FFFF,
SSBY = 0
Interrupt*1
All
module-clocks-stop
mode
Any interrupt
SLEEP
instruction
External
interrupt*2
Program execution state
: Transition after exception handling
Sleep mode
SSBY = 1
Software
standby mode
Program-halted state
: Power- down mode
From any state, a transition to hardware standby mode occurs when STBY is driven low.
From any state except hardware standby mode, a transition to the reset state occurs
when RES is driven low.
1. NMI, IRQ0 to IRQ15*3, 8-bit timer interrupts, watchdog timer interrupts.
(8-bit timer interrupts are valid when MSTP0 = 0.)
2. NMI, IRQ0 to IRQ15*3, and resume
(IRQ0 to IRQ15*3 are valid when the corresponding bit in SSIER is 1.)
3. IRQ8 to IRQ15 are not supported by the H8S/2454 group.
Notes: •
•
Figure 24.1 Mode Transitions
Page 1216 of 1408
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24.1
Section 24 Power-Down Modes
Register Descriptions
The registers relating to the power-down mode are shown below. For details on the PLL control
register (PLLCR), see section 23.1.2, PLL Control Register (PLLCR).
•
•
•
•
•
•
•
•
PLL control register (PLLCR)
Standby control register (SBYCR)
Module stop control register H (MSTPCRH)
Module stop control register L (MSTPCRL)
Extension module stop control register H (EXMSTPCRH)
Extension module stop control register L (EXMSTPCRL)
RAM module stop control register H (RMMSTPCRH)
RAM module stop control register L (RMMSTPCRL)
24.1.1
Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit
7
Bit Name
SSBY
Initial Value
0
R/W
Description
R/W
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP
instruction is executed
1: Shifts to software standby mode after the
SLEEP instruction is executed
This bit does not change from 1 when clearing the
software standby mode by using external
interrupts and shifting to normal operation. This bit
should be written 0 when clearing.
6
OPE
1
R/W
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS, LCAS) is retained or set to the
high-impedance state in software standby mode.
0: In software standby mode, address bus and bus
control signals are high-impedance
1: In software standby mode, address bus and bus
control signals retain output state
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Section 24 Power-Down Modes
Bit
Bit Name
Initial Value
R/W
Description
5
⎯
0
⎯
Reserved
This bit is always read as 0. The initial value
should not be changed.
4
⎯
0
⎯
Reserved
This bit is always read as 0. The write value
should always be 0.
3
STS3
1
R/W
Standby Timer Select 3 to 0
2
STS2
1
R/W
1
STS1
1
R/W
0
STS0
1
R/W
These bits select the time the MCU waits for the
clock to stabilize when software standby mode is
cleared by an external interrupt. With crystal
oscillation, see table 24.2 and make a selection
according to the operating frequency so that the
standby time is at least the oscillation stabilization
time. With an external clock, a PLL circuit
stabilization time is necessary. See table 24.2 to
set the standby time. When DRAM is used and
self-refreshing in the software standby state is
selected, note that the DRAM’s tRAS (self-refresh
RAS pulse width) specification must be satisfied.
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: Setting prohibited
0100: Setting prohibited
0101: Standby time = 64 states
0110: Standby time = 512 states
0111: Standby time = 1024 states
1000: Standby time = 2048 states
1001: Standby time = 4096 states
1010: Standby time = 16384 states
1011: Standby time = 32768 states
1100: Standby time = 65536 states
1101: Standby time = 131072 states
1110: Standby time = 262144 states
1111: Standby time = 524288 states
Page 1218 of 1408
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24.1.2
Section 24 Power-Down Modes
Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCR performs module stop state control. Setting a bit to 1, the corresponding module enters
the module stop state, while clearing the bit to 0 clears the module stop state.
• MSTPCRH
Bit
Bit Name
Initial Value
R/W
Module
15
ACSE
0
R/W
All Module Clocks Stop Mode Enable
Enables or disables all module clocks stop mode,
in which, when the CPU executes a SLEEP
instruction after the module stop state has been
set for all the on-chip peripheral functions
controlled by MSTPCR and EXMSTPCR or the
on-chip peripheral functions except the TMR.
0: All module clocks stop mode disabled
14
MSTP14
0
R/W
1: All module clocks stop mode enabled
EXDMA controller (EXDMAC)*
13
MSTP13
0
R/W
DMA controller (DMAC)
12
MSTP12
0
R/W
Data transfer controller (DTC)
11
MSTP11
1
R/W
16-bit timer pulse unit 0 (TPU_0)
10
MSTP10
1
R/W
Programmable pulse generator (PPG)
9
MSTP9
1
R/W
16-bit timer pulse unit 1 (TPU_1)
8
MSTP8
1
R/W
D/A converter (channels 2 and 3)
Note:
*
Not supported by the H8S/2454 Group.
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Section 24 Power-Down Modes
• MSTPCRL
Bit
Bit Name
Initial Value
R/W
Module
7
MSTP7
1
R/W
A/D converter unit 1
6
MSTP6
1
R/W
A/D converter unit 0
5
MSTP5
1
R/W
Serial communication interface 4 (SCI_4)
4
MSTP4
1
R/W
Serial communication interface 3 (SCI_3)
3
MSTP3
1
R/W
Serial communication interface 2 (SCI_2)
2
MSTP2
1
R/W
Serial communication interface 1 (SCI_1)
1
MSTP1
1
R/W
Serial communication interface 0 (SCI_0)
0
MSTP0
1
R/W
8-bit timer (TMR)
24.1.3
Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL)
EXMSTPCR performs module stop state control. Setting a bit to 1, the corresponding module
enters the module stop state, while clearing the bit to 0 clears the module stop state. When entering
all module clocks stop mode, set EXMSTPCR to H'FFFF.
• EXMSTPCRH
Bit
Bit Name
Initial Value
R/W
Module
15
MSTP31
1
R/W
⎯
14
MSTP30
1
R/W
⎯
13
MSTP29
1
R/W
⎯
12
MSTP28
1
R/W
⎯
11
MSTP27
1
R/W
⎯
10
MSTP26
1
R/W
⎯
9
MSTP25
1
R/W
⎯
8
MSTP24
1
R/W
⎯
Page 1220 of 1408
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Section 24 Power-Down Modes
• EXMSTPCRL
Bit
Bit Name
Initial Value
R/W
Module
7
MSTP23
1
R/W
Synchronous serial communication unit (SSU)
6
MSTP22
1
R/W
I2C bus interface 2_3 (IIC2_3)
5
MSTP21
1
R/W
I2C bus interface 2_2 (IIC2_2)
4
MSTP20
1
R/W
I2C bus interface 2_1 (IIC2_1)
3
MSTP19
1
R/W
I2C bus interface 2_0 (IIC2_0)
2
MSTP18
1
R/W
USB function module (USB) (system clock)
1
MSTP17
1
R/W
USB function module (USB) (48 MHz clock)
0
MSTP16
1
R/W
⎯
24.1.4
RAM Module Stop Control Registers H and L (RMMSTPCRH, RMMSTPCRL)
RMMSTPCR performs module stop state control of the RAM area. Setting bits MSTP32 to
MSTP39 to 1 stops the corresponding on-chip RAM area. During access to an on-chip RAM area,
do not set bits MSTP32 to MSTP39 corresponding to the area to 1. While bit RAME in SYSCR is
1, and bits MSTP32 to MSTP39 are 1, do not access the corresponding RAM area.
• RMMSTPCRH
Bit
Bit Name
Initial Value
R/W
Module
15
MSTP47
0
R/W
⎯
14
MSTP46
0
R/W
⎯
13
MSTP45
0
R/W
⎯
12
MSTP44
0
R/W
⎯
11
MSTP43
0
R/W
⎯
10
MSTP42
0
R/W
⎯
9
MSTP41
0
R/W
⎯
8
MSTP40
0
R/W
⎯
R01UH0309EJ0500 Rev. 5.00
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 24 Power-Down Modes
• RMMSTPCRL
Bit
Bit Name
Initial Value
R/W
Module
7
MSTP39
0
R/W
On-chip RAM_7 (H'FEC000 to H'FEDFFF)*
6
MSTP38
0
R/W
On-chip RAM_6 (H'FEE000 to H'FEFFFF)*
5
MSTP37
0
R/W
On-chip RAM_5 (H'FF0000 to H'FF1FFF)
4
MSTP36
0
R/W
On-chip RAM_4 (H'FF2000 to H'FF3FFF)
3
MSTP35
0
R/W
On-chip RAM_3 (H'FF4000 to H'FF5FFF)
2
MSTP34
0
R/W
On-chip RAM_2 (H'FF6000 to H'FF7FFF)
1
MSTP33
0
R/W
On-chip RAM_1 (H'FF8000 to H'FF9FFF)
0
MSTP32
0
R/W
On-chip RAM_0 (H'FFA000 to H'FFBFFF)
Note:
*
Not supported by the H8S/24568R, H8S/24568, H8S/24565R, H8S/24565,
H8S/24561R, H8S/24561, H8S/24548, H8S/24545, and H8S/24541 Groups.
Page 1222 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
24.2
Operation
24.2.1
Clock Division Mode
Section 24 Power-Down Modes
When bits STC1 and STC0 in PLLCR are set to 11, a transition is made to clock division mode,
and the system clock frequency is divided with respect to the oscillator frequency. Clock division
mode is cancelled by clearing bits STC1 and STC0 to a value other than 11. The timings of
transition and clearing depend on the STCS bit setting in SCKCR. For the operation at transition
and clearing, see section 23.3, System-Clock PLL Circuit and Divider.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external or internal
interrupt, clock division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.
R01UH0309EJ0500 Rev. 5.00
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Page 1223 of 1408
Section 24 Power-Down Modes
24.2.2
(1)
H8S/2456, H8S/2456R, H8S/2454 Group
Sleep Mode
Transition to Sleep Mode
When the SLEEP instruction is executed while the SSBY bit is 0 in SBYCR, the CPU enters the
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers
are retained. Other peripheral functions do not stop.
(2)
Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
• Exiting Sleep Mode by Interrupts:
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting Sleep Mode by RES Pin:
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high starts the CPU performing reset exception processing.
• Exiting Sleep Mode by STBY Pin:
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Page 1224 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
24.2.3
(1)
Section 24 Power-Down Modes
Software Standby Mode
Transition to Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
However, the contents of the CPU's internal registers, RAM data, and the states of on-chip
peripheral functions other than the SCI, IIC, and SSU, and the states of I/O ports, are retained.
Whether the address bus and bus control signals are placed in the high-impedance state or retain
the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
(2)
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ15*), an
internal interrupt (resume of USB), or by means of the RES pin or STBY pin. Setting the SSI bit
in SSIER to 1 enables IRQ0 to IRQ15* to be used as software standby mode clearing sources.
• Clearing with an Interrupt:
When an NMI or IRQ0 to IRQ15* interrupt request signal is input, or if the USB module
receives the resume signal from up-stream in the suspended state, USB clock oscillation starts,
and stable clocks are supplied to the entire LSI after the elapse of the time set in bits STS3 to
STS0 in SBYCR. Then, software standby mode is cleared, and interrupt exception handling is
started.
When clearing software standby mode with an IRQ0 to IRQ15* interrupt, set the
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ15* is generated. Software standby mode cannot be cleared if the interrupt has
been masked on the CPU side or has been designated as a DTC activation source.
Note: * IRQ8 to IRQ15 are not supported by the H8S/2454 Group.
• Clearing with the RES Pin:
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
• Clearing with the STBY Pin:
When the STBY pin is driven low, a transition is made to hardware standby mode.
Note: * The IRQ8 to IRQ15 are not supported by the H8S/2454 Group.
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Section 24 Power-Down Modes
(3)
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS3 to STS0 in SBYCR should be set as described below.
• Using a Crystal Resonator:
Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time.
Table 24.2 shows the standby times for operating frequencies and settings of bits STS3 to
STS0.
• Using an External Clock:
A PLL circuit stabilization time is necessary. See table 24.2 to set the wait time.
Table 24.2 Oscillation Stabilization Time Settings
φ* [MHz]
Standby
STS3 STS2 STS1 STS0 Time
33
25
20
13
10
8
Unit
0
µs
0
0
1
1
0
1
1
0
0
1
1
0
1
Note:
*
0
Reserved
⎯
⎯
⎯
⎯
⎯
⎯
1
Reserved
⎯
⎯
⎯
⎯
⎯
⎯
0
Reserved
⎯
⎯
⎯
⎯
⎯
⎯
1
Reserved
⎯
⎯
⎯
⎯
⎯
⎯
0
Reserved
⎯
⎯
⎯
⎯
⎯
⎯
1
64
1.9
2.6
3.2
4.9
6.4
8.0
0
512
15.5
20.5
25.6
39.4
51.2
64.0
1
1024
31.0
41.0
51.2
78.8
102.4
128.0
0
2048
62.1
81.9
102.4
157.5
204.8
256.0
1
4096
0.12
0.16
0.20
0.32
0.41
0.51
0
16384
0.50
0.66
0.82
1.26
1.64
2.05
1
32765
0.99
1.31
1.64
2.52
3.28
4.10
0
65536
1.99
2.62
3.28
5.04
6.55
8.19
1
131072
3.97
5.24
6.55
10.08
13.11
16.38
0
262144
7.94
10.49
13.11
20.16
26.21
32.77
1
524288
15.89
20.97
26.21
40.33
52.43
65.54
ms
φ is the frequency divider output.
Page 1226 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
(4)
Section 24 Power-Down Modes
Software Standby Mode Application Example
Figure 24.2 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, after an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0
(falling edge specification), the NMIEG bit is set to 1 (rising edge specification). And after the
SSBY bit is set to 1, a SLEEP instruction is executed, causing a transition to software standby
mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG=1
SSBY=1
Software standby mode
(power-down mode)
Oscillation
stabilization
time tOSC2
NMI exception
handling
SLEEP instruction
Figure 24.2 Software Standby Mode Application Example
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Page 1227 of 1408
Section 24 Power-Down Modes
24.2.4
(1)
H8S/2456, H8S/2456R, H8S/2454 Group
Hardware Standby Mode
Transition to Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this
LSI is in hardware standby mode.
(2)
Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until the clock oscillator stabilizes (for details on the
oscillation stabilization time, see table 24.2). When the RES pin is subsequently driven high, a
transition is made to the program execution state via the reset exception handling state.
Page 1228 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
(3)
Section 24 Power-Down Modes
Hardware Standby Mode Timing
Figure 24.3 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,
waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 24.3 Hardware Standby Mode Timing
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Section 24 Power-Down Modes
(4)
Hardware Standby Mode Timing when Power Is Supplied
When entering hardware standby mode immediately after the power is supplied, the RES signal
must be driven low for a given period with retaining the STBY signal high. After the RES signal is
canceled, drive the STBY signal low.
(1) Power supply
RES
(2) Reset period
STBY
(3) Hardware standby mode
Figure 24.4 Hardware Standby Mode Timing when Power Is Supplied
Page 1230 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
24.2.5
Section 24 Power-Down Modes
Module Stop Function
Module stop function can be set for individual on-chip peripheral modules.
When an MSTP bit in MSTPCR, EXMSTPCR, or RMMSTPCR is set to 1, the corresponding
module stops operation at the end of the bus cycle and a transition is made to module stop state.
The CPU continues operating independently.
When an MSTP bit is cleared to 0, the corresponding module stop state is cleared and the module
starts operating at the end of the bus cycle. In module stop state, part of SCI registers and the
internal state of SSU are reset but the internal states of the other modules are retained.
After reset clearance, all modules other than the EXDMAC*, DMAC, DTC, and on-chip RAM are
in module stop state.
The module registers that are set in module stop state cannot be read or written to.
The module-stop function for RAM is only effective for on-chip RAM. When an area of on-chip
RAM is set up as an external address space by bits RAME and EXPE in SYSCR, the resulting
external space is accessible regardless of the module-stop setting. Table 24.3 lists the kinds of
operation in case of access to the on-chip RAM area.
Note: * The EXDMAC is not supported by the H8S/2454 Group.
Table 24.3 Combinations of SYSCR Settings and Operation in Access to On-Chip RAM
Register Settings
RAME
EXPE
mstp
Target for Access Description
1
X
1
⎯
0
On-chip RAM
0
1
X
External address
space
0
X
⎯
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
This area is not readable/writable and access is
prohibited.
This area is not readable/writable and access is
prohibited.
Page 1231 of 1408
Section 24 Power-Down Modes
24.2.6
H8S/2456, H8S/2456R, H8S/2454 Group
All Module Clocks Stop Mode
When the ACSE bit in MSTPCRH is set to 1 and module stop state is set for all the on-chip
peripheral functions controlled by MSTPCR or EXMSTPCR (MSTPCR = H'FFFF, EXMSTPCR
= H'FFFF), or for all the on-chip peripheral functions except the 8-bit timer (MSTPCR = H'FFFE,
EXMSTPCR = H'FFFF), executing a SLEEP instruction while the SSBY bit in SBYCR is cleared
to 0 will cause all the on-chip peripheral functions (except the 8-bit timer and watchdog timer), the
bus controller, and the I/O ports to stop operating, and a transition to be made to all module clocks
stop mode at the end of the bus cycle.
Operation or stopping of the 8-bit timer can be selected by means of the MSTP0 bit.
To further reduce the current consumption in all module clocks stop mode, stop the modules
controlled by RMMSTPCR (RMMSTPCR = H'FFFF).
All module clocks stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15* pins),
RES pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the
normal program execution state via the exception handling state. All module clocks stop mode is
not cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Note: * IRQ8 to IRQ15 are not supported by the H8S/2454 Group.
Page 1232 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 24 Power-Down Modes
φ Clock Output Control
24.3
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 24.4 shows the state of the φ pin in each processing state.
Table 24.4 φ Pin State in Each Processing State
Register Setting
DDR
PSTOP
0
X
High impedance
High impedance
High impedance
High impedance
High
impedance
1
0
φ output
φ output
Fixed high
High impedance
φ output
1
1
Fixed high
Fixed high
Fixed high
High impedance
Fixed high
R01UH0309EJ0500 Rev. 5.00
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Software
Standby Mode
Hardware
Standby Mode
All Module
Clocks Stop
Mode
Normal
Operating State Sleep Mode
Page 1233 of 1408
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Section 24 Power-Down Modes
24.4
SDRAMφ Clock Output Control
Output of the SDRAMφ clock can be controlled by the SDPSTP bit in SCKCR. When the
SDPSTP bit is set to 1, the SDRAMφ clock stops at the end of the bus cycle and the pin can be
used as a general port. SDRAMφ clock output is enabled when the SDPSTP bit is cleared to 0
regardless of the DDR value. Table 24.5 shows the state of the SDRAMφ pin in each processing
state.
Note: The SDRAM interface is not supported by the H8S/2456 Group and H8S/2454 Group.
Table 24.5 SDRAMφ Pin State in Each Processing State
Register Setting
Software
Standby Mode
Hardware
Standby Mode
All Module
Clocks Stop
Mode
SDPSTP
DDR
Normal
Operating State Sleep Mode
0
X
SDRAMφ output
SDRAMφ output
Fixed low
High impedance
SDRAMφ
output
1
0
High impedance
High impedance
High impedance
High impedance
High
impedance
1
1
PH1/CS5/RAS5
output
H1/CS5/RAS5
output
H1/CS5/RAS5
output
High impedance
H1/CS5/RAS5
output
Note: SDRAM is not available in the H8S/2456 and H8S/2454 Groups.
In these products, this pin functions as a general pin regardless of the SDPSTP bit setting.
Page 1234 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
24.5
Usage Notes
24.5.1
I/O Port Status
Section 24 Power-Down Modes
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
24.5.2
Current Dissipation during Oscillation Stabilization Standby Period
Current dissipation increases during the oscillation stabilization standby period.
24.5.3
EXDMAC, DMAC, and DTC Module Stop
Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP13
and may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop state should be
carried out only when the respective module is not activated.
For details, see section 8, EXDMA Controller (EXDMAC), section 7, DMA Controller (DMAC),
and section 9, Data Transfer Controller (DTC).
Note: The EXDMAC is not supported by the H8S/2454 Group.
24.5.4
On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in the module stop state. Consequently, if the
module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DMAC or DTC activation source.
Interrupts should therefore be disabled before entering the module stop state.
Note: The EXDMAC is not supported by the H8S/2454 Group.
24.5.5
Writing to MSTPCR, EXMSTPCR, and RMMSTPCR
MSTPCR, EXMSTPCR, and RMMSTPCR should only be written to by the CPU.
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Page 1235 of 1408
Section 24 Power-Down Modes
24.5.6
H8S/2456, H8S/2456R, H8S/2454 Group
Notes on Clock Division Mode
The following points should be noted in clock division mode.
• Select the clock division ratio by the STC1 and STC0 bits so that the frequency of φ is within
the operation guaranteed range of clock cycle time tcyc shown in the Electrical Characteristics.
In other words, the frequency of φ must be 8 MHz or higher; be careful not so specify φ < 8
MHz.
• All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, the wait time for clearing software standby mode differs by changing the clock
division ratio.
• Note that the frequency of φ will be changed by changing the clock division ratio.
Page 1236 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Section 25 List of Registers
The address list gives information on the on-chip register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1.
•
•
•
Register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified by functional modules.
The access size is indicated.
2.
•
•
•
Register bits
Bit configurations of the registers are described in the same order as the register addresses.
Reserved bits are indicated by ⎯ in the bit name column.
For the registers of 16 or 32 bits, the MSB is described first.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, see the section on that on-chip peripheral module.
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Section 25 List of Registers
25.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
DTC mode register A
MRA
8
DTC
16/32
2
DTC source address register
SAR
24
DTC
16/32
2
DTC mode register B
MRB
8
DTC
16/32
2
DTC destination address register
DAR
24
DTC
16/32
2
DTC transfer count register A
CRA
16
DTC
16/32
2
DTC transfer count register B
CRB
16
DTC
16/32
2
Interrupt flag register 0
IFR0
8
H'FB00
USB
8
3
Interrupt flag register 1
IFR1
8
H'FB01
USB
8
3
Interrupt flag register 2
IFR2
8
H'FB02
USB
8
3
Interrupt enable register 0
IER0
8
H'FB08
USB
8
3
Interrupt enable register 1
IER1
8
H'FB09
USB
8
3
Interrupt enable register 2
IER2
8
H'FB0A
USB
8
3
Interrupt select register 0
ISR0
8
H'FB10
USB
8
3
Interrupt select register 1
ISR1
8
H'FB11
USB
8
3
H'BC00 to
H'BFFF
Interrupt select register 2
ISR2
8
H'FB12
USB
8
3
EP0i data register
EPDR0i
32
H'FB20
USB
8
3
EP0o data register
EPDR0o
32
H'FB24
USB
8
3
EP0s data register
EPDR0s
32
H'FB28
USB
8
3
EP1 data register
EPDR1
32
H'FB30
USB
8
3
EP2 data register
EPDR2
32
H'FB34
USB
8
3
EP3 data register
EPDR3
32
H'FB38
USB
8
3
EP0o receive data size register
EPSZ0o
8
H'FB80
USB
8
3
EP1 receive data size register
EPSZ1
8
H'FB81
USB
8
3
Data status register 0
DASTS0
8
H'FB88
USB
8
3
Data status register 1
DASTS1
8
H'FB89
USB
8
3
Trigger register 0
TRG0
8
H'FB90
USB
8
3
Trigger register 1
TRG1
8
H'FB91
USB
8
3
Page 1238 of 1408
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H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
FIFO clear register 0
FCLR0
8
H'FB98
USB
8
3
FIFO clear register 1
FCLR1
8
H'FB99
USB
8
3
Endpoint stall register 0
EPSTL0
8
H'FBA0
USB
8
3
Endpoint stall register 1
EPSTL1
8
H'FBA1
USB
8
3
Stall status register 1
STLSR1
8
H'FBA9
USB
8
3
DMA transfer setting register
DMAR
8
H'FBB0
USB
8
3
Configuration value register
CVR
8
H'FBB4
USB
8
3
Control register
CTLR
8
H'FBB8
USB
8
3
Endpoint information register
EPIR
32
H'FBC0
USB
8
3
Transceiver test register 0
TRNTREG0
8
H'FBD0
USB
8
3
Transceiver test register 1
TRNTREG1
8
H'FBD1
USB
8
3
RAM module stop control register H
RMMSTPCRH 8
H'FC80
SYSTEM
8
2
RAM module stop control register L
RMMSTPCRL 8
H'FC81
SYSTEM
8
2
USB PLL control register
USPLLCR
8
H'FC82
SYSTEM
8
2
Interrupt priority register L
IPRL
16
H'FC90
INT
16
2
Interrupt priority register M
IPRM
16
H'FC92
INT
16
2
Interrupt priority register N
IPRN
16
H'FC94
INT
16
2
DTC enable register I
DTCERI
8
H'FC96
DTC
16
2
DTC control register
DTCCR
8
H'FC98
DTC
16
2
A/D data register A_1
ADDRA_1
16
H'FCA0
A/D_1
16
2
A/D data register B_1
ADDRB_1
16
H'FCA2
A/D_1
16
2
A/D data register C_1
ADDRC_1
16
H'FCA4
A/D_1
16
2
A/D data register D_1
ADDRD_1
16
H'FCA6
A/D_1
16
2
A/D data register E_1
ADDRE_1
16
H'FCA8
A/D_1
16
2
A/D data register F_1
ADDRF_1
16
H'FCAA
A/D_1
16
2
A/D data register G_1
ADDRG_1
16
H'FCAC
A/D_1
16
2
A/D data register H_1
ADDRH_1
16
H'FCAE
A/D_1
16
2
A/D control/status register_1
ADCSR_1
8
H'FCB0
A/D_1
16
2
A/D control register_1
ADCR_1
8
H'FCB1
A/D_1
16
2
Timer start register_1
TSTRB
8
H'FCC0
TPU
16
2
Timer synchronous register_1
TSYRB
8
H'FCC1
TPU
16
2
Timer control register_6
TCR_6
8
H'FCD0
TPU_6
16
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1239 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Timer mode register_6
TMDR_6
8
H'FCD1
TPU_6
16
2
Timer I/O control register H_6
TIORH_6
8
H'FCD2
TPU_6
16
2
Timer I/O control register L_6
TIORL_6
8
H'FCD3
TPU_6
16
2
Timer interrupt enable register_6
TIER_6
8
H'FCD4
TPU_6
16
2
Timer status register_6
TSR_6
8
H'FCD5
TPU_6
16
2
Timer counter_6
TCNT_6
16
H'FCD6
TPU_6
16
2
Timer general register A_6
TGRA_6
16
H'FCD8
TPU_6
16
2
Timer general register B_6
TGRB_6
16
H'FCDA
TPU_6
16
2
Timer general register C_6
TGRC_6
16
H'FCDC
TPU_6
16
2
Timer general register D_6
TGRD_6
16
H'FCDE
TPU_6
16
2
Timer control register_7
TCR_7
8
H'FCE0
TPU_7
16
2
Timer mode register_7
TMDR_7
8
H'FCE1
TPU_7
16
2
Timer I/O control register_7
TIOR_7
8
H'FCE2
TPU_7
16
2
Timer interrupt enable register_7
TIER_7
8
H'FCE4
TPU_7
16
2
Timer status register_7
TSR_7
8
H'FCE5
TPU_7
16
2
Timer counter_7
TCNT_7
16
H'FCE6
TPU_7
16
2
Timer general register A_7
TGRA_7
16
H'FCE8
TPU_7
16
2
Timer general register B_7
TGRB_7
16
H'FCEA
TPU_7
16
2
Timer control register_8
TCR_8
8
H'FCF0
TPU_8
16
2
Timer mode register_8
TMDR_8
8
H'FCF1
TPU_8
16
2
Timer I/O control register_8
TIOR_8
8
H'FCF2
TPU_8
16
2
Timer interrupt enable register_8
TIER_8
8
H'FCF4
TPU_8
16
2
Timer status register_8
TSR_8
8
H'FCF5
TPU_8
16
2
Timer counter_8
TCNT_8
16
H'FCF6
TPU_8
16
2
Timer general register A_8
TGRA_8
16
H'FCF8
TPU_8
16
2
Timer general register B_8
TGRB_8
16
H'FCFA
TPU_8
16
2
Timer control register_9
TCR_9
8
H'FD00
TPU_9
16
2
Timer mode register_9
TMDR_9
8
H'FD01
TPU_9
16
2
Timer I/O control register H_9
TIORH_9
8
H'FD02
TPU_9
16
2
Timer I/O control register L_9
TIORL_9
8
H'FD03
TPU_9
16
2
Timer interrupt enable register_9
TIER_9
8
H'FD04
TPU_9
16
2
Timer status register_9
TSR_9
8
H'FD05
TPU_9
16
2
Page 1240 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Timer counter_9
TCNT_9
16
H'FD06
TPU_9
16
2
Timer general register A_9
TGRA_9
16
H'FD08
TPU_9
16
2
Timer general register B_9
TGRB_9
16
H'FD0A
TPU_9
16
2
Timer general register C_9
TGRC_9
16
H'FD0C
TPU_9
16
2
Timer general register D_9
TGRD_9
16
H'FD0E
TPU_9
16
2
Timer control register_10
TCR_10
8
H'FD10
TPU_10
16
2
Timer mode register_10
TMDR_10
8
H'FD11
TPU_10
16
2
Timer I/O control register_10
TIOR_10
8
H'FD12
TPU_10
16
2
Timer interrupt enable register_10
TIER_10
8
H'FD14
TPU_10
16
2
Timer status register_10
TSR_10
8
H'FD15
TPU_10
16
2
Timer counter_10
TCNT_10
16
H'FD16
TPU_10
16
2
Timer general register A_10
TGRA_10
16
H'FD18
TPU_10
16
2
Timer general register B_10
TGRB_10
16
H'FD1A
TPU_10
16
2
Timer control register_11
TCR_11
8
H'FD20
TPU_11
16
2
Timer mode register_11
TMDR_11
8
H'FD21
TPU_11
16
2
Timer I/O control register_11
TIOR_11
8
H'FD22
TPU_11
16
2
Timer interrupt enable register_11
TIER_11
8
H'FD24
TPU_11
16
2
Timer status register_11
TSR_11
8
H'FD25
TPU_11
16
2
Timer counter_11
TCNT_11
16
H'FD26
TPU_11
16
2
Timer general register A_11
TGRA_11
16
H'FD28
TPU_11
16
2
Timer general register B_11
TGRB_11
16
H'FD2A
TPU_11
16
2
Port 1 open drain control register
P1ODR
8
H'FD40
PORT
8
2
Port 2 open drain control register
P2ODR
8
H'FD41
PORT
8
2
Port 5 open drain control register
P5ODR
8
H'FD42
PORT
8
2
Port 6 open drain control register
P6ODR
8
H'FD43
PORT
8
2
Port 8 open drain control register
P8ODR
8
H'FD44
PORT
8
2
Port B open drain control register
PBODR
8
H'FD45
PORT
8
2
Port C open drain control register
PCODR
8
H'FD46
PORT
8
2
Port D open drain control register
PDODR
8
H'FD47
PORT
8
2
Port E open drain control register
PEODR
8
H'FD48
PORT
8
2
Port F open drain control register
PFODR
8
H'FD49
PORT
8
2
Port G open drain control register
PGODR
8
H'FD4A
PORT
8
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1241 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Port H open drain control register
PHODR
8
H'FD4B
PORT
8
2
Port J open drain control register
PJODR
8
H'FD4C
PORT
8
2
2
ICCRA_0
8
H'FD58
IIC2_0
8
2
2
ICCRB_0
8
H'FD59
IIC2_0
8
2
I C bus control register A_0
I C bus control register B_0
2
ICMR_0
8
H'FD5A
IIC2_0
8
2
2
ICIER_0
8
H'FD5B
IIC2_0
8
2
I C bus status register_0
2
ICSR_0
8
H'FD5C
IIC2_0
8
2
Slave address register_0
I C bus mode register_0
I C bus interrupt enable register_0
SAR_0
8
H'FD5D
IIC2_0
8
2
2
ICDRT_0
8
H'FD5E
IIC2_0
8
2
2
ICDRR_0
8
H'FD5F
IIC2_0
8
2
2
ICCRA_1
8
H'FD60
IIC2_1
8
2
2
ICCRB_1
8
H'FD61
IIC2_1
8
2
I C transfer data register_0
I C receive data register_0
I C bus control register A_1
I C bus control register B_1
2
ICMR_1
8
H'FD62
IIC2_1
8
2
2
ICIER_1
8
H'FD63
IIC2_1
8
2
2
I C bus status register_1
ICSR_1
8
H'FD64
IIC2_1
8
2
Slave address register_1
I C bus mode register_1
I C bus interrupt enable register_1
SAR_1
8
H'FD65
IIC2_1
8
2
2
ICDRT_1
8
H'FD66
IIC2_1
8
2
2
ICDRR_1
8
H'FD67
IIC2_1
8
2
2
ICCRA_2
8
H'FD68
IIC2_2
8
2
2
ICCRB_2
8
H'FD69
IIC2_2
8
2
I C transfer data register_1
I C receive data register_1
I C bus control register A_2
I C bus control register B_2
2
ICMR_2
8
H'FD6A
IIC2_2
8
2
2
ICIER_2
8
H'FD6B
IIC2_2
8
2
I C bus status register_2
2
ICSR_2
8
H'FD6C
IIC2_2
8
2
Slave address register_2
I C bus mode register_2
I C bus interrupt enable register_2
SAR_2
8
H'FD6D
IIC2_2
8
2
2
ICDRT_2
8
H'FD6E
IIC2_2
8
2
2
ICDRR_2
8
H'FD6F
IIC2_2
8
2
2
ICCRA_3
8
H'FD70
IIC2_3
8
2
2
ICCRB_3
8
H'FD71
IIC2_3
8
2
I C transfer data register_2
I C receive data register_2
I C bus control register A_3
I C bus control register B_3
2
ICMR_3
8
H'FD72
IIC2_3
8
2
2
ICIER_3
8
H'FD73
IIC2_3
8
2
2
I C bus status register_3
ICSR_3
8
H'FD74
IIC2_3
8
2
Slave address register_3
SAR_3
8
H'FD75
IIC2_3
8
2
I C bus mode register_3
I C bus interrupt enable register_3
Page 1242 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
2
ICDRT_3
8
H'FD76
IIC2_3
8
2
2
I C receive data register_3
ICDRR_3
8
H'FD77
IIC2_3
8
2
Serial expansion mode register_2
SEMR_2
8
H'FDA8
SCI_2
8
2
SS control register H
SSCRH
8
H'FDB0
SSU
16
2
Register Name
I C transfer data register_3
SS control register L
SSCRL
8
H'FDB1
SSU
16
2
SS mode register
SSMR
8
H'FDB2
SSU
16
2
SS enable register
SSER
8
H'FDB3
SSU
16
2
SS status register
SSSR
8
H'FDB4
SSU
16
2
SS control register 2
SSCR2
8
H'FDB5
SSU
16
2
SS transmit data register 0
SSTDR0
8
H'FDB6
SSU
16
2
SS transmit data register 1
SSTDR1
8
H'FDB7
SSU
16
2
SS transmit data register 2
SSTDR2
8
H'FDB8
SSU
16
2
SS transmit data register 3
SSTDR3
8
H'FDB9
SSU
16
2
SS receive data register 0
SSRDR0
8
H'FDBA
SSU
16
2
SS receive data register 1
SSRDR1
8
H'FDBB
SSU
16
2
SS receive data register 2
SSRDR2
8
H'FDBC
SSU
16
2
SS receive data register 3
SSRDR3
8
H'FDBD
SSU
EXDMA source address register_2
EDSAR_2
32
H'FDE0
16
2
3
16
2
3
16
2
3
16
2
3
16
2
3
16
2
3
16
2
3
16
2
3
16
2
3
16
2
3
EXDMAC_2*
EXDMA destination address
register_2
EDDAR_2
32
H'FDE4
EXDMAC_2*
EXDMA transfer count register_2
EDTCR_2
32
H'FDE8
EXDMAC_2*
EXDMA mode control register_2
EXDMA address control register_2
EXDMA source address register_3
EDMDR_2
EDACR_2
EDSAR_3
16
16
32
H'FDEC
H'FDEE
H'FDF0
EXDMAC_2*
EXDMAC_2*
EXDMAC_3*
EXDMA destination address
register_3
EDDAR_3
32
H'FDF4
EXDMAC_3*
EXDMA transfer count register_3
EDTCR_3
32
H'FDF8
EXDMAC_3*
EXDMA mode control register_3
EDMDR_3
16
H'FDFC
EXDMAC_3*
EXDMA address control register_3
EDACR_3
16
H'FDFE
EXDMAC_3*
16
2
Interrupt priority register A
IPRA
16
H'FE00
INT
16
2
Interrupt priority register B
IPRB
16
H'FE02
INT
16
2
Interrupt priority register C
IPRC
16
H'FE04
INT
16
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1243 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Interrupt priority register D
IPRD
16
H'FE06
INT
16
2
Interrupt priority register E
IPRE
16
H'FE08
INT
16
2
Interrupt priority register F
IPRF
16
H'FE0A
INT
16
2
Interrupt priority register G
IPRG
16
H'FE0C
INT
16
2
Interrupt priority register H
IPRH
16
H'FE0E
INT
16
2
Interrupt priority register I
IPRI
16
H'FE10
INT
16
2
Interrupt priority register J
IPRJ
16
H'FE12
INT
16
2
Interrupt priority register K
IPRK
16
H'FE14
INT
16
2
IRQ pin select register
ITSR
16
H'FE16
INT
16
2
Software standby release IRQ
enable register
SSIER
16
H'FE18
INT
16
2
IRQ sense control register H
ISCRH
16
H'FE1A
INT
16
2
IRQ sense control register L
ISCRL
16
H'FE1C
INT
16
2
IrDA control register_0
IrCR_0
8
H'FE1E
IrDA
8
2
Port 1 data direction register
P1DDR
8
H'FE20
PORT
8
2
Port 2 data direction register
P2DDR
8
H'FE21
PORT
8
2
Port 3 data direction register
P3DDR
8
H'FE22
PORT
8
2
Port 5 data direction register
P5DDR
8
H'FE24
PORT
8
2
Port 6 data direction register
P6DDR
8
H'FE25
PORT
8
2
Port 8 data direction register
P8DDR
8
H'FE27
PORT
8
2
Port A data direction register
PADDR
8
H'FE29
PORT
8
2
Port B data direction register
PBDDR
8
H'FE2A
PORT
8
2
Port C data direction register
PCDDR
8
H'FE2B
PORT
8
2
Port D data direction register
PDDDR
8
H'FE2C
PORT
8
2
Port E data direction register
PEDDR
8
H'FE2D
PORT
8
2
Port F data direction register
PFDDR
8
H'FE2E
PORT
8
2
Port G data direction register
PGDDR
8
H'FE2F
PORT
8
2
Port function control register 0
PFCR0
8
H'FE32
PORT
8
2
Port function control register 1
PFCR1
8
H'FE33
PORT
8
2
Port function control register 2
PFCR2
8
H'FE34
PORT
8
2
Port A pull-up MOS control register
PAPCR
8
H'FE36
PORT
8
2
Port B pull-up MOS control register
PBPCR
8
H'FE37
PORT
8
2
Page 1244 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Port C pull-up MOS control register
PCPCR
8
H'FE38
PORT
8
2
Port D pull-up MOS control register
PDPCR
8
H'FE39
PORT
8
2
Port E pull-up MOS control register
PEPCR
8
H'FE3A
PORT
8
2
Port 3 open drain control register
P3ODR
8
H'FE3C
PORT
8
2
Port A open drain control register
PAODR
8
H'FE3D
PORT
8
2
Serial mode register_3
SMR_3
8
H'FE40
SCI_3
8
2
Bit rate register_3
BRR_3
8
H'FE41
SCI_3
8
2
Serial control register_3
SCR_3
8
H'FE42
SCI_3
8
2
Transmit data register_3
TDR_3
8
H'FE43
SCI_3
8
2
Serial status register_3
SSR_3
8
H'FE44
SCI_3
8
2
Receive data register_3
RDR_3
8
H'FE45
SCI_3
8
2
Smart card mode register_3
SCMR_3
8
H'FE46
SCI_3
8
2
Serial mode register_4
SMR_4
8
H'FE48
SCI_4
8
2
Bit rate register_4
BRR_4
8
H'FE49
SCI_4
8
2
Serial control register_4
SCR_4
8
H'FE4A
SCI_4
8
2
Transmit data register_4
TDR_4
8
H'FE4B
SCI_4
8
2
Serial status register_4
SSR_4
8
H'FE4C
SCI_4
8
2
Receive data register_4
RDR_4
8
H'FE4D
SCI_4
8
2
Smart card mode register_4
SCMR_4
8
H'FE4E
SCI_4
8
2
Timer control register_3
TCR_3
8
H'FE80
TPU_3
16
2
Timer mode register_3
TMDR_3
8
H'FE81
TPU_3
16
2
Timer I/O control register H_3
TIORH_3
8
H'FE82
TPU_3
16
2
Timer I/O control register L_3
TIORL_3
8
H'FE83
TPU_3
16
2
Timer interrupt enable register_3
TIER_3
8
H'FE84
TPU_3
16
2
Timer status register_3
TSR_3
8
H'FE85
TPU_3
16
2
Timer counter_3
TCNT_3
16
H'FE86
TPU_3
16
2
Timer general register A_3
TGRA_3
16
H'FE88
TPU_3
16
2
Timer general register B_3
TGRB_3
16
H'FE8A
TPU_3
16
2
Timer general register C_3
TGRC_3
16
H'FE8C
TPU_3
16
2
Timer general register D_3
TGRD_3
16
H'FE8E
TPU_3
16
2
Timer control register_4
TCR_4
8
H'FE90
TPU_4
16
2
Timer mode register_4
TMDR_4
8
H'FE91
TPU_4
16
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1245 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Timer I/O control register_4
TIOR_4
8
H'FE92
TPU_4
16
2
Timer interrupt enable register_4
TIER_4
8
H'FE94
TPU_4
16
2
Timer status register_4
TSR_4
8
H'FE95
TPU_4
16
2
Timer counter_4
TCNT_4
16
H'FE96
TPU_4
16
2
Timer general register A_4
TGRA_4
16
H'FE98
TPU_4
16
2
Timer general register B_4
TGRB_4
16
H'FE9A
TPU_4
16
2
Timer control register_5
TCR_5
8
H'FEA0
TPU_5
16
2
Timer mode register_5
TMDR_5
8
H'FEA1
TPU_5
16
2
Timer I/O control register_5
TIOR_5
8
H'FEA2
TPU_5
16
2
Timer interrupt enable register_5
TIER_5
8
H'FEA4
TPU_5
16
2
Timer status register_5
TSR_5
8
H'FEA5
TPU_5
16
2
Timer counter_5
TCNT_5
16
H'FEA6
TPU_5
16
2
Timer general register A_5
TGRA_5
16
H'FEA8
TPU_5
16
2
Timer general register B_5
TGRB_5
16
H'FEAA
TPU_5
16
2
Flash memory control register 1
FLMCR1
8
H'FEB0
FLASH
8
2
Flash memory data block protect
register
FLMDBPR
8
H'FEB2
FLASH
8
2
Flash memory status register
FLMSTR
8
H'FEB3
FLASH
8
2
Bus width control register
ABWCR
8
H'FEC0
BSC
16
2
Access state control register
ASTCR
8
H'FEC1
BSC
16
2
Wait control register AH
WTCRAH
8
H'FEC2
BSC
16
2
Wait control register AL
WTCRAL
8
H'FEC3
BSC
16
2
Wait control register BH
WTCRBH
8
H'FEC4
BSC
16
2
Wait control register BL
WTCRBL
8
H'FEC5
BSC
16
2
Read strobe timing control register
RDNCR
8
H'FEC6
BSC
16
2
CS assertion period control
register H
CSACRH
8
H'FEC8
BSC
16
2
CS assertion period control register L CSACRL
8
H'FEC9
BSC
16
2
Burst ROM interface control
register H
BROMCRH
8
H'FECA
BSC
16
2
Burst ROM interface control
register L
BROMCRL
8
H'FECB
BSC
16
2
Bus control register
BCR
16
H'FECC
BSC
16
2
Page 1246 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register Name
Section 25 List of Registers
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Address/data multiplexed I/O control MPXCR
register
8
H'FECF
BSC
16
2
DRAM control register L
16
H'FED0
BSC
16
2
DRAMCR
DRAM access control register H
DRACCRH
8
H'FED2
BSC
16
2
DRAM access control register L
DRACCRL
8
H'FED3
BSC
16
2
Refresh control register
REFCR
16
H'FED4
BSC
16
2
Refresh timer counter
RTCNT
8
H'FED6
BSC
16
2
Refresh time constant register
RTCOR
8
H'FED7
BSC
16
2
Memory address register_0AH
MAR_0AH
16
H'FEE0
DMAC
16
2
Memory address register_0AL
MAR_0AL
16
H'FEE2
DMAC
16
2
I/O address register_0A
IOAR_0A
16
H'FEE4
DMAC
16
2
Transfer count register_0A
ETCR_0A
16
H'FEE6
DMAC
16
2
Memory address register_0BH
MAR_0BH
16
H'FEE8
DMAC
16
2
Memory address register_0BL
MAR_0BL
16
H'FEEA
DMAC
16
2
I/O address register_0B
IOAR_0B
16
H'FEEC
DMAC
16
2
Transfer count register_0B
ETCR_0B
16
H'FEEE
DMAC
16
2
Memory address register_1AH
MAR_1AH
16
H'FEF0
DMAC
16
2
Memory address register_1AL
MAR_1AL
16
H'FEF2
DMAC
16
2
I/O address register_1A
IOAR_1A
16
H'FEF4
DMAC
16
2
Transfer count register_1A
ETCR_1A
16
H'FEF6
DMAC
16
2
Memory address register_1BH
MAR_1BH
16
H'FEF8
DMAC
16
2
Memory address register_1BL
MAR_1BL
16
H'FEFA
DMAC
16
2
I/O address register_1B
IOAR_1B
16
H'FEFC
DMAC
16
2
Transfer count register_1B
ETCR_1B
16
H'FEFE
DMAC
16
2
DMA write enable register
DMAWER
8
H'FF20
DMAC
8
2
DMA terminal control register
DMATCR
8
H'FF21
DMAC
8
2
DMA control register_0A
DMACR_0A
8
H'FF22
DMAC
16
2
DMA control register_0B
DMACR_0B
8
H'FF23
DMAC
16
2
DMA control register_1A
DMACR_1A
8
H'FF24
DMAC
16
2
DMA control register_1B
DMACR_1B
8
H'FF25
DMAC
16
2
DMA band control register H
DMABCRH
8
H'FF26
DMAC
16
2
DMA band control register L
DMABCRL
8
H'FF27
DMAC
16
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1247 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
DTC enable register A
DTCERA
8
H'FF28
DTC
16
2
DTC enable register B
DTCERB
8
H'FF29
DTC
16
2
DTC enable register C
DTCERC
8
H'FF2A
DTC
16
2
DTC enable register D
DTCERD
8
H'FF2B
DTC
16
2
DTC enable register E
DTCERE
8
H'FF2C
DTC
16
2
DTC enable register F
DTCERF
8
H'FF2D
DTC
16
2
DTC enable register G
DTCERG
8
H'FF2E
DTC
16
2
DTC enable register H
DTCERH
8
H'FF2F
DTC
16
2
DTC vector register
DTVECR
8
H'FF30
DTC
16
2
Interrupt control register
INTCR
8
H'FF31
INT
16
2
IRQ enable register
IER
16
H'FF32
INT
16
2
IRQ status register
ISR
16
H'FF34
INT
16
2
Standby control register
SBYCR
8
H'FF3A
SYSTEM
8
2
System clock control register
SCKCR
8
H'FF3B
SYSTEM
8
2
System control register
SYSCR
8
H'FF3D
SYSTEM
8
2
Mode control register
MDCR
8
H'FF3E
SYSTEM
8
2
Module stop control register H
MSTPCRH
8
H'FF40
SYSTEM
8
2
Module stop control register L
MSTPCRL
8
H'FF41
SYSTEM
8
2
Extension module stop control
register H
EXMSTPCRH 8
H'FF42
SYSTEM
8
2
Extension module stop control
register L
EXMSTPCRL 8
H'FF43
SYSTEM
8
2
PLL control register
PLLCR
8
H'FF45
SYSTEM
8
2
PPG output control register
PCR
8
H'FF46
PPG
8
2
PPG output mode register
PMR
8
H'FF47
PPG
8
2
Next data enable register H
NDERH
8
H'FF48
PPG
8
2
Next data enable register L
NDERL
8
H'FF49
PPG
8
2
Output data register H
PODRH
8
H'FF4A
PPG
8
2
Output data register L
PODRL
8
H'FF4B
PPG
8
2
NDRHH
8
H'FF4C
PPG
8
2
NDRLH
8
H'FF4D
PPG
8
2
NDRHL
8
H'FF4E
PPG
8
2
1
Next data register H*
1
Next data register L*
1
Next data register H*
Page 1248 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Next data register L*
NDRLL
8
H'FF4F
PPG
8
2
Port 1 register
PORT1
8
H'FF50
PORT
8
2
Port 2 register
PORT2
8
H'FF51
PORT
8
2
Port 3 register
PORT3
8
H'FF52
PORT
8
2
Port 4 register
PORT4
8
H'FF53
PORT
8
2
Port 5 register
PORT5
8
H'FF54
PORT
8
2
Port 6 register
PORT6
8
H'FF55
PORT
8
2
Port 8 register
PORT8
8
H'FF57
PORT
8
2
Port 9 register
PORT9
8
H'FF58
PORT
8
2
Port A register
PORTA
8
H'FF59
PORT
8
2
Port B register
PORTB
8
H'FF5A
PORT
8
2
Port C register
PORTC
8
H'FF5B
PORT
8
2
Port D register
PORTD
8
H'FF5C
PORT
8
2
Port E register
PORTE
8
H'FF5D
PORT
8
2
Port F register
PORTF
8
H'FF5E
PORT
8
2
Port G register
PORTG
8
H'FF5F
PORT
8
2
Port 1 data register
P1DR
8
H'FF60
PORT
8
2
Port 2 data register
P2DR
8
H'FF61
PORT
8
2
Port 3 data register
P3DR
8
H'FF62
PORT
8
2
Port 5 data register
P5DR
8
H'FF64
PORT
8
2
Port 6 data register
P6DR
8
H'FF65
PORT
8
2
Port 8 data register
P8DR
8
H'FF67
PORT
8
2
Port A data register
PADR
8
H'FF69
PORT
8
2
Port B data register
PBDR
8
H'FF6A
PORT
8
2
Port C data register
PCDR
8
H'FF6B
PORT
8
2
Port D data register
PDDR
8
H'FF6C
PORT
8
2
Port E data register
PEDR
8
H'FF6D
PORT
8
2
Port F data register
PFDR
8
H'FF6E
PORT
8
2
Port G data register
PGDR
8
H'FF6F
PORT
8
2
Port H register
PORTH
8
H'FF70
PORT
8
2
Port J register
PORTJ
8
H'FF71
PORT
8
2
Port H data register
PHDR
8
H'FF72
PORT
8
2
Register Name
1
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1249 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Port J data register
PJDR
8
H'FF73
PORT
8
2
Port H data direction register
PHDDR
8
H'FF74
PORT
8
2
Port J data direction register
PJDDR
8
H'FF75
PORT
8
2
Serial mode register_0
SMR_0
8
H'FF78
SCI_0
8
2
Bit rate register_0
BRR_0
8
H'FF79
SCI_0
8
2
Serial control register_0
SCR_0
8
H'FF7A
SCI_0
8
2
Transmit data register_0
TDR_0
8
H'FF7B
SCI_0
8
2
Serial status register_0
SSR_0
8
H'FF7C
SCI_0
8
2
Receive data register_0
RDR_0
8
H'FF7D
SCI_0
8
2
Smart card mode register_0
SCMR_0
8
H'FF7E
SCI_0
8
2
Serial mode register_1
SMR_1
8
H'FF80
SCI_1
8
2
Bit rate register_1
BRR_1
8
H'FF81
SCI_1
8
2
Serial control register_1
SCR_1
8
H'FF82
SCI_1
8
2
Transmit data register_1
TDR_1
8
H'FF83
SCI_1
8
2
Serial status register_1
SSR_1
8
H'FF84
SCI_1
8
2
Receive data register_1
RDR_1
8
H'FF85
SCI_1
8
2
Smart card mode register_1
SCMR_1
8
H'FF86
SCI_1
8
2
Serial mode register_2
SMR_2
8
H'FF88
SCI_2
8
2
Bit rate register_2
BRR_2
8
H'FF89
SCI_2
8
2
Serial control register_2
SCR_2
8
H'FF8A
SCI_2
8
2
Transmit data register_2
TDR_2
8
H'FF8B
SCI_2
8
2
Serial status register_2
SSR_2
8
H'FF8C
SCI_2
8
2
Receive data register_2
RDR_2
8
H'FF8D
SCI_2
8
2
Smart card mode register_2
SCMR_2
8
H'FF8E
SCI_2
8
2
A/D data register A_0
ADDRA_0
16
H'FF90
A/D_0
16
2
A/D data register B_0
ADDRB_0
16
H'FF92
A/D_0
16
2
A/D data register C_0
ADDRC_0
16
H'FF94
A/D_0
16
2
A/D data register D_0
ADDRD_0
16
H'FF96
A/D_0
16
2
A/D data register E_0
ADDRE_0
16
H'FF98
A/D_0
16
2
A/D data register F_0
ADDRF_0
16
H'FF9A
A/D_0
16
2
A/D data register G_0
ADDRG_0
16
H'FF9C
A/D_0
16
2
A/D data register H_0
ADDRH_0
16
H'FF9E
A/D_0
16
2
Page 1250 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
A/D control/status register_0
ADCSR_0
8
H'FFA0
A/D_0
16
2
A/D control register_0
ADCR_0
8
H'FFA1
A/D_0
16
2
D/A data register 2
DADR2
8
H'FFA8
D/A
8
2
D/A data register 3
DADR3
8
H'FFA9
D/A
8
2
D/A control register 23
DACR23
8
H'FFAA
D/A
8
2
Timer control register_0
TCR_0
8
H'FFB0
TMR_0
16
2
Timer control register_1
TCR_1
8
H'FFB1
TMR_1
16
2
Timer control/status register_0
TCSR_0
8
H'FFB2
TMR_0
16
2
Timer control/status register_1
TCSR_1
8
H'FFB3
TMR_1
16
2
Time constant register A_0
TCORA_0
8
H'FFB4
TMR_0
16
2
Time constant register A_1
TCORA_1
8
H'FFB5
TMR_1
16
2
Time constant register B_0
TCORB_0
8
H'FFB6
TMR_0
16
2
Time constant register B_1
TCORB_1
8
H'FFB7
TMR_1
16
2
Timer counter_0
TCNT_0
8
H'FFB8
TMR_0
16
2
Timer counter_1
TCNT_1
8
H'FFB9
TMR_1
16
2
Timer counter control register_0
TCCR_0
8
H'FFBA
TMR
16
2
Timer counter control register_1
TCCR_1
8
H'FFBB
Timer control/status register
TCSR
8
TMR
16
2
2
WDT
16
2
2
WDT
16
2
2
WDT
16
2
H'FFBC*
(Write)
H'FFBC
(Read)
Timer counter
TCNT
8
H'FFBC*
(Write)
H'FFBD
(Read)
Reset control/status register
RSTCSR
8
H'FFBE*
(Write)
H'FFBF
(Read)
Timer start register
TSTR
8
H'FFC0
TPU
16
2
Timer synchronous register
TSYR
8
H'FFC1
TPU
16
2
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1251 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module
Data
Width
Access
States
Port function control register 3
PFCR3
8
H'FFC8
PORT
8
2
Port function control register 4
PFCR4
8
H'FFC9
PORT
8
2
Port function control register 5
PFCR5
8
H'FFCA
PORT
8
2
Timer control register_0
TCR_0
8
H'FFD0
TPU_0
16
2
Timer mode register_0
TMDR_0
8
H'FFD1
TPU_0
16
2
Timer I/O control register H_0
TIORH_0
8
H'FFD2
TPU_0
16
2
Timer I/O control register L_0
TIORL_0
8
H'FFD3
TPU_0
16
2
Timer interrupt enable register_0
TIER_0
8
H'FFD4
TPU_0
16
2
Timer status register_0
TSR_0
8
H'FFD5
TPU_0
16
2
Timer counter_0
TCNT_0
16
H'FFD6
TPU_0
16
2
Timer general register A_0
TGRA_0
16
H'FFD8
TPU_0
16
2
Timer general register B_0
TGRB_0
16
H'FFDA
TPU_0
16
2
Timer general register C_0
TGRC_0
16
H'FFDC
TPU_0
16
2
Timer general register D_0
TGRD_0
16
H'FFDE
TPU_0
16
2
Timer control register_1
TCR_1
8
H'FFE0
TPU_1
16
2
Timer mode register_1
TMDR_1
8
H'FFE1
TPU_1
16
2
Timer I/O control register_1
TIOR_1
8
H'FFE2
TPU_1
16
2
Timer interrupt enable register_1
TIER_1
8
H'FFE4
TPU_1
16
2
Timer status register_1
TSR_1
8
H'FFE5
TPU_1
16
2
Timer counter_1
TCNT_1
16
H'FFE6
TPU_1
16
2
Timer general register A_1
TGRA_1
16
H'FFE8
TPU_1
16
2
Timer general register B_1
TGRB_1
16
H'FFEA
TPU_1
16
2
Timer control register_2
TCR_2
8
H'FFF0
TPU_2
16
2
Timer mode register_2
TMDR_2
8
H'FFF1
TPU_2
16
2
Timer I/O control register_2
TIOR_2
8
H'FFF2
TPU_2
16
2
Timer interrupt enable register_2
TIER_2
8
H'FFF4
TPU_2
16
2
Timer status register_2
TSR_2
8
H'FFF5
TPU_2
16
2
Timer counter_2
TCNT_2
16
H'FFF6
TPU_2
16
2
Timer general register A_2
TGRA_2
16
H'FFF8
TPU_2
16
2
Timer general register B_2
TGRB_2
16
H'FFFA
TPU_2
16
2
Page 1252 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Notes: 1. If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
2. For writing, see section 14.6.1, Notes on Register Access.
3. Not supported by the H8S/2454 Group.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1253 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
25.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below.
Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MRA
SM1
SM0
DM1
DM0
MD1
MD0
DTS
Sz
DTC*1
SAR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MRB
CHNE
DISEL
CHNS
⎯
⎯
⎯
⎯
⎯
DAR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
IFR0
BRST
CFDN
SURSS
SURSF
SETC
SET1
VBUSMN
VBUSF
IFR1
⎯
⎯
⎯
SOF
SETUPTS
EPOoTS
EPOiTR
EPOiTS
CRA
CRB
IFR2
⎯
⎯
EP3TR
EP3TS
EP2TR
EP2EMPTY
EP2ALLEMP
EP1FULL
IER0
BRSTE
CFDNE
SSRSME
SURSFE
SETCE
SETIE
⎯
VBUSFE
IER1
⎯
⎯
⎯
SOFE
SETUPTSE
EPOoTSE
EPOiTRE
EPOiTSE
IER2
⎯
⎯
EP3TRE
EP3TSE
EP2TRE
EP2EMPTYE
EP2ALLEMPE
EP1FULLE
ISR0
BRSTS
CFDNS
⎯
SURSFS
SETCS
SETIS
⎯
VBUSFS
ISR1
⎯
⎯
⎯
SOFS
SETUPTSS
EPOoTSS
EPOiTRS
EPOiTSS
ISR2
⎯
⎯
EP3TRS
EP3TSS
EP2TRS
EP2EMPTYS
EP2ALLEMPS
EP1FULLS
EPDR0i
D7
D6
D5
D4
D3
D2
D1
D0
EPDR0o
D7
D6
D5
D4
D3
D2
D1
D0
Page 1254 of 1408
USB
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
EPDR0s
D7
D6
D5
D4
D3
D2
D1
D0
USB
EPDR1
D7
D6
D5
D4
D3
D2
D1
D0
EPDR2
D7
D6
D5
D4
D3
D2
D1
D0
EPDR3
D7
D6
D5
D4
D3
D2
D1
D0
EPSZ0o
⎯
⎯
⎯
D4
D3
D2
D1
D0
EPSZ1
⎯
D6
D5
D4
D3
D2
D1
D0
DASTS0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EP0iDE
DASTS1
⎯
⎯
⎯
⎯
⎯
EP3DE
EP2DE
⎯
TRG0
⎯
⎯
⎯
⎯
⎯
EP0sRDFN
EP0oRDFN
EP0iPKTE
TRG1
⎯
⎯
⎯
⎯
⎯
EP3PKTE
EP2PKTE
EP1RDFN
FCLR0
⎯
⎯
⎯
⎯
⎯
⎯
EP0oCLR
EP0iCLR
FCLR1
⎯
⎯
⎯
⎯
⎯
EP3CLR
EP2CLR
EP1CLR
EPSTL0
⎯
⎯
⎯
EP0STLC
⎯
⎯
⎯
EP0STLS
EPSTL1
⎯
EP3STLC
EP2STLC
EP1STLC
⎯
EP3STLS
EP2STLS
EP1STLS
STLSR1
⎯
EP3ASCE
EP2ASCE
EP1ASCE
⎯
EP3STLST
EP2STLST
EP1STLST
DMAR
⎯
⎯
⎯
⎯
⎯
⎯
EP1DMAE
EP2DMAE
CVR
CNFV1
CNFV0
INTV1
INTV0
⎯
ALTV2
ALTV1
ALTV0
CTLR
PULLUPE
⎯
⎯
RWUPS
RSME
PWMD
EP0ASCE
PRTRST
EPIR
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
TRNTREG0
PTSTE
⎯
⎯
⎯
SUSPEND
txenl
txse0
txdata
TRNTREG1
⎯
⎯
⎯
⎯
⎯
xver_data
dpls
dmns
RMMSTPCRH
MSTP47
MSTP46
MSTP45
MSTP44
MSTP43
MSTP42
MSTP41
MSTP40
RMMSTPCRL
MSTP39
MSTP38
MSTP37
MSTP36
MSTP35
MSTP34
MSTP33
MSTP32
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
SYSTEM
Page 1255 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
IPRL
⎯
IPRL14
IPRL13
IPRL12
⎯
IPRL10
IPRL9
IPRL8
INTC
⎯
IPRL6
IPRL5
IPRL4
⎯
IPRL2
IPRL1
IPRL0
⎯
IPRM14
IPRM13
IPRM12
⎯
IPRM10
IPRM9
IPRM8
⎯
IPRM6
IPRM5
IPRM4
⎯
IPRM2
IPRM1
IPRM0
IPRM
⎯
IPRN14
IPRN13
IPRN12
⎯
IPRN10
IPRN9
IPRN8
⎯
IPRN6
IPRN5
IPRN4
⎯
IPRN2
IPRN1
IPRN0
DTCERI
DTCEI7
DTCEI6
DTCEI5
DTCEI4
DTCEI3
DTCEI2
DTCEI1
DTCEI0
DTCCR
SWDTE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADDRA_1
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
IPRN
ADDRB_1
ADDRC_1
ADDRD_1
ADDRE_1
ADDRF_1
ADDRG_1
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
ADCSR_1
ADF
ADIE
ADST
EXCKS
CH3
CH2
CH1
CH0
ADCR_1
TRGS1
TRGS0
SCANE
SCANS
CKS1
CKS0
ADSTCLR
EXTRGS
TSTRB
⎯
⎯
CST11
CST10
CST9
CST8
CST7
CST6
TSYRB
⎯
⎯
SYNC11
SYNC10
SYNC9
SYNC8
SYNC7
SYNC6
ADDRH_1
TCR_6
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_6
⎯
⎯
BFB
BFA
MD3
MD2
MD1
MD0
TIORH_6
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
Page 1256 of 1408
A/D_1
TPU
TPU_6
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TIORL_6
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TPU_6
TIER_6
TTGE
⎯
⎯
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_6
⎯
⎯
⎯
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_6
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TGRA_6
TGRB_6
TGRC_6
TGRD_6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_7
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_7
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_7
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_7
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_7
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TCNT_7
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_7
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_8
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_8
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_8
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_8
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_8
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TCNT_8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TGRB_7
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
TPU_7
TPU_8
Page 1257 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TGRA_8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TPU_8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TGRB_8
TCR_9
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_9
⎯
⎯
BFB
BFA
MD3
MD2
MD1
MD0
TIORH_9
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_9
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TIER_9
TTGE
⎯
⎯
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_9
⎯
⎯
⎯
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_9
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_9
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_10
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_10
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_10
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_10
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_10
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TCNT_10
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TGRB_9
TGRC_9
TGRD_9
TGRA_10
TGRB_10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 1258 of 1408
TPU_9
TPU_10
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCR_11
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TPU_11
TMDR_11
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_11
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_11
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_11
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TCNT_11
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1ODR
P17ODR
P16ODR
P15ODR
P14ODR
P13ODR
P12ODR
P11ODR
P10ODR
P2ODR
P27ODR
P26ODR
P25ODR
⎯
⎯
⎯
⎯
P20ODR
P5ODR
⎯
⎯
⎯
⎯
P53ODR
P52ODR
P51ODR
P500DR
P6ODR
⎯
⎯
P65ODR
P64ODR
P63ODR
P62ODR
P61ODR
P60ODR
P8ODR
⎯
⎯
P85ODR
P84ODR
P83ODR
P82ODR
P81ODR
P80ODR
PBODR
PB7ODR
PB6ODR
PB5ODR
PB4ODR
PB3ODR
PB2ODR
PB1ODR
PB0ODR
PCODR
PC7ODR
PC6ODR
PC5ODR
PC4ODR
PC3ODR
PC2ODR
PC1ODR
PC0ODR
PDODR
PD7ODR
PD6ODR
PD5ODR
PD4ODR
PD3ODR
PD2ODR
PD1ODR
PD0ODR
PEODR
PE7ODR
PE6ODR
PE5ODR
PE4ODR
PE3ODR
PE2ODR
PE1ODR
PE0ODR
PFODR
PF7ODR
PF6ODR
PF5ODR
PF4ODR
PF3ODR
PF2ODR
PF1ODR
PF0ODR
PGODR
⎯
PG6ODR
PG5ODR
PG4ODR
PG3ODR
PG2ODR
PG1ODR
PG0ODR
PHODR
⎯
⎯
⎯
⎯
PH3ODR
PH2ODR
PH1ODR
PH0ODR
PJODR
⎯
⎯
⎯
⎯
⎯
⎯
PJ1ODR
PJ0ODR
ICCRA_0
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
ICCRB_0
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
⎯
ICMR_0
⎯
WAIT
⎯
⎯
BCWP
BC2
BC1
BC0
ICIER_0
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR_0
TDRE
TEND
RDRF
NACKF
STOP
AL
AAS
ADZ
SAR_0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
⎯
ICDRT_0
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
ICDRR_0
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
TGRA_11
TGRB_11
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
PORT
IIC2_0
Page 1259 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
ICCRA_1
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
IIC2_1
ICCRB_1
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
⎯
ICMR_1
⎯
WAIT
⎯
⎯
BCWP
BC2
BC1
BC0
ICIER_1
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR_1
TDRE
TEND
RDRF
NACKF
STOP
AL
AAS
ADZ
SAR_1
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
⎯
ICDRT_1
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
ICDRR_1
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
ICCRA_2
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
ICCRB_2
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
⎯
ICMR_2
⎯
WAIT
⎯
⎯
BCWP
BC2
BC1
BC0
ICIER_2
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR_2
TDRE
TEND
RDRF
NACKF
STOP
AL
AAS
ADZ
SAR_2
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
⎯
ICDRT_2
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
ICDRR_2
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
ICCRA_3
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
ICCRB_3
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
⎯
ICMR_3
⎯
WAIT
⎯
⎯
BCWP
BC2
BC1
BC0
ICIER_3
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR_3
TDRE
TEND
RDRF
NACKF
STOP
AL
AAS
ADZ
SAR_3
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
⎯
ICDRT_3
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
ICDRR_3
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
SEMR_2
⎯
⎯
⎯
⎯
ABCS
ACS2
ACS1
ACS0
SCI_2
SSCRH
MSS
BIDE
⎯
SOL
SOLP
SCKS
CSS1
CSS0
SSU
SSCRL
⎯
SSUMS
SRES
⎯
⎯
⎯
DATS1
DATS0
SSMR
MLS
CPOS
CPHS
⎯
⎯
CKS2
CKS1
CKS0
SSER
TE
RE
⎯
⎯
TEIE
TIE
RIE
CEIE
SSSR
⎯
ORER
⎯
⎯
TEND
TDRE
RDRF
CE
SSCR2
SDOS
SSCKOS
SCSOS
TENDSTS
SCSATS
SSODTS
⎯
⎯
Page 1260 of 1408
IIC2_2
IIC2_3
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
SSTDR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSU
SSTDR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSTDR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSTDR3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSRDR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSRDR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSRDR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSRDR3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDSAR_2
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDDAR_2
EDTCR_2
EDMDR_2
EDACR_2
EDSAR_3
7
EXDMAC_2*
EDA
BEF
EDRAKE
ETENDE
EDREQS
AMS
MDS1
MDS0
EDIE
IRF
TCEIE
SDIR
DTSIZE
BGUP
⎯
⎯
SAT1
SAT0
SARIE
SARA4
SARA3
SARA2
SARA1
SARA0
DAT1
DAT0
DARIE
DARA4
DARA3
DARA2
DARA1
DARA0
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
EXDMAC_3*7
Page 1261 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
EDDAR_3
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
EXDMAC_3*7
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EDA
BEF
EDRAKE
ETENDE
EDREQS
AMS
MDS1
MDS0
EDIE
IRF
TCEIE
SDIR
DTSIZE
BGUP
⎯
⎯
SAT1
SAT0
SARIE
SARA4
SARA3
SARA2
SARA1
SARA0
EDTCR_3
EDMDR_3
EDACR_3
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
DAT1
DAT0
DARIE
DARA4
DARA3
DARA2
DARA1
DARA0
⎯
IPRA14
IPRA13
IPRA12
⎯
IPRA10
IPRA9
IPRA8
⎯
IPRA6
IPRA5
IPRA4
⎯
IPRA2
IPRA1
IPRA0
⎯
IPRB14
IPRB13
IPRB12
⎯
IPRB10
IPRB9
IPRB8
⎯
IPRB6
IPRB5
IPRB4
⎯
IPRB2
IPRB1
IPRB0
⎯
IPRC14
IPRC13
IPRC12
⎯
IPRC10
IPRC9
IPRC8
⎯
IPRC6
IPRC5
IPRC4
⎯
IPRC2
IPRC1
IPRC0
⎯
IPRD14
IPRD13
IPRD12
⎯
IPRD10
IPRD9
IPRD8
⎯
IPRD6
IPRD5
IPRD4
⎯
IPRD2
IPRD1
IPRD0
⎯
IPRE14
IPRE13
IPRE12
⎯
IPRE10
IPRE9
IPRE8
⎯
IPRE6
IPRE5
IPRE4
⎯
IPRE2
IPRE1
IPRE0
⎯
IPRF14
IPRF13
IPRF12
⎯
IPRF10
IPRF9
IPRF8
⎯
IPRF6
IPRF5
IPRF4
⎯
IPRF2
IPRF1
IPRF0
⎯
IPRG14
IPRG13
IPRG12
⎯
IPRG10
IPRG9
IPRG8
⎯
IPRG6
IPRG5
IPRG4
⎯
IPRG2
IPRG1
IPRG0
⎯
IPRH14
IPRH13
IPRH12
⎯
IPRH10
IPRH9
IPRH8
⎯
IPRH6
IPRH5
IPRH4
⎯
IPRH2
IPRH1
IPRH0
⎯
IPRI14
IPRI13
IPRI12
⎯
IPRI10
IPRI9
IPRI8
⎯
IPRI6
IPRI5
IPRI4
⎯
IPRI2
IPRI1
IPRI0
Page 1262 of 1408
INT
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
IPRJ
⎯
IPRJ14
IPRJ13
IPRJ12
⎯
IPRJ10
IPRJ9
IPRJ8
INT
⎯
IPRJ6
IPRJ5
IPRJ4
⎯
IPRJ2
IPRJ1
IPRJ0
⎯
IPRK14
IPRK13
IPRK12
⎯
IPRK10
IPRK9
IPRK8
⎯
IPRK6
IPRK5
IPRK4
⎯
IPRK2
IPRK1
IPRK0
IPRK
ITSR
SSIER
ISCRH
ISCRL
ITS15
ITS14
ITS13
⎯
⎯
⎯
⎯
ITS8
ITS7
ITS6
ITS5
ITS4
ITS3
ITS2
ITS1
ITS0
SSI15
SSI14
SSI13
SSI12
SSI11
SSI10
SSI9
SSI8
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
IRQ15SCB
IRQ15SCA
IRQ14SCB
IRQ14SCA
IRQ13SCB
IRQ13SCA
IRQ12SCB
IRQ12SCA
IRQ11SCB
IRQ11SCA
IRQ10SCB
IRQ10SCA
IRQ9SCB
IRQ9SCA
IRQ8SCB
IRQ8SCA
IRQ7SCB
IRQ7SCA
IRQ6SCB
IRQ6SCA
IRQ5SCB
IRQ5SCA
IRQ4SCB
IRQ4SCA
IRQ3SCB
IRQ3SCA
IRQ2SCB
IRQ2SCA
IRQ1SCB
IRQ1SCA
IRQ0SCB
IRQ0SCA
IrCR_0
IrE
IrCKS2
IrCKS1
IrCKS0
IrTxINV
IrRxINV
⎯
⎯
IrDA
P1DDR
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
PORT
P2DDR
P27DDR
P26DDR
P25DDR
⎯
⎯
⎯
⎯
P20DDR
P3DDR
⎯
⎯
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
P5DDR
⎯
⎯
⎯
⎯
P53DDR
P52DDR
P51DDR
P50DDR
P6DDR
⎯
⎯
P65DDR
P64DDR
P63DDR
P62DDR
P61DDR
P60DDR
P8DDR
⎯
⎯
P85DDR
P84DDR
P83DDR
P82DDR
P81DDR
P80DDR
PADDR
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
PBDDR
PB7DDR
PB6DDR
PB5DDR
PB4DDR
PB3DDR
PB2DDR
PB1DDR
PB0DDR
PCDDR
PC7DDR
PC6DDR
PC5DDR
PC4DDR
PC3DDR
PC2DDR
PC1DDR
PC0DDR
PDDDR
PD7DDR
PD6DDR
PD5DDR
PD4DDR
PD3DDR
PD2DDR
PD1DDR
PD0DDR
PEDDR
PE7DDR
PE6DDR
PE5DDR
PE4DDR
PE3DDR
PE2DDR
PE1DDR
PE0DDR
PFDDR
PF7DDR
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR
PF1DDR
PF0DDR
PGDDR
⎯
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
PFCR0
CS7E
CS6E
CS5E
CS4E
CS3E
CS2E
CS1E
CS0E
PFCR1
A23E
A22E
A21E
A20E
A19E
A18E
A17E
A16E
PFCR2
⎯
⎯
⎯
⎯
ASOE
LWROE
OES
⎯
PAPCR
PA7PCR
PA6PCR
PA5PCR
PA4PCR
PA3PCR
PA2PCR
PA1PCR
PA0PCR
PBPCR
PB7PCR
PB6PCR
PB5PCR
PB4PCR
PB3PCR
PB2PCR
PB1PCR
PB0PCR
PCPCR
PC7PCR
PC6PCR
PC5PCR
PC4PCR
PC3PCR
PC2PCR
PC1PCR
PC0PCR
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1263 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PDPCR
PD7PCR
PD6PCR
PD5PCR
PD4PCR
PD3PCR
PD2PCR
PD1PCR
PD0PCR
PORT
PEPCR
PE7PCR
PE6PCR
PE5PCR
PE4PCR
PE3PCR
PE2PCR
PE1PCR
PE0PCR
P3ODR
⎯
⎯
P35ODR
P34ODR
P33ODR
P32ODR
P31ODR
P30ODR
PA7ODR
PA6ODR
PA5ODR
PA4ODR
PA3ODR
PA2ODR
PA1ODR
PA0ODR
PAODR
SMR_3*
4
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SMR_3*5
GM
BLK
PE
O/E
BCP1
BCP0
CKS1
CKS0
BRR_3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCR_3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
SCI_3,
Smartcard
interface_3
TDR_3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR_3*
4
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SSR_3*
5
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCMR_3
BCP2
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
SMR_4*4
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SMR_4*5
GM
BLK
PE
O/E
BCP1
BCP0
CKS1
CKS0
BRR_4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCR_4
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
RDR_3
SCI_4,
Smartcard
interface_4
TDR_4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR_4*
4
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SSR_4*
5
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
RDR_4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCMR_4
BCP2
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
TCR_3
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_3
⎯
⎯
BFB
BFA
MD3
MD2
MD1
MD0
TIORH_3
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_3
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TIER_3
TTGE
⎯
⎯
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_3
⎯
⎯
⎯
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_3
TGRA_3
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 1264 of 1408
TPU_3
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TGRB_3
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TPU_3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TGRC_3
TGRD_3
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_4
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_4
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_4
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_4
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_4
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TCNT_4
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_5
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_5
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_5
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_5
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_5
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TCNT_5
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FLMCR1
⎯
CBIDB
⎯
⎯
⎯
⎯
⎯
FMCMDEN
FLMDBPR
⎯
⎯
⎯
⎯
⎯
⎯
⎯
FMDBPT0
FLMSTR
⎯
⎯
FMERSF
⎯
FMPRSF
⎯
⎯
FMRDY
TGRA_4
TGRB_4
TGRA_5
TGRB_5
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
TPU_4
TPU_5
FLASH
Page 1265 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
ABWCR
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
BSC
ASTCR
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
WTCRAH
⎯
W72
W71
W70
⎯
W62
W61
W60
WTCRAL
⎯
W52
W51
W50
⎯
W42
W41
W40
WTCRBH
⎯
W32
W31
W30
⎯
W22
W21
W20
WTCRBL
⎯
W12
W11
W10
⎯
W02
W01
W00
RDNCR
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
CSACRH
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
CSACRL
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
BROMCRH
BSRM0
BSTS02
BSTS01
BSTS00
⎯
⎯
BSWD01
BSWD00
BROMCRL
BSRM1
BSTS12
BSTS11
BSTS10
⎯
⎯
BSWD11
BSWD10
BCR
BRLE
BREQOE
⎯
IDLC
ICIS1
ICIS0
WDBE
WAITE
⎯
⎯
⎯
⎯
⎯
ICIS2
⎯
⎯
MPXCR
MPXE
⎯
⎯
⎯
⎯
⎯
⎯
ADDEX
DRAMCR
OEE
RAST
⎯
CAST
⎯
RMTS2
RMTS1
RMTS0
BE
RCDM
DDS
EDDS
⎯
MXC2
MXC1
MXC0
DRMI
⎯
TPC1
TPC0
SDWCD
⎯
RCD1
RCD0
⎯
⎯
⎯
⎯
CKSPE
⎯
RDXC1
RDXC0
CMF
CMIE
RCW1
RCW0
⎯
RTCK2
RTCK1
RTCK0
RFSHE
CBRM
RLW1
RLW0
SLFRF
TPCS2
TPCS1
TPCS0
DRACCR
REFCR
RTCNT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RTCOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MAR_0AH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MAR_0AL
IOAR_0A
ETCR_0A
MAR_0BH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 1266 of 1408
DMAC
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MAR_0BL
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
DMAC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOAR_0B
ETCR_0B
MAR_1AH
MAR_1AL
IOAR_1A
ETCR_1A
MAR_1BH
MAR_1BL
IOARV1B
ETCR_1B
DMAWER
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
⎯
⎯
⎯
⎯
WE1B
WE1A
WE0B
WE0A
⎯
⎯
TEE1
TEE0
⎯
⎯
⎯
⎯
2
DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
3
DTSZ
SAID
SAIDE
BLKDIR
BLKE
⎯
⎯
⎯
2
DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
3
⎯
DAID
DAIDE
⎯
DTF3
DTF2
DTF1
DTF0
DMACR_1A*
2
DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
DMACR_1A*3
DTSZ
SAID
SAIDE
BLKDIR
BLKE
⎯
⎯
⎯
DMACR_1B*2
DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
⎯
DAID
DAIDE
⎯
DTF3
DTF2
DTF1
DTF0
DMATCR
DMACR_0A*
DMACR_0A*
DMACR_0B*
DMACR_0B*
3
DMACR_1B*
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1267 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
DMABCRH*
2
FAE1
FAE0
SAE1
SAE0
DTA1B
DTA1A
DTA0B
DTA0A
DMAC
DMABCRH*
3
FAE1
FAE0
⎯
⎯
DTA1
⎯
DTA0
⎯
DMABCRL*
2
DTE1B
DTE1A
DTE0B
DTE0A
DTIE1B
DTIE1A
DTIE0B
DTIE0A
DMABCRL*
3
DTME1
DTE1
DTME0
DTE0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
DTCERA
DTCEA7
DTCEA6
DTCEA5
DTCEA4
DTCEA3
DTCEA2
DTCEA1
DTCEA0
DTCERB
DTCEB7
DTCEB6
DTCEB5
DTCEB4
DTCEB3
DTCEB2
DTCEB1
DTCEB0
DTCERC
DTCEC7
DTCEC6
DTCEC5
DTCEC4
DTCEC3
DTCEC2
DTCEC1
DTCEC0
DTCERD
DTCED7
DTCED6
DTCED5
DTCED4
DTCED3
DTCED2
DTCED1
DTCED0
DTCERE
DTCEE7
DTCEE6
DTCEE5
DTCEE4
DTCEE3
DTCEE2
DTCEE1
DTCEE0
DTCERF
DTCEF7
DTCEF6
DTCEF5
DTCEF4
DTCEF3
DTCEF2
DTCEF1
DTCEF0
DTCERG
DTCEG7
DTCEG6
DTCEG5
DTCEG4
DTCEG3
DTCEG2
DTCEG1
DTCEG0
DTCERH
DTCEH7
DTCEH6
DTCEH5
DTCEH4
DTCEH3
DTCEH2
DTCEH1
DTCEH0
DTVECR
DTVEC7
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
INTCR
⎯
⎯
INTM1
INTM0
NMIEG
⎯
⎯
⎯
IER
IRQ15E
IRQ14E
IRQ13E
IRQ12E
IRQ11E
IRQ10E
IRQ9E
IRQ8E
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
SBYCR
SSBY
OPE
⎯
⎯
STS3
STS2
STS1
STS0
SCKCR
PSTOP
⎯
SDPSTP
⎯
STCS
⎯
⎯
⎯
SYSCR
⎯
⎯
MACS
⎯
FLSHE
⎯
EXPE
RAME
MDCR
⎯
⎯
⎯
⎯
⎯
MDS2
MDS1
MDS0
MSTPCRH
ACSE
MSTP14
MSTP13
MSTP12
MSTP11
MSTP10
MSTP9
MSTP8
MSTPCRL
MSTP7
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
EXMSTPCRH
MSTP31
MSTP30
MSTP29
MSTP28
MSTP27
MSTP26
MSTP25
MSTP24
EXMSTPCRL
MSTP23
MSTP22
MSTP21
MSTP20
MSTP19
MSTP18
MSTP17
MSTP16
PLLCR
⎯
⎯
⎯
⎯
⎯
⎯
STC1
STC0
PCR
G3CMS1
G3CMS0
G2CMS1
G2CMS0
G1CMS1
G1CMS0
G0CMS1
G0CMS0
ISR
PMR
G3INV
G2INV
G1INV
G0INV
G3NOV
G2NOV
G1NOV
G0NOV
NDERH
NDER15
NDER14
NDER13
NDER12
NDER11
NDER10
NDER9
NDER8
NDERL
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
PODRH
POD15
POD14
POD13
POD12
POD11
POD10
POD9
POD8
Page 1268 of 1408
DTC
INT
SYSTEM
PPG
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PODRL
POD7
POD6
POD5
POD4
POD3
POD2
POD1
POD0
PPG
6
NDRHH*
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
6
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
NDRHL*
6
⎯
⎯
⎯
⎯
NDR11
NDR10
NDR9
NDR8
NDRLL*
6
⎯
⎯
⎯
⎯
NDR3
NDR2
NDR1
NDR0
PORT1
P17
P16
P15
P14
P13
P12
P11
P10
PORT2
P27
P26
P25
⎯
⎯
⎯
⎯
P20
PORT3
⎯
⎯
P35
P34
P33
P32
P31
P30
PORT4
P47
P46
P45
P44
P43
P42
P41
P40
PORT5
⎯
⎯
⎯
⎯
P53
P52
P51
P50
PORT6
⎯
⎯
P65
P64
P63
P62
P61
P60
PORT8
⎯
⎯
P85
P84
P83
P82
P81
P80
PORT9
P97
P96
P95
P94
P93
P92
P91
P90
PORTA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORTC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PORTD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PORTE
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORTF
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PORTG
⎯
PG6
PG5
PG4
PG3
PG2
PG1
PG0
NDRLH*
PORT
P1DR
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
P2DR
P27DR
P26DR
P25DR
⎯
⎯
⎯
⎯
P20DR
P3DR
⎯
⎯
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
P5DR
⎯
⎯
⎯
⎯
P53DR
P52DR
P51DR
P50DR
P6DR
⎯
⎯
P65DR
P64DR
P63DR
P62DR
P61DR
P60DR
P8DR
⎯
⎯
P85DR
P84DR
P83DR
P82DR
P81DR
P80DR
PADR
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
PBDR
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
PCDR
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
PDDR
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
PEDR
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
PFDR
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1269 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PGDR
⎯
PG6DR
PG5DR
PG4DR
PG3DR
PG2DR
PG1DR
PG0DR
PORT
PORTH
⎯
⎯
⎯
⎯
PH3
PH2
PH1
PH0
PORTJ
⎯
⎯
⎯
⎯
⎯
PJ2
PJ1
PJ0
PHDR
⎯
⎯
⎯
⎯
PH3DR
PH2DR
PH1DR
PH0DR
PJDR
⎯
⎯
⎯
⎯
⎯
⎯
PJ1DR
PJ0DR
PHDDR
⎯
⎯
⎯
⎯
PH3DDR
PH2DDR
PH1DDR
PH0DDR
⎯
⎯
⎯
⎯
⎯
⎯
PJ1DDR
PJ0DDR
4
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SMR_0*
5
GM
BLK
PE
O/E
BCP1
BCP0
CKS1
CKS0
BRR_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCR_0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
PJDDR
SMR_0*
SCI_0, Smart
card
interface_0
TDR_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SSR_0*5
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
RDR_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR_0*
BCP2
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
4
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SMR_1*
5
GM
BLK
PE
O/E
BCP1
BCP0
CKS1
CKS0
BRR_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCR_1
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
SCMR_0
SMR_1*
SCI_1, Smart
card
interface_1
TDR_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR_1*4
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SSR_1*5
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
RDR_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BCP2
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
4
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SMR_2*
5
GM
BLK
PE
O/E
BCP1
BCP0
CKS1
CKS0
BRR_2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCR_2
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR_2*4
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SCMR_1
SMR_2*
SCI_2, Smart
card
interface_2
Page 1270 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
SSR_2*
TDRE
RDRF
ORER
ERS
PER
TEND
MPB
MPBT
SCI_2, Smart
RDR_2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCMR_2
BCP2
⎯
⎯
⎯
SDIR
SINV
⎯
SMIF
ADDRA_0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
⎯
⎯
⎯
⎯
⎯
⎯
ADCSR_0
ADF
ADIE
ADST
⎯
CH3
CH2
CH1
CH0
ADCR_0
TRGS1
TRGS0
SCANE
SCANS
CKS1
CKS0
⎯
⎯
DADR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DADR3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DACR23
DAOE3
DAOE2
DAE
⎯
⎯
⎯
⎯
⎯
TCR_0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TMR_0
TCR_1
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TMR_1
TCSR_0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
TCSR_1
CMFB
CMFA
OVF
⎯
OS3
OS2
OS1
OS0
TCORA_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCORA_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCORB_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCORB_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5
card
interface_2
ADDRB_0
ADDRC_0
ADDRD_0
ADDRE_0
ADDRF_0
ADDRG_0
ADDRH_0
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
A/D_0
D/A
Page 1271 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCNT_0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR_0
TCNT_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR_1
TCCR0
⎯
⎯
⎯
⎯
TMRIS
⎯
ICKS1
ICKS0
8-bit
TCCR1
⎯
⎯
⎯
⎯
TMRIS
⎯
ICKS1
ICKS0
TCSR
OVF
WT/IT
TME
⎯
⎯
CKS2
CKS1
CKS0
TCNT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSTCSR
WOVF
RSTE
⎯
⎯
⎯
⎯
⎯
⎯
TSTR
⎯
⎯
CST5
CST4
CST3
CST2
CST1
CST0
TSYR
⎯
⎯
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
PFCR3
⎯
PPGS
TPUS
TMRS
⎯
⎯
USBDRQE
⎯
PFCR4
WAITS
BREQS
BACKS
BREQOS
⎯
TXD4S
RXD4S
SCK4S
PFCR5
SSO0S1
SSO0S0
SSI0S1
SSI0S0
SSCK0S1
SSCK0S0
SCS0S1
SCS0S0
TCR_0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_0
⎯
⎯
BFB
BFA
MD3
MD2
MD1
MD0
TIORH_0
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_0
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TIER_0
TTGE
⎯
⎯
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_0
⎯
⎯
⎯
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TGRA_0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_1
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_1
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_1
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_1
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TGRB_0
TGRC_0
TGRD_0
Page 1272 of 1408
TMR
WDT
TPU
PORT
TPU_0
TPU_1
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TSR_1
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TPU_1
TCNT_1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TGRA_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCR_2
⎯
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_2
⎯
⎯
⎯
⎯
MD3
MD2
MD1
MD0
TIOR_2
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_2
TTGE
⎯
TCIEU
TCIEV
⎯
⎯
TGIEB
TGIEA
TSR_2
TCFD
⎯
TCFU
TCFV
⎯
⎯
TGFB
TGFA
TGRB_1
TCNT_2
TGRA_2
TGRB_2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TPU_2
Notes: 1. Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
2. For short address mode
3. For full address mode
4. For normal mode
5. For smart card interface mode
6. If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
7. Not supported by the H8S/2454 Group.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1273 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
25.3
Register States in Each Operating Mode
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
MRA
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTC
SAR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MRB
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DAR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
CRA
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
CRB
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IFR0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IFR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IFR2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IER0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IER1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IER2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ISR0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ISR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ISR2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPDR0i
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPDR0o
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPDR0s
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPDR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPDR2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPDR3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPSZ0o
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPSZ1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DASTS0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DASTS1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TRG0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TRG1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
FCLR0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
FCLR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPSTL0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Page 1274 of 1408
Software
Hardware
USB
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
EPSTL1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
USB
STLSR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMAR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
CVR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
CTLR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EPIR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TRNTREG0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TRNTREG1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
RMMSTPCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
RMMSTPCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRM
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRN
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERI
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRA_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRB_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRC_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRD_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRE_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRF_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRG_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRH_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADCSR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADCR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSTRB
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSYRB
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORH_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORL_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Software
Hardware
SYSTEM
INT
DTC
A/D_1
TPU
TPU_6
Page 1275 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
TSR_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TPU_6
TCNT_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRC_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRD_6
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_7
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_8
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORH_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORL_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRC_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Page 1276 of 1408
Software
Hardware
TPU_7
TPU_8
TPU_9
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
TGRD_9
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TPU_9
TCR_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TPU_10
TMDR_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_10
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_11
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P1ODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P2ODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P5ODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P6ODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P8ODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PBODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PCODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PDODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PEODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PGODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PHODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PJODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Software
Hardware
TPU_11
PORT
Page 1277 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
ICCRA_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IIC2_0
ICCRB_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICMR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICIER_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICSR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SAR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRT_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICCRA_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICCRB_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICMR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICIER_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICSR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SAR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRT_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICCRA_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICCRB_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICMR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICIER_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICSR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SAR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRT_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICCRA_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICCRB_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICMR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICIER_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICSR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SAR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRT_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ICDRR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Page 1278 of 1408
Software
Hardware
IIC2_1
IIC2_2
IIC2_3
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
SEMR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCI_2
SSCRH
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSU
SSCRL
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSMR
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSER
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSSR
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSCR2
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSTDR0
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSTDR1
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSTDR2
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSTDR3
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSRDR0
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSRDR1
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSRDR2
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSRDR3
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
EDSAR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDDAR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDTCR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDMDR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDACR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDSAR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDDAR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDTCR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDMDR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EDACR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRA
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRB
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRC
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRD
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRE
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRF
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRG
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Software
Hardware
EXDMAC_2*
EXDMAC_3*
INT
Page 1279 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
IPRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
INT
IPRI
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRJ
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IPRK
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ITSR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SSIER
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ISCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ISCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IrCR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IrDA
P1DDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PORT
P2DDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P3DDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P5DDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P6DDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P8DDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PADDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PBDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PCDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PDDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PEDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PGDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFCR0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFCR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFCR2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PAPCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PBPCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PCPCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PDPCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PEPCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P3ODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PAODR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Page 1280 of 1408
Software
Hardware
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
SMR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCI_3
BRR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TDR_3
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSR_3
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
RDR_3
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SCMR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SMR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
BRR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TDR_4
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSR_4
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
RDR_4
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SCMR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORH_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORL_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRC_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRD_3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Software
Hardware
SCI_4
TPU_3
TPU_4
Page 1281 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
TGRB_4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TPU_4
TCR_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TPU_5
TMDR_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
FLMCR1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DFPR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
FLMSTR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ABWCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ASTCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
WTCRAH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
WTCRAL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
WTCRBH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
WTCRBL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
RDNCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
CSACRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
CSACRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
BROMCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
BROMCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
BCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MPXCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DRAMCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DRACCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DRACCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
REFCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
RTCNT
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
RTCOR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Page 1282 of 1408
Software
Hardware
FLASH
BSC
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
MAR_0AH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMAC
MAR_0AL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IOAR_0A
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ETCR_0A
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MAR_0BH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MAR_0BL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IOAR_0B
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ETCR_0B
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MAR_1AH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MAR_1AL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IOAR_1A
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ETCR_1A
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MAR_1BH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MAR_1BL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
IOAR_1B
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ETCR_1B
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMAWER
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMATCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMACR_0A
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMACR_0B
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMACR_1A
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMACR_1B
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMABCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DMABCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERA
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERB
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERC
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERD
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERE
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERF
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERG
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTCERH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Software
Hardware
DTC
Page 1283 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
DTVECR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DTC
INTCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
INT
IER
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ISR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SBYCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCKCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SYSCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MDCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MSTPCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
MSTPCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EXMSTPCRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
EXMSTPCRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PLLCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PCR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PMR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
NDERH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
NDERL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PODRH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PODRL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
NDRHH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
NDRLH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
NDRHL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
NDRLL
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PORT1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT3
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT6
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT9
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORTA
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Page 1284 of 1408
Software
Hardware
SYSTEM
PPG
PORT
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
PORTB
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORT
PORTC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORTD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORTE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORTF
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PORTG
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P1DR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P2DR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P3DR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P5DR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P6DR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
P8DR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PADR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PBDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PCDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PEDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PGDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PORTH
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PHDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PJDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PHDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PJDDR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SMR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
BRR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TDR_0
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSR_0
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
RDR_0
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SCMR_0
Initialized
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
⎯
Software
Hardware
SCI_0
Page 1285 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
SMR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCI_1
BRR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TDR_1
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSR_1
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
RDR_1
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SCMR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SMR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
BRR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
SCR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TDR_2
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SSR_2
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
RDR_2
Initialized
⎯
⎯
⎯
Initialized Initialized
Initialized
Initialized
SCMR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRA_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRB_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRC_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRD_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRE_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRF_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRG_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADDRH_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADCSR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
ADCR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DADR2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DADR3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
DACR23
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Page 1286 of 1408
Software
Hardware
SCI_2
A/D_0
D/A
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Register
Section 25 List of Registers
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
TCR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMR_0
TCR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMR_1
TCSR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCSR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCORA_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCORA_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCORB_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCORB_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCCR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCCR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCSR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
RSTCSR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TSTR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSYR
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFCR3
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFCR4
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
PFCR5
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORH_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIORL_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRC_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRD_0
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Software
Hardware
TMR
WDT
TPU
PORT
TPU_0
Page 1287 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 25 List of Registers
Register
High-
Clock
Module
All Module
Abbreviation
Reset
Speed
Division
Sleep
Stop
Clock Stop Standby
Standby
Module
TMDR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TPU_0
TIOR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_1
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TMDR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIOR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TIER_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TSR_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TCNT_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRA_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
TGRB_2
Initialized
⎯
⎯
⎯
⎯
⎯
⎯
Initialized
Note:
*
Software
Hardware
TPU_1
TPU_2
Not supported by the H8S/2454 Group.
Page 1288 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Section 26 Electrical Characteristics
26.1
Electrical Characteristics for H8S/2456 Group and
H8S/2456R Group
26.1.1
Absolute Maximum Ratings
Table 26.1 lists the absolute maximum ratings.
Table 26.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
−0.3 to +4.3
V
PLLVCC
DrVCC
Input voltage (except ports 4, 9, 2, P32 to
P35, P50, P51, and PJ0 to PJ2)
Vin
−0.3 to VCC +0.3
V
Input voltage (ports 2, P32 to P35, P50,
P51, and PJ0 to PJ2)
Vin
−0.3 to +6.5
V
Input voltage (ports 4 and 9)
Vin
−0.3 to AVCC +0.3
V
Reference power supply voltage
Vref
−0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
−0.3 to +4.3
V
Analog input voltage
VAN
−0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications:
−20 to +75*
°C
Wide-range specifications:
−40 to +85*
°C
−55 to +125
°C
Storage temperature
Caution:
Note: *
Tstg
Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Ranges of operating temperature when flash memory is programmed/erased:
Regular specifications: 0 to +75°C
Wide-range specifications: 0 to +85°C
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1289 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
26.1.2
DC Characteristics
Table 26.2 DC Characteristics (1)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*1
Typ.
Max.
Test
Unit Conditions
⎯
⎯
V
⎯
VCC × 0.7
V
⎯
⎯
V
VCC × 0.9
⎯
VCC +0.3
V
RES, NMI, FWE
VCC × 0.9
⎯
VCC +0.3
V
EXTAL
VCC × 0.7
⎯
VCC +0.3
V
P14 to P17*5,
P25*5, P26*5,
port 3*3,
P50 to P53*3,
3
3
ports 6* and 8* ,
3
*
ports A to J
2.2
⎯
VCC +0.3
V
Port 4, Port 9
2.2
⎯
AVCC +0.3
V
−0.3
⎯
VCC × 0.1
V
NMI, EXTAL
−0.3
⎯
VCC × 0.2
V
P14 to P17*5,
P25*5, P26*5,
3
3
ports 3* , 5* ,
3
*
and 6 ,
port 8*3,
3
ports A to J*
−0.3
⎯
VCC × 0.2
V
Port 4, Port 9
−0.3
⎯
AVCC +0.2
V
Item
Symbol
Min.
Schmitt
Port 1*6, port 2*6, VT−
VCC × 0.2
trigger input P32 to P35*2,
+
VT
⎯
2
voltage
P50 to P53* ,
+
−
2
2
*
port 6 , port 8* , VT − VT VCC × 0.07
2
PA4 to PA7* ,
2
port B* ,
2
2
port C* , PF1* ,
2
2
*
*
PF2 , PH2 ,
2
PH3*
Input high
voltage
Input low
voltage
STBY,
MD2 to MD0
RES, STBY,
MD2 to MD0,
EMLE
Page 1290 of 1408
VIH
VIL
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol
Min.
Typ.
Max.
Test
Unit Conditions
Output high All output pins
voltage
VOH
VCC − 0.3
⎯
⎯
V
IOH = −200 μA
VCC − 0.5
⎯
⎯
V
IOH = −1 mA
VCC − 0.8
⎯
⎯
V
IOH = −2 mA
⎯
⎯
0.4
V
IOL = 4.0 mA
⎯
⎯
0.4
V
IOL = 8.0 mA
⎯
⎯
10.0
μA
STBY, NMI,
MD2 to MD0
⎯
⎯
1.0
μA
Vin = 0.5 to
VCC −0.5 V
Port 4, Port 9
⎯
⎯
1.0
μA
Output low
voltage
All output pins
4
P26 to P27* ,
P32 to P35*4,
P50 to P51*4
VOL
Input
leakage
current
RES
|Iin|
Vin = 0.5 to
AVCC −0.5 V
Notes: Port 2, P32 to P35, P50, P51, PJ0 to PJ2 are 5-V-tolerant pins.
1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not
be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
2. When used as IRQ, TIOC, TCLK, TMRI, SCL, or SDA.
3. When used as other than IRQ, TIOC, TCLK, TMRI, SCL, or SDA.
4. When used as SCL or SDA.
5. When used as SSO, SSI, SSCK, SCS, WAIT, or ADTRG1.
6. When used as other than SSO, SSI, SSCK, SCS, WAIT, or ADTRG1.
R01UH0309EJ0500 Rev. 5.00
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Page 1291 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Table 26.3 DC Characteristics (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*1
Item
Symbol Min.
Typ.
Max.
Test
Unit Conditions
Three-state
leakage
current
(off state)
Ports 1 to 3,
P50 to P53,
ports 6 and 8,
ports A to I
| ITSI |
⎯
⎯
1.0
μA
Vin = 0.5 to
VCC −0.5 V
Input pull-up
MOS current
Ports A to E
−Ip
10
⎯
300
μA
VCC = 3.0 to
3.6 V
Vin = 0 V
Input
capacitance
Supply
current*2
RES
⎯
⎯
30
pF
Vin = 0 V
NMI
⎯
⎯
30
pF
f = 1 MHz
All input pins
except RES
and NMI
⎯
⎯
18
pF
Ta = 25°C
Normal operation ICC*4
⎯
45
60
(3.3 V)
mA
f = 33 MHz
Sleep mode
⎯
35
45
(3.3 V)
mA
f = 33 MHz
Standby mode*3
⎯
20
80
μA
Ta ≤ 50°C
⎯
80
500
μA
50°C < Ta
⎯
0.5
2.0
(3.3 V)
mA
When channel
1 is in use
⎯
0.01
5.0
μA
When channel
1 is in use
⎯
0.5
1.0
(3.3 V)
mA
⎯
0.01
5.0
μA
2.5
⎯
⎯
V
Analog power During A/D and
supply current D/A conversion
Cin
AICC
Idle
Reference
power supply
current
During A/D and
D/A conversion
AICC
Idle
RAM standby voltage
V start voltage*5
VCC start
⎯
⎯
0.3
V
VCC rising slope*5
SVCC
⎯
⎯
20
ms/V
CC
VRAM
Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not
be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
2. Supply current values are for VIHmin = VCC −0.2 V and VILmax = 0.2 V with all output pins
unloaded and all input pull-up MOSs in the off state.
Page 1292 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 5.2 (mA) + 1.66 (mA/(MHz)) × f (normal operation)
ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode)
5. Applied when RES is low at power-on.
Table 26.4 Permissible Output Currents
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*
Item
Symbol
Min.
Typ.
Max.
Unit
IOL
⎯
⎯
4.0
mA
I C output pins
IOL
⎯
⎯
8.0
mA
Permissible output low
current (total)
Total of all output
pins
ΣIOL
⎯
⎯
80
mA
Permissible output high
current (per pin)
All output pins
−IOH
⎯
⎯
2.0
mA
Permissible output high
current (total)
Total of all output
pins
Σ−IOH
⎯
⎯
40
mA
Permissible output low
current (per pin)
All output pins
except the I2C pins
2
Caution:
Note: *
To protect the LSI’s reliability, do not exceed the output current values in table 26.30.
When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS
pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1293 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
26.1.3
AC Characteristics
The following shows the timings of the clock, control signals, bus, DMAC, EXDMAC, and onchip peripheral functions. For the AC characteristic test conditions, see figure 26.1.
(1)
Clock Timing
Table 26.5 Clock Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
Clock cycle time
tcyc
30.3
125
ns
Figure 26.3
Clock pulse high width
tCH
10
⎯
ns
Figure 26.3
Clock pulse low width
tCL
10
⎯
ns
Clock rising time
tCr
⎯
5
ns
Clock falling time
tCf
⎯
5
ns
Reset oscillation settling time
(crystal)
tOSC1
15
⎯
ms
Figure 26.5(1)
Software standby oscillation
settling time (crystal)
tOSC2
5
⎯
ms
Figure 26.5(2)
External clock output delay
settling time
tDEXT
15
⎯
ms
Figure 26.5(1)
Clock phase difference*
tcdif
1/4 × tcyc −3
1/4 × tcyc +3
ns
Figure 26.4
Clock pulse high width
(SDRAMφ)*
tSDCH
10
⎯
ns
Figure 26.4
Clock pulse low width
(SDRAMφ)*
tSDCL
10
⎯
ns
Figure 26.4
Clock rising time (SDRAMφ)*
Clock falling time (SDRAMφ)*
tsdcr
⎯
5
ns
Figure 26.4
tsdcf
⎯
5
ns
Figure 26.4
Note:
*
Supported only by the H8S/2456R Group.
Page 1294 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
3V
RL
C=50pF: Ports A to J (except for PH1 when SDRAMφ is in use.)
C=30pF: Ports 1 to 3, P50 to P52, Port6, Port8, and PH1 when SDRAMφ is in use.
LSI output pin
RL=2.4kΩ
RH=12kΩ
I/O timing test level 1.5V: (Vcc=3.0 to 3.6V)
C
RH
Note: * Not supported by the H8S/2456R Group.
Figure 26.1 Output Load Circuit
(2)
Control Signal Timing
Table 26.6 Control Signal Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
RES setup time
tRESS
200
⎯
ns
Figure 26.6
RES pulse width
tRESW
2
⎯
ms
NMI setup time
tNMIS
150
⎯
ns
NMI hold time
tNMIH
10
⎯
NMI pulse width (in recovery from
software standby mode)
tNMIW
200
⎯
IRQ setup time
tIRQS
150
⎯
IRQ hold time
tIRQH
10
⎯
IRQ pulse width (in recovery from
software standby mode)
tIRQW
200
⎯
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Figure 26.7
ns
Page 1295 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
(3)
Bus Timing
Table 26.7 Bus Timing (1)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
Address setup time 1
tAS1
⎯
20
ns
0.5 × tcyc −13
⎯
ns
Figures 26.8 to
26.23, 26.29, and
26.30
Address setup time 2
tAS2
1.0 × tcyc −13
⎯
ns
Address setup time 3
tAS3
1.5 × tcyc −13
⎯
ns
Address setup time 4
tAS4
2.0 × tcyc −13
⎯
ns
Address hold time 1
tAH1
0.5 × tcyc −8
⎯
ns
Address hold time 2
tAH2
1.0 × tcyc −8
⎯
ns
Address hold time 3
tAH3
1.5 × tcyc −8
⎯
ns
CS delay time 1
tCSD1
⎯
15
ns
CS delay time 2
tCSD2
⎯
15
ns
CS delay time 3
tCSD3
⎯
20
ns
AS delay time
tASD
⎯
15
ns
RD delay time 1
tRSD1
⎯
15
ns
RD delay time 2
tRSD2
⎯
15
ns
Read data setup time 1
tRDS1
15
⎯
ns
Read data setup time 2
tRDS2
15
⎯
ns
Read data hold time 1
tRDH1
0
⎯
ns
Read data hold time 2
tRDH2
0
⎯
ns
Read data access time 1
tAC1
⎯
1.0 × tcyc − 25
ns
Read data access time 2
tAC2
⎯
1.5 × tcyc − 25
ns
Read data access time 3
tAC3
⎯
2.0 × tcyc − 25
ns
Read data access time 4
tAC4
⎯
2.5 × tcyc − 25
ns
Read data access time 5
tAC5
⎯
1.0 × tcyc − 25
ns
Read data access time 6
tAC6
⎯
2.0 × tcyc − 25
ns
Read data access time 7
tAC7
⎯
4.0 × tcyc − 25
ns
Read data access time 8
tAC8
⎯
3.0 × tcyc − 25
ns
Counter address read data access time 1
tAA1
⎯
1.0 × tcyc − 25
ns
Page 1296 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol
Min.
Max.
Unit
Test Conditions
Counter address read data access time 2
tAA2
⎯
1.5 × tcyc − 25
ns
Counter address read data access time 3
tAA3
⎯
2.0 × tcyc − 25
ns
Figures 26.8 to
26.23, 26.29, and
26.30
Counter address read data access time 4
tAA4
⎯
2.5 × tcyc − 25
ns
Counter address read data access time 5
tAA5
⎯
3.0 × tcyc − 25
ns
Counter address read data access time 6
tAA6
⎯
4.0 × tcyc − 25
ns
Multiplexed address delay time
tMAD
⎯
20
ns
Multiplexed address setup time 1
tMAS1
0.5 × tcyc − 15
⎯
ns
Multiplexed address setup time 2
tMAS2
1.5 × tcyc − 15
⎯
ns
Multiplexed address hold time
tMAH
1.0 × tcyc − 15
⎯
ns
AH delay time
tAHD
⎯
15
ns
Table 26.8 Bus Timing (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS =
0 V, φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
WR delay time 1
tWRD1
⎯
15
ns
WR delay time 2
tWRD2
⎯
15
ns
WR pulse width 1
tWSW1
1.0 × tcyc −13
⎯
Figures 26.8 to
26.23, 26.29, and
26.30
ns
WR pulse width 2
tWSW2
1.5 × tcyc −13
⎯
ns
Write data delay time
tWDD
⎯
23
ns
Write data setup time 1
tWDS1
0.5 × tcyc −15
⎯
ns
Write data setup time 2
tWDS2
1.0 × tcyc −15
⎯
ns
Write data setup time 3
tWDS3
1.5 × tcyc −15
⎯
ns
Write data hold time 1
tWDH1
0.5 × tcyc −13
⎯
ns
Write data hold time 2
tWDH2
1.0 × tcyc −13
⎯
ns
Write data hold time 3
tWDH3
1.5 × tcyc −13
⎯
ns
Write command setup time 1
tWCS1
0.5 × tcyc −10
⎯
ns
Write command setup time 2
tWCS2
1.0 × tcyc −10
⎯
ns
Write command hold time 1
tWCH1
0.5 × tcyc −10
⎯
ns
Write command hold time 2
tWCH2
1.0 × tcyc −10
⎯
ns
Read command setup time 1
tRCS1
1.5 × tcyc −10
⎯
ns
Read command setup time 2
tRCS2
2.0 × tcyc −10
⎯
ns
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1297 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol
Min.
Max.
Unit
Test Conditions
Read command hold time
tRCH
0.5 × tcyc −10
⎯
ns
CAS delay time 1
tCASD1
⎯
15
ns
CAS delay time 2
Figures 26.8 to
26.23, 26.29, and
26.30
tCASD2
⎯
15
ns
CAS setup time 1
tCSR1
0.5 × tcyc −10
⎯
ns
CAS setup time 2
tCSR2
1.5 × tcyc −10
⎯
ns
CAS pulse width 1
tCASW1
1.0 × tcyc −20
⎯
ns
CAS pulse width 2
tCASW2
1.5 × tcyc −20
⎯
ns
CAS precharge time 1
tCPW1
1.0 × tcyc −20
⎯
ns
CAS precharge time 2
tCPW2
1.5 × tcyc −20
⎯
ns
OE delay time 1*
1
tOED1
⎯
15
ns
tOED1B
⎯
19
ns
OE delay time 2*
1
tOED2
⎯
15
ns
tOED2B
⎯
19
ns
Precharge time 1
tPCH1
1.0 × tcyc −20
⎯
ns
Precharge time 2
tPCH2
1.5 × tcyc −20
⎯
ns
Self-refresh precharge time 1
tRPS1
2.5 × tcyc −20
⎯
ns
Self-refresh precharge time 2
tRPS2
3.0 × tcyc −20
⎯
ns
WAIT setup time
tWTS
25
⎯
ns
WAIT hold time
tWTH
1
⎯
ns
BREQ setup time
tBREQS
30
⎯
ns
BACK delay time
tBACD
⎯
15
ns
Bus floating time
tBZD
⎯
40
ns
BREQO delay time
tBRQOD
⎯
25
ns
Figure 26.25
Address delay time 2*
tAD2
⎯
16.5
ns
Figure 26.26
CS delay time 4*
2
tCSD4
⎯
16.5
ns
Figure 26.26
2
tDQMD
⎯
16.5
ns
Figure 26.26
2 3
tCKED
⎯
16.5
ns
tCKEDB
⎯
19
ns
Figures 26.27
and 26.28
tRDS3
15
⎯
ns
Figure 26.26
tRDH3
0
⎯
ns
Figure 26.26
tWDD
⎯
31.5
ns
Figure 26.26
tWDH4
2
⎯
ns
Figure 26.26
2
DQM delay time*
CKE delay time * *
2
Read data setup time 3*
2
Read data hold time 3*
2
Write data delay time 2*
2
Write data hold time 4*
Page 1298 of 1408
Figures 26.22
and 26.23
Figures 26.10,
26.16, and 26.35
Figure 26.24
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Notes: 1. tOED1, and tOED2 correspond to the OE-A and RD, and, tOED1B, and tOED2B correspond to the
OE-B.
2. Supported only by the H8S/2456R Group.
3. tCKED corresponds to the CKE-A, tCKEDB corresponds to the CKE-B.
(4)
DMAC and EXDMAC Timing
Table 26.9 DMAC and EXDMAC Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
DREQ setup time
tDRQS
25
⎯
ns
Figure 26.34
DREQ hold time
tDRQH
10
⎯
TEND delay time
tTED
⎯
18
ns
Figure 26.33
DACK delay time 1
tDACD1
⎯
18
DACK delay time 2
tDACD2
⎯
18
EDREQ setup time
tEDRQS
25
⎯
EDREQ hold time
tEDRQH
10
⎯
ETEND delay time
tETED
⎯
EDACK delay time 1
tEDACD1
EDACK delay time 2
tEDACD2
EDRAK delay time
tEDRKD
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Figures 26.31 and 26.32
ns
Figure 26.34
18
ns
Figure 26.33
⎯
18
ns
Figures 26.31 and 26.32
⎯
18
⎯
18
ns
Figure 26.35
Page 1299 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
(5)
Timing of On-Chip Peripheral Modules
Table 26.10 Timing of On-Chip Peripheral Modules
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol Min.
Max.
Unit
Test Conditions
40
ns
Figure 26.39
tPWD
⎯
Input data setup time
tPRS
25
⎯
ns
Input data hold time
tPRH
25
⎯
ns
PPG
Pulse output delay time
tPOD
⎯
40
ns
Figure 26.40
TPU
Timer output delay time
tTOCD
⎯
40
ns
Figure 26.41
Timer input setup time
tTICS
25
⎯
ns
Timer clock input setup time tTCKS
25
⎯
ns
Timer clock Single-edge
pulse width specification
tTCKWH
1.5
⎯
tcyc
Both-edge
specification
tTCKWL
2.5
⎯
tcyc
tTMOD
⎯
40
ns
Figure 26.43
Timer reset input setup time tTMRS
25
⎯
ns
Figure 26.45
Timer clock input setup time tTMCS
25
⎯
ns
Figure 26.44
Timer clock Single-edge
pulse width specification
tTMCWH
1.5
⎯
tcyc
Both-edge
specification
tTMCWL
2.5
⎯
tcyc
I/O ports
8-bit timer
Output data delay time
Timer output delay time
WDT
Overflow output delay time
SCI
Input clock
cycle
Asynchronous
tWOVD
⎯
40
ns
Figure 26.46
tScyc
4
⎯
tcyc
Figure 26.47
6
⎯
Synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rising time
tSCKr
⎯
1.5
tcyc
Input clock falling time
tSCKf
⎯
1.5
Transmit data delay time
tTXD
⎯
40
ns
Receive data setup time
(synchronous)
tRXS
40
⎯
ns
Receive data hold time
(synchronous)
tRXH
40
⎯
ns
Page 1300 of 1408
Figure 26.42
Figure 26.48
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol Min.
Max.
Unit
Test Conditions
A/D
converter
Trigger input setup time
tTRGS
30
⎯
ns
Figure 26.49
IIC2
SCL input cycle time
tSCL
12 tcyc +600 ⎯
ns
Figure 26.50
SCL input high pulse width
tSCLH
3 tcyc +300
⎯
ns
SCL input low pulse width
tSCLL
5 tcyc +300
⎯
ns
SCL, SDA input falling time
tSf
⎯
300
ns
SCL, SDA input spike pulse
removal time
tSP
⎯
1 tcyc
ns
SDA input bus free time
tBUF
5 tcyc
⎯
ns
Start condition input hold
time
tSTAH
3 tcyc
⎯
ns
Retransmit start condition
input setup time
tSTAS
3 tcyc
⎯
ns
Stop condition input setup
time
tSTOS
3 tcyc
⎯
ns
Data input setup time
tSDAS
1 tcyc +20
⎯
ns
Data input hold time
tSDAH
0
⎯
ns
SCL, SDA capacitive load
Cb
⎯
400
pF
SCL, SDA falling time
tSf
⎯
300
ns
Clock cycle
tSUcyc
4
256
tcyc
4
256
48
⎯
48
⎯
48
⎯
48
⎯
SSU*
Master
Slave
Clock high pulse
width
Master
Clock low pulse
width
Master
tHI
Slave
tLO
Slave
ns
ns
Clock rising time
tRISE
⎯
12
ns
Clock falling time
tFALL
⎯
12
ns
tSU
25
⎯
ns
30
⎯
10
⎯
10
⎯
2.5
⎯
2.5
⎯
Data input setup
time
Master
Data input hold
time
Master
SCS setup time
Master
Slave
Slave
Slave
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
tH
tLEAD
Figures 26.51 to
26.54
ns
tcyc
Page 1301 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
SCS hold time
SSU*
Master
Symbol Min.
Max.
Unit
Test Conditions
tLAG
2.5
⎯
tcyc
2.5
⎯
Figures 26.51 to
26.54
⎯
40
⎯
40
−5
⎯
0
⎯
2.5
⎯
2.5
⎯
Slave
Note
*
26.1.4
Data output delay
time
Master
Data output hold
time
Master
tOD
Slave
tOH
Slave
ns
ns
Continuous
Master
transmit delay time Slave
tTD
tcyc
Slave access time
tSA
⎯
1
tcyc
Slave out release time
tREL
⎯
1
tcyc
Figures 26.53
and 26.54
SSU: Synchronous serial communication unit
A/D Conversion Characteristics
Table 26.11 A/D Conversion Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Min.
Typ.
Max.
Unit
Resolution
10
10
10
Bit
Conversion time
2.5*
⎯
⎯
μs
Analog input capacitance
⎯
⎯
15
pF
Permissible signal source impedance
⎯
⎯
5
kΩ
Nonlinearity error
⎯
⎯
±3.5
LSB
Offset error
⎯
⎯
±3.5
LSB
Full-scale error
⎯
⎯
±3.5
LSB
Quantization error
⎯
⎯
±0.5
LSB
Absolute accuracy
⎯
⎯
±6.0
LSB
Note:
*
For 40 states at ADCLK = 16 MHz.
Page 1302 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
26.1.5
Section 26 Electrical Characteristics
D/A Conversion Characteristics
Table 26.12 D/A Conversion Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz
Item
Min.
Typ.
Max.
Unit
Resolution
8
8
8
Bit
Conversion time
⎯
⎯
10
μs
Absolute accuracy
⎯
±2.0
±3.0
LSB
2 MΩ resistive load
⎯
⎯
±2.0
LSB
4 MΩ resistive load
26.1.6
Test Conditions
20 pF capacitive load
USB Characteristics
Table 26.13 USB Characteristics when On-Chip USB Transceiver is Used
(USD+, USD- pin characteristics)
Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0V,
CKU = 48MHz
Item
Input
Output
Symbol Min
Max
Unit
Test Conditions
Input high voltage
VIH
2.0
⎯
V
Input low voltage
VIL
⎯
0.8
V
Differential input sensitivity
VDI
0.2
⎯
V
Differential common mode
range
VCM
0.8
2.5
V
Output high voltage
VOH
2.8
⎯
V
IOH =-200µA
Output low voltage
VOL
⎯
0.3
V
IOL = 2mA
Crossover voltage
VCRS
1.3
2.0
V
Rising time
tR
4
20
ns
Falling time
tF
4
20
ns
Ratio of rising time to falling
time
tRFM
90
111.11 %
Output resistance
ZDRV
28
44
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Ω
Figure 26.36
and 26.37
|(D+)-(D-)|
(TR/TF)
Including
RS = 27Ω
Page 1303 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Table 26.14 USB PLL Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6, Vref = 3.0 V to AVCC,
VSS = AVSS = 0V, EXTAL = 8 to 16 MHz
Item
Symbol
Min
Max
Unit
Test Conditions
PLL for USB: oscillation
stabilization time
tUSOSC
1
⎯
ms
Figure 26.38
26.1.7
Flash Memory Characteristics
Table 26.15 Flash Memory Characteristics
Conditions:
VCC = 3.0 to 3.6V, AVCC = 3.0 to 3.6V, Vref = 3.0 V to AVCC, VSS = AVSS = 0V,
φ = 8 MHz to 33 MHz
Standard value
Item
Applicable area
Programming and erase count*
1
User ROM
Min.
2
1000*
Typ.
Max.
Unit
⎯
⎯
Times
Data flash area
10000*
⎯
⎯
Programming time
(per 4 bytes)
User ROM
⎯
150
4000
Data flash area
⎯
300
4000
Erase time (per 1 block)
User ROM
⎯
300
3000
Data flash area
⎯
300
3000
3.0
⎯
3.6
V
3.0
⎯
3.6
V
User ROM
1
⎯
⎯
State
Data flash area
2
⎯
⎯
Programming and erase voltage User ROM
2
μs
ms
Data flash area
Read voltage
User ROM
Data flash area
Access state
Notes:
1. When programming is to be performed multiple times on a system, reduce the effective number of
programming operations by shifting the writing addresses in sequence and so on until the
remaining blank area is as small as possible and only then erasing the entire block once. For
example, if sets of 16 bytes are being programmed, erasing the block once after programming the
maximum number of sets (256) minimizes the effective number of programming operations.
We recommend keeping information on the number of times erasure is performed for each block,
and setting up the limit on the number of times.
2. If an erase error occurs during erasure, execute the clear status command and then the erase
command at least 3 times until the erase does not recur.
Page 1304 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
*1. Determination of the number of times for programming/erasure operations.
Number of times programming/erasure is performed in each block.
When the number of times for programming/erasure operations is n (n = 100), data can be erased
n times in each block.
For example, if programming of 4 bytes is done 1024 times, each at a different address in a 4kbyte per block, and the block is then erased, this counts as programming/erasure one time.
However, programming of any location in a block multiple times is not possible (overwriting is
prohibited).
*2. This is the number of times for which all electrical characteristics are guaranteed.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1305 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
26.2
Electrical Characteristics for H8S/2454 Group
26.2.1
Absolute Maximum Ratings
Table 26.16 lists the absolute maximum ratings.
Table 26.16 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
−0.3 to +4.3
V
PLLVCC
DrVCC
Input voltage (except ports 4, 9, 2, P32 to
P35, P50, P51, P81, and P83)
Vin
−0.3 to VCC +0.3
V
Input voltage (ports 2, P32 to P35, P50,
P51, P81, and P83)
Vin
−0.3 to +6.5
V
Input voltage (ports 4 and 9)
Vin
−0.3 to AVCC +0.3
V
Reference power supply voltage
Vref
−0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
−0.3 to +4.3
V
Analog input voltage
VAN
−0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications:
−20 to +75*
°C
Wide-range specifications:
−40 to +85*
°C
−55 to +125
°C
Storage temperature
Caution:
Note: *
Tstg
Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Ranges of operating temperature when flash memory is programmed/erased:
Regular specifications: 0 to +75°C
Wide-range specifications: 0 to +85°C
Page 1306 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
26.2.2
Section 26 Electrical Characteristics
DC Characteristics
Table 26.17 DC Characteristics (1)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*1
Typ.
Max.
Test
Unit Conditions
VCC × 0.2
⎯
⎯
V
⎯
⎯
VCC × 0.7
V
VCC × 0.07 ⎯
⎯
V
VCC × 0.9
⎯
VCC +0.3
V
VCC × 0.7
⎯
VCC +0.3
V
P10 to P11* ,
P14 to P17*5,
5
5
P25* , P26* ,
3
port 3* ,
P50 to P53*3,
3
port 8* ,
ports A to G*3
2.2
⎯
VCC +0.3
V
Port 4, Port 9
2.2
⎯
AVCC +0.3
V
−0.3
⎯
VCC × 0.1
V
−0.3
⎯
VCC × 0.2
V
P10 to P11* ,
P14 to P17*5
P25*6, P26*6
ports 3*3 and 5*3,
port 8*3,
3
ports A to G*
−0.3
⎯
VCC × 0.2
V
Port 4, Port 9
−0.3
⎯
AVCC × 0.2 V
Item
Symbol
Schmitt
Port 1*6, port 2*6, VT−
trigger input P32 to P35*2,
VT+
2
voltage
P50 to P53* ,
2
VT+ − VT−
port 8* , PA4 to
2
2
PA7* , port B* ,
2
2
port C* , PF1* ,
2
2
PF2* , P81* ,
P83*2
Input high
voltage
STBY,
MD2 to MD0
VIH
Min.
RES, NMI, EMLE
EXTAL
5
Input low
voltage
RES, STBY,
MD2 to MD0,
EMLE
NMI, EXTAL
5
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
VIL
Page 1307 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol
Min.
Typ.
Max.
Test
Unit Conditions
Output high All output pins
voltage
VOH
VCC − 0.3
⎯
⎯
V
IOH = −200 μA
VCC − 0.5
⎯
⎯
V
IOH = −1 mA
VCC − 0.8
⎯
⎯
V
IOH = −2 mA
⎯
⎯
0.4
V
IOL = 4.0 mA
⎯
⎯
0.4
V
IOL = 8.0 mA
⎯
⎯
10.0
μA
STBY, NMI,
MD2 to MD0
⎯
⎯
1.0
μA
Vin = 0.5 to
VCC −0.5 V
Port 4, Port 9
⎯
⎯
1.0
μA
Output low
voltage
All output pins
4
P26 to P27* ,
P32 to P35*4,
P50 to P51*4
VOL
Input
leakage
current
RES
|Iin|
Vin = 0.5 to
AVCC −0.5 V
Notes: Port 2, P32 to P35, P50, P51, P81, and P83 are 5 V-tolerant pins.
1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not
be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
2. When used as IRQ, TIOC, TCLK, TMRI, SCL, or SDA.
3. When used as other than IRQ, TIOC, TCLK, TMRI, SCL, or SDA.
4. When used as SCL or SDA.
5. When used as SSO, SSI, SSCK, SCS, WAIT, ADTRG1 or DREQ.
6. When used as other than SSO, SSI, SSCK, SCS, WAIT, ADTRG1 or DREQ.
Page 1308 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Table 26.18 DC Characteristics (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*1
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Three-state
leakage
current
(off state)
Ports 1 to 3,
P50 to P53,
Ports 8,
Ports A to G
| ITSI |
⎯
⎯
1.0
μA
Vin = 0.5 to
VCC −0.5 V
Input pull-up
MOS current
Ports A to E
−Ip
10
⎯
300
μA
VCC = 3.0 to
3.6 V
Vin = 0 V
Input
capacitance
Supply
current*2
RES
⎯
⎯
30
pF
Vin = 0 V
NMI
⎯
⎯
30
pF
f = 1 MHz
All input pins
except RES and
NMI
⎯
⎯
18
pF
Ta = 25°C
⎯
45
60
(3.3 V)
mA
f = 33 MHz
Sleep mode
⎯
35
45
(3.3 V)
mA
f = 33 MHz
Standby mode*3
⎯
20
80
μA
Ta ≤ 50°C
⎯
80
500
μA
50°C < Ta
⎯
0.5
2.0
(3.3 V)
mA
When channel 1
is in use
⎯
0.01
5.0
μA
When channel 1
is in use
⎯
0.5
1.0
(3.3 V)
mA
⎯
0.01
5.0
μA
2.5
⎯
⎯
V
Normal operation
Analog power During A/D and
supply current D/A conversion
Cin
ICC*4
AICC
Idling
Reference
power supply
current
During A/D and
D/A conversion
AICC
Idling
RAM standby voltage
V start voltage*5
VRAM
VCC start
⎯
⎯
0.3
V
VCC rising slope*5
SVCC
⎯
⎯
20
ms/V
CC
Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not
be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
2. Supply current values are for VIHmin = VCC −0.2 V and VILmax = 0.2 V with all output pins
unloaded and all input pull-up MOSs in the off state.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1309 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 5.2 (mA) + 1.66 (mA/(MHz)) × f (normal operation)
ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode)
5. Applied when RES is low at power-on.
Table 26.19 Permissible Output Currents
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*
Item
Symbol
Min.
Typ.
Max.
Unit
IOL
⎯
⎯
4.0
mA
I C output pins
IOL
⎯
⎯
8.0
mA
Permissible output low
current (total)
Total of all output
pins
ΣIOL
⎯
⎯
80
mA
Permissible output high
current (per pin)
All output pins
−IOH
⎯
⎯
2.0
mA
Permissible output high
current (total)
Total of all output
pins
Σ−IOH
⎯
⎯
40
mA
Permissible output low
current (per pin)
All output pins
except the I2C pins
2
Caution:
Note: *
To protect the LSI’s reliability, do not exceed the output current values in table 26.30.
When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS
pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
Page 1310 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
26.2.3
Section 26 Electrical Characteristics
AC Characteristics
The following shows the timings of the clock, control signals, bus, DMAC, and on-chip peripheral
functions. For the AC characteristic test conditions, see figure 26.2.
(1)
Clock Timing
Table 26.20 Clock Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
Clock cycle time
tcyc
30.3
125
ns
Figure 26.3
Clock pulse high width
tCH
10
⎯
ns
Figure 26.3
Clock pulse low width
tCL
10
⎯
ns
Clock rising time
tCr
⎯
5
ns
Clock falling time
tCf
⎯
5
ns
Reset oscillation settling time
(crystal)
tOSC1
15
⎯
ms
Figure 26.5(1)
Software standby oscillation
settling time (crystal)
tOSC2
5
⎯
ms
Figure 26.5(2)
External clock output delay
settling time
tDEXT
15
⎯
ms
Figure 26.5(1)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1311 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
3V
RL
C=50pF: Ports A to G
C=30pF: Ports 1 to 3, P50 to P53, and Port8
RL=2.4kΩ
RH=12kΩ
I/O timing test level1.5V: (Vcc=3.0 to 3.6V)
LSI output pin
C
RH
Figure 26.2 Output Load Circuit
(2)
Control Signal Timing
Table 26.21 Control Signal Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
RES setup time
tRESS
200
⎯
ns
Figure 26.6
RES pulse width
tRESW
2
⎯
ms
NMI setup time
tNMIS
150
⎯
ns
NMI hold time
tNMIH
10
⎯
NMI pulse width (in recovery from
software standby mode)
tNMIW
200
⎯
IRQ setup time
tIRQS
150
⎯
IRQ hold time
tIRQH
10
⎯
IRQ pulse width (in recovery from
software standby mode)
tIRQW
200
⎯
Page 1312 of 1408
Figure 26.7
ns
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(3)
Section 26 Electrical Characteristics
Bus Timing
Table 26.22 Bus Timing (1)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
Address delay time
tAD
⎯
20
ns
Address setup time 1
tAS1
0.5 × tcyc −13
⎯
ns
Figures 26.8 to
26.23, 26.29, and
26.30
Address setup time 2
tAS2
1.0 × tcyc −13
⎯
ns
Address setup time 3
tAS3
1.5 × tcyc −13
⎯
ns
Address setup time 4
tAS4
2.0 × tcyc −13
⎯
ns
Address hold time 1
tAH1
0.5 × tcyc −8
⎯
ns
Address hold time 2
tAH2
1.0 × tcyc −8
⎯
ns
Address hold time 3
tAH3
1.5 × tcyc −8
⎯
ns
CS delay time 1
tCSD1
⎯
15
ns
CS delay time 2
tCSD2
⎯
15
ns
CS delay time 3
tCSD3
⎯
20
ns
AS delay time
tASD
⎯
15
ns
RD delay time 1
tRSD1
⎯
15
ns
RD delay time 2
tRSD2
⎯
15
ns
Read data setup time 1
tRDS1
15
⎯
ns
Read data setup time 2
tRDS2
15
⎯
ns
Read data hold time 1
tRDH1
0
⎯
ns
Read data hold time 2
tRDH2
0
⎯
ns
Read data access time 1
tAC1
⎯
1.0 × tcyc − 25
ns
Read data access time 2
tAC2
⎯
1.5 × tcyc − 25
ns
Read data access time 3
tAC3
⎯
2.0 × tcyc − 25
ns
Read data access time 4
tAC4
⎯
2.5 × tcyc − 25
ns
Read data access time 5
tAC5
⎯
1.0 × tcyc − 25
ns
Read data access time 6
tAC6
⎯
2.0 × tcyc − 25
ns
Read data access time 7
tAC7
⎯
4.0 × tcyc − 25
ns
Read data access time 8
tAC8
⎯
3.0 × tcyc − 25
ns
Counter address read data access time 1 tAA1
⎯
1.0 × tcyc − 25
ns
Counter address read data access time 2 tAA2
⎯
1.5 × tcyc − 25
ns
Counter address read data access time 3 tAA3
⎯
2.0 × tcyc − 25
ns
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1313 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Min.
Max.
Unit
Test Conditions
Counter address read data access time 4 tAA4
Symbol
⎯
2.5 × tcyc − 25
ns
Counter address read data access time 5 tAA5
⎯
3.0 × tcyc − 25
ns
Figures 26.8 to
26.23, 26.29, and
26.30
Counter address read data access time 6 tAA6
⎯
4.0 × tcyc − 25
ns
Multiplex address delay time 6
TMAD
⎯
20
ns
Multiplex address setup time 1
TMAS1
0.5 × tcyc − 15
⎯
ns
Multiplex address setup time 2
TMAS2
1.5 × tcyc − 15
⎯
ns
Multiplex address hold time
TMAH
1.0 × tcyc − 15
⎯
ns
AH delay time
TAHD
⎯
15
ns
Page 1314 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Table 26.22 Bus Timing (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS =
0 V, φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
WR delay time 1
tWRD1
⎯
15
ns
WR delay time 2
tWRD2
⎯
15
ns
WR pulse width 1
tWSW1
1.0 × tcyc −13
⎯
Figures 26.8 to
26.23, 26.29, and
26.30
ns
WR pulse width 2
tWSW2
1.5 × tcyc −13
⎯
ns
Write data delay time
tWDD
⎯
23
ns
Write data setup time 1
tWDS1
0.5 × tcyc −15
⎯
ns
Write data setup time 2
tWDS2
1.0 × tcyc −15
⎯
ns
Write data setup time 3
tWDS3
1.5 × tcyc −15
⎯
ns
Write data hold time 1
tWDH1
0.5 × tcyc −13
⎯
ns
Write data hold time 2
tWDH2
1.0 × tcyc −13
⎯
ns
Write data hold time 3
tWDH3
1.5 × tcyc −13
⎯
ns
Write command setup time 1
tWCS1
0.5 × tcyc −10
⎯
ns
Write command setup time 2
tWCS2
1.0 × tcyc −10
⎯
ns
Write command hold time 1
tWCH1
0.5 × tcyc −10
⎯
ns
Write command hold time 2
tWCH2
1.0 × tcyc −10
⎯
ns
Read command setup time 1
tRCS1
1.5 × tcyc −10
⎯
ns
Read command setup time 2
tRCS2
2.0 × tcyc −10
⎯
ns
Read command hold time
tRCH
0.5 × tcyc −10
⎯
ns
CAS delay time 1
tCASD1
⎯
15
ns
CAS delay time 2
tCASD2
⎯
15
ns
CAS setup time 1
tCSR1
0.5 × tcyc −10
⎯
ns
CAS setup time 2
tCSR2
1.5 × tcyc −10
⎯
ns
CAS pulse width 1
tCASW1
1.0 × tcyc −20
⎯
ns
CAS pulse width 2
tCASW2
1.5 × tcyc −20
⎯
ns
CAS precharge time 1
tCPW1
1.0 × tcyc −20
⎯
ns
CAS precharge time 2
tCPW2
1.5 × tcyc −20
⎯
ns
OE delay time 1*
tOED1
⎯
15
ns
tOED1B
⎯
19
ns
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1315 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol
Min.
Max.
Unit
Test Conditions
OE delay time 2*
tOED2
⎯
15
ns
Figures 26.8 to
26.23, 26.29, and
26.30
tOED2B
⎯
19
ns
Precharge time 1
tPCH1
1.0 × tcyc −20
⎯
ns
Precharge time 2
tPCH2
1.5 × tcyc −20
⎯
ns
Self-refresh precharge time 1
tRPS1
2.5 × tcyc −20
⎯
ns
Self-refresh precharge time 2
tRPS2
3.0 × tcyc −20
⎯
ns
WAIT setup time
tWTS
25
⎯
ns
WAIT hold time
tWTH
1
⎯
ns
BREQ setup time
tBREQS
30
⎯
ns
BACK delay time
tBACD
⎯
15
ns
Bus floating time
tBZD
⎯
40
ns
BREQO delay time
tBRQOD
⎯
25
ns
Note:
(4)
*
Figures 26.22
and 26.23
Figures 26.10,
26.16, and 26.35
Figure 26.24
Figure 26.25
tOED1 and tOED2.correspond to OE-A and RD, and tOED1B and tOED2B.correspond to OE-B.
DMAC Timing
Table 26.23 DMAC Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol
Min.
Max.
Unit
Test Conditions
DREQ setup time
tDRQS
25
⎯
ns
Figure 26.34
DREQ hold time
tDRQH
10
⎯
TEND delay time
tTED
⎯
18
Figure 26.32
DACK delay time 1
tDACD1
⎯
18
Figures 26.31 and 26.32
DACK delay time 2
tDACD2
⎯
18
Page 1316 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(5)
Section 26 Electrical Characteristics
Timing of On-Chip Peripheral Modules
Table 26.24 Timing of On-Chip Peripheral Modules
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Symbol Min.
Max.
Unit
Test Conditions
Figure 26.39
tPWD
⎯
40
ns
Input data setup time
tPRS
25
⎯
ns
Input data hold time
tPRH
25
⎯
ns
PPG
Pulse output delay time
tPOD
⎯
40
ns
Figure 26.40
TPU
Timer output delay time
tTOCD
⎯
40
ns
Figure 26.41
Timer input setup time
tTICS
25
⎯
ns
Timer clock input setup time tTCKS
25
⎯
ns
Timer clock Single-edge
pulse width specification
tTCKWH
1.5
⎯
tcyc
Both-edge
specification
tTCKWL
2.5
⎯
tcyc
tTMOD
⎯
40
ns
Figure 26.43
Timer reset input setup time tTMRS
25
⎯
ns
Figure 26.45
Timer clock input setup time tTMCS
25
⎯
ns
Figure 26.44
Timer clock Single-edge
pulse width specification
tTMCWH
1.5
⎯
tcyc
Both-edge
specification
tTMCWL
2.5
⎯
tcyc
I/O ports
8-bit timer
Output data delay time
Timer output delay time
WDT
Overflow output delay time
SCI
Input clock
cycle
Asynchronous
tWOVD
⎯
40
ns
Figure 26.46
tScyc
4
⎯
tcyc
Figure 26.47
6
⎯
Synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rising time
tSCKr
⎯
1.5
tcyc
Input clock falling time
tSCKf
⎯
1.5
Transmit data delay time
tTXD
⎯
40
ns
Receive data setup time
(synchronous)
tRXS
40
⎯
ns
Receive data hold time
(synchronous)
tRXH
40
⎯
ns
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Figure 26.42
Figure 26.48
Page 1317 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
Symbol Min.
Max.
Unit
Test Conditions
A/D
converter
Trigger input setup time
tTRGS
30
⎯
ns
Figure 26.49
IIC2
SCL input cycle time
tSCL
12 tcyc +600 ⎯
ns
Figure 26.50
SCL input high pulse width
tSCLH
3 tcyc +300
⎯
ns
SCL input low pulse width
tSCLL
5 tcyc +300
⎯
ns
SCL, SDA Input falling time
tSf
⎯
300
ns
SCL, SDA Input spike pulse tSP
removal time
⎯
1 tcyc
ns
SDA input bus free time
tBUF
5 tcyc
⎯
ns
Start condition input hold
time
tSTAH
3 tcyc
⎯
ns
Retransmit start condition
input setup time
tSTAS
3 tcyc
⎯
ns
Stop condition input setup
time
tSTOS
3 tcyc
⎯
ns
Data input setup time
tSDAS
1 tcyc +20
⎯
ns
Data input hold time
tSDAH
0
⎯
ns
SCL, SDA capacitive load
Cb
⎯
400
PF
SCL, SDA falling time
tSf
⎯
300
ns
Clock cycle
tSUcyc
4
256
tcyc
4
256
48
⎯
48
⎯
48
⎯
48
⎯
IIC2
SSU*
Master
Slave
Clock high pulse
width
Master
Clock low pulse
width
Master
tHI
Slave
tLO
Slave
ns
tRISE
⎯
20
ns
Clock falling time
tFALL
⎯
20
ns
tSU
25
⎯
ns
30
⎯
10
⎯
10
⎯
2.5
⎯
2.5
⎯
Master
Data input hold
time
Master
SCS setup time
Master
Slave
Slave
Slave
Page 1318 of 1408
tH
tLEAD
Figures 26.51 to
26.54
ns
Clock rising time
Data input setup
time
Figure 26.50
ns
tcyc
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Item
SCS hold time
SSU*
Master
Symbol Min.
Max.
Unit
Test Conditions
tLAG
2.5
⎯
tcyc
2.5
⎯
Figures 26.51 to
26.54
⎯
40
⎯
40
Slave
Note
*
26.2.4
Data output delay
time
Master
Data output hold
time
Master
tOD
Slave
tOH
Slave
0
⎯
0
⎯
2.5
⎯
2.5
⎯
ns
ns
Continuous
Master
transmit delay time Slave
tTD
tcyc
Slave access time
tSA
⎯
1
tcyc
Slave out release time
tREL
⎯
1
tcyc
Figures 26.53
and 26.54
SSU: Synchronous serial communication unit
A/D Conversion Characteristics
Table 26.25 A/D Conversion Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Min.
Typ.
Max.
Unit
Resolution
10
10
10
Bit
Conversion time
2.5*
⎯
⎯
μs
Analog input capacitance
⎯
⎯
15
pF
Permissible signal source impedance
⎯
⎯
5
kΩ
Nonlinearity error
⎯
⎯
±3.5
LSB
Offset error
⎯
⎯
±3.5
LSB
Full-scale error
⎯
⎯
±3.5
LSB
Quantization error
⎯
⎯
±0.5
LSB
Absolute accuracy
⎯
⎯
±6.0
LSB
Note:
*
For 40 states at ADCLK = 16 MHz.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1319 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
26.2.5
D/A Conversion Characteristics
Table 26.26 D/A Conversion Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz
Item
Min.
Typ.
Max.
Unit
Resolution
8
8
8
Bit
Conversion time
⎯
⎯
10
μs
Absolute accuracy
⎯
±2.0
±3.0
LSB
2 MΩ resistive load
⎯
⎯
±2.0
LSB
4 MΩ resistive load
26.2.6
Test Conditions
20 pF capacitive load
USB Characteristics
Table 26.27 USB Characteristics when On-Chip USB Transceiver is Used
(USD+, USD- pin characteristics)
Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0V,
CKU = 48MHz
Item
Input
Symbol min
max
Unit
Test Conditions
Input high voltage
VIH
2.0
⎯
V
Input low voltage
VIL
⎯
0.8
V
Differential input sensitivity
VDI
0.2
⎯
V
Differential common mode
range
VCM
0.8
2.5
V
VOH
2.8
⎯
V
IOH =-200µA
IOL = 2mA
Output Output high voltage
Output low voltage
VOL
⎯
0.3
V
Crossover voltage
VCRS
1.3
2.0
V
Rising time
tR
4
20
ns
Falling time
tF
4
20
ns
Ratio of rising time to falling
time
tRFM
90
111.11 %
Output resistance
ZDRV
28
44
Page 1320 of 1408
Ω
Figures 26.36
and 26.37
|(D+)-(D-)|
(TR/TF)
Including
RS = 27Ω
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
Table 26.28 USB PLL Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6, Vref = 3.0 V to AVCC,
VSS = AVSS = 0V, EXTAL = 8 to 16 MHz
Item
Symbol
Min
Max
Unit
Test Conditions
PLL for USB: oscillation
stabilization time
tUSOSC
1
⎯
ms
Figure 26.38
26.2.7
Flash Memory Characteristics
Table 26.29 Flash Memory Characteristics
Conditions:
VCC = 3.0 to 3.6V, AVCC = 3.0 to 3.6V, Vref = 3.0 V to AVCC, VSS = AVSS = 0V,
φ = 8 MHz to 33 MHz
Standard value
Item
Applicable area
Programming and erase count*
1
User ROM
Min.
2
1000*
Typ.
Max.
Unit
⎯
⎯
Times
Data flash area
10000*
⎯
⎯
Programming time
(per 4 bytes)
User ROM
⎯
150
4000
Data flash area
⎯
300
4000
Erase time (per 1 block)
User ROM
⎯
300
3000
Data flash area
⎯
300
3000
3.0
⎯
3.6
V
3.0
⎯
3.6
V
User ROM
1
⎯
⎯
State
Data flash area
2
⎯
⎯
Programming and erase voltage User ROM
2
μs
ms
Data flash area
Read voltage
User ROM
Data flash area
Access state
Notes:
1. In the system where multiple programming are executed, erase once so as to effectively diminish
the programming times after having written with leaving the blank area as least as possible by
shifting writing address one by one.
For example, if 16 bytes per 1 set is being programmed, erase once after maximum 256 sets of
programming has been done, which diminish the effective programming times.
Keep the information of the times of erasure and set up the limitation times is recommended.
2. If an erase error is occurred, execute the clear status command -> erase command for at least 3
times until no erase error is occurred.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1321 of 1408
Section 26 Electrical Characteristics
H8S/2456, H8S/2456R, H8S/2454 Group
*1. Determination of the number of times the programming/erase operation.
Number of times the programming/erase performed in each block.
When the number of times the programming/erase is n times (n = 100), data can be erased n times
in each block.
For example, if 4 bytes programming is done 1024 times, each at a different address in a 4-kbyte
per block, and then the block is erased, number of times the programming/erase can be one time.
However, programming cannot be done multiple times in the block (overwriting is prohibited).
*2. Number of times that ensures all the electrical characteristics
Page 1322 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
26.3
Timing Charts
26.3.1
Clock Timing
Section 26 Electrical Characteristics
The clock timings are shown below.
tcyc
tCH
tCf
φ
tCL
tCr
Figure 26.3 System Clock Timing
tcyc
tCH
tCf
φ
tCr
tCL
tcdif
tsdcf
tsdcr
SDRAMφ
tSDCH
tSDCL
Figure 26.4 SDRAMφ Timing
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1323 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
EXTAL
tDEXT
tDEXT
VCC
STBY
tOSC1
tOSC1
RES
φ
Figure 26.5 (1) Oscillation Settling Timing
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception handling
NMI exception
handling
NMIEG = 1
SSBY = 1
Software standby mode
(power-down state)
Oscillation
stabilization time
tOSC2
SLEEP
instruction
Figure 26.5 (2) Oscillation Settling Timing
Page 1324 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
26.3.2
Section 26 Electrical Characteristics
Control Signal Timing
The control signal timings are shown below.
φ
tRESS
tRESS
RES
tRESW
Figure 26.6 Reset Input Timing
φ
tNMIS tNMIH
NMI
tNMIW
tIRQW
IRQi
(i = 0 to 15)*
tIRQS tIRQH
IRQ
(edge input)
tIRQS
IRQ
(level input)
Note: * SSIER setting is necessary to clear software standby mode.
Figure 26.7 Interrupt Input Timing
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1325 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
26.3.3
Bus Timing
The bus timings are shown below.
T2
T1
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tASD tASD
tAH1
AS
tAS1
tRSD1
tRSD1
RD
Read
(RDNn = 1)
tRDS1 tRDH1
tAC5
tAA2
D15 to D0
tAS1
tRSD1
tRSD2
RD
Read
(RDNn = 0)
tAC2
tRDS2 tRDH2
tAA3
D15 to D0
tAS1
tWRD2 tWRD2
tAH1
HWR, LWR
tWDD
Write
tWSW1
tWDH1
D15 to D0
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Figure 26.8 Basic Bus Timing: Two-State Access
Page 1326 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
T1
T3
T2
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tASD
tASD
tAH1
AS
tAS1
tRSD1
tRSD1
RD
Read
(RDNn = 1)
tRDS1 tRDH1
tAC6
tAA4
D15 to D0
tAS1
tRSD1
tRSD2
RD
Read
(RDNn = 0)
tRDS2
tAC4
tRDH2
tAA5
D15 to D0
tAS2
tWRD2
tAH1
tWRD1
HWR, LWR
tWDS1
tWDD
Write
tWSW2
tWDH1
D15 to D0
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Figure 26.9 Basic Bus Timing: Three-State Access
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1327 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Section 26 Electrical Characteristics
T1
T2
Tw
tWTS tWTH
tWTS tWTH
T3
φ
A23 to A0
CS7 to CS0
AS
RD
Read
(RDNn = 1)
D15 to D0
RD
Read
(RDNn = 0)
D15 to D0
HWR, LWR
Write
D15 to D0
WAIT
Figure 26.10 Basic Bus Timing: Three-State Access, One Wait
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Section 26 Electrical Characteristics
T1
Th
T2
Tt
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tAH1
tASD
tASD
AS
tAS3
tAH3
tRSD1 tRSD1
RD
Read
(RDNn = 1)
tAC5
tRDS1 tRDH1
tRSD1
tRSD2
D15 to D0
tAS3
tAH2
RD
Read
(RDNn = 0)
tAC2
tRDS2 tRDH2
D15 to D0
tAS3
tWRD2 tWRD2
tAH3
HWR, LWR
tWDD
Write
tWDS2
tWSW1
tWDH3
D15 to D0
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Figure 26.11 Basic Bus Timing: Two-State Access (CS Assertion Period Extended)
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Section 26 Electrical Characteristics
Th
T1
T2
T3
Tt
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tASD
tAH1
tASD
AS
tAS3
tRSD1
tAH3
tRSD1
RD
Read
(RDNn = 1)
tRDS1 tRDH1
tAC6
D15 to D0
tAS3
tAH2
tRSD2
tRSD1
RD
Read
(RDNn = 0)
tRDS2 tRDH2
tAC4
D15 to D0
tAS4
tAH3
tWRD1
HWR, LWR
tWDD
Write
tWRD2
tWDS3
tWSW2
tWDH3
D15 to D0
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Figure 26.12 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)
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Section 26 Electrical Characteristics
T1
T2
T1
T1
φ
A23 to A6,
A0
tAD
A5 to A1
CS1, CS0
AS
tRSD2
RD
tAA1 tRDS2 tRDH2
Read
D15 to D0
HWR, LWR
Figure 26.13 Burst ROM Access Timing: One-State Burst Access
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Section 26 Electrical Characteristics
T1
T2
T3
T1
T2
φ
A23 to A6,
A0
tAD
A5 to A1
CS1, CS0
tAH1
tAS1
tASD
AS
tASD
tRSD2
RD
Read
tAA3
tRDS2 tRDH2
D15 to D0
HWR, LWR
Figure 26.14 Burst ROM Access Timing: Two-State Burst Access
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Section 26 Electrical Characteristics
Tr
Tp
Tc1
Tc2
φ
tAD
tAD
A23 to A0
tAS3
RAS5 to RAS2
tCSD3
tAH1
tCSD2
tAS2
tPCH2
tAH2
tCASD1
tCASD1
UCAS
tCASW1
LCAS
tOED1/
tOED1B
tOED1/
tOED1B
tAC1
OE, RD
Read
HWR
tAA3
tRDS2 tRDH2
tAC4
D15 to D0
OE, RD
tWRD2
Write
tWCS1 tWCH1
tWRD2
HWR
tWDD
tWDS1
tWDH2
D15 to D0
AS
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Figure 26.15 DRAM Access Timing: Two-State Access
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Section 26 Electrical Characteristics
Tp
Tr
Tc1
Tcw
Tcwp
Tc2
φ
A23 to A0
RAS5 to RAS2
UCAS, LCAS
OE, RD
Read
HWR
D15 to D0
UCAS, LCAS
OE, RD
Write
HWR
D15 to D0
AS
tWTS tWTH
tWTS tWTH
WAIT
DACK0, DACK1
EDACK2, EDACK3
Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Tcw:
Wait cycle inserted by programmable wait function
Tcwp: Wait cycle inserted by pin wait function
Figure 26.16 DRAM Access Timing: Two-State Access, One Wait
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Tp
Section 26 Electrical Characteristics
Tr
Tc1
Tc2
Tc1
Tc2
φ
A23 to A0
RAS5 to RAS2
tCPW1
UCAS
LCAS
OE, RD
Read
HWR
tAC3
D15 to D0
OE, RD
Write
tRCH
HWR
tRCS1
D15 to D0
AS
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Figure 26.17 DRAM Access Timing: Two-State Burst Access
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Section 26 Electrical Characteristics
Tp
Tr
Tc1
Tc3
Tc2
φ
tAD
tAD
A23 to A0
tAS2
RAS5 to RAS2
tCSD3
tAH2
tCSD1
tPCH1
tAS3
tAH3
tCASD1
tCASD2
UCAS
tCASW2
LCAS
tOED2/
tOED2B
tOED1/
tOED1B
tAC2
OE, RD
Read
HWR
tAA5
tRDS2 tRDH2
tAC7
D15 to D0
OE, RD
Write
tWRD2
tWCS2
tWCH2
tWRD2
HWR
tWDD
tWDS2
tWDH3
D15 to D0
AS
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Figure 26.18 DRAM Access Timing: Three-State Access (RAST = 1)
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Tp
Section 26 Electrical Characteristics
Tr
Tc1
Tc2
Tc3
Tc1
Tc2
Tc3
φ
A23 to A0
RAS5 to RAS0
tCPW2
UCAS
LCAS
OE, RD
Read HWR
tAC8
D15 to D0
OE, RD
Write
tRCH
HWR
tRCS2
D15 to D0
AS
DACK0, DACK1
EDACK2, EDACK3
Note:
DACK and EDACK timing: when DDS = 1 and EDDS = 1
RAS timing: when RAST = 1
Figure 26.19 DRAM Access Timing: Three-State Burst Access
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Section 26 Electrical Characteristics
TRp
TRc1
TRr
TRc2
φ
tCSD1
tCSD2
RAS5 to RAS2
tCSR1
tCASD1
tCASD1
UCAS, LCAS
OE
Figure 26.20 CAS-Before-RAS Refresh Timing
TRp
TRrw
TRr
TRc1
TRcw
TRc2
φ
tCSD1
tCSD2
RAS5 to RAS2
UCAS, LCAS
tCSR2
tCASD1
tCASD1
OE
Figure 26.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion)
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Section 26 Electrical Characteristics
Self-refresh
TRp
TRr
TRc
TRc
DRAM access
TRp
Tp
Tr
φ
tCSD2
tCSD2
RAS5 to RAS2
tRPS2
tCASD1
tCASD1
UCAS, LCAS
OE
Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0)
Self-refresh
TRp
TRr
TRc
TRc
TRp
DRAM access
Tp
Tr
φ
tCSD2
RAS5 to RAS2
tCASD1
tCSD2
tRPS1
tCASD1
UCAS, LCAS
OE
Figure 26.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)
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Section 26 Electrical Characteristics
φ
tBREQS
tBREQS
BREQ
tBACD
tBACD
BACK
tBZD
tBZD
A23 to A0
CS7 to CS0
(RAS5 to RAS2)
D15 to D0
AS, RD
HWR, LWR
UCAS, LCAS, OE
Figure 26.24 External Bus Release Timing
φ
BACK
tBRQOD
tBRQOD
BREQO
Figure 26.25 External Bus Request Output Timing
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Section 26 Electrical Characteristics
Tr
Tp
Tc1
Tw
Tc2
φ
SDRAMφ
tAD2
Address bus
Precharge-sel
RAS
tCSD4
tCSD4
tCSD4
CAS
Read
tCSD4
tCSD4
tCSD4
WE
CKE
tDQMD
tDQMD
High
DQMU,
DQML
tRDS3
tRDH3
Data bus
tCSD4
tCSD4
RAS
tCSD4
CAS
tCSD4
tCSD4
tCSD4
WE
tCSD4
tCSD4
Write
CKE
High
tDQMD
DQMU,
DQML
tDQMD
tWDD
Data bus
tWDH4
Figure 26.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)
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Section 26 Electrical Characteristics
TRp
TRr
Software standby
TRr2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
tCKED/
tCKEDB
CKE
tCKED/
tCKEDB
Figure 26.27 Synchronous DRAM Self-Refresh Timing
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Tp
Section 26 Electrical Characteristics
Tr
Tc1
Tc2
TRr
Ttp2
φ
SDRAMφ
Address bus
Precharge-sel
RAS
CAS
WE
tCKED/
tCKEDB
tCKED/
tCKEDB
CKE
DQMU,
DQML
Data bus
DACK or EDACK
Figure 26.28 Read Data: Two-State Expansion (CAS Latency 2)
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Section 26 Electrical Characteristics
26.3.4
H8S/2456, H8S/2456R, H8S/2454 Group
DMAC and EXDMAC Timing
The DMAC and EXDMAC timings are shown below.
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Section 26 Electrical Characteristics
Tma1
Tma2
T1
T2
φ
tAD
A23 to A0
tCSD1
CS7, CS6
tAHD
AH
tRSD1
tRSD2
RD
tAC2
Read
(RDNn=0)
tAA6
tMAD
tMAS1
tMAH
tRDS2
A15 to A0
AD15 to AD0
tRDH2
D15 toD0
tWRD2
tWRD2
HWR, LWR
Write
tWSW
tMAD
AD15 to AD0
tWDD
A15 to A0
tWDH1
D15 toD0
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0,
DACK1
EDACK2,
EDACK3
Figure 26.29 Multiplexed Bus Timing: Data Two-State Access
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Section 26 Electrical Characteristics
Tma1
Tmaw
Tma2
T1
T2
Tw
T3
φ
tAD
A23 to A0
tCSD1
CS7, CS6
tAHD
AH
tRSD1
tRSD2
RD
Read
(RDNn=0)
tMAD tMAS2
AD15 to AD0
tRDS2 tRDH2
tMAH
A15 to A0
D15 to D0
tWRD1
tWRD2
HWR, LWR
Write
tWDD tWDS1
tMAD
AD15 to AD0
tWDH1
D15 to D0
A15 to A0
tWTS tWTH
tWTS tWTH
WAIT
Figure 26.30 Multiplexed Bus Timing: Data Three-State Access, One Wait
(with Address Wait: When ADDEX = 1)
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Section 26 Electrical Characteristics
T1
T2
φ
A23 to A0
CS7 to CS0
AS
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK0 to EDACK3
Figure 26.31 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access
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Section 26 Electrical Characteristics
T1
T2
T3
φ
A23 to A0
CS7 to CS0
AS
RD
(read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tDACD1
tDACD2
tEDACD1
tEDACD2
DACK0, DACK1
EDACK2, EDACK3
Figure 26.32 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access
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Section 26 Electrical Characteristics
T1
T2 or T3
φ
tTED
tTED
tETED
tETED
TEND0, TEND1
ETEND2, ETEND3
Figure 26.33 DMAC and EXDMAC, TEND/ETEND Output Timing
φ
tDRQS tDRQH
DREQ0, DREQ1
tEDRQS tEDRQH
EDREQ2, EDREQ3
Figure 26.34 DMAC and EXDMAC, DREQ/EDREQ Input Timing
φ
tEDRKD
tEDRKD
EDRAK2, EDRAK3
Figure 26.35 EXDMAC, EDRAK Output Timing
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Section 26 Electrical Characteristics
26.3.5
USB Characteristics
The following figures describe USB characteristics.
Rise Time
USD+, USD-
VCRS
90%
Fall Time
90%
10%
Differential
Data Liness
10%
tR
tF
Figure 26.36 Data Signal Timing
Rs=27Ω
USD+
Test Point
CL=50pF
Rs=27Ω
USD-
Test Point
CL=50pF
Figure 26.37 Load Conditions
Oscillator
φ
USPLLCR/
USSTC1, USSTC0
00
other than 00
Oscillation stabilization time
tUSOSC
USB PLL output clock
EXMSTPCRL/
MSTPI7
Two 48-MHz USB clocks
48-MHz USB clock
(cku)
Figure 26.38 Timing of Oscillation Stabilization Time of USB PLL
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26.3.6
Section 26 Electrical Characteristics
Timing of On-Chip Peripheral Modules
The on-chip peripheral module timings are shown below.
T1
T2
φ
tPRS tPRH
Ports 1 to 6, 8, 9,
A to J (read)
tPWD
Ports 1 to 3, 6, 8,
P53 to P50,
ports A to J
(write)
Figure 26.39 I/O Port Input/Output Timing
φ
tPOD
PO15 to PO0
Figure 26.40 PPG Output Timing
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Section 26 Electrical Characteristics
φ
tTOCD
Output compare
output*
tTICS
Input capture
input*
Note: * TIOCA0 to TIOCA11, TIOCB0 to TIOCB11, TIOCC0, TIOCC3, TIOCC6, TIOCC9,
TIOCD0, TIOCD3, TIOCD6, and TIOCD9
Figure 26.41 TPU Input/Output Timing
φ
tTCKS
tTCKS
TCLKA to TCLKH
tTCKWL
tTCKWH
Figure 26.42 TPU Clock Input Timing
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Section 26 Electrical Characteristics
φ
tTMOD
TMO0, TMO1
Figure 26.43 8-Bit Timer Output Timing
φ
tTMCS
tTMCS
TMCI0, TMCI1
tTMCWL
tTMCWH
Figure 26.44 8-Bit Timer Clock Input Timing
φ
tTMRS
TMRI0, TMRI1
Figure 26.45 8-Bit Timer Reset Input Timing
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Section 26 Electrical Characteristics
φ
tWOVD
tWOVD
WDTOVF
Figure 26.46 WDT Output Timing
tSCKW
tSCKr
tSCKf
SCK0 to SCK4
tScyc
Figure 26.47 SCK Clock Input Timing
SCK0 to SCK4
tTXD
TxD0 to TxD4
(transmit data)
tRXS tRXH
RxD0 to RxD4
(receive data)
Figure 26.48 SCI Input/Output Timing: Synchronous Mode
φ
tTRGS
ADTRG0,
ADTRG1
Figure 26.49 A/D Converter External Trigger Input Timing
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Section 26 Electrical Characteristics
VIH
SDA0
to
SDA1
VIL
tBUF
tSCLH
tSTAH
SCL0
to
SCL1
P*
S*
tSf
tSTOS
Sr*
tSCLL
tSr
P*
tSDAS
tSCL
Note:
tSP
tSTAS
tSDAH
S, P, and Sr represent the following conditions:
S: Start condition
P: Stop condition
Sr: Retransmit start condition
Figure 26.50 I2C Bus Interface 2 Input/Output Timing
SCS (output)
tTD
tLEAD
tFALL
tHI
tRISE
tLAG
SSCK (output)
CPOS = 1
tLO
tHI
SSCK (output)
CPOS = 0
tLO
tSUcyc
SSO (output)
tOH
tOD
SSI (input)
tSU
tH
Figure 26.51 SSU Timing (Master, CPHS = 1)
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Section 26 Electrical Characteristics
SCS (output)
tTD
tFALL
tHI
tLEAD
tRISE
tLAG
SSCK (output)
CPOS = 1
tLO
tHI
SSCK (output)
CPOS = 0
tLO
tSUcyc
SSO (output)
tOH
tOD
SSI (input)
tSU
tH
Figure 26.52 SSU Timing (Master, CPHS = 0)
SCS (input)
tLEAD
tFALL
tHI
tRISE
tLAG
tTD
SSCK (input)
CPOS = 1
tLO
tHI
SSCK (input)
CPOS = 0
tLO
tSUcyc
SSO (input)
tSU
tH
tREL
SSI (output)
tSA
tOH
tOD
Figure 26.53 SSU Timing (Slave, CPHS = 1)
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Section 26 Electrical Characteristics
SCS (input)
tLEAD
tFALL
tHI
tRISE
tLAG
tTD
SSCK (input)
CPOS = 1
tLO
tHI
SSCK (input)
CPOS = 0
tSUcyc
tLO
SSO (input)
tSU
tH
tREL
SSI (output)
tSA
tOH
tOD
Figure 26.54 SSU Timing (Slave, CPHS = 0)
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Section 26 Electrical Characteristics
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Appendix
Appendix
A.
Port States in Each Processing State
Table A.1
Port States in Each Processing State (H8S/2456R Group and H8S/2456 Group)
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
State
Mode
Program
Execution State
Sleep Mode
Port 1
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
P27 to P26
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
P25/WAIT
1, 2, 3, 4, 7 T
T
[WAIT-B input]
T
[WAIT-B input]
T
[WAIT-B input]
WAIT-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
P20
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
P34 to P30
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
P35/OE-B/
1
CKE-B*
1, 2, 3, 4, 7 T
T
[OE-B,
CKE-B output,
OPE = 0]
T
[OE-B,
CKE-B output,
OPE = 0]
T
[OE-B,
CKE-B output,
OPE = 0]
OE-B, CKE-B
[OE-B output,
OPE = 1]
H
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CKE-B output,
OPE = 1]
L
[Other than the
above]
Keep
Port 4
1, 2, 3, 4, 7 T
T
T
T
Input port
P53
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
P52/
BACK-B
1, 2, 3, 4, 7 T
T
[BACK-B output]
BACK-B
[BACK-B output]
BACK-B
[BACK-B output]
BACK-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1359 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
P51/
BREQ-B
P50/
BREQO-B
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
Program
Execution State
Sleep Mode
1, 2, 3, 4, 7 T
T
1, 2, 3, 4, 7 T
T
[BREQ-B input]
T
[BREQ-B input]
BREQ-B
[BREQ-B input]
BREQ-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[BREQO-B output] [BREQO-B output] [BREQO-B output]
BREQO-B
BREQO-B
BREQO-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
Port 6
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
Port 8
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
P97 to P96
1, 2, 3, 4, 7 T
T
T
T
Input port
P95/DA3
1, 2, 3, 4, 7 T
T
[DAOE3 = 1]
Keep
Keep
Input port
Keep
Input port
[DAOE3 = 0]
T
P94/DA2
1, 2, 3, 4, 7 T
T
[DAOE2 = 1]
Keep
[DAOE2 = 0]
T
P93 to P90
1, 2, 3, 4, 7 T
T
T
T
Input port
PA7/A23
1, 2, 3, 4, 7 T
T
[Address output,
OPE = 0]
T
[Address output]
T
[Address output]
A23 to A21
[Other than the
above]
Keep
[Other than the
above]
I/O port
PA6/A22
PA5/A21
[Address output,
OPE = 1]
Keep
[Other than the
above]
Keep
Page 1360 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
Program
Execution State
Sleep Mode
PA4/A20
1, 2
T
T
[Address output]
A20 to A16
[Address output]
T
[Address output]
A20 to A16
[Other than the
above]
Keep
[Other than the
above]
I/O port
T
[Address output]
A15 to A8
[Address output]
T
[Address output]
A15 to A8
[Other than the
above]
Keep
[Other than the
above]
I/O port
L
PA3/A19
[OPE = 0]
T
[OPE = 1]
Keep
PA2/A18
PA1/A17
3, 4, 7
T
T
PA0/A16
[Address output,
OPE = 0]
T
[Address output,
OPE = 1]
Keep
[Other than the
above]
Keep
Port B
1, 2
L
T
[OPE = 0]
T
[OPE = 1]
Keep
3, 4, 7
T
T
[Address output,
OPE = 0]
T
[Address output,
OPE = 1]
Keep
[Other than the
above]
Keep
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1361 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
Program
Execution State
Sleep Mode
Port C
1, 2
T
T
[Address output]
A7 to A0
[Address output]
T
[Address output]
A7 to A0
[Other than the
above]
Keep
[Other than the
above]
I/O port
L
[OPE = 0]
T
[OPE = 1]
Keep
3, 4, 7
T
T
[Address output,
OPE = 0]
T
[Address output,
OPE = 1]
Keep
[Other than the
above]
Keep
Port D
Port E
1, 2, 4
T
T
T
T
D15 to D8,
AD15 to AD8
3, 7
T
T
[Data bus,
address/data
multiplexed bus]
T
[Data bus,
address/data
multiplexed bus]
T
[Other than the
above]
Keep
[Other than the
above]
Keep
[Data bus,
address/data
multiplexed bus]
D15 to D8,
AD15 to AD8
1,
2,
4
Page 1362 of 1408
[Other than the
above]
I/O port
8-bit T
bus
T
Keep
Keep
I/O port
16bit
bus
T
T
T
D7 to D0,
AD7 to AD0
T
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
Program
Execution State
Sleep Mode
Port E
3, 7
8-bit T
bus
T
Keep
Keep
I/O port
16bit
bus
T
[Data bus,
address/data
multiplexed bus]
T
[Data bus,
address/data
multiplexed bus]
T
[Other than the
above]
Keep
[Other than the
above]
Keep
[Data bus,
address/data
multiplexed bus]
D7 to D0,
AD7 to AD0
[Clock output]
H
[Clock output]
Clock output
[Clock output]
Clock output
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
Input port
[AS output,
OPE = 0]
T
[AS output]
T
[AS output]
AS
[Other than the
above]
Keep
[Other than the
above]
I/O port
T
RD, HWR
PF7/φ
PF6/AS/AH
T
1, 2, 4
Clock
output
3, 7
T
1, 2, 4
H
3, 7
T
T
T
[AS output,
OPE = 1]
H
[Other than the
above]
I/O port
[Other than the
above]
Keep
PF5/RD
1, 2, 4
H
PF4/HWR
T
[OPE = 0] T
[OPE = 1] H
3, 7
T
[RD, HWR output, [RD, HWR output]
OPE = 0]
T
T
[Other than the
[RD, HWR output, above]
OPE = 1]
Keep
H
[RD, HWR output]
RD, HWR
[Other than the
above]
I/O port
[Other than the
above]
Keep
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1363 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
Program
Execution State
Sleep Mode
PF3/LWR
1, 2, 4
H
T
3, 7
T
[LWR output]
T
[LWR output]
LWR
[Other than the
above]
Keep
[Other than the
above]
I/O port
[LCAS, DQML
output, OPE = 0]
T
[LCAS, DQML
output]
T
[LCAS, DQML
output]
LCAS, DQML
[LCAS, DQML
output, OPE = 1]
H
[Other than the
above]
Keep
[Other than the
above]
I/O port
[UCAS, DQMU
output, OPE = 0]
T
[UCAS, DQMU
output]
T
[UCAS, DQMU
output]
UCAS
[UCAS, DQMU
output, OPE = 1]
H
[Other than the
above]
Keep
[Other than the
above]
I/O port
[WAIT-A input]
T
[WAIT-A input]
T
[WAIT-A input]
WAIT-A
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[BREQ-A input]
T
[BREQ-A input]
BREQ-A
[BREQ-A input]
BREQ-A
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[LWR output,
OPE = 0]
T
[LWR output,
OPE = 1]
H
[Other than the
above]
Keep
PF2/LCAS/
1
DQML*
1, 2, 3, 4, 7 T
T
[Other than the
above]
Keep
PF1/UCAS/
1
DQMU*
1, 2, 3, 4, 7 T
T
[Other than the
above]
Keep
PF0/WAIT-A 1, 2, 3, 4, 7 T
PG6/
BREQ-A
1, 2, 3, 4, 7 T
Page 1364 of 1408
T
T
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Port Name
Pin Name
PG5/
BACK-A
PG4/
Appendix
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
Program
Execution State
Sleep Mode
1, 2, 3, 4, 7 T
T
1, 2, 3, 4, 7 T
T
BREQO-A
PG3/CS3
1, 2, 3, 4, 7 T
1
RAS3/CAS*
T
PG2/CS2
1
RAS2/RAS*
[BACK-A output]
BACK-A
[BACK-A output]
BACK-A
[BACK-A output]
BACK-A
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[BREQO-A output] [BREQO-A output] [BREQO-A output]
BREQO-A
BREQO-A
BREQO-A
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS output,
OPE = 0]
T
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS output,
OPE = 1]
H
PG1/CS1
[Other than the
above]
Keep
PG0/CS0
1, 2
H
3, 4, 7
T
T
[CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1365 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
PH3/OE-A/
1
CKE-A* /
CS7
MCU
Operating
Mode
Reset
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
1, 2, 3, 4, 7 T
T
[OE-A, CS,
CKE-A output,
OPE = 0]
T
[OE-A output,
OPE = 1]
H
Program
Execution State
Sleep Mode
[OE-A, CS,
CKE-A output]
T
[OE-A, CKE-A
output]
OE-A, CKE-A
[Other than the
above]
Keep
[CS output]
CS
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS output,
OPE = 1]
H
[Other than the
above]
I/O port
[CKE-A output,
OPE = 1]
L
[Other than the
above]
Keep
PH2/CS6
1, 2, 3, 4, 7 T
T
[CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
Page 1366 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Port Name
Pin Name
PH1/CS5/
RAS5
1
SDRAMφ*
MCU
Operating
Mode
Reset
Appendix
Hardware
Standby Software Standby Bus Release
Mode
Mode
State
1, 2, 3, 4, 7 [H8S/2456R [H8S/2456R [SDPSTP = 0 in
Group]
Group]
H8S/2456R
Clock
L
Group]
output
L
[H8S/2456
Group]
T
[H8S/2456
Group]
T
[SDPSTP = 1 in
H8S/2456R
Group, or
H8S/2456 Group,
CS output,
OPE = 0]
T
[SDPSTP = 1 in
H8S/2456R
Group, or
H8S/2456 Group,
CS output,
OPE = 1]
H
Program
Execution State
Sleep Mode
[SDPSTP = 0 in
H8S/2456R
Group]
Clock output
[SDPSTP = 0 in
H8S/2456R
Group]
Clock output
[SDPSTP = 1 in
H8S/2456R
Group, or
H8S/2456 Group,
CS output]
T
[SDPSTP = 1 in
H8S/2456R
Group, or
H8S/2456 Group,
CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
Keep
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[Other than the
above]
Keep
1, 2, 3, 4, 7 T
PH0/CS4/
1
RAS4/WE*
T
[CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
PJ2
1, 2, 3, 4, 7 T
T
T
T
Input port
PJ1 to PJ0
1, 2, 3, 4, 7 T
T
Keep
Keep
I/O port
WDTOVF
1, 2, 3, 4, 7 H
H
H
H
H*
USD+, USD− 1, 2, 3, 4, 7 T
T
T
Keep
USD+, USD−
2
[Legend]
H:
High-level
L:
Low-level
Keep: Input ports become high-impedance, and output ports retain their state.
T:
High-impedance
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1367 of 1408
Appendix
H8S/2456, H8S/2456R, H8S/2454 Group
DDR: Data direction register
OPE: Output port enable
Notes: 1. Not supported by the H8S/2456 Group.
2. Low output if a watchdog timer overflow occurs when WT/IT is 1.
Page 1368 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Table A.2
Appendix
Port States in Each Processing State (H8S/2454 Group)
Port Name
Pin Name
MCU
Operating
Mode
Port 1
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
1, 2, 3, 4, 7
T
T
Keep
Keep
I/O port
P27, P26
1, 2, 3, 4, 7
T
T
Keep
Keep
I/O port
P25/WAIT-B
1, 2, 3, 4, 7
T
T
[WAIT-B input]
T
[WAIT-B input]
T
[WAIT-B input]
WAIT-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
P20
1, 2, 3, 4, 7
T
T
Keep
Keep
I/O port
P34 to P30
1, 2, 3, 4, 7
T
T
Keep
Keep
I/O port
P35/OE-B
1, 2, 3, 4, 7
T
T
[OE-B output,
OPE = 0]
T
[OE-B output]
T
[OE-B output]
OE
[Other than the
above]
Keep
[Other than the
above]
I/O port
[OE-B output,
OPE = 1]
H
[Other than the
above]
Keep
Port 4
1, 2, 3, 4, 7
T
T
T
T
Input port
P53
1, 2, 3, 4, 7
T
T
Keep
Keep
I/O port
P52/BACK-B
1, 2, 3, 4, 7
T
T
[BACK-B output] [BACK-B output] [BACK-B output]
BACK-B
BACK-B
BACK-B
P51/BREQ-B
1, 2, 3, 4, 7
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
T
T
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[BREQ-B input]
T
[BREQ-B input]
BREQ-B
[BREQ-B input]
BREQ-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
Page 1369 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
P50/
BREQO-B
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
1, 2, 3, 4, 7
T
T
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
[BREQO-B
output]
BREQO-B
[BREQO-B
output]
BREQO-B
[BREQO-B
output]
BREQO-B
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
Port 8
1, 2, 3, 4, 7
T
T
Keep
Keep
I/O port
P95/DA3
1, 2, 3, 4, 7
T
T
[DAOE3 = 1]
Keep
Keep
Input port
Keep
Input port
[CS output]
T
[CS output]
CS
[DAOE3 = 0]
T
P94/DA2
1, 2, 3, 4, 7
T
T
[DAOE2 = 1]
Keep
[DAOE2 = 0]
T
PA7/A23/CS7 1, 2, 3, 4, 7
T
T
[CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Address output] [Address output]
T
A23
[Other than the
above]
[Address output, Keep
OPE = 0]
T
[Other than the
above]
I/O port
[Address output,
OPE = 1]
Keep
[Other than the
above]
Keep
Page 1370 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
PA6/A22
1, 2, 3, 4, 7
T
T
PA5/A21
Software
Standby Mode
Bus Release
State
[Address output, [Address output]
OPE = 0]
T
T
[Other than the
[Address output, above]
OPE = 1]
Keep
Keep
Program
Execution State
Sleep Mode
[Address output]
A22 to A21
[Other than the
above]
I/O port
[Other than the
above]
Keep
PA4/A20
1, 2
L
T
PA3/A19
[OPE = 0]
T
T
[Address output]
A20 to A16
[OPE = 1]
Keep
PA2/A18
PA1/A17
3, 4, 7
PA0/A16
T
T
[Address output, [Address output]
OPE = 0]
T
T
[Other than the
[Address output, above]
OPE = 1]
Keep
Keep
[Address output]
A20 to A16
[Other than the
above]
I/O port
[Other than the
above]
Keep
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1371 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Port B
1, 2
L
T
Software
Standby Mode
Bus Release
State
[OPE = 0]
T
T
Program
Execution State
Sleep Mode
[Address output]
A15 to A8
[OPE = 1]
Keep
4
T
T
[Address output, [Address output]
OPE = 0]
T
T
[Other than the
[Address output, above]
OPE = 1]
Keep
Keep
[Address output]
A15 to A8
[Other than the
above]
I/O port
[Other than the
above]
Keep
3, 7
T
T
[Address output, [Address output]
OPE = 0]
T
T
[Other than the
[Address output, above]
OPE = 1]
Keep
Keep
[Address output]
A15 to A8
[Other than the
above]
I/O port
[Other than the
above]
Keep
Page 1372 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Port C
1, 2
L
T
Software
Standby Mode
Bus Release
State
[OPE = 0]
T
T
Program
Execution State
Sleep Mode
[Address output]
A7 to A0
[OPE = 1]
Keep
4
T
T
[Address output, [Address output]
OPE = 0]
T
T
[Other than the
[Address output, above]
OPE = 1]
Keep
Keep
[Address output]
A7 to A0
[Other than the
above]
I/O port
[Other than the
above]
Keep
3, 7
T
T
[Address output, [Address output]
OPE = 0]
T
T
[Other than the
[Address output, above]
OPE = 1]
Keep
Keep
[Address output]
A7 to A0
[Other than the
above]
I/O port
[Other than the
above]
Keep
Port D
1, 2, 4
T
T
T
T
D15 to D8,
AD15 to AD8
3, 7
T
T
[Data bus,
address/data
multiplexed bus]
T
[Data bus,
address/data
multiplexed bus]
T
[Other than the
above]
Keep
[Other than the
above]
Keep
[Data bus,
address/data
multiplexed bus]
D15 to D8,
AD15 to AD8
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
[Other than the
above]
I/O port
Page 1373 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
Port E
PF7/φ
PF6/AS
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
1,
2,
4
8-bit bus T
T
Keep
Keep
I/O port
16-bit
bus
T
T
T
T
D7 to D0,
AD7 to AD0
3,
7
8-bit bus T
T
Keep
Keep
I/O port
16-bit
bus
T
[Data bus,
address/data
multiplexed bus]
T
[Data bus,
address/data
multiplexed bus]
T
[Other than the
above]
Keep
[Other than the
above]
Keep
[Data bus,
address/data
multiplexed bus]
D7 to D0,
AD7 to AD0
[Clock output]
H
[Clock output]
Clock output
[Clock output]
Clock output
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
Input port
[AS output,
OPE = 0]
T
[AS output]
T
[AS output]
AS
[Other than the
above]
Keep
[Other than the
above]
I/O port
T
RD, HWR
T
1, 2, 4
Clock
output
3, 7
T
1, 2, 4
H
3, 7
T
T
T
[AS output,
OPE = 1]
H
[Other than the
above]
I/O port
[Other than the
above]
Keep
PF5/RD
1, 2, 4
H
PF4/HWR
T
[OPE = 0] T
[OPE = 1] H
3, 7
T
[RD, HWR
[RD, HWR
output, OPE = 0] output]
T
T
[RD, HWR
output]
RD, HWR
[RD, HWR
[Other than the
output, OPE = 1] above]
H
Keep
[Other than the
above]
I/O port
[Other than the
above]
Keep
Page 1374 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
PF3/LWR
1, 2, 4
H
T
3, 7
T
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
[LWR output,
OPE = 0]
T
[LWR output]
T
[LWR output]
LWR
[Other than the
above]
Keep
[Other than the
above]
I/O port
[LCAS output]
T
[LCAS output]
LCAS
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[UCAS output]
T
[UCAS output]
UCAS
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[LWR output,
OPE = 1]
H
[Other than the
above]
Keep
PF2/LCAS/
CS6
1, 2, 3, 4, 7
T
T
[LCAS output,
OPE = 0]
T
[LCAS output,
OPE = 1]
H
[CS output,
OPE = 1]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
PF1/UCAS/
CS5
1, 2, 3, 4, 7
T
T
[UCAS output,
OPE = 0]
T
[UCAS output,
OPE = 1]
H
[CS output,
OPE = 1]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1375 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Port Name
Pin Name
PF0/
WAIT-A/
OE-A
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
1, 2, 3, 4, 7
T
T
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
[WAIT-A input]
T
[WAIT-A input]
T
[WAIT-A input]
WAIT-A
[OE-A output]
T
[OE-A output,
OPE = 0]
T
[OE-A output,
OPE = 0]
OE-A
[Other than the
above]
Keep
[Other than the
above]
I/O port
[BREQ-A input]
T
[BREQ-A input]
BREQ-A
[BREQ-A input]
BREQ-A
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[OE-A output,
OPE = 1]
H
[Other than the
above]
Keep
PG6/BREQ-A 1, 2, 3, 4, 7
PG5/BACK-A 1, 2, 3, 4, 7
PG4/
BREQO-A/
CS4
1, 2, 3, 4, 7
T
T
T
T
T
T
[BACK-A output] [BACK-A output] [BACK-A output]
BACK-A
BACK-A
BACK-A
[Other than the
above]
Keep
[Other than the
above]
Keep
[Other than the
above]
I/O port
[BREQO-A
output]
BREQO-A
[BREQO-A
output]
BREQO-A
[BREQO-A
output]
BREQO-A
[CS4 output,
OPE = 0]
T
[CS4 output]
T
[CS4 output]
CS4
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS4 output,
OPE = 1]
H
[Other than the
above]
Keep
Page 1376 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Port Name
Pin Name
PG3/CS3/
RAS3
Appendix
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
1, 2, 3, 4, 7
T
T
PG2/CS2/
RAS2
Software
Standby Mode
Bus Release
State
Program
Execution State
Sleep Mode
[CS output,
OPE = 0]
T
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS output]
T
[CS output]
CS
[Other than the
above]
Keep
[Other than the
above]
I/O port
[CS output,
OPE = 1]
H
PG1/CS1
[Other than the
above]
Keep
PG0/CS0
1, 2
H
3, 4, 7
T
T
[CS output,
OPE = 0]
T
[CS output,
OPE = 1]
H
[Other than the
above]
Keep
WDTOVF
1, 2, 3, 4, 7
H
H
H
H
H*
USD+, USD− 1, 2, 3, 4, 7
T
T
T
Keep
USD+, USD−
[Legend]
H:
High-level
L:
Low-level
Keep: Input ports become high-impedance, and output ports retain their state.
T:
High-impedance
DDR: Data direction register
OPE: Output port enable
Note: * Low output if a watchdog timer overflow occurs when WT/IT is 1.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1377 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
B.
Package Dimensions
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
Reference Dimension in Millimeters
Symbol
*2
E
HE
c1
b1
Terminal cross section
Index mark
ZD
c
A
36
A2
37
1
ZE
144
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
A1
F
L
L1
*3
e
y
bp
x
e
x
y
ZD
ZE
L
L1
Detail F
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Figure B.1 Package Dimensions (PLQP144KA-A)
Page 1378 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
JEITA Package Code
P-TFLGA145-9x9-0.65
Appendix
RENESAS Code
PTLG0145JB-A
Previous Code
-
MASS[Typ.]
0.15g
D
w S B
E
w S A
x4
v
y1 S
A
S
y S
e
A
ZD
e
N
M
L
K
J
B
H
G
F
E
D
ZE
C
B
Reference
Symbol
Dimension in Millimeters
Min
9.0
E
9.0
1
2
3
4
5
6
7
φb
8
9 10 11 12 13
0.15
w
0.20
A
1.2
A1
b
0.65
0.30
0.35
0.40
0.08
x
φxn S A B
Max
v
e
A
Nom
D
y
0.1
y1
0.20
SD
SE
ZD
0.6
ZE
0.6
Figure B.2 Package Dimensions (PTLG0145JB-A)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1379 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
JEITA Package Code
P-LQFP120-14x14-0.40
RENESAS Code
PLQP0120LA-A
Previous Code
120P6R-A / FP-120B / FP-120BV
MASS[Typ.]
0.7g
HD
*1
D
90
61
60
91
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
120
31
1
ZD
ZE
Terminal cross section
30
Index mark
c
L
A1
A
A2
F
y
e
*3
e
x
y
ZD
ZE
L
L1
L1
bp
x
Detail F
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.13 0.18 0.23
0.16
0.09 0.145 0.20
0.125
8°
0°
0.4
0.07
0.08
1.2
1.2
0.35 0.5 0.65
1.0
Figure B.3 Package Dimensions (PLQP0120LA-A)
Page 1380 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
JEITA Package Code
P-LQFP120-16x16-0.50
Appendix
RENESAS Code
PLQP0120KA-A
Previous Code
—
MASS[Typ.]
0.9g
HD
*1
D
90
61
60
91
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
c1
Reference Dimension in Millimeters
Symbol
*2
E
HE
b1
120
31
1
ZD
ZE
Terminal cross section
30
Index mark
c
L
A1
A
A2
F
e
y
*3
L1
bp
x
Detail F
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
15.9 16.0 16.1
15.9 16.0 16.1
1.4
17.8 18.0 18.2
17.8 18.0 18.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.08
0.75
0.75
0.35 0.5 0.65
1.0
Figure B.4 Package Dimensions (PLQ0120KA-A)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1381 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
C.
Treatment of Unused Pins
The treatments of unused pins are listed in table C.1
Table C.1
Treatment of Unused Pins
Pin Name
Mode 1
Mode 2
Mode 4
RES
•
Connect this pin to VCC via a pull-up resistor
STBY
•
Connect this pin to VCC via a pull-up resistor
EMLE
•
Connect this pin to VSS via a pull-down resistor
MD2 to MD0
(Always used as mode pins)
Mode 7
NMI
•
EXTAL
(Always used as a clock pin)
XTAL
•
Leave this pin open
WDTOVF
•
Leave this pin open
Port 1
•
Connect these pins to VCC via a pull-up resistor or to VSS via a pull-down
resistor, respectively
Port 2
Connect this pin to VCC via a pull-up resistor
Port 3
Port 5
Port 8
PA7 to PA5
PF2 to PF0
PG7 to PG1
PH3, PH2,
PH0
PJ2 to PJ0
Ports 4 and 9 •
Page 1382 of 1408
Connect these pins to AVCC via a pull-up resistor or to AVSS via a pull-down
resistor, respectively
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Appendix
Pin Name
Mode 1
PF7
•
This pin is left open in the initial state for the φ output.
PF6
•
This pin is left open in the initial state for the AS output.
PF5
•
This pin is left open in the initial state for the RD output.
PF4
•
This pin is left open in the initial state for the HWR
output.
PF3
•
This pin is left open in the initial state for the LWR
output.
PG0
•
This pin is left open in the initial
state for the CS0 output.
PA4 to PA0
•
These pins are left open in the
initial state for the address output.
•
This pin is left open in the initial state for the SDRAMφ
output. (H8S/2456R)
•
Connect this pin to VCC via a pull-up resistor or to VSS via
a pull-down resistor, respectively. (H8S/2456 and
H8S/2454)
Port B
Mode 2
Mode 4
Mode 7
•
Connect these
pins to VCC via a
pull-up resistor or
to VSS via a pulldown resistor,
respectively
Port C
PH1
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1383 of 1408
Appendix
Page 1384 of 1408
H8S/2456, H8S/2456R, H8S/2454 Group
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Main Revisions and Additions in this Edition
Item
Page Revision (See Manual for Details)
4.3 Reset
100
Amended
A reset has the highest exception priority. When the RES pin goes
low, all processing halts and this LSI enters the reset. To ensure
that this LSI is reset, hold the RES pin low for at least 15 ms at
power-up. To reset this LSI during operation, hold the RES pin low
for at least 2 ms.
7.1 Features
321
Amended
•
Activation sources: internal interrupt, external request, autorequest (depending on transfer mode)
⎯ Six compare match/input capture interrupts of 16-bit timerpulse unit (TPU0 to TPU5)
⎯ Transmit data empty and receive data full interrupts of serial
communication interface (SCI_0, SCI_1)
7.3.4 DMA Control
Registers (DMACRA
and DMACRB)
331,
332
Amended
Bit
Bit Name
Description
• Channel A
3
DTF3
(1) Short Address
Mode:
2
DTF2
0100: Activated by SCI channel 0 transmit data empty interrupt
1
DTF1
0101: Activated by SCI channel 0 receive data full interrupt
•
0
DTF0
0110: Activated by SCI channel 1 transmit data empty interrupt
DMACR_0A,
DMACR_0B,
DMACR_1A, and
DMARC_1B
0111: Activated by SCI channel 1 receive data full interrupt
• Channel B
0100: Activated by SCI channel 0 transmit data empty interrupt
0101: Activated by SCI channel 0 receive data full interrupt
0110: Activated by SCI channel 1 transmit data empty interrupt
0111: Activated by SCI channel 1 receive data full interrupt
(2) Full Address Mode
•
DMACR_0B and
DMACR_1B
336
Amended
Bit
Bit Name
Description
3
DTF3
• Block Transfer Mode
2
DTF2
0100: Activated by SCI channel 0 transmit data empty interrupt
1
DTF1
0101: Activated by SCI channel 0 receive data full interrupt
0
DTF0
0110: Activated by SCI channel 1 transmit data empty interrupt
0111: Activated by SCI channel 1 receive data full interrupt
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1385 of 1408
Item
Page Revision (See Manual for Details)
Table 7.4 DMAC
Transfer Modes
354,
355
Amended
Transfer Source
• TPU channel 0 to 5 compare match/input capture A interrupt
• SCI transmit data empty interrupt
• SCI receive data full interrupt
• A/D converter conversion end interrupt
• External request
• TPU channel 0 to 5 compare match/input capture A interrupt
• SCI transmit data empty interrupt
• SCI receive data full interrupt
• A/D converter conversion end interrupt
• External request
7.5.2 Sequential Mode 357
Amended
Transfer requests (activation sources) consist of A/D converter
conversion end interrupts, external requests, SCI transmit data
empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can
only be specified for channel B.
7.5.3 Idle Mode
359
Amended
Transfer requests (activation sources) consist of A/D converter
conversion end interrupts, external requests, SCI transmit data
empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can
only be specified for channel B.
7.5.4 Repeat Mode
363
Amended
Transfer requests (activation sources) consist of A/D converter
conversion end interrupts, external requests, SCI transmit data
empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can
only be specified for channel B.
7.5.7 Block Transfer
Mode
Page 1386 of 1408
376
Amended
Transfer requests (activation sources) consist of A/D converter
conversion end interrupts, external requests, SCI transmit data
empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can
only be specified for channel B.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
Page Revision (See Manual for Details)
10.1.5 Pin Functions
527
(1) Pin Functions of
H8S/2456 Group and
H8S/2456R Group
•
P17/PO15/TIOCB2/
TCLKD/EDRAK3/
SCS0-A
Notes amended
3.
When using as SCS0-A input, set SCS0S1 and SCS0S0 in
PFCR5 to B'00 before other register setting.
4.
When using as SCS0-A output, set SCS0S1 and SCS0S0 in
PFCR5 to B'00 before other register setting.
5.
When using as SCS0-A input/output, set SCS0S1 and
SCS0S0 in PFCR5 to B'00 before other register setting.
•
Modes 3 and 7
(EXPE = 0)
•
P16/PO14/TIOCA2/ 529
EDRAK2/SSCK0-A
3.
Modes 3 and 7
(EXPE = 0)
When using as SSCK0-A input, set SSCK0S1 and SSCK0S0
in PFCR5 to B'00 before other register setting.
4.
When using as SSCK0-A output, set SSCK0S1 and SSCK0S0
in PFCR5 to B'00 before other register setting.
P15/PO13/TIOCB1/ 530
TCLKC/SSI0-A
3.
When using as SSI0-A input, set SSI0S1 and SSI0S0 in
PFCR5 to B'00 before other register setting.
4.
When using as SSI0-A output, set SSI0S1 and SSI0S0 in
PFCR5 to B'00 before other register setting.
•
•
•
P14/PO12/TIOCA1/ 532
SSO0-A
(2) Pin Functions of
H8S/2454 Group
•
•
538
P17/PO15/TIOCB2/
TCLKD/SCS0-A
P16/PO14/TIOCA2/ 540
SSCK0-A
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Notes amended
Notes amended
Notes amended
3.
When using as SSO0-A input, set SSO0S1 and SSO0S0 in
PFCR5 to B'00 before other register setting.
4.
When using as SSO0-A output, set SSO0S1 and SSO0S0 in
PFCR5 to B'00 before other register setting.
Notes amended
3.
When using as SCS0-A input, set SCS0S1 and SCS0S0 in
PFCR5 to B'00 before other register setting.
4.
When using as SCS0-A output, set SCS0S1 and SCS0S0 in
PFCR5 to B'00 before other register setting.
5.
When using as SCS0-A input/output, set SCS0S1 and
SCS0S0 in PFCR5 to B'00 before other register setting.
Notes amended
2.
When using as SSCK0-A input, set SSCK0S1 and SSCK0S0
in PFCR5 to B'00 before other register setting.
3.
When using as SSCK0-A output, set SSCK0S1 and SSCK0S0
in PFCR5 to B'00 before other register setting.
Page 1387 of 1408
Item
•
•
•
Page Revision (See Manual for Details)
P15/DACK1/PO13/ 541
TIOCB1/TCLKC/
SSI0-A
P14/DACK0/PO12/ 543
TIOCA1/SSO0-A
P10/DREQ0/PO8/
TIOCA0
10.2.5 Pin Functions
548
555
•
P25/PO5-A/
TIOCB4-A/
IRQ13-B/WAIT-B/
VBUS
•
Modes 3 and 7
(EXPE = 0)
•
557
P20/PO0-A/
TIOCA3-A/IRQ8-B/
PUPD+
•
•
P25/WAIT-B/
PO5-A/TIOCB4-A/
TMO1-A/VBUS
Modes 3 and 7
(EXPE = 0)
Page 1388 of 1408
3.
When using as SSI0-A input, set SSI0S1 and SSI0S0 in
PFCR5 to B'00 before other register setting.
4.
When using as SSI0-A output, set SSI0S1 and SSI0S0 in
PFCR5 to B'00 before other register setting.
Notes amended
2.
When using as SSO0-A input, set SSO0S1 and SSO0S0 in
PFCR5 to B'00 before other register setting.
3.
When using as SSO0-A output, set SSO0S1 and SSO0S0 in
PFCR5 to B'00 before other register setting.
Notes amended
3.
(1) Pin Functions of
H8S/2456 Group and
H8S/2456R Group
(2) Pin Functions of
H8S/2454 Group
Notes amended
560
When using as DREQ0 input, set USBDRQE in PFCR3 to 0
before other register setting. When USBDRQE is 1, use of the
DREQ0 signal from the DREQ0 input pin is not allowed.
Notes amended
3.
When using as PO5-A output, set PPGS in PFCR3 to 0 before
other register setting.
4.
When using as TIOCB4-A input/output, set TPUS in PFCR3 to
0 before other register setting.
Notes amended
4.
When using as PO0-A output, set PPGS in PFCR3 to 0 before
other register setting.
5.
When using as TIOCA3-A input/output, set TPUS in PFCR3 to
0 before other register setting.
Notes amended
2.
When using as PO5-A output, set PPGS in PFCR3 to 0 before
other register setting.
3.
When using as TIOCB4-A input/output, set TPUS in PFCR3 to
0 before other register setting.
4.
When using as TMO1-A output, set TMRS in PFCR3 to 0
before other register setting.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
Page Revision (See Manual for Details)
•
562
P20/PO0-A/
TIOCA3-A/
TMRI0-A/PUPD+
10.3.5 Pin Functions
•
•
•
•
•
•
576
P52/SCK2/IRQ2-A/
BACK-B/PO4-B/
TIOCA4-B/TMO0-B
Modes 3 and 7
(EXPE = 0)
P51/RxD2/IRQ1-A/ 579
SCL3/BREQ-B/
PO2-B/TIOCC3-B/
TMCI0-B
Modes 3 and 7
(EXPE = 0)
P50/TxD2/IRQ0-A/ 581
SDA3/BREQO-B/
PO0-B/TIOCA3-B/
TMRI0-B
Modes 3 and 7
(EXPE = 0)
10.6.5 Pin Functions
•
P65/IRQ13-A/
DACK1/TMO1-A
•
P64/IRQ12-A/
DACK0/TMO0-A
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
4.
When using as PO0-A output, set PPGS in PFCR3 to 0 before
other register setting.
5.
When using as TIOCA3-A input/output, set TPUS in PFCR3 to
0 before other register setting.
6.
When using as TMRI0-A input, set TMRS in PFCR3 to 0
before other register setting.
Notes amended
3.
P34/SCK0/SCK4-A/
SDA0
10.5.5 Pin Functions
•
567
Notes amended
584
Notes amended
4.
When using as PO4-B output, set PPGS in PFCR3 to 1 before
other register setting.
5.
When using as TIOCA4-B input/output, set TPUS in PFCR3 to
1 before other register setting.
6.
When using as TMO0-B output, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
6.
When using as PO2-B output, set PPGS in PFCR3 to 1 before
other register setting.
7.
When using as TIOCC3-B input/output, set TPUS in PFCR3 to
1 before other register setting.
8.
When using as TMCI0-B input, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
6.
When using as PO0-B output, set PPGS in PFCR3 to 1 before
other register setting.
7.
When using as TIOCA3-B input/output, set TPUS in PFCR3 to
1 before other register setting.
8.
When using as TMRI0-B input, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
2.
585
When using as SCK4-A input/output, set SCK4S in PFCR4 to
0 before other register setting.
When using as TMO1-A output, set TMRS in PFCR3 to 0
before other register setting.
Notes amended
2.
When using as TMO0-A output, set TMRS in PFCR3 to 0
before other register setting.
Page 1389 of 1408
Item
Page Revision (See Manual for Details)
•
P63/IRQ11-A/
TEND1/TMCI1-A
585
P62/IRQ10-A/
TEND0/TMCI0-A
586
P61/IRQ9A/DREQ1/
TMRI1-A
586
•
•
•
P60/IRQ8A/DREQ0/
TMRI0-A
10.7.5 Pin Functions
3.
587
591
P85/EDACK3/
IRQ5-B/SCK3/
PO5-B/TIOCB4-B/
TMO1-B
•
Modes 3 and 7
(EXPE = 0)
•
P83/ETEND3/
IRQ3-B/RxD3/
PO3-B/TIOCD3-B/
TMCI1-B
•
Modes 3 and 7
(EXPE = 0)
Page 1390 of 1408
594
When using as TMCI1-A input, set TMRS in PFCR3 to 0
before other register setting.
Notes amended
3.
(1) Pin Functions of
H8S/2456 Group and
H8S/2456R Group
•
Notes amended
When using as TMCI0-A input, set TMRS in PFCR3 to 0
before other register setting.
Notes amended
3.
When using as TMRI1-A input, set TMRS in PFCR3 to 0
before other register setting.
4.
When using as DREQ1 input, set USBDRQE in PFCR3 to 0
before other register setting.
Notes amended
3.
When using as TMRI0-A input, set TMRS in PFCR3 to 0
before other register setting.
4.
When using as DREQ0 input, set USBDRQE in PFCR3 to 0
before other register setting. When USBDRQE is 1, use of the
DREQ0 signal from the DREQ0 input pin is not allowed.
Notes amended
3.
When using as PO5-B output, set PPGS in PFCR3 to 1 before
other register setting.
4.
When using as TIOCB4-B input/output, set TPUS in PFCR3 to
1 before other register setting.
5.
When using as TMO1-B output, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
4.
When using as PO3-B output, set PPGS in PFCR3 to 1 before
other register setting.
5.
When using as TIOCD3-B input/output, set TPUS in PFCR3 to
1 before other register setting.
6.
When using as TMCI1-B input, set TMRS in PFCR3 to 1
before other register setting.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
Page Revision (See Manual for Details)
•
595
P81/EDREQ3/
IRQ1-B/TxD3/
PO1-B/TIOCB3-B/
TMRI1-B
(2) Pin Functions of
H8S/2454 Group
•
•
•
597
P85/SCK3/PO5-B/
TIOCB4-B/TMO1-B
P83/PO3-B/
TIOCD3-B/
TMCI1-B/RxD3
P81/PO1-B/
TIOCB3-B/
TMRI1-B/TxD3
10.9.6 Pin Functions
598
599
609
Notes amended
4.
When using as PO1-B output, set PPGS in PFCR3 to 1 before
other register setting.
5.
When using as TIOCB3-B input/output, set TPUS in PFCR3 to
1 before other register setting.
6.
When using as TMRI1-B input, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
2.
When using as PO5-B output, set PPGS in PFCR3 to 1 before
other register setting.
3.
When using as TIOCB4-B input/output, set TPUS in PFCR3 to
1 before other register setting.
4.
When using as TMO1-B output, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
3.
When using as PO3-B output, set PPGS in PFCR3 to 1 before
other register setting.
4.
When using as TIOCD3-B input/output, set TPUS in PFCR3 to
1 before other register setting.
5.
When using as TMCI1-B input, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
3.
When using as PO1-B output, set PPGS in PFCR3 to 1 before
other register setting.
4.
When using as TIOCB3-B input/output, set TPUS in PFCR3 to
1 before other register setting.
5.
When using as TMRI1-B input, set TMRS in PFCR3 to 1
before other register setting.
Notes amended
•
PA7/A23/CS7* /
IRQ7-A/SSO0-B
2.
When using as SSO0-B input, set SSO0S1 and SSO0S0 in
PFCR5 to B'01 before other register setting.
•
Modes 3 and 7
(EXPE = 0)
3.
When using as SSO0-B output, set SSO0S1 and SSO0S0 in
PFCR5 to B'01 before other register setting.
6
R01UH0309EJ0500 Rev. 5.00
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Page 1391 of 1408
Item
Page Revision (See Manual for Details)
•
PA6/A22/IRQ6-A/
SSI0-B
610
•
Modes 3 and 7
•
PA5/A21/IRQ5-A/
SSCK0-B
•
Modes 3 and 7
•
•
PA4/A20/IRQ4-A/
SCS0-B
PA3/A19/SCK4-B
612
613
615
Notes amended
2.
When using as SSI0-B input, set SSI0S1 and SSI0S0 in
PFCR5 to B'01 before other register setting.
3.
When using as SSI0-B output, set SSI0S1 and SSI0S0 in
PFCR5 to B'01 before other register setting.
Notes amended
2.
When using as SSCK0-B input, set SSCK0S1 and SSCK0S0
in PFCR5 to B'01 before other register setting.
3.
When using as SSCK0-B output, set SSCK0S1 and SSCK0S0
in PFCR5 to B'01 before other register setting.
Notes amended
2.
When using as SCS0-B input, set SCS0S1 and SCS0S0 in
PFCR5 to B'01 before other register setting.
3.
When using as SCS0-B output, set SCS0S1 and SCS0S0 in
PFCR5 to B'01 before other register setting.
4.
When using as SCS0-B input/output, set SCS0S1 and
SCS0S0 in PFCR5 to B'01 before other register setting.
Notes amended
*
•
PA2/A18/RxD4-B
615
Notes amended
*
•
PA1/A17/TxD4-B
616
•
PF3/LWR/SSO0-C
Page 1392 of 1408
658
When using as RxD4-B input, set RXD4S in PFCR4 to 1
before other register setting.
Notes amended
*
10.14.5 Pin Functions
When using as SCK4-B input/output, set SCK4S in PFCR4 to
1 before other register setting.
When using as TxD4-B output, set TXD4S in PFCR4 to 1
before other register setting.
Notes amended
1.
When using as SSO0-C input, set SSO0S1 and SSO0S0 in
PFCR5 to B'10 before other register setting.
2.
When using as SSO0-C output, set SSO0S1 and SSO0S0 in
PFCR5 to B'10 before other register setting.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
•
Page Revision (See Manual for Details)
6
PF2/LCAS/DQML* / 659
Notes amended
IRQ15-A/SSI0-C
2.
(H8S/2456 Group
and H8S/2456R
Group)
When using as SSI0-C input, set SSI0S1 and SSI0S0 in
PFCR5 to B'10 before other register setting.
3.
When using as SSI0-C output, set SSI0S1 and SSI0S0 in
PFCR5 to B'10 before other register setting.
•
Modes 3 and 7
(EXPE = 0)
•
PF2/CS6/LCAS/SSI 661
0-C (H8S/2454
Group)
Notes amended
1.
When using as SSI0-C input, set SSI0S1 and SSI0S0 in
PFCR5 to B'10 before other register setting.
2.
When using as SSI0-C output, set SSI0S1 and SSI0S0 in
PFCR5 to B'10 before other register setting.
•
Modes 3 and 7
(EXPE = 0)
•
6
PF1/UCAS/DQMU* / 662
Notes amended
IRQ14-A/SSCK0-C
2.
(H8S/2456 Group
and H8S/2456R
Group)
When using as SSCK0-C input, set SSCK0S1 and SSCK0S0
in PFCR5 to B'10 before other register setting.
3.
When using as SSCK0-C output, set SSCK0S1 and SSCK0S0
in PFCR5 to B'10 before other register setting.
•
Modes 3 and 7
(EXPE = 0)
•
PF1/CS5/UCAS/
SSCK0-C
(H8S/2454 Group)
•
Modes 3 and 7
(EXPE = 0)
•
PF0/WAIT-A/
•
663
665
Notes amended
1.
When using as SSCK0-C input, set SSCK0S1 and SSCK0S0
in PFCR5 to B'10 before other register setting.
2.
When using as SSCK0-C output, set SSCK0S1 and SSCK0S0
in PFCR5 to B'10 before other register setting.
Notes amended
ADTRG0-B/SCS0-C
2.
(H8S/2456 Group
and H8S/2456R
Group)
When using as SCS0-C input, set SCS0S1 and SCS0S0 in
PFCR5 to B'10 before other register setting.
3.
When using as SCS0-C output, set SCS0S1 and SCS0S0 in
PFCR5 to B'10 before other register setting.
4.
When using as SCS0-C input/output, set SCS0S1 and
SCS0S0 in PFCR5 to B'10 before other register setting.
Modes 3 and 7
(EXPE = 0)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1393 of 1408
Item
Page Revision (See Manual for Details)
•
667
•
PF0/WAIT-A/
ADTRG0-B/
SCS0-C/OE-A
(H8S/2454 Group)
Modes 3 and 7
(EXPE = 0)
15.3.7 Serial Status
Register (SSR)
881
Smart Card Interface
Mode (When SMIF bit
in SCMR is 1)
Notes amended
3.
When using as SCS0-C input, set SCS0S1 and SCS0S0 in
PFCR5 to B'10 before other register setting.
4.
When using as SCS0-C output, set SCS0S1 and SCS0S0 in
PFCR5 to B'10 before other register setting.
5.
When using as SCS0-C input/output, set SCS0S1 and
SCS0S0 in PFCR5 to B'10 before other register setting.
Amended
Bit
Bit Name
Description
2
TEND
Timing to set this bit differs according to the register
settings.
GM = 0, BLK = 0: 12.5 etu after transmission
GM = 0, BLK = 1: 11.5 etu after transmission
GM = 1, BLK = 0: 11.0 etu after transmission
GM = 1, BLK = 1: 11.0 etu after transmission
Table 15.2
883
Relationships between
N Setting in BRR and
Bit Rate B
Amended and added
Bit Rate
N=
N=
N=
N=
Table 16.1 Pin
Configuration
Page 1394 of 1408
950
φ × 106
64 × 2 2n−1 × B
φ × 106
32 × 2 2n−1 × B
φ × 106
−1
−1
−1
8 × 2 2n−1 × B
φ × 106
S × 2 2n+1 × B
−1
Amended
Pin Name
I/O
PUPD+
Output
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
Page Revision (See Manual for Details)
17.7 Usage Notes
1056, Added
1057 5. Restriction on Setting Transfer Rate in Use of Multi-Master
6. Restriction on Use of Bit Manipulation Instructions to Set MST
and TRS in Use of Multi-Master
7. Note on Master Receive Mode
8. Notes on Changing from Master Transmit Mode to Master
Receive Mode
18.3.4 A/D Control
Register (ADCR_0)
Unit 0
1072, Added
1073 Bit
Bit Name
Description
7
TRGS1
6
TRGS0
010: Enables A/D conversion start by external
trigger from TPU (units 0 and 1)*
0
EXTRGS
Note:* If this bit is set the same as the TRGS_1, TRGS0, and EXTRGS bits
in ADCR_1, the A/D converter units 0 and 1 start A/D conversion by
conversion start trigger from TPU (units 0 and 1).
18.3.5 A/D Control
Register (ADCR_1)
Unit 1
1074, Added
1075 Bit
Bit Name
Description
7
TRGS1
6
TRGS0
Enables A/D conversion start by external trigger
1
from TPU (units 0 and 1)*
0
EXTRGS
5
SCANE
4
SCANS
11: Scan mode. A/D conversion is performed
2
continuously for channels 1 to 8.*
Notes: 1. If this bit is set the same as the TRGS_1, TRGS0, and EXTRGS
bits in ADCR_0, the A/D converter units 0 and 1 start A/D
conversion by conversion start trigger from TPU (units 0 and 1).
2. Setting prohibited in the H8S/2424 Group.
18.7.10 otes on Start of 1093
A/D Conversion by
Conversion Start
Trigger from TPU
(Units 0 and 1)
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Added
Page 1395 of 1408
Item
Page Revision (See Manual for Details)
20.3.5 SS Status
Register (SSSR)
1112, Deleted
1113 Bit Bit Name
6
ORER
Description
[Clearing condition]
When writing 0 after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
hile the corresponding interrupt is enabled, be sure to
ead the flag after writing 0 to it.)
3
TEND
[Clearing condition]
• When writing 0 after reading TEND = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
2
TDRE
[Clearing condition]
• When writing 0 after reading TDRE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
1
RDRF
[Clearing condition]
• When writing 0 after reading RDRF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
0
CE
[Clearing condition]
• When writing 0 after reading CE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Page 1396 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
Page Revision (See Manual for Details)
Figure 22.2 Setting and 1154
Clearing EW0 Mode
Amended
Programming control program*4
Write 0 to the FMCMDEN bit and then write 1
to it (user program mode enabled).*1
Clear CBIDB to 0.
Write 1 to the CBIDB bit (user program mode
disabled).
Jump to a desired address in the flash memory.
Notes: 1.
2.
3.
Table 26.2 DC
Characteristics (1)
To set the FMCMDEN bit to 1, write 0 to the bit and then write 1 to it in a row.
Write to the FMCMDEN bit from an area outside the on-chip flash memory.
After a read array command, disable user programming mode.
In user program mode, execute the programming control program in
the on-chip RAM or external area.
1290, Added and amended
1291
Item
6
6
Schmitt trigger
input voltage
Ports 1* and 2* ,
2
P32 to P35* ,
2
P50 to P53* ,
2
2
ports 6* and 8* ,
2
PA4 to PA7* ,
2
2
ports B* and C* ,
2
2
PF1* , PF2* ,
2
2
PH2* , PH3*
Input high voltage
P14 to P17* ,
5
5
P25* , P26* ,
3
port 3* ,
3
P50 to P53* ,
3
3
ports 6* and 8* ,
3
ports A to J*
Input low voltage
P14 to P17* ,
5
5
P25* , P26* ,
3
3
3
ports 3* , 5* , and 6* ,
3
port 8* ,
3
ports A to J*
5
5
Notes: 5. When used as SSO, SSI, SSCK, SCS, WAIT, or ADTRG1.
6. When used as other than SSO, SSI, SSCK, SCS, WAIT, or
ADTRG1.
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1397 of 1408
Item
Page Revision (See Manual for Details)
Table 26.15 Flash
Memory
Characteristics
1304
Table 26.29 Flash
Memory
Characteristics
1321
Deleted and amended
Item
Symbol
Test
Conditions
Standard
Value
Applicable Area
Max.
Programming ROM
⎯
Data flash area
⎯
Programming time
Programming ROM
4000
(per 4 bytes)
Data flash area
4000
Erase time (per 1
block)
Programming ROM
3000
Data flash area
3000
Programming ROM
3.6
Programming and
erase count*1
Programming and
erase voltage
Read voltage
Data flash area
Programming ROM
3.6
Data flash area
Access state
Page 1398 of 1408
Programming ROM
⎯
Data flash area
⎯
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Item
Page Revision (See Manual for Details)
Table 26.17 DC
Characteristics (1)
1307, Amended and added
1308 Item
6
6
Schmitt trigger input Ports 1* and 2* ,
2
voltage
P32 to P35* ,
2
P50 to P53* ,
2
port 8* , PA4 to
2
2
PA7* , ports B*
2
2
and C* , PF1* ,
2
2
PF2* , P81*
2
and P83*
5
Input high voltage
P10 to P11* ,
5
P14 to P17* ,
5
5
P25* ,P26* ,
3
port 3* ,
3
P50 to P53* ,
3
port 8* , ports A
3
to G*
Input low voltage
P10 to P11* ,
5
P14 to P17* ,
6
6
P24* , P26* ,
3
ports 3* ,
3
3
and 5* , port 8,*
3
ports A to G*
5
Notes: 5. When used as SSO, SSI, SSCK, SCS, WAIT, ADTRG1 or
DREQ.
6. When used as other than SSO, SSI, SSCK, SCS, WAIT,
ADTRG1 or DREQ.
Table 26.24 Timing of
On-Chip Peripheral
Modules
1318
Amended
Item
SSU*
Clock cycle
Master
Symbol
Min.
tSUcyc
4
Slave
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Clock high pulse
width
Master
Clock low pulse
width
Master
4
tHI
48
Slave
Slave
48
tLO
48
48
Page 1399 of 1408
Page 1400 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Index
Numerics
16-Bit counter mode ............................... 839
16-Bit timer pulse unit (TPU)................. 693
8-Bit timer (TMR) .................................. 821
A
A/D conversion accuracy...................... 1086
A/D Converter ...................................... 1059
A/D converter activation......................... 776
Absolute accuracy................................. 1086
Absolute address....................................... 75
Acknowledge .............................. 1021, 1038
Activation by external request ................ 353
Activation by software.................... 498, 501
Address mode ......................................... 424
Address space ........................................... 53
Addressing modes..................................... 74
Advanced mode ........................................ 51
Arithmetic operations ......................... 62, 65
Asynchronous mode ............................... 894
Auto request mode.................................. 428
B
Basic timing............................................ 197
Bcc...................................................... 62, 70
Bit manipulation instructions.................... 68
Bit rate .................................................... 883
Block data transfer instructions ................ 72
Block transfer mode................ 371, 432, 496
Branch instructions ................................... 70
Break....................................................... 942
Buffer operation...................................... 752
Bulk-in transfer..................................... 1005
Bulk-out transfer................................... 1004
Burst mode.............................................. 380
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Burst Mode ............................................. 430
Burst ROM interface............................... 287
Bus arbitration......................................... 315
Bus controller (BSC)............................... 151
Bus release .............................................. 318
C
Cascaded connection............................... 839
Cascaded operation ................................. 756
Chain transfer.......................................... 497
Chain transfer when counter = 0 ............. 504
Clock Pulse Generator .......................... 1201
Clock synchronous communication
mode ..................................................... 1134
Clocked synchronous mode .................... 912
CMI......................................................... 132
CMIA ...................................................... 840
CMIA0 .................................................... 133
CMIA1 .................................................... 133
CMIB ...................................................... 840
CMIB0 .................................................... 133
CMIB1 .................................................... 133
Communications Protocol..................... 1174
Compare match count mode ................... 839
Condition field .......................................... 72
Condition-code register (CCR) ................. 57
Control transfer ....................................... 998
CPU operating modes ............................... 49
Cycle steal mode ..................................... 429
D
Data direction register............................. 509
Data register............................................ 509
Data size and data alignment .................. 194
Data stage.............................................. 1000
Page 1401 of 1408
Data transfer controller (DTC) ............... 477
Data transfer instructions.......................... 64
DMA controller (DMAC)....................... 321
DMTEND0A .......................................... 133
DMTEND0B .......................................... 133
DMTEND1A .......................................... 133
DMTEND1B .......................................... 133
DRAM interface ............................. 209, 223
DTC vector table .................................... 487
Dual address mode.................................. 424
E
Effective address extension ...................... 72
Ending DMA transfer ............................. 471
ERI0........................................................ 939
ERI1........................................................ 134
ERI2........................................................ 134
ERI3........................................................ 134
ERI4........................................................ 134
Exception handling ................................... 97
Exception handling vector table ............... 98
EXDMA controller (EXDMAC) ............ 407
EXDMTEND2........................................ 134
EXDMTEND3........................................ 134
Extended register (EXR) .......................... 56
Extension of chip select (CS)
assertion period............................... 208, 221
External request mode ............................ 428
I
I/O Port States in Each Processing
State ...................................................... 1359
I/O ports .................................................. 509
I2C Bus Format ..................................... 1037
I2C Bus Interface (IIC).......................... 1021
Idle cycle................................................. 290
Idle mode ................................................ 358
IICI0................................................ 135, 136
IICI1................................................ 135, 136
immediate ................................................. 76
Input capture function ............................. 748
Input pull-up MOS.................................. 509
Instruction set............................................ 62
Interrupt control modes........................... 138
Interrupt exception handling ................... 104
Interrupt exception handling vector
table ........................................................ 131
Interrupt mask bit...................................... 57
interrupt mask level .................................. 56
Interrupt priority register (IPR)............... 109
Interrupt sources ..................................... 401
Interrupt-in transfer............................... 1007
Interval timer mode................................. 854
IrDA operation........................................ 935
IRQ0 ....................................................... 131
L
List of Registers .................................... 1237
Logic operations instructions.................... 67
F
Flash Memory....................................... 1145
Framing error.......................................... 901
Full-scale error...................................... 1086
G
General Call Address............................ 1035
General registers ....................................... 55
Page 1402 of 1408
M
Mark state ............................................... 942
MCU operating modes.............................. 83
memory indirect........................................ 77
Multi-channel operation.......................... 395
Multiply-accumulate register (MAC) ....... 58
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
N
Q
NMI ........................................................ 148
NMI interrupt.......................................... 129
Nonlinearity error ................................. 1086
Non-overlapping pulse output ................ 813
Normal mode ...................... 49, 50, 368, 494
Normal transfer mode ............................. 431
Quantization error ................................. 1086
O
Offset error ........................................... 1086
On-board programming ........................ 1152
On-board programming mode .............. 1152
Open-drain control register..................... 509
Operation field.......................................... 72
Output trigger ......................................... 806
Overflow................................................. 852
Overrun error .......................................... 901
Overview .................................................... 1
OVI ......................................................... 840
OVI0 ....................................................... 133
OVI1 ....................................................... 133
P
Parity error.............................................. 901
Phase counting mode .............................. 764
PLL Circuit ........................................... 1209
Port function control register 2 ............... 687
Product Code Lineup ............................ 1378
Program counter (PC) ............................... 56
Program-counter relative .......................... 76
Programmable pulse generator ............... 797
Programmer Mode................................ 1200
Pull-up MOS control register.................. 509
Pulse output .................................... 833, 834
PWM modes ........................................... 758
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
R
RAM ..................................................... 1143
Read strobe (RD) timing ................. 206, 220
Register Addresses................................ 1238
Register Bits.......................................... 1254
Register direct ........................................... 74
Register field............................................. 72
Register indirect ........................................ 74
Register indirect with displacement .......... 75
Register indirect with post-increment ....... 75
Register indirect with pre-decrement ........ 75
Register information ............................... 487
Register States in Each Operating
Mode ..................................................... 1274
Registers
ABWCR.............................................. 158
ADCSR ............................................. 1067
ASTCR................................................ 158
BCR .................................................... 170
BROMCR ........................................... 169
BRR .................................................... 883
CRA .................................................... 482
CRB .................................................... 482
CSACR ............................................... 167
CTLR .................................................. 977
CVR .................................................... 977
DACR ............................................... 1098
DADR ............................................... 1097
DAR.................................................... 482
DASTS........................................ 965, 966
DMA ................................................... 974
DMABCR ........................................... 337
DMACR.............................................. 329
DMATCR ........................................... 350
Page 1403 of 1408
DMAWER.......................................... 348
DRACCR............................................ 181
DRAMCR........................................... 173
DTCER............................................... 483
DTVECR ............................................ 483
EDACR .............................................. 419
EDDAR .............................................. 411
EDMDR.............................................. 414
EDSAR............................................... 411
EDTCR............................................... 412
EPDR.................................................. 963
EPDR0i............................................... 961
EPDR0o.............................................. 962
EPDR0s .............................................. 962
EPIR ................................................... 979
EPSTL ........................................ 971, 972
EPSZ0o............................................... 964
EPSZ1................................................. 964
ETCR.................................................. 328
EXMSTPCR ..................................... 1220
FCLR .......................................... 969, 970
ICCRA.............................................. 1026
ICCRB .............................................. 1028
ICDRR.............................................. 1036
ICDRS .............................................. 1036
ICDRT .............................................. 1036
ICIER................................................ 1031
ICMR................................................ 1029
ICSR ................................................. 1033
IER...................................................... 116
IER (USB) .......................................... 956
IFR (USB) .......................................... 952
INTCR ................................................ 113
IOAR .................................................. 327
IPR...................................................... 114
IrCR .................................................... 891
ISCR ................................................... 118
ISR...................................................... 124
ISR (USB) .......................................... 959
ITSR ................................................... 125
Page 1404 of 1408
MAR ................................................... 326
MDCR................................................... 84
MRA ................................................... 479
MRB ........................................... 481, 484
MSTPCR........................................... 1219
NDER ................................................. 801
NDR.................................................... 803
P1DDR................................................ 523
P1DR................................................... 524
P2DDR................................................ 549
P2DR................................................... 550
P3DDR........................................ 563, 682
P3DR........................................... 564, 682
P3ODR................................................ 565
P5DDR................................................ 572
P5DR................................................... 572
P6DDR................................................ 582
P6DR................................................... 583
P8DDR................................................ 588
P8DR................................................... 589
PADDR............................................... 604
PADR.................................................. 606
PAODR............................................... 607
PAPCR................................................ 607
PBDDR ............................................... 618
PBDR.................................................. 619
PBPCR................................................ 620
PCDDR ............................................... 630
PCDR.................................................. 631
PCPCR................................................ 632
PCR..................................................... 806
PDDDR............................................... 642
PDDR.................................................. 643
PDPCR................................................ 644
PEDDR ............................................... 647
PEDR .................................................. 648
PEPCR ................................................ 649
PFDDR ............................................... 653
PFDR .................................................. 655
PGDDR............................................... 669
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
PGDR ................................................. 670
PHDDR............................................... 675
PHDR ................................................. 677
PLLCR.............................................. 1204
PMR.................................................... 807
PODR ................................................. 802
PORT1................................................ 524
PORT2................................................ 550
PORT3................................................ 564
PORT4................................................ 570
PORT5................................................ 573
PORT6................................................ 583
PORT8................................................ 589
PORT9................................................ 600
PORTA ............................................... 606
PORTB ............................................... 619
PORTC ............................................... 631
PORTD ............................................... 643
PORTE ............................................... 648
PORTF................................................ 655
PORTG ............................................... 670
PORTH ............................................... 677
RDNCR .............................................. 165
RDR.................................................... 864
REFCR ............................................... 184
RMMSTPCR .................................... 1221
RSR..................................................... 864
RSTCSR ............................................. 851
RTCNT ............................................... 187
RTCOR............................................... 187
SAR .................................................... 482
SBYCR ............................................. 1217
SCKCR ............................................. 1202
SCMR ................................................. 882
SCR..................................................... 869
SEMR ................................................. 892
SMR.................................................... 865
SSCR2 .............................................. 1114
SSCRH ............................................. 1107
SSCRL.............................................. 1109
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
SSER................................................. 1111
SSIER.................................................. 128
SSMR................................................ 1110
SSR ..................................................... 874
SSRDR.............................................. 1117
SSSR ................................................. 1112
SSTDR .............................................. 1116
SSTRSR ............................................ 1117
SYSCR.................................................. 85
TCNT .................................................. 825
TCORA............................................... 825
TCORB ............................................... 825
TCR............................................. 708, 826
TCSR .................................................. 849
TDR .................................................... 865
TGR ............................................ 729, 737
TIER.................................................... 732
TIOR ................................................... 715
TMDR................................................. 713
TRG ............................................ 967, 968
TRNTREG .......................................... 983
TSR ..................................................... 734
TSTR........................................... 737, 739
TSYR .......................................... 738, 740
WTCR................................................. 159
Repeat area function ............................... 434
Repeat mode ................................... 361, 495
Reset ....................................................... 100
Reset exception handling ........................ 100
Resolution ............................................. 1086
RXI0 ....................................................... 939
RXI1 ....................................................... 134
RXI2 ....................................................... 134
RXI3 ....................................................... 134
RXI4 ....................................................... 134
S
Sample-and-hold circuit........................ 1082
Scan mode............................................. 1078
Page 1405 of 1408
Sequential mode ..................................... 356
Serial communication interface .............. 859
Serial Communication Interface
Specification ......................................... 1171
Setup stage.............................................. 999
Shift instructions....................................... 67
Single address mode ....................... 365, 425
Single mode .......................................... 1076
Slave address ........................................ 1038
Slave-address........................................ 1021
Software activation ................................. 506
SSU mode............................................. 1122
stack pointer (SP) ..................................... 55
Stack status after exception handling...... 107
Stall operations ..................................... 1009
Start condition ...................................... 1038
Status stage ........................................... 1002
Stop condition....................................... 1038
SWDTEND............................................. 498
Synchronous DRAM interface ............... 255
Synchronous operation ........................... 749
Synchronous serial communication
unit (SSU)............................................. 1103
System control instructions ...................... 71
T
TCI0V..................................................... 132
TCI1U............................................. 773, 774
TCI1V............................................. 773, 774
TCI2U............................................. 773, 774
TCI2V............................................. 773, 774
TCI3V............................................. 773, 774
TCI4U............................................. 773, 774
TCI4V............................................. 773, 774
TCI5U............................................. 773, 774
TCI5V............................................. 773, 774
TCNT incrementation timing ................. 835
TEI0........................................................ 939
Page 1406 of 1408
TEI1 ........................................................ 134
TEI2 ........................................................ 134
TEI3 ........................................................ 134
TEI4 ........................................................ 134
TGI0A............................................. 773, 774
TGI0B ............................................. 773, 774
TGI0C ............................................. 773, 774
TGI0D............................................. 773, 774
TGI1A............................................. 773, 774
TGI1B ............................................. 773, 774
TGI2A............................................. 773, 774
TGI2B ............................................. 773, 774
TGI3A............................................. 773, 774
TGI3B ............................................. 773, 774
TGI3C ............................................. 773, 774
TGI3D............................................. 773, 774
TGI4A............................................. 773, 774
TGI4B ............................................. 773, 774
TGI5A............................................. 773, 774
TGI5B ............................................. 773, 774
Toggle output.................................. 747, 844
Trace bit .................................................... 56
Trace exception handling................ 103, 106
Transfer clock ....................................... 1118
Transfer mode ......................................... 353
Transfer Rate ........................................ 1027
Trap instruction exception handling ....... 105
TRAPA instruction ........................... 76, 105
TXI0........................................................ 939
TXI1........................................................ 134
TXI2........................................................ 134
TXI3........................................................ 134
TXI4........................................................ 134
U
USB function module (USB) .................. 949
USB standard commands...................... 1008
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
V
W
Valid strobes ........................................... 196
Vector number for the software activation
interrupt .................................................. 483
Wait control .................................... 205, 219
Watchdog timer (WDT) .......................... 847
Waveform output by compare match...... 745
WOVI...................................................... 854
Write data buffer ..................................... 310
Write data buffer function....................... 394
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
Page 1407 of 1408
Page 1408 of 1408
R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group User’s Manual: Hardware
Publication Date: Rev.1.00
Rev.5.00
Published by:
Sep 19, 2008
Sep 24, 2012
Renesas Electronics Corporation
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
Colophon 1.3
H8S/2456, H8S/2456R, H8S/2454 Group
R01UH0309EJ0500
(REJ09B0467-0350)
